Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
  • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/10—Bump connectors; Manufacturing methods related thereto
  • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
  • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
  • H01L2224/13001—Core members of the bump connector
  • H01L2224/13099—Material
  • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
  • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
  • H01L2224/13111—Tin [Sn] as principal constituent
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/10—Bump connectors; Manufacturing methods related thereto
  • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
  • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
  • H01L2224/161—Disposition
  • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
  • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/10—Bump connectors; Manufacturing methods related thereto
  • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
  • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
  • H01L2224/161—Disposition
  • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/10—Bump connectors; Manufacturing methods related thereto
  • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
  • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
  • H01L2224/161—Disposition
  • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
  • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
  • H01L2224/757—Means for aligning
  • H01L2224/75753—Means for optical alignment, e.g. sensors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
  • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
  • H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
  • H01L2224/81011—Chemical cleaning, e.g. etching, flux
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
  • H01L2224/8112—Aligning
  • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
  • H01L2224/818—Bonding techniques
  • H01L2224/81801—Soldering or alloying
  • H01L2224/81815—Reflow soldering
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/10—Bump connectors ; Manufacturing methods related thereto
  • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
  • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/10—Bump connectors ; Manufacturing methods related thereto
  • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
  • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Definitions

• the present invention relates broadly to semiconductor manufacturing, and more particularly but not exclusively, to a system and method for positioning a semiconductor chip with a bond head, and to a thermal bonding system and method.
• Flip chip bonding is widely used in semiconductor manufacturing.
• integrated circuit (IC) chips first need to be picked up from diced wafers or chip trays and then mounted onto a substrate using heat and pressure.
• Mounting is typically carried out using a bond tool (hereinafter interchangeably referred to as a bond head).
• the uniformity of heat and pressure distribution is typically determined by factors such as the size of the bond tool, the positioning of the chip on the bond tool, etc.
• underfill is pre-dispensed onto the substrate prior to mounting, it is also important to position the chip precisely relative to the bond tool to minimize or eliminate the risk of an underfill creeping up to the bond head along the edges of the chip in a thermal compression bonding process. This can happen if a portion of the bond head is exposed, for example, if the chip is mis-aligned with the bond head, or if the size of the bond head is greater than the size of the chip.
• a flux is usually used to increase wettability and clean the bonding surfaces by reacting with any oxide layer present.
• fluxing/underfilling is done on the substrate and the chip is aligned to the substrate. The chip is then made to contact the substrate and the temperature of the chip is raised until the temperature reaches a melting point of a solder whereupon bonding takes place.
• this process is rather slow since the steps are carried out sequentially, and expensive since it requires use of an expensive heating system which needs to be powered on and off intermittently.
• a modified version also known as melt and touch-down "MTD" bonding
• fluxing/underfilling is still done on the substrate, but the solder is molten before contacting the substrate.
• the bond head may be heated before or after picking up the chip, and transfers the heat to the solder.
• the chip is first aligned to the substrate and then made to contact the substrate whereupon bonding takes place.
• the oxide formation on the molten solder may not be sufficiently cleaned by the flux on the substrate, causing thin oxide entrapment which may weaken the bond or form cracks.
• FIG. 1 shows a schematic diagram illustrating another conventional flip chip fluxing and bonding process which involves dipping the chip in a reservoir with a controlled depth and retracting the chip.
• a chip 102 is dipped in to a flux reservoir 104 of a flux plate 106 using a bond head 108.
• the chip 102 is then retracted and aligned to a substrate 1 10 using the bond head 108, before being placed on the substrate 110.
• the solder molten before fluxing, the solder may smear at the point of fluxing and the direct heat from the chip 102 may change the flux properties in the reservoir 104.
• the bonding process may be much slower.
• such conventional fluxing process often has the limitation of the flux being inadequate as a result of dipping speed, dipping time, viscosity of the flux, or the parallelism between the chip 102 and the flux reservoir 104, etc.
• a system for positioning a semiconductor chip with a bond head comprising:
• first transporting means coupled to the controller and configured to hold and move the semiconductor chip to a first position
• second transporting means coupled to the controller and configured to receive the semiconductor chip at the first position and move the semiconductor chip to a second position to be picked up by the bond head
• the first transporting means controllably corrects a position of the semiconductor chip such that the semiconductor chip is in a first alignment relative to the bond head at the first position;
• the second transporting means further controllably corrects the position of the semiconductor chip such that the semiconductor chip is in a second alignment relative to the bond head at the second position.
• the first alignment may comprise an angular alignment and a linear alignment along at least one horizontal reference axis.
• the second alignment may. comprise an angular alignment and a linear alignment along two horizontal reference axes.
• the second transporting means maybe a die feeder, the die feeder comprising: a chip receiving section moveable between the first position and the second position;
• a drive mechanism configured to move the chip receiving section from the first position to the second position.
• the holding means may comprise a sticky flux
• the chip receiving section may comprise a flux reservoir for containing said sticky flux at a predetermined depth.
• the semiconductor chip may be disposed in the flux reservoir for a predetermined fluxing duration.
• the flux material may have a stable volume over a temperature range of the bond head.
• the system may further comprise a first optical imager coupled to the controller for determining relative linear and angular offset values of the semiconductor chip held by the first transporting means.
• the first optical imager may comprise a camera configured to capture a first image of the semiconductor chip, and the controller may be configured to calculate and compare linear and angular offset values of the position of the semiconductor chip with respect to a reference position based on the first image captured by the camera.
• the first transporting means may comprise a rotary actuator coupled to the controller and configured to correct an angular position of the semiconductor chip based on the relative angular offset value.
• the first transporting means may further comprise a linear actuator coupled to the controller for moving the semiconductor chip horizontally to the first position, and the linear actuator may be configured to correct a linear position of the semiconductor chip based on the relative linear offset value.
• the system may further comprise a second optical imager coupled to the controller and configured to capture a second image of the semiconductor chip together with the bond head at the second position, and the controller may be configured to determine alignment of the semiconductor chip with the bond head based on the second image.
• the second optical imager may be configured to capture a third image of the semiconductor chip and a substrate for determining alignment between the semiconductor chip and the substrate.
• a thermal bonding system comprising:
• a bond head for picking up the semiconductor chip at the second position; and heating means coupled to the bond head and configured to heat the bond head to a temperature higher than a melting point of a solder attached to the semiconductor chip, the bond head thereby melting the solder.
• the bond head may be configured to dispose the semiconductor chip onto a substrate based on the alignment between the semiconductor chip and the bond head.
• a method for positioning a semiconductor chip with a bond head comprising the steps of: moving the semiconductor chip to a first position;
• the first alignment may comprise an angular alignment and a linear alignment along at least one horizontal reference axis.
• the second alignment may comprise an angular alignment and a linear alignment along two horizontal reference axes.
• the step of moving the semiconductor chip to from the first position to second position may comprise holding the semiconductor chip firmly in place in a predetermined depth of a sticky flux.
• the method may further comprise holding the semiconductor chip firmly in place in a predetermined depth of a sticky flux for a predetermined fluxing duration.
• the step of correcting a position of the semiconductor chip while moving the semiconductor chip to the first position may comprise determining relative linear and angular offset values of the semiconductor chip.
• Determining the relative linear and angular offset values of the semiconductor chip may comprise:
• the step of correcting a position of the semiconductor chip while moving the semiconductor chip to the first position may further comprise correcting an angular position of the semiconductor chip based on the relative angular offset value.
• the step of correcting a position of the semiconductor chip while moving the semiconductor chip to the first position may further comprise correcting a linear position of the semiconductor chip based on the relative linear offset value.
• the method may further comprise:
• thermo bonding method comprising the steps of:
• the step of picking up the semiconductor chip at the second position using the heated bond head may comprise detaching the semiconductor chip from a sticky flux before the bond head contacts the semiconductor chip.
• Figure 1 shows a schematic diagram illustrating a conventional fluxing process.
• Figure 2 shows a perspective view of a thermal bonding machine according to an example embodiment.
• Figure 3a shows a perspective view of a system for positioning a semiconductor chip with a bond head according to an example embodiment.
• Figure 3b shows a schematic diagram of the system of Figure 3a.
• Figure 4 shows an enlarged perspective view of the first transporting means used in the system of Figure 3a according to an example embodiment.
• Figure 5 shows an enlarged perspective view of the first optical imager used in the system of Figure 3a according to an example embodiment.
• Figure 6 shows an enlarged perspective view of the second transporting means used in the system of Figure 3a according to an example embodiment.
• Figure 7a shows an enlarged perspective view illustrating the system of Figure 3a picking a semiconductor chip.
• Figure 7b shows a schematic diagram corresponding to Figure 7a.
• Figure 8a shows an enlarged perspective view illustrating the system of Figure 3a determining offset values of semiconductor chip picked up in Figure 7a.
• Figure 8b shows a schematic diagram corresponding to Figure 8a.
• Figure 9a shows an enlarged perspective view illustrating the system of Figure 3a making a first positional correction.
• Figure 9b shows a schematic diagram corresponding to Figure 9a.
• Figure 10a shows an enlarged perspective view illustrating the system of Figure 3a making a second positional correction.
• Figure 10b shows a schematic diagram corresponding to Figure 10a.
• Figure 11 shows a schematic diagram illustrating a fluxing method according to an example embodiment.
• Figure 12a-12c show enlarged views of the chip receiving section of the die feeder according to an example embodiment.
• Figure 13a-13b show results comparing the flux sizes based on different fluxing durations.
• Figure 14a-14b shows results comparing flux size uniformity between the method of Figure 11 and a conventional method.
• Figure 15 shows a flow chart illustrating a method for positioning a semiconductor chip with a bond head according to an example embodiment.
• Figure 16 shows a flow chart illustrating a thermal bonding method according to an example embodiment.
• the example embodiments provide systems and methods for thermally bonding a semiconductor chip to a substrate, including systems and methods for positioning the semiconductor chip with a bond head prior to bonding. Specifically, the example embodiments relate to systems and methods for high speed and precise flip chip bonding of semiconductor chip to substrate.
• the semiconductor chip in the subsequent description refers to a bumped chip having a plurality of interconnections disposed thereon.
• the plurality of interconnections are preferably solder bumps or pillar bumps comprising a fusible or solder material, such as tin, capable of electrically and/or physically connecting with the substrate.
• the substrate refers to a device carrier capable of receiving and supporting the semiconductor chip, such as a printed circuit board, laminate substrate, flexible substrate, silicon substrate, leadframe or another semiconductor chip.
• FIG 2 shows a schematic diagram illustrating a thermal bonding machine 200 according to an example embodiment.
• the bonding machine 200 is made up of two bonding stations or systems 202, 204 which may perform the same or different bonding functions.
• Each bonding system 202, 204 includes a respective system for positioning a semiconductor chip with a bond head, as described in more detail with respect to Figures 3a-3b.
• the bonding machines 200 may also include a control box (not shown) where control equipment is housed.
• Figures 3a-3b show a system 300 for positioning a semiconductor chip with a bond head according to an example embodiment.
• the positioning system 300 includes first transporting means 302 for picking up the semiconductor chip 303 ( Figure 3b) at a pick-up location, e.g. from a flipper 304, and moving the semiconductor chip 303 to a first position, a first optical imager 306 for determining the amount of offset of the semiconductor chip 303 as picked up by the first transporting means 302, and second transporting means 308 for receiving the semiconductor chip 303 at the first position and moving the semiconductor chip 303 to a second position where the semiconductor chip 303 is picked up by a bond head 310.
• the first transporting means 302, first optical imager 306, second transporting means 308, and bond head 310 are coupled to a controller (not shown) which calculates relative angular and linear offset values of the semiconductor chip 303 based on data provided by the first optical imager 306, and instructs the first and second transporting means 302, 308 to make the necessary correction or compensation.
• the positioning system 300 further includes a second optical imager 312 coupled to the controller for determining alignment of the semiconductor chip 303 with the bond head 310 and alignment between the semiconductor chip 303 and the corresponding substrate at the second position for feedback to the first optical imager 306 and for a final positional correction if necessary.
• the first transporting means 302 includes a rotary actuator to correct an angular offset of the semiconductor chip 303 and a linear actuator to correct a linear offset of the semiconductor chip 303 along a first horizontal reference axis (e.g. X-axis 314 in Figure 3b) when moving the semiconductor chip 303 to the first position.
• the second transporting means 308 includes another linear actuator to correct a linear offset of the semiconductor chip 303 along a second horizontal reference axis (e.g. Y-axis 316 in Figure 3b).
• the first transporting means 302 may carry out a coarse positional correction
• the second transporting means 308 may carry out a fine positional correction
• the bond head 310 may be movable horizontally for final alignment with the semiconductor chip, e.g. based on data provided by the second optical imager 312.
• the semiconductor chip 303 is both angularly aligned and linearly aligned along two horizontal reference axes with the bond head 310 prior to being picked up by the bond head 310.
• FIG 4 shows an enlarged perspective view of the first transporting means 302 used in the system 300 of Figure 3a according to an example embodiment.
• the first transporting means 302 is in the form of a pick-and-place mechanism 400 which typically includes a pick up head 402 configured to pick up the semiconductor chip using vacuum or other suitable means, a first motorized mechanism such as a rotary actuator 404 configured to rotate the chip about its own axis, a second motorized mechanism such as a linear actuator 406 configured to move the chip in a vertical direction for pick and place motions, and a third motorized mechanism such as a linear actuator 408 to move the chip horizontally along X-axis, Y- axis or a combination of X- and Y-axes.
• a pick up head 402 configured to pick up the semiconductor chip using vacuum or other suitable means
• a first motorized mechanism such as a rotary actuator 404 configured to rotate the chip about its own axis
• a second motorized mechanism such as a linear actuator 406 configured to move
• Figure 5 shows an enlarged perspective view of the first optical imager 306 used in the system 300 of Figure 3a according to an example embodiment.
• the first optical imager 306 is in the form of a look-up camera 500 or an equivalent image capturing system configured to capture an image of the semiconductor chip, process the images of fiducial points or edges of the semiconductor chip, and send the data to the controller to calculate the relative X-Y offset (i.e. relative linear offset values) and relative theta offset (i.e. relative angular offset value)-.
• the look-up camera 500 typically includes a vision camera unit 502 having an image processor and a light source (covered in Figure 5).
• the look-up camera 500 also includes a half-mirror half-glass body 504, which is normally used if the camera unit 502 is placed at an angle to the surface of the semiconductor chip to be imaged.
• FIG. 6 shows an enlarged perspective view of the second transporting means 308 used in the system 300 of Figure 3a according to an example embodiment.
• the second transporting means is in the form of a die feeder 600 which includes a chip receiving section 602, i.e. a defined location to receive the semiconductor chip.
• the die feeder 600 also includes holding means configured to hold the semiconductor chip in place firmly until the semiconductor chip is handed to a bond tool 604.
• the holding means includes a sticky surface or patch, such as a sticky flux as described in more detail below with respect to Figures 11-12.
• the sticky flux is contained in a flux reservoir forming the chip receiving section 602. Other arrangements are possible.
• the holding means may securely hold the semiconductor chip by vacuum suction or other means which allow the semiconductor chip to be released prior to it being picked up by the bond tool 604.
• the die feeder 600 further includes a drive mechanism such as a linear actuator 606 configured to carry the chip to the bond head 604.
• a semiconductor chip 702 is provided at a pick up location, for example, from a chip flipper 704.
• the first transporting means in the form of the pick-and-place mechanism 400 ( Figure 4) picks up the chip 702 from the pick up location by using vacuum or other means.
• the semiconductor chip 702 at this stage may not have an ideal positioning and may appear shifted due to factors such as variation in the chip ejection from the wafer, variation in the pick up by the tool of the chip flipper 704, variation in the handover to the pick up tool, etc.
• the shift or misalignment is corrected as a preparation step prior to bonding with a substrate.
• the pick-and-place mechanism 400 carries the chip 702 to a predefined inspection location for image processing.
• the first optical imager in the form of the look-up camera 500 ( Figure 5) captures a first image of the chip 702, and the first image is processed and sent to the controller.
• the controller calculates and compares the offset values of the position of the chip 702 with respect to a reference position, and sends the offset values to the respective motorized mechanisms (e.g. rotary and linear actuators) of the pick-and-place mechanism 400 for a positional correction of the chip 702 in the horizontal reference axes and about its own axis (that is, a vertical axis through the plane of the chip 702).
• the respective motorized mechanisms e.g. rotary and linear actuators
• the pick-and-place mechanism 400 uses the respective actuators to make a first correction by rotating the chip 702 to a desired angle and moving the chip 702 along the first horizontal reference axis (i.e. X-axis) with the required linear compensation.
• the pick-and-place mechanism 400 then places the chip on a designated location (e.g. the chip receiving section) of the second transporting means while ensuring that the plane of the chip 702 is substantially parallel with the plane of the chip receiving section.
• the second transporting means in the form of the die feeder 600 receives the chip 702 at the chip receiving section, holds the chip 702 in place, and moves the chip 702 along the second horizontal reference axis (i.e. Y-axis) with the required correction in this direction until the chip 702 is at the second position.
• the second optical imager in the form of a vision camera 1000 captures a second image of the chip 702 on the bond head 1002 and sends the image to the controller, which calculates and compares the chip's position with respect to the previously captured image of the bond tool 1002 or a preceding chip.
• This comparison information is used to determine alignment of the chip 702 with the bond tool 1002 prior to placing the chip 702 onto a substrate. If the chip is not properly aligned to the bond tool 1002, the offset values are sent back to the controller to instruct the first optical imager 306 ( Figure 3a), the first transporting means and the second transporting means to make the necessary adjustments for the subsequent chip.
• the vision camera 1000 can also capture images of the chip 702 and the substrate to determine alignment between the chip and the substrate. If the chip 702 is only angularly offset with respect to the substrate, the bond tool 1002 can make the necessary angular correction to position the chip 702 in alignment with the substrate. On the other hand, if the offset values of the chip 702 with the bond tool 1002 or the substrate are outside of acceptable ranges, the chip 702 is removed and no bonding with the substrate takes place.
• a preferred method of holding the chip 702 in place while transporting the chip 702 from the first position to the second position comprises using a sticky material such as flux; however, other methods, such as using vacuum suction, can also be used.
• FIG. 11 shows a schematic diagram illustrating a fluxing method according to an example embodiment.
• a semiconductor chip 1 106 is brought to a flux reservoir 1108 containing a flux 1110 such as a sticky flux, and placed into the flux reservoir 1108 to a predetermined depth such that the flux substantially covers the solder underneath the chip 1106.
• the chip 1106 is typically handled using a pick-and-place mechanism 1112 similar to the pick-and-place mechanism 400 of Figure 4 in these steps, and the flux reservoir 1 108 preferably forms the chip receiving section 602 ( Figure 6) of the die feeder 600.
• step 1114 chip 1106 is moved to a bond head 116 while being held in place by the flux 1110.
• the sticky flux 1110 could be a sticky surface or patch to hold the chip 1 06 in place.
• the total duration of the chip 1106 being disposed in the flux 1 110 can be calculated based on the duration the chip 1106 is at the first position, the duration of movement, and the duration the chip is at the second position before being picked up by the bond head 11 16.
• a check of the alignment between the chip 1106 and the bond head 1116 may be carried out using the second optical imager in the form of the vision camera 1000 ( Figure 10a).
• the bond head 1 16 which is maintained at a temperature higher than the melting point of the solder using a heater (not shown) coupled thereto, picks up the chip 1106.
• the bond head 1116 includes suction means which causes the chip 1106 to be detached from the sticky flux 1110 away from the flux reservoir 1108 before the bond head 1116 contacts the chip 1106.
• the bond head 1 16 maintains a gap with the chip 1106 and through suction means, caused the chip 1106 to transverse across the gap to contact the bond head 1116.
• the heat from the bond head is not transferred to the sticky flux 11 10, and the properties of the sticky flux 1110 are not changed during this process.
• the bond head 1116 is not maintained at an elevated temperature, but rather, is heated up just prior to picking up the chip 1106. In yet another implementation, the bond head 11 16 is heated up only after picking up the chip 1 06 or after placing the chip 1 116 onto the substrate. In such instance, the bond head 1116 is not at an elevated temperature and may contact the chip 1106 directly while the chip 1106 is still in the flux reservoir 1108 to pick up the chip 1106.
• the bond head 1116 picks up the chip 1106, the heat is transferred from the bond head 11 16 to the chip 1106 and then the solder, thereby melting the solder while the solder is covered by the flux. Finally, in step 1120, the bond head 1116 places the chip 1106 onto a substrate 1122 after a confirmation of the realignment between the chip 106 and the substrate 1122 as described above with reference to Figures 10a-10b, while the flux reservoir 1108 is moved back to the first position to receive the next chip.
• the solder is molten only after fluxing, thereby avoiding smearing at the point of fluxing and changing the flux properties in the reservoir.
• the fluxing of the semiconductor chip can be incorporated into the process of positioning the semiconductor chip with the bond head, allowing simultaneous operations.
• the relatively bulky bond head needs only small movements to pick up the semiconductor chip, align and place the chip onto the substrate to effect bonding, thereby improving on the throughput.
• the bond head is maintained at substantially the same elevated temperature instead of requiring intermittent switching on and off.
• the thermal bonding method in the example embodiments can be carried out more efficiently and accurately.
• Figure 12a-12c show enlarged views of a flux reservoir 1200 forming the chip receiving section of the die feeder according to an example embodiment.
• the flux reservoir 1200 is being topped up with flux using a flux cup 1202. This may take place after each chip is transferred to the bond head, or after a predetermined number of transfers.
• the chip is disposed in the flux reservoir 1200, and ready to be transferred.
• the driving mechanism of the die feeder moves the flux reservoir 1200 together with the chip held thereon along a direction parallel to a guide rod 1204. As described above, a positional correction along a reference axis parallel to the guide rod can be carried out based on the initial offset of the chip.
• the amount of flux picked up during the fluxing process in the example embodiments can be determined based on the fluxing duration.
• Figure 13a- 3b show results comparing the flux sizes based on different fluxing durations.
• the fluxing duration is 200 milliseconds (ms)
• the fluxing duration is 1000 ms.
• the flux sizes are greater when the fluxing duration is longer, indicating that greater volumes of the flux are being picked up by the solder bumps.
• the fluxing method in the example embodiments can provide uniform flux volumes picked up by the solder bumps.
• Figure 14a-i4b shows results comparing flux size uniformity between the method of Figure 11 and a conventional method.
• Figure 14a illustrating the present fluxing method
• the sizes of the solder bumps are relatively uniform across different section of the chip.
• Figure 14b which illustrates a conventional punch fluxing method
• the sizes of the solder bumps vary, particularly nearer to the corners of the chip.
• Figure 15 shows a flow chart 500 illustrating a method for positioning a semiconductor chip with a bond head according to an example embodiment.
• the semiconductor chip is moved to a first position.
• a position of the semiconductor chip is corrected while moving the semiconductor chip to the first position such that the semiconductor chip is in a first alignment relative to the bond head at the first position.
• the semiconductor chip is moved from the first position to a second position adjacent the bond head.
• the position of the semiconductor chip is further corrected while moving the semiconductor chip to the second position such that the semiconductor chip is in a second alignment relative to the bond head at the second position.
• Figure 16 shows a flow chart 1600 illustrating a thermal bonding method according to an example embodiment.
• a semiconductor chip is positioned with a bond head using the method as described above with respect to Figure 15.
• the bond head is heated to a temperature higher than a melting point of a solder attached to the semiconductor chip.
• the semiconductor chip is picked up at the second position using the heated bond head, thereby melting the solder.
• the semiconductor chip is disposed onto a substrate based on the alignment between the semiconductor chip and the bond head.

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• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Manufacturing & Machinery (AREA)
• Wire Bonding (AREA)
• Die Bonding (AREA)

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• 2014
  • 2014-09-15 WO PCT/SG2014/000433 patent/WO2015038074A1/en active Application Filing
  • 2014-09-15 TW TW103131727A patent/TWI648811B/zh active
  • 2014-09-15 CN CN201480050265.0A patent/CN105531809B/zh active Active

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