WO2015037478A1 - Supporting glass substrate and conveyance element using same - Google Patents
Supporting glass substrate and conveyance element using same Download PDFInfo
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- WO2015037478A1 WO2015037478A1 PCT/JP2014/073085 JP2014073085W WO2015037478A1 WO 2015037478 A1 WO2015037478 A1 WO 2015037478A1 JP 2014073085 W JP2014073085 W JP 2014073085W WO 2015037478 A1 WO2015037478 A1 WO 2015037478A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68757—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a coating or a hardness or a material
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- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C3/00—Glass compositions
- C03C3/04—Glass compositions containing silica
- C03C3/076—Glass compositions containing silica with 40% to 90% silica, by weight
- C03C3/089—Glass compositions containing silica with 40% to 90% silica, by weight containing boron
- C03C3/091—Glass compositions containing silica with 40% to 90% silica, by weight containing boron containing aluminium
- C03C3/093—Glass compositions containing silica with 40% to 90% silica, by weight containing boron containing aluminium containing zinc or zirconium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Definitions
- the present invention relates to a supporting glass substrate and a transport body using the same, and specifically to a supporting glass substrate used for supporting a processed substrate in a manufacturing process of a semiconductor package (semiconductor device) and a transport body using the same.
- Portable electronic devices such as mobile phones, notebook personal computers, and PDAs (Personal Data Assistance) are required to be smaller and lighter.
- the mounting space of semiconductor chips used in these electronic devices is also strictly limited, and high-density mounting of semiconductor chips has become a problem. Therefore, in recent years, high-density mounting of semiconductor packages has been achieved by three-dimensional mounting technology, that is, by stacking semiconductor chips and interconnecting the semiconductor chips.
- a conventional wafer level package is manufactured by forming bumps in a wafer state and then separating them by dicing.
- the semiconductor chip is likely to be chipped.
- the fan-out type WLP can increase the number of pins, and can prevent chipping of the semiconductor chip by protecting the end portion of the semiconductor chip.
- the fan-out type WLP includes a step of forming a processed substrate by molding a plurality of semiconductor chips with a resin sealing material and then wiring to one surface of the processed substrate, a step of forming a solder bump, and the like.
- the sealing material may be deformed and the processed substrate may change in dimensions.
- the dimension of the processed substrate changes, it becomes difficult to perform wiring with high density on one surface of the processed substrate, and it becomes difficult to accurately form solder bumps.
- the present invention has been made in view of the above circumstances, and its technical problem is to create a support substrate that hardly causes a dimensional change of a processed substrate and a carrier using the same, thereby high-density mounting of a semiconductor package. To contribute.
- the present inventors have found that the above technical problem can be solved by adopting a glass substrate as a support substrate and strictly regulating the thermal expansion coefficient of the glass substrate.
- This is proposed as the present invention. That is, the supporting glass substrate of the present invention is characterized in that the average linear thermal expansion coefficient in the temperature range of 20 to 200 ° C. is 50 ⁇ 10 ⁇ 7 / ° C. or more and 66 ⁇ 10 ⁇ 7 / ° C. or less.
- the “average linear thermal expansion coefficient in the temperature range of 20 to 200 ° C.” can be measured with a dilatometer.
- the glass substrate is easy to smooth the surface and has high rigidity. Therefore, when a glass substrate is used as the support substrate, the processed substrate can be supported firmly and accurately. In addition, the glass substrate easily transmits light such as ultraviolet light. Therefore, when a glass substrate is used as the support substrate, the processed substrate and the support glass substrate can be easily fixed by providing an adhesive layer or the like. Further, by providing a release layer or the like, the processed substrate and the supporting glass substrate can be easily separated.
- the average linear thermal expansion coefficient in the temperature range of 20 to 200 ° C. is regulated to 50 ⁇ 10 ⁇ 7 / ° C. or more and 66 ⁇ 10 ⁇ 7 / ° C. or less.
- the linear thermal expansion coefficients of the processed substrate and the supporting glass substrate are easily matched.
- the linear thermal expansion coefficients of the two match, it becomes easy to suppress dimensional changes (particularly warp deformation) of the processed substrate during processing.
- wiring on one surface of the processed substrate can be performed with high density, and solder bumps can be accurately formed.
- the supporting glass substrate of the present invention is characterized in that an average linear thermal expansion coefficient in a temperature range of 30 to 380 ° C. is 50 ⁇ 10 ⁇ 7 / ° C. or more and 70 ⁇ 10 ⁇ 7 / ° C. or less.
- the “average linear thermal expansion coefficient in the temperature range of 30 to 380 ° C.” can be measured with a dilatometer.
- the supporting glass substrate of the present invention is preferably used for supporting a processed substrate in a semiconductor package manufacturing process.
- the support glass substrate of the present invention preferably has an ultraviolet transmittance of 40% or more at a wavelength of 300 nm in the thickness direction.
- the “ultraviolet transmittance at a wavelength of 300 nm in the plate thickness direction” can be evaluated by measuring the spectral transmittance at a wavelength of 300 nm using, for example, a double beam type spectrophotometer.
- the supporting glass substrate of the present invention preferably has a Young's modulus of 65 GPa or more.
- Young's modulus refers to a value measured by a bending resonance method. 1 GPa corresponds to approximately 101.9 kgf / mm 2 .
- the supporting glass substrate of the present invention has a glass composition of 50% to 80% by weight of SiO 2 , 1 to 20% Al 2 O 3, 3 to 20% B 2 O 3 , and 0 to 10% MgO.
- CaO 0 to 10%, SrO 0 to 7%, BaO 0 to 7%, ZnO 0 to 7%, Na 2 O 5 to 15%, K 2 O 0 to 10% are preferably contained.
- the supporting glass substrate of the present invention has, as a glass composition, SiO 2 55 to 70%, Al 2 O 3 3 to 15%, B 2 O 3 5 to 20%, MgO 0 to 5% by mass.
- CaO 0 to 10%, SrO 0 to 5%, BaO 0 to 5%, ZnO 0 to 5%, Na 2 O 5 to 15%, K 2 O 0 to 10% are preferably contained.
- the supporting glass substrate of the present invention preferably has a thickness of less than 2.0 mm, a wafer shape having a diameter of 100 to 500 mm or a substantially disc shape, and a thickness deviation of 30 ⁇ m or less. .
- the transport body of the present invention is a transport body including at least a processed substrate and a supporting glass substrate for supporting the processed substrate, wherein the supporting glass substrate is the above-described supporting glass substrate.
- the manufacturing method of the semiconductor package of this invention WHEREIN: The process of obtaining a conveyance body provided with at least a process board
- the “process for transporting the transport body” and the “process for processing the processed substrate” do not need to be performed separately and may be performed simultaneously. Specifically, processing may be performed on the processed substrate of the transport body during transport, or when the transport body is being transported, or when transport of the transport body is started. The processing may be performed on the processed substrate of the transport body at the previous stop or at the stop after the transport of the transport body is finished.
- the processing process includes a process of wiring on one surface of the processed substrate.
- the processing includes a process of forming solder bumps on one surface of the processed substrate.
- the semiconductor package of the present invention is manufactured by the above-described method for manufacturing a semiconductor package.
- the electronic device of this invention is an electronic device provided with a semiconductor package, and a semiconductor package is said semiconductor package.
- the average linear thermal expansion coefficient in the temperature range of 20 to 200 ° C. is 50 ⁇ 10 ⁇ 7 / ° C. or more and 66 ⁇ 10 ⁇ 7 / ° C. or less, preferably 53 ⁇ 10 ⁇ 7. / ° C. or more and 65 ⁇ 10 ⁇ 7 / ° C. or less, particularly preferably 55 ⁇ 10 ⁇ 7 / ° C. or more and 63 ⁇ 10 ⁇ 7 / ° C. or less.
- the average linear thermal expansion coefficient in the temperature range of 20 to 200 ° C. is outside the above range, it becomes difficult to match the linear thermal expansion coefficients of the processed substrate and the supporting glass substrate. If the linear thermal expansion coefficients of the two become mismatched, a dimensional change (particularly warp deformation) of the processed substrate is likely to occur during processing.
- the average linear thermal expansion coefficient in the temperature range of 30 to 380 ° C. is 50 ⁇ 10 ⁇ 7 / ° C. or more and 70 ⁇ 10 ⁇ 7 / ° C. or less, preferably 55 ⁇ 10 ⁇ 7 / ° C. or more and 65 ⁇ 10 -7 / ° C or less.
- the linear thermal expansion coefficients of the processed substrate and the supporting glass substrate are difficult to match. If the linear thermal expansion coefficients of the two become mismatched, a dimensional change (particularly warp deformation) of the processed substrate is likely to occur during processing.
- the ultraviolet transmittance at a wavelength of 300 nm with respect to the thickness direction is preferably 40% or more, 50% or more, 60% or more, or 70. % Or more, particularly preferably 80% or more. If the ultraviolet transmittance is too low, it becomes difficult to bond the processed substrate and the supporting substrate by the adhesive layer due to the irradiation of ultraviolet light, and it becomes difficult to separate the supporting substrate from the processed substrate by the release layer.
- the supporting glass substrate of the present invention has a glass composition of 50 to 80% by mass, SiO 2 50 to 80%, Al 2 O 3 1 to 20%, B 2 O 3 3 to 20%, MgO 0 to 10%, CaO 0 to It preferably contains 10%, SrO 0-7%, BaO 0-7%, ZnO 0-7%, Na 2 O 5-15%, K 2 O 0-10%.
- the reason for limiting the content of each component as described above will be described below.
- % display represents the mass% unless there is particular notice.
- SiO 2 is a main component that forms a glass skeleton.
- the content of SiO 2 is preferably 50 to 80%, 55 to 75% or 55 to 70%, particularly preferably 55 to 65%.
- the Young's modulus, acid resistance tends to decrease.
- the content of SiO 2 is too large, the higher the viscosity at high temperature in addition to the meltability tends to decrease, devitrification crystals cristobalite becomes easy to precipitate, the liquid phase temperature tends to rise become.
- Al 2 O 3 is a component that enhances the Young's modulus and a component that suppresses phase separation and devitrification.
- the content of Al 2 O 3 is preferably 1 to 20%, 3 to 18%, 4 to 16%, 5 to 13.5% or 6 to 12%, particularly preferably 7 to 10%.
- the content of Al 2 O 3 is too small, easily Young's modulus is lowered and also the glass phase separation, easily devitrified.
- the content of Al 2 O 3 is too large, the higher the viscosity at high temperature meltability, moldability tends to decrease.
- B 2 O 3 is a component that enhances meltability and devitrification resistance, and is a component that improves the ease of scratching and increases strength.
- the content of B 2 O 3 is preferably 3 to 20%, 5 to 20% or 7 to 18%, particularly preferably 10 to 15%.
- meltability, devitrification resistance is liable to lower, also resistance tends to decrease with respect to hydrofluoric acid chemical.
- Young's modulus, acid resistance tends to decrease.
- MgO is a component that lowers the viscosity at high temperature and increases the meltability, and among alkaline earth metal oxides, it is a component that significantly increases the Young's modulus.
- the content of MgO is preferably 0 to 10%, 0 to 8%, 0 to 6% or 0 to 5%, particularly preferably 0 to 1%. When there is too much content of MgO, devitrification resistance will fall easily.
- CaO is a component that lowers the high temperature viscosity and remarkably increases the meltability. Further, among the alkaline earth metal oxides, since the introduced raw material is relatively inexpensive, it is a component that lowers the raw material cost.
- the content of CaO is preferably 0 to 10%, 0.5 to 8% or 1 to 6%, particularly preferably 2 to 5%. When there is too much content of CaO, it will become easy to devitrify glass. In addition, when there is too little content of CaO, it will become difficult to receive the said effect.
- SrO is a component that suppresses phase separation and is a component that improves devitrification resistance.
- the content of SrO is preferably 0 to 7%, 0 to 5% or 0 to 3%, particularly preferably 0 to less than 1%. When there is too much content of SrO, it will become easy to devitrify glass.
- BaO is a component that increases devitrification resistance.
- the content of BaO is preferably 0-7%, 0-5%, 0-3% or 0-1%. When there is too much content of BaO, it will become easy to devitrify glass.
- ZnO is a component that lowers the high temperature viscosity and remarkably increases the meltability.
- the content of ZnO is preferably 0 to 7% or 0.1 to 5%, particularly preferably 0.5 to 3%. When there is too little content of ZnO, it will become difficult to receive the said effect. In addition, when there is too much content of ZnO, it will become easy to devitrify glass.
- Na 2 O is an important component for optimizing the coefficient of thermal expansion, and is a component that contributes to the initial melting of the glass raw material while lowering the high-temperature viscosity to significantly increase the meltability.
- the content of Na 2 O is preferably 5 to 15% or 6 to 13.5%, particularly preferably 7 to 13%. If the content of Na 2 O is too small, the meltability tends to be lowered, and the thermal expansion coefficient may be unduly lowered. On the other hand, when the content of Na 2 O is too large, there is a concern that the thermal expansion coefficient becomes unduly high.
- the mass ratio (Al 2 O 3 + Na 2 O) / SiO 2 is preferably 0.2 to 0.4, 0.23 to 0.35, or 0.25 to 0.00 from the viewpoint of optimizing the thermal expansion coefficient. 3, particularly preferably 0.26 to 0.29.
- K 2 O is a component for adjusting the thermal expansion coefficient, and is a component that contributes to the initial melting of the glass raw material while lowering the high-temperature viscosity to increase the meltability.
- the content of K 2 O is preferably 0 to 15%, 0 to 10% or 0 to 5%, particularly preferably 0 to 1%. When the content of K 2 O is too large, there is a concern that the thermal expansion coefficient becomes unduly high.
- the content of other components other than the above components is preferably 10% or less, and particularly preferably 5% or less in total, from the viewpoint of accurately enjoying the effects of the present invention.
- Fe 2 O 3 is a component that can be introduced as an impurity component or a fining agent component.
- the content of Fe 2 O 3 is preferably 0.05% or less or 0.03% or less, particularly preferably 0.02% or less.
- “Fe 2 O 3 ” referred to in the present invention includes divalent iron oxide and trivalent iron oxide, and the divalent iron oxide is handled in terms of Fe 2 O 3 . Similarly, other oxides are handled based on the indicated oxide.
- the content of As 2 O 3 is preferably 1% or less or 0.5% or less, particularly preferably 0.1% or less, and it is desirable that it is not substantially contained.
- “substantially does not contain As 2 O 3 ” refers to the case where the content of As 2 O 3 in the glass composition is less than 0.05%.
- the content of Sb 2 O 3 is preferably 1% or less or 0.5% or less, particularly preferably 0.1% or less, and it is desirable that the Sb 2 O 3 content is not substantially contained.
- “substantially does not contain Sb 2 O 3 ” refers to a case where the content of Sb 2 O 3 in the glass composition is less than 0.05%.
- SnO 2 is a component having a good clarification action in a high temperature region and a component that lowers the high temperature viscosity.
- the content of SnO 2 is preferably 0 to 1%, 0.001 to 1% or 0.01 to 0.9%, particularly preferably 0.05 to 0.7%.
- the content of SnO 2 is too large, the devitrification crystal SnO 2 is likely to precipitate. Incidentally, when the content of SnO 2 is too small, it becomes difficult to enjoy the above-mentioned effects.
- metal powders such as F, Cl, SO 3 , C, Al, Si, etc. may be introduced up to about 3% each as a fining agent.
- CeO 2 or the like can be introduced up to about 3%, but it is necessary to pay attention to a decrease in ultraviolet transmittance.
- Cl is a component that promotes melting of glass. If Cl is introduced into the glass composition, the melting temperature can be lowered and the clarification action can be promoted. As a result, the melting cost can be lowered and the glass production kiln can be easily extended. However, when there is too much Cl content, there is a possibility of corroding the metal parts around the glass manufacturing kiln. Therefore, the Cl content is preferably 3% or less, 1% or less, or 0.5% or less, and particularly preferably 0.1% or less.
- P 2 O 5 is a component that can suppress the precipitation of devitrified crystals.
- the content of P 2 O 5 is preferably 0 to 2.5%, 0 to 1.5% or 0 to 0.5%, particularly preferably 0 to 0.3%.
- TiO 2 is a component that lowers the high-temperature viscosity and increases the meltability, and also suppresses solarization. However, when a large amount of TiO 2 is introduced, the glass is colored and the transmittance tends to decrease. Therefore, the content of TiO 2 is preferably 0 to 5%, 0 to 3% or 0 to 1%, particularly preferably 0 to 0.02%.
- ZrO 2 is a component that improves chemical resistance and Young's modulus.
- the content of ZrO 2 is preferably 0 to 5%, 0 to 3% or 0 to 1%, particularly preferably 0 to 0.5%.
- Y 2 O 3 , Nb 2 O 5 , and La 2 O 3 have a function of increasing the strain point, Young's modulus, and the like. However, if the content of these components is more than 5% or 1%, the raw material cost and the product cost may increase.
- the supporting glass substrate of the present invention preferably has the following characteristics.
- the Young's modulus is preferably 65 GPa or more, 67 GPa or more, 68 GPa or more, 69 GPa or more, or 70 GPa or more, and particularly preferably 71 GPa or more. If the Young's modulus is too low, it becomes difficult to maintain the rigidity of the conveyance body, and the processed substrate is likely to be deformed, warped, or damaged.
- the liquidus temperature is preferably less than 1150 ° C, 1120 ° C or less, 1100 ° C or less, 1080 ° C or less, 1050 ° C or less, 1010 ° C or less, 980 ° C or less, 960 ° C or less, or 950 ° C or less, particularly preferably 940 ° C or less. is there.
- the glass substrate can be easily formed by the downdraw method, particularly the overflow downdraw method, so that it is easy to produce a glass substrate having a small plate thickness, and the plate thickness deviation can be reduced without polishing the surface. As a result, the manufacturing cost of the glass substrate can be reduced.
- the “liquid phase temperature” is obtained by passing the standard sieve 30 mesh (500 ⁇ m) and putting the glass powder remaining on the 50 mesh (300 ⁇ m) in a platinum boat, and holding it in a temperature gradient furnace for 24 hours. It can be calculated by measuring the temperature at which precipitation occurs.
- the viscosity at the liquidus temperature is preferably 10,000 dPa ⁇ s or more, 30000 dPa ⁇ s or more, 60000 dPa ⁇ s or more, 100000 dPa ⁇ s or more, 150,000 dPa ⁇ s or more, 200000 dPa ⁇ s or more, 250,000 dPa ⁇ s or more, 300000 dPa ⁇ s or more, or 350,000 dPa ⁇ s.
- ⁇ S or more particularly preferably 400,000 dPa ⁇ s or more.
- the glass substrate can be easily formed by the downdraw method, particularly the overflow downdraw method, so that it is easy to produce a glass substrate having a small plate thickness, and the plate thickness deviation can be reduced without polishing the surface.
- the manufacturing cost of the glass substrate can be reduced.
- the “viscosity at the liquidus temperature” can be measured by a platinum ball pulling method. The viscosity at the liquidus temperature is an index of moldability. The higher the viscosity at the liquidus temperature, the better the moldability.
- the temperature at 10 2.5 dPa ⁇ s is preferably 1580 ° C. or lower, 1550 ° C. or lower, 1520 ° C. or lower, 1500 ° C. or lower, or 1480 ° C. or lower, particularly preferably 1300 to 1470 ° C.
- “temperature at 10 2.5 dPa ⁇ s” can be measured by a platinum ball pulling method. The temperature at 10 2.5 dPa ⁇ s corresponds to the melting temperature, and the lower the temperature, the better the melting property.
- the support glass substrate of the present invention is preferably formed by a downdraw method, particularly an overflow downdraw method.
- molten glass overflows from both sides of a heat-resistant bowl-shaped structure, and the overflowed molten glass joins at the lower top end of the bowl-shaped structure and is formed downward to produce a glass substrate. It is a method to do.
- the surface to be the surface of the glass substrate is not in contact with the bowl-shaped refractory, and is formed in a free surface state. For this reason, it becomes easy to produce a glass substrate having a small plate thickness, and the plate thickness deviation can be reduced without polishing the surface. As a result, the manufacturing cost of the glass substrate can be reduced.
- the structure and material of a bowl-shaped structure will not be specifically limited if a desired dimension and surface accuracy are realizable.
- the method of applying a force when performing downward stretch molding is not particularly limited. For example, a method may be adopted in which a heat-resistant roll having a sufficiently large width is rotated and stretched in contact with glass, or a plurality of pairs of heat-resistant rolls are contacted only near the end face of the glass. It is also possible to adopt a method of stretching by stretching.
- the glass substrate forming method in addition to the overflow downdraw method, for example, a slot down method, a redraw method, a float method, or the like can be adopted.
- the glass substrate of the present invention preferably has a substantially disk shape or wafer shape, and the diameter is preferably 100 mm or more and 500 mm or less, particularly 150 mm or more and 450 mm or less. In this way, it becomes easy to apply to the manufacturing process of a semiconductor package. You may process into other shapes, for example, shapes, such as a rectangle, as needed.
- the plate thickness is preferably less than 2.0 mm, 1.5 mm or less, 1.2 mm or less, 1.1 mm or less, or 1.0 mm or less, particularly preferably 0.9 mm or less.
- the plate thickness is preferably 0.1 mm or more, 0.2 mm or more, 0.3 mm or more, 0.4 mm or more, 0.5 mm or more, or 0.6 mm or more, and particularly preferably more than 0.7 mm.
- the thickness deviation is preferably 30 ⁇ m or less, 20 ⁇ m or less, 10 ⁇ m or less, 5 ⁇ m or less, 4 ⁇ m or less, 3 ⁇ m or less, 2 ⁇ m or less, or 1 ⁇ m or less, particularly preferably 0.1 to less than 1 ⁇ m.
- the arithmetic average roughness Ra is preferably 100 nm or less, 50 nm or less, 20 nm or less, 10 nm or less, 5 nm or less, 2 nm or less, or 1 nm or less, particularly preferably 0.5 nm or less. The higher the surface accuracy, the easier it is to improve the processing accuracy.
- the “arithmetic average roughness Ra” can be measured by a stylus type surface roughness meter or an atomic force microscope (AFM).
- the support glass substrate of the present invention is preferably formed by polishing the surface after being formed by the overflow downdraw method. If it does in this way, it will become easy to regulate board thickness deviation to 2 micrometers or less or 1 micrometer or less, especially less than 1 micrometer.
- the support glass substrate of the present invention is preferably not chemically strengthened from the viewpoint of production efficiency, and preferably chemically strengthened from the viewpoint of mechanical strength. That is, it is preferable not to have a compressive stress layer on the surface from the viewpoint of production efficiency, and it is preferable to have a compressive stress layer on the surface from the viewpoint of mechanical strength.
- the carrier of the present invention is a carrier comprising at least a processed substrate and a supporting glass substrate for supporting the processed substrate, wherein the supporting glass substrate is the supporting glass substrate described above.
- the technical characteristics (preferable structure and effect) of the carrier of the present invention overlap with the technical characteristics of the support glass substrate of the present invention. Therefore, in the present specification, detailed description of the overlapping portions is omitted.
- the carrier of the present invention preferably has an adhesive layer between the processed substrate and the supporting glass substrate.
- the adhesive layer is preferably a resin, for example, a thermosetting resin, a photocurable resin (particularly an ultraviolet curable resin), or the like.
- a resin for example, a thermosetting resin, a photocurable resin (particularly an ultraviolet curable resin), or the like.
- medical solution used in the manufacturing process of a semiconductor package, or the gas and plasma used in the case of dry etching is preferable.
- what has the heat resistance which can endure the heat processing in the manufacturing process of a semiconductor package is preferable. Thereby, it becomes difficult to melt
- the carrier of the present invention preferably further has a release layer between the processed substrate and the supporting glass substrate, more specifically between the processed substrate and the adhesive layer. If it does in this way, it will become easy to peel a processed substrate from a support glass substrate, after performing predetermined processing processing to a processed substrate. Peeling of the processed substrate is preferably performed with irradiation light such as laser light from the viewpoint of productivity.
- the peeling layer is made of a material that causes “in-layer peeling” or “interfacial peeling” by irradiation light such as laser light. That is, when light of a certain intensity is irradiated, the bonding force between atoms or molecules in an atom or molecule disappears or decreases, and ablation or the like is caused to cause peeling.
- the component contained in the release layer is released as a gas due to irradiation of irradiation light, the separation layer is released, and when the release layer absorbs light and becomes a gas, and its vapor is released, resulting in separation There is.
- the supporting glass substrate is preferably larger than the processed substrate.
- the method for manufacturing a semiconductor package of the present invention includes a step of obtaining a transport body including at least a processing substrate and a supporting glass substrate for supporting the processing substrate, a step of transporting the transport body, and a processing process on the processing substrate.
- a supporting glass substrate is the above-described supporting glass substrate.
- the processing is preferably performed by wiring on one surface of the processed substrate or forming solder bumps on one surface of the processed substrate.
- the processing since the processed substrate is difficult to change in dimensions during these processes, these steps can be appropriately performed.
- one surface of a processed substrate (usually the surface opposite to the supporting glass substrate) is mechanically polished, and one surface of the processed substrate (usually a supporting glass substrate) Either a process of dry-etching the surface on the opposite side or a process of wet-etching one surface of the processed substrate (usually the surface opposite to the supporting glass substrate) may be used.
- the processed substrate is unlikely to warp and the rigidity of the carrier can be maintained high. As a result, the above processing can be performed appropriately.
- the semiconductor package of the present invention is manufactured by the above-described semiconductor package manufacturing method.
- the technical characteristics (preferable configuration and effect) of the semiconductor package of the present invention overlap with the technical characteristics of the manufacturing method of the supporting glass substrate, the carrier, and the semiconductor package of the present invention. Therefore, in the present specification, detailed description of the overlapping portions is omitted.
- An electronic device of the present invention is an electronic device including a semiconductor package, and the semiconductor package is the semiconductor package described above.
- the technical characteristics (preferable structure and effect) of the electronic device of the present invention overlap with the technical characteristics of the supporting glass substrate, the carrier, the semiconductor package manufacturing method, and the semiconductor package of the present invention. Therefore, in the present specification, detailed description of the overlapping portions is omitted.
- FIG. 1 is a conceptual perspective view showing an example of the carrier 1 of the present invention.
- the carrier 1 includes a supporting glass substrate 10 and a processed substrate (semiconductor substrate) 11.
- the supporting glass substrate 10 is attached to the processed substrate 11 in order to prevent a dimensional change of the processed substrate 11.
- a release layer 12 and an adhesive layer 13 are disposed between the support glass substrate 10 and the processed substrate 11.
- the peeling layer 12 is in contact with the supporting glass substrate 10, and the adhesive layer 13 is in contact with the processed substrate 11.
- the carrier 1 is laminated in the order of a supporting glass substrate 10, a release layer 12, an adhesive layer 13, and a processed substrate 11.
- the shape of the support glass substrate 10 is determined according to the processed substrate 11, in FIG. 1, the shapes of the support glass substrate 10 and the processed substrate 11 are both substantially disk shapes.
- the release layer 12 is made of silicon oxide, silicate compound, silicon nitride, aluminum nitride, titanium nitride, or the like.
- the release layer 12 is formed by plasma CVD, spin coating by a sol-gel method, or the like.
- the adhesive layer 13 is made of a resin, and is applied and formed by, for example, various printing methods, inkjet methods, spin coating methods, roll coating methods, and the like.
- the adhesive layer 13 is removed by dissolution with a solvent or the like after the supporting glass substrate 10 is peeled from the processed substrate 11 by the peeling layer 12.
- FIG. 2 a to 2g are conceptual cross-sectional views showing manufacturing processes of a fan-out type WLP.
- FIG. 2 a shows a state in which an adhesive layer 21 is formed on one surface of the support member 20. A peeling layer may be formed between the support member 20 and the adhesive layer 21 as necessary.
- FIG. 2 b a plurality of semiconductor chips 22 are stuck on the adhesive layer 21. At that time, the surface on the active side of the semiconductor chip 22 is brought into contact with the adhesive layer 21.
- FIG. 2 c the semiconductor chip 22 is molded with a resin sealing material 23.
- the sealing material 23 is made of a material having little dimensional change after compression molding and little dimensional change when forming a wiring. Subsequently, as shown in FIGS.
- the processed substrate 24 on which the semiconductor chip 22 is molded is separated from the support member 20, and then bonded and fixed to the support glass substrate 26 through the adhesive layer 25.
- the surface of the processed substrate 24 opposite to the surface on which the semiconductor chip 22 is embedded is disposed on the supporting glass substrate 26 side.
- the transport body 27 can be obtained.
- the wiring 28 is formed on the surface of the processed substrate 24 on the side where the semiconductor chip 22 is embedded, and then on the exposed portion side of the wiring 28. A plurality of solder bumps 29 are formed.
- the processed substrate 24 is cut for each semiconductor chip 22 and used for the subsequent packaging process.
- Table 1 shows examples of the present invention (sample Nos. 1 to 7).
- a glass batch in which glass raw materials were prepared so as to have the glass composition in the table was placed in a platinum crucible and melted at 1550 ° C. for 4 hours.
- the mixture was stirred and homogenized using a platinum stirrer.
- the molten glass was poured out on a carbon plate, formed into a plate shape, and then gradually cooled from a temperature about 20 ° C. higher than the annealing point to room temperature at 3 ° C./min.
- the temperature at 0 dPa ⁇ s, the liquidus temperature TL, the viscosity ⁇ at the liquidus temperature TL, the Young's modulus E, and the ultraviolet transmittance T at a wavelength of 300 nm with respect to the plate thickness direction were evaluated.
- Average linear thermal expansion coefficient alpha 30 ⁇ 380 in the temperature range of average linear thermal expansion coefficient ⁇ 20 ⁇ 200, 30 ⁇ 380 °C in the temperature range of 20 ⁇ 200 ° C. is a value measured by a dilatometer.
- the density ⁇ is a value measured by the well-known Archimedes method.
- strain point Ps, the annealing point Ta, and the softening point Ts are values measured based on the method of ASTM C336.
- the temperature at a high temperature viscosity of 10 4.0 dPa ⁇ s, 10 3.0 dPa ⁇ s, and 10 2.5 dPa ⁇ s is a value measured by a platinum ball pulling method.
- the liquid phase temperature TL is the temperature at which crystals pass after passing through a standard sieve 30 mesh (500 ⁇ m), putting the glass powder remaining on 50 mesh (300 ⁇ m) into a platinum boat and holding it in a temperature gradient furnace for 24 hours. It is the value measured by microscopic observation.
- the viscosity ⁇ at the liquidus temperature is a value obtained by measuring the viscosity of the glass at the liquidus temperature TL by the platinum ball pulling method.
- the Young's modulus E refers to a value measured by the resonance method.
- the ultraviolet transmittance T at a wavelength of 300 nm is a value obtained by measuring the spectral transmittance at a wavelength of 300 nm in the plate thickness direction using a double beam type spectrophotometer.
- a plate having a thickness of 0.7 mm and both surfaces polished to an optically polished surface (mirror surface) was used as a measurement sample.
- the arithmetic surface roughness Ra of this evaluation sample was measured by AFM, it was 0.5 to 1.0 nm in a measurement region of 10 ⁇ m ⁇ 10 ⁇ m.
- sample No. 1 to 7 have an average linear thermal expansion coefficient ⁇ 30 to 200 in the temperature range of 20 to 200 ° C. of 56 ⁇ 10 ⁇ 7 / ° C. to 65 ⁇ 10 ⁇ 7 / ° C., and an average in the temperature range of 30 to 380 ° C.
- the linear thermal expansion coefficient ⁇ 30 to 380 was 58 ⁇ 10 ⁇ 7 / ° C. to 68 ⁇ 10 ⁇ 7 / ° C.
- Sample No. In Nos. 1 to 7 the Young's modulus E was 70 GPa or more, and the ultraviolet transmittance T at a wavelength of 300 nm in the thickness direction was 55% or more. Therefore, sample no. Nos. 1 to 7 are considered to be suitable as supporting glass substrates used for supporting the processed substrate in the manufacturing process of the semiconductor manufacturing apparatus.
- sample Nos. Listed in Table 1 were used. After preparing the glass raw material so as to have a glass composition of 1 to 7, the glass raw material is supplied to a glass melting furnace and melted at 1500 to 1600 ° C., and then the molten glass is supplied to an overflow downdraw molding apparatus, and the sheet thickness is 0 Each was molded to 7 mm. About the obtained glass substrate, both surfaces were machine-polished and the plate
Abstract
Description
10、26 支持ガラス基板
11、24 加工基板
12 剥離層
13、21、25 接着層
20 支持部材
22 半導体チップ
23 封止材
28 配線
29 半田バンプ
1, 27
Claims (14)
- 20~200℃の温度範囲における平均線熱膨張係数が50×10-7/℃以上で且つ66×10-7/℃以下であることを特徴とする支持ガラス基板。 A supporting glass substrate having an average linear thermal expansion coefficient of 50 × 10 −7 / ° C. or more and 66 × 10 −7 / ° C. or less in a temperature range of 20 to 200 ° C.
- 30~380℃の温度範囲における平均線熱膨張係数が50×10-7/℃以上で且つ70×10-7/℃以下であることを特徴とする支持ガラス基板。 A supporting glass substrate having an average linear thermal expansion coefficient of 50 × 10 −7 / ° C. or more and 70 × 10 −7 / ° C. or less in a temperature range of 30 to 380 ° C.
- 半導体パッケージの製造工程で加工基板の支持に用いることを特徴とする請求項1又は2に記載の支持ガラス基板。 The supporting glass substrate according to claim 1, wherein the supporting glass substrate is used for supporting a processed substrate in a manufacturing process of a semiconductor package.
- 板厚方向に対する波長300nmにおける紫外線透過率が40%以上であることを特徴とする請求項1~3の何れかに記載の支持ガラス基板。 The supporting glass substrate according to any one of claims 1 to 3, which has an ultraviolet transmittance of 40% or more at a wavelength of 300 nm in the plate thickness direction.
- ヤング率が65GPa以上であることを特徴とする請求項1~4の何れかに記載の支持ガラス基板。 5. The supporting glass substrate according to claim 1, wherein Young's modulus is 65 GPa or more.
- ガラス組成として、質量%で、SiO2 50~80%、Al2O3 1~20%、B2O3 3~20%、MgO 0~10%、CaO 0~10%、SrO 0~7%、BaO 0~7%、ZnO 0~7%、Na2O 5~15%、K2O 0~10%を含有することを特徴とする請求項1~5の何れかに記載の支持ガラス基板。 As a glass composition, SiO 2 50-80%, Al 2 O 3 1-20%, B 2 O 3 3-20%, MgO 0-10%, CaO 0-10%, SrO 0-7% by mass%. The supporting glass substrate according to any one of claims 1 to 5, comprising: BaO 0 to 7%, ZnO 0 to 7%, Na 2 O 5 to 15%, K 2 O 0 to 10%. .
- ガラス組成として、質量%で、SiO2 55~70%、Al2O3 3~15%、B2O3 5~20%、MgO 0~5%、CaO 0~10%、SrO 0~5%、BaO 0~5%、ZnO 0~5%、Na2O 5~15%、K2O 0~10%を含有することを特徴とする請求項6に記載の支持ガラス基板。 Glass composition is SiO 2 55-70%, Al 2 O 3 3-15%, B 2 O 3 5-20%, MgO 0-5%, CaO 0-10%, SrO 0-5% by mass%. The supporting glass substrate according to claim 6, further comprising BaO 0 to 5%, ZnO 0 to 5%, Na 2 O 5 to 15%, K 2 O 0 to 10%.
- 板厚が2.0mm未満であり、直径が100~500mmのウェハ形状又は略円板形状であり、且つ板厚偏差が30μm以下であることを特徴とする請求項1~7の何れかに記載の支持ガラス基板。 The plate thickness is less than 2.0 mm, the wafer has a diameter of 100 to 500 mm or a substantially disk shape, and the thickness deviation is 30 μm or less. Supporting glass substrate.
- 少なくとも加工基板と加工基板を支持するための支持ガラス基板とを備える搬送体であって、支持ガラス基板が請求項1~8の何れかに記載の支持ガラス基板であることを特徴とする搬送体。 A carrier comprising at least a processed substrate and a supporting glass substrate for supporting the processed substrate, wherein the supporting glass substrate is the supporting glass substrate according to any one of claims 1 to 8. .
- 少なくとも加工基板と加工基板を支持するための支持ガラス基板とを備える搬送体を得る工程と、
搬送体を搬送する工程と、
加工基板に対して、加工処理を行う工程と、を有すると共に、
支持ガラス基板が請求項1~8の何れかに記載の支持ガラス基板であることを特徴とする半導体パッケージの製造方法。 Obtaining a carrier comprising at least a processed substrate and a supporting glass substrate for supporting the processed substrate;
A step of conveying the carrier;
A process of performing processing on the processed substrate,
A method for producing a semiconductor package, wherein the supporting glass substrate is the supporting glass substrate according to any one of claims 1 to 8. - 加工処理が、加工基板の一方の表面に配線する処理を含むことを特徴とする請求項10に記載の半導体パッケージの製造方法。 The method for manufacturing a semiconductor package according to claim 10, wherein the processing includes processing for wiring on one surface of the processing substrate.
- 加工処理が、加工基板の一方の表面に半田バンプを形成する処理を含むことを特徴とする請求項10又は11に記載の半導体パッケージの製造方法。 12. The method of manufacturing a semiconductor package according to claim 10, wherein the processing includes a process of forming a solder bump on one surface of the processed substrate.
- 請求項10~12の何れかに記載の半導体パッケージの製造方法により作製されたことを特徴とする半導体パッケージ。 A semiconductor package manufactured by the method for manufacturing a semiconductor package according to any one of claims 10 to 12.
- 半導体パッケージを備える電子機器であって、
半導体パッケージが、請求項13に記載の半導体パッケージであることを特徴とする電子機器。
An electronic device including a semiconductor package,
An electronic device, wherein the semiconductor package is the semiconductor package according to claim 13.
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JPWO2017104514A1 (en) * | 2015-12-16 | 2018-10-04 | 日本電気硝子株式会社 | Support crystallized glass substrate and laminate using the same |
KR102584795B1 (en) | 2015-12-16 | 2023-10-05 | 니폰 덴키 가라스 가부시키가이샤 | Supported crystallized glass substrate and laminate using the same |
KR20180095513A (en) * | 2015-12-17 | 2018-08-27 | 니폰 덴키 가라스 가부시키가이샤 | Manufacturing method of support glass substrate |
JP2022025147A (en) * | 2015-12-17 | 2022-02-09 | 日本電気硝子株式会社 | Method of manufacturing glass support plate |
JPWO2017104513A1 (en) * | 2015-12-17 | 2018-10-04 | 日本電気硝子株式会社 | Manufacturing method of supporting glass substrate |
WO2017104513A1 (en) * | 2015-12-17 | 2017-06-22 | 日本電気硝子株式会社 | Method of manufacturing a glass support plate |
JP7268718B2 (en) | 2015-12-17 | 2023-05-08 | 日本電気硝子株式会社 | Manufacturing method of supporting glass substrate |
KR102588111B1 (en) | 2015-12-17 | 2023-10-12 | 니폰 덴키 가라스 가부시키가이샤 | Manufacturing method of supporting glass substrate |
KR20180098556A (en) | 2015-12-28 | 2018-09-04 | 에이지씨 가부시키가이샤 | Glass substrate, laminated substrate, laminate, and method of manufacturing semiconductor package |
US10882778B2 (en) | 2015-12-28 | 2021-01-05 | AGC Inc. | Glass substrate, laminated substrate, laminate, and method for producing semiconductor package |
Also Published As
Publication number | Publication date |
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TWI644881B (en) | 2018-12-21 |
JP6593669B2 (en) | 2019-10-23 |
JP2015078113A (en) | 2015-04-23 |
KR20160055104A (en) | 2016-05-17 |
TW201522269A (en) | 2015-06-16 |
CN105307993A (en) | 2016-02-03 |
CN112159100A (en) | 2021-01-01 |
KR102200850B1 (en) | 2021-01-11 |
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