WO2015033649A1 - Laser à cavité verticale émettant par la surface et son procédé de fabrication - Google Patents

Laser à cavité verticale émettant par la surface et son procédé de fabrication Download PDF

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Publication number
WO2015033649A1
WO2015033649A1 PCT/JP2014/067105 JP2014067105W WO2015033649A1 WO 2015033649 A1 WO2015033649 A1 WO 2015033649A1 JP 2014067105 W JP2014067105 W JP 2014067105W WO 2015033649 A1 WO2015033649 A1 WO 2015033649A1
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layer
high resistance
resistance region
current confinement
emitting laser
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PCT/JP2014/067105
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English (en)
Japanese (ja)
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哲郎 鳥塚
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株式会社村田製作所
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Priority to TW103127170A priority Critical patent/TW201511433A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/2054—Methods of obtaining the confinement
    • H01S5/2059—Methods of obtaining the confinement by means of particular conductivity zones, e.g. obtained by particle bombardment or diffusion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H01S5/18308—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] having a special structure for lateral current or light confinement
    • H01S5/18311—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] having a special structure for lateral current or light confinement using selective oxidation
    • H01S5/18313—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] having a special structure for lateral current or light confinement using selective oxidation by oxidizing at least one of the DBR layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H01S5/18308—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] having a special structure for lateral current or light confinement
    • H01S5/18322—Position of the structure
    • H01S5/1833—Position of the structure with more than one structure
    • H01S5/18333—Position of the structure with more than one structure only above the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H01S5/18308—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] having a special structure for lateral current or light confinement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H01S5/18308—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] having a special structure for lateral current or light confinement
    • H01S5/18322—Position of the structure
    • H01S5/18327—Structure being part of a DBR

Definitions

  • the present invention relates to a vertical cavity surface emitting laser and a method for manufacturing the same.
  • a vertical cavity surface emitting laser (VCSEL: Vertical Cavity Surface Emitting Laser) is a laser device that outputs laser light in a direction perpendicular to a substrate surface by forming an optical resonator in a direction perpendicular to the substrate surface.
  • VCSEL Vertical Cavity Surface Emitting Laser
  • a current confinement structure is formed in order to concentrate the current in the light emitting region.
  • Al oxidation confinement structure an opening structure formed by oxidizing the outer peripheral side of an AlAs (aluminum arsenic) layer (hereinafter referred to as “Al oxidation confinement structure”) is used (for example, Japanese Patent Laid-Open No. 2006-2006) (Refer to the third embodiment of JP-A-19679 (Patent Document 1)).
  • Al oxidation confinement structure for example, Japanese Patent Laid-Open No. 2006-2006
  • Patent Document 1 Patent Document 1
  • Patent Document 2 discloses a technique in which an ion implantation confinement structure is formed in a P-type semiconductor region by implanting protons (hydrogen ions) and then thermally annealed at a temperature of 500 ° C. to 700 ° C. Is disclosed. Protons attract P-type dopants such as nitrogen, carbon, zinc, and magnesium, so that protons remain after thermal annealing in the P-type semiconductor region, but hydrogen in non-doped regions such as the active layer is released.
  • protons hydrogen ions
  • the distribution in the substrate vertical direction of the high resistance region can be generally controlled by adjusting the dose amount of ions and the acceleration energy.
  • some implanted ions can reach the active layer.
  • the light output rapidly decreases because the defect grows due to non-radiative recombination at the defect.
  • Patent Document 2 hydrogen ions in the active layer can be released by annealing, so that the above-described decrease in reliability can be suppressed.
  • unstable hydrogen ions existing near the active layer may move to the active layer in accordance with the current injection operation during light emission. As a result, if a defect is formed in the active layer, reliability (life) is reduced.
  • the present invention has been made in consideration of the above problems, and an object thereof is to provide a highly reliable VCSEL while reducing parasitic capacitance.
  • a vertical cavity surface emitting laser includes a plurality of semiconductor layers stacked on a substrate.
  • the plurality of semiconductor layers include a first reflecting mirror layer, a second reflecting mirror layer, an active layer, and a current confinement layer.
  • the first reflecting mirror layer is formed of a semiconductor multilayer film having the first conductivity type.
  • the second reflecting mirror layer is formed of a semiconductor multilayer film having the second conductivity type at a position farther from the substrate than the first reflecting mirror layer.
  • the active layer is provided between the first reflecting mirror layer and the second reflecting mirror layer.
  • the current confinement layer is provided in the second reflecting mirror layer or between the second reflecting mirror layer and the active layer, and includes an oxidized portion and an unoxidized portion surrounded by the oxidized portion.
  • a high resistance region is formed by ion implantation in a region adjacent to the oxidized portion of the current confinement layer. When viewed from the direction perpendicular to the substrate, the high resistance region is separated from the unoxidized portion of the current confinement layer.
  • first and second conductivity types one of them is P-type and the other is N-type.
  • the parasitic capacitance can be reduced as compared with the case of the current confinement layer alone. Furthermore, since the high resistance region is separated from the non-oxidized portion of the current confinement layer, the implanted ions can be moved away from the current path, and the reliability deterioration due to the growth of defects can be suppressed.
  • the distribution shape of the high resistance region is a three-dimensional shape having through holes.
  • the through hole overlaps with the unoxidized portion of the current confinement layer.
  • the vertical cavity surface emitting laser further includes an electrode layer stacked on the surface of the second reflecting mirror layer on the side away from the substrate.
  • the high resistance region is formed at a position separated from the electrode layer.
  • the distance from the position farthest from the first reflector layer to the current confinement layer in the high resistance region is the current confinement from the position farthest from the first reflector layer in the second reflector layer. 2/3 or less of the distance to the layer.
  • the current flow from the electrode layer above the second reflecting mirror layer can be prevented from being hindered, so that an increase in element resistance can be suppressed.
  • the dimension of the cross-section of the through hole changes in a plurality of steps or continuously, and increases as the distance from the active layer increases.
  • current flow from the electrode layer above the second reflecting mirror layer can be prevented from being hindered, and an increase in element resistance can be suppressed.
  • the ion concentration implanted into the high resistance region is higher than the impurity concentration of the second reflecting mirror layer.
  • the resistance and insulation of the ion implantation region can be increased.
  • the high resistance region is formed in a region doped with an impurity of the second conductivity type among the plurality of semiconductor layers stacked on the substrate.
  • the above configuration can be realized by detaching ions implanted in the non-doped region by annealing to about 500 ° C. after ion implantation.
  • a method for manufacturing a vertical cavity surface emitting laser the step of forming a first reflecting mirror layer on a substrate by a semiconductor multilayer film having a first conductivity type, Forming a first cladding layer on the reflector layer; forming an active layer on the first cladding layer; forming a second cladding layer on the active layer; Forming a second reflecting mirror layer on the two cladding layers with a semiconductor multilayer film having the second conductivity type.
  • the step of forming the second reflecting mirror layer includes the step of forming a current confinement layer with a semiconductor film having the second conductivity type.
  • the vertical cavity surface emitting laser manufacturing method further includes the step of forming a high resistance region by increasing the resistance of a region adjacent to a part of the current confinement layer by ion implantation, and forming the high resistance region. Thereafter, the current confinement layer is oxidized from the peripheral side to form an oxidized portion and an unoxidized portion surrounded by the oxidized portion in the current confinement layer.
  • the high resistance region is separated from the unoxidized portion of the current confinement layer.
  • the above manufacturing method can provide a vertical cavity surface emitting laser with reduced parasitic capacitance and high reliability. Furthermore, since the implanted ions in the active layer can be released in the current confinement layer oxidation step performed after the ion implantation step, the reliability can be further improved.
  • FIG. 2 is a diagram schematically showing a cross-sectional structure along the line II-II in FIG. 1. It is the figure which expanded a part of FIG. It is a distribution map of Al composition of each layer of FIG.
  • FIG. 5 is a cross-sectional view schematically showing a multilayer epitaxial film in a VCSEL manufacturing process. It is sectional drawing which shows typically formation of a high resistance area
  • FIG. 1 is a plan view schematically showing the configuration of the VCSEL according to the first embodiment.
  • FIG. 2 is a diagram schematically showing a cross-sectional structure along the line II-II in FIG.
  • FIG. 3 is an enlarged view of a part of FIG. 2 and 3 are schematic diagrams, and the thickness of each layer in the drawings is not proportional to the actual thickness of the device.
  • the VCSEL 1 is disposed inside the substrate 10, the semiconductor multilayer reflector layers 11, 15, the clad layers 12, 14, the active layer 13, and the semiconductor multilayer reflector layer 15. It includes a current confinement layer 16 provided, a high resistance region 25 formed in a region from the semiconductor multilayer reflector layer 15 to the cladding layer 14, an anode electrode layer 19, and a cathode electrode layer 20.
  • a GaAs (gallium arsenide) semiconductor substrate exhibiting N-type conductivity is used as the substrate 10.
  • a cathode electrode layer (back electrode layer) 20 is formed on the back surface of the substrate 10.
  • a non-doped GaAs substrate exhibiting semi-insulating properties may be used as the substrate 10.
  • the cathode electrode layer 20 is formed on the surface of the DBR layer 11.
  • a semiconductor multilayer reflector (DBR: Distributed Bragg Reflector) layer 11 made of a compound semiconductor having N-type conductivity is formed on the substrate 10.
  • the DBR layer 11 includes, for example, a structure in which Al 0.15 Ga 0.85 As and Al 0.9 Ga 0.1 As are alternately stacked by an optical film thickness ⁇ / 4 ( ⁇ represents a wavelength).
  • Si silicon
  • Si is doped to give an N-type conductivity, and its concentration is, for example, 2 to 3 ⁇ 10 18 [cm ⁇ 3 ].
  • Si coordinates to a Ga (Al) site and easily becomes a donor.
  • Al X Ga (1-X) As (aluminum, gallium, arsenic) is a mixed crystal semiconductor of GaAs and AlAs.
  • Al composition (X) when the Al composition (X) is not specified, it may be described as AlGaAs.
  • the active region for generating laser light is formed on the DBR layer 11.
  • the active region includes the clad layers 12 and 14 and the active layer 13 having an optical gain sandwiched between the clad layers 12 and 14.
  • a multiple quantum well (MQW) in which a quantum well layer and a barrier layer are stacked in multiple layers is formed.
  • the active layer 13 is a non-doped region where impurities are not introduced.
  • the cladding layers 12 and 14 can be non-doped or partially doped depending on the design of the resistance value of the device.
  • a part of the cladding layers 12 and 14 in contact with the N-type and P-type DBR layers 11 and 15 are doped with impurities having the same conductivity type as the adjacent DBR layers 11 and 15.
  • An upper DBR layer 15 made of a compound semiconductor having a P-type conductivity is formed on the active region.
  • the upper DBR layer 15 and the lower DRB layer 11 constitute an optical resonator.
  • the DBR layer 15 is made of Al 0.15 Ga 0.85 As and Al 0.9 Ga 0.1 As alternately with an optical film thickness ⁇ / 4, for example, in the same manner as the DBR layer 11 on the lower layer side (substrate side).
  • C carbon
  • C is doped, and its concentration is, for example, 2 to 3 ⁇ 10 18 [cm ⁇ 3 ]. C is easily coordinated to the As site and becomes an acceptor.
  • the conductivity type may be reversed, the substrate 10 may be a P-type semiconductor substrate, the lower DBR layer 11 may be P-type, and the upper DBR layer 15 may be N-type.
  • the first and second conductivity types are described, one of the first and second conductivity types is P-type, and the other is N-type.
  • a current confinement layer 16 is formed in a part of the upper DBR layer 15 to efficiently inject current into the active region and bring about a lens effect.
  • the current confinement layer 16 has an unoxidized portion 18 at the central portion and an oxidized portion 17 of a substantially insulator around the central portion.
  • the current confinement layer 16 is selectively oxidized from the surroundings in a heated steam atmosphere. Since only the unoxidized portion 18 in the central portion serves as a current path, current can be efficiently injected into the active region.
  • a high resistance region 25 is provided adjacent to the oxidized portion 17 of the current confinement layer 16.
  • the high resistance region 25 is formed by implanting ions that can increase the resistance of P-type AlGaAs (GaAs) or N-type AlGaAs (GaAs), such as hydrogen ions (protons), boron ions, or oxygen ions. .
  • ions that can increase the resistance of P-type AlGaAs (GaAs) or N-type AlGaAs (GaAs), such as hydrogen ions (protons), boron ions, or oxygen ions.
  • the distribution in the substrate surface direction of the high resistance region 25 can be controlled with high accuracy by a mask shape such as a photoresist, and the distribution in the substrate vertical direction can be generally controlled by adjusting the dose amount of ions and the acceleration energy. .
  • annealing is performed to about 500 ° C. to 700 ° C. after the ion implantation to release the hydrogen ions in the non-doped region such as the active layer 13 while retaining the hydrogen ions in the P-type doped region 31. be able to.
  • the high resistance region 25 is formed in the P-type doped region 31.
  • the distribution shape of the high resistance region 25 is a three-dimensional shape having through holes, and specifically, a donut shape (torus shape).
  • the through hole overlaps with the unoxidized portion 18 of the current confinement layer 16, and the cross-sectional dimension b of the through hole is larger than the dimension a of the unoxidized portion 18 of the current confinement layer 16. large. Accordingly, when viewed from the direction perpendicular to the substrate 10, the high resistance region 25 is separated from the unoxidized portion 18 of the current confinement layer 16.
  • the high resistance region 25 Due to the arrangement of the high resistance region 25 as described above, even if the high resistance region 25 reaches the vicinity of the active layer 13 or the inside of the active layer 13, the current path is limited by the oxidation portion 17 of the current confinement layer 16. The implanted ions can be moved away from this current path. Therefore, the progress of defects to the active layer 13 can be suppressed, and the reliability of the VCSEL can be improved.
  • the high resistance region 25 is separated from the anode electrode layer 19. More specifically, the distance B from the position farthest from the lower DBR layer 11 in the high resistance region 25 to the current confinement layer 16 is the farthest from the lower DBR layer 11 in the upper DBR layer 15. It is desirable that the distance A is about 1/3 to 2/3 of the distance A from the position to the current confinement layer 16. With the above arrangement, the flow of current from the anode electrode layer 19 can be prevented from being hindered, and an increase in element resistance can be prevented.
  • a moisture-proof insulating film 21 (also referred to as a moisture-resistant film) is formed on an epitaxial multilayer film having a mesa post structure. An opening is formed in the insulating film 21 above the mesa post so that the surface of the DBR layer 15 is exposed.
  • An anode electrode layer 19 (ring electrode layer) is connected to the exposed surface of the DBR layer 15.
  • a pad electrode 23 for bonding is connected to the anode electrode layer 19.
  • a polyimide pattern 22 is provided between the pad electrode 23 and the DBR layer 11 in order to reduce parasitic capacitance.
  • Al composition distribution 4 is a distribution diagram of the Al composition of each layer in FIG.
  • the vertical axis of FIG. 4 indicates the Al content (X) of Al X Ga (1-X) As, and the horizontal axis indicates the depth direction of the VCSEL in arbitrary units (AU).
  • a low refractive index layer having a high Al content and a high refractive index layer having a low Al content are alternately laminated.
  • the region adjacent to the cladding layers 12 and 14 in the DBR layers 11 and 15 corresponds to the first low refractive index layer.
  • the current confinement layer 16 is formed at a position farthest from the active layer 13 in the first low refractive index layer of the DBR layer 15.
  • the current confinement layer 16 may be disposed on a lower layer side (for example, a position adjacent to the clad layer 14) in the first low refractive index layer.
  • the P-type doped region 31 extends from the DBR layer 15 to a part of the cladding layer 14.
  • a high resistance region 25 is formed in the P-type doped region 31.
  • FIGS. 5 to 12 are cross-sectional views schematically showing a VCSEL manufacturing process.
  • FIG. 13 is a flowchart showing a VCSEL manufacturing process.
  • a manufacturing method of the VCSEL 1 shown in FIGS. 1 to 4 will be described with reference to FIGS.
  • multilayer epitaxial films 11 to 16 are formed on a semiconductor substrate 10 (here, an N-type GaAs substrate).
  • a method such as MOCVD (Metal Organic Chemical Vapor Deposition) or MBE (Molecular Beam Epitaxy) is suitable.
  • the DBR layer 11 showing the N-type conductivity is first formed on the GaAs substrate 10 (step S100 in FIG. 13).
  • the DBR layer 11 is formed in 30 to 40 layers with a pair of optical film thicknesses such that the high refractive region and the low refractive region are each ⁇ / 4.
  • about 2 ⁇ 10 18 [cm ⁇ 3 ] is introduced with Si as an impurity.
  • an active layer 13 including a quantum well (QW) is formed on the N-type DBR layer 11 so as to be sandwiched between the cladding layers 12 and 14 (steps S105 to S115 in FIG. 13).
  • the thickness and material of the active layer 13 and the cladding layers 12 and 14 can be appropriately adjusted according to the oscillation wavelength.
  • GaAs can be used as the material of the active layer 13 and the oscillation wavelength can be adjusted to 850 nm.
  • P-type DBR layers 15 and 15A are formed on the cladding layer 14 (steps S120 to S130 in FIG. 13). Similarly to the N-type DBR layer 11, the P-type DBR layers 15 and 15A are formed to have about 20 layers with a pair of optical film thicknesses such that the high refractive region and the low refractive region are each ⁇ / 4.
  • about 2 ⁇ 10 18 [cm ⁇ 3 ] is introduced with C as an impurity.
  • the current confinement layer 16 is formed in the first low refractive index layer in contact with the cladding layer 14.
  • the Al composition X is increased to 0.95 or more, whereby an Al x Ga (1-x) As layer (however, 0.95 ⁇ X ⁇ 1) is formed while introducing C (carbon) of about 2 to 3 ⁇ 10 18 [cm ⁇ 3 ] (step S125 in FIG. 13).
  • the current confinement layer 16 is desirably 40 nm or less in order to suppress the influence of the distortion. As described with reference to FIG. 4, the current confinement layer 16 may be formed at a position near the upper layer or at a position near the lower layer in the first low refractive index layer.
  • step S135 in FIG. 13 After the formation of multilayer epitaxial films 11 to 16, hydrogen ions are implanted using a photoresist as a mask (step S135 in FIG. 13). Thereby, the high resistance region 25 is formed.
  • the epitaxial multilayer film formed on substrate 10 as described above is processed into a mesa post pattern of, for example, ⁇ 30 ⁇ m in order to form a current confinement structure (step S140 in FIG. 13).
  • the mesa post pattern is formed by photolithography and dry etching techniques. Dry etching is performed to a depth at which the lower DBR layer 11 is exposed.
  • the substrate with the epitaxial multilayer film processed into the mesa post pattern is heated to 450 ° C. or higher in a water vapor atmosphere, so that the oxidation proceeds selectively from the outer periphery of the current confinement layer 16.
  • the oxidized portion 17 is formed (step S145 in FIG. 13).
  • the oxidation time is adjusted so that the unoxidized portion 18 in the central portion becomes ⁇ 10 ⁇ m.
  • a silicon nitride film or a silicon oxide film is formed (step S150 in FIG. 13).
  • a technique such as CVD or sputtering can be applied.
  • an opening for the contact electrode layer is formed by a technique of photolithography and dry etching (step S155 in FIG. 13).
  • a P-type contact electrode layer (anode electrode layer) 19 is formed in the opening at the top of the mesa post, for example, by photolithography and vapor deposition (step S160 in FIG. 13).
  • a laminated film made of Ti (titanium), Pt (platinum), and Au (gold) can be used.
  • polyimide pattern 22 is formed for the purpose of capacity reduction under pad electrode 23 (step S165 in FIG. 13).
  • a pad electrode 23 connected to the P-type contact electrode layer 19 is formed by, for example, a technique of photolithography and sputtering film formation (step S170 in FIG. 13).
  • the back electrode layer 20 is formed (step S175 in FIG. 13).
  • the back electrode layer 20 for example, a laminated film made of Au, Ge, and Ni can be used.
  • the VCSEL 1 is completed by performing an annealing process (step S180 in FIG. 13) for making an ohmic contact between the electrode layers 19 and 20 and the semiconductor layer.
  • the high resistance region 25 thicker than the thickness of the current confinement layer 16 made of an oxide film is formed by ion implantation adjacent to the oxidation portion 17 of the current confinement layer 16.
  • the parasitic capacitance can be reduced as compared with the case of the current confinement layer 16 alone. This enables high-speed modulation.
  • the high resistance region 25 does not overlap the unoxidized portion 18 of the current confinement layer 16, but is spaced apart from the unoxidized portion 18. Can be kept away from the current path. This makes it difficult for implanted ions to move and grow defects, thereby reducing the possibility that the reliability of the VCSEL is impaired.
  • the concentration of implanted ions needs to be higher than the impurity concentration of the DBR layer 15.
  • Implanted ions are regarded as defects, a defect level is formed, and carriers (electrons or holes) are trapped in the defect level. Therefore, when the inflow ion concentration is higher than the P-type dope concentration, the resistance of the ion implantation region is increased.
  • the resistance is increased by ion implantation up to the top of the DBR layer 15, the current flow from the anode electrode layer 19 is hindered, resulting in an increase in device resistance. Therefore, it is desirable that the high resistance region 25 be separated from the anode electrode layer 19, and more specifically, the distance from the top of the high resistance region 25 to the current confinement layer 16 is the current from the top of the DBR layer 15. It is desirable that the distance to the constriction layer 16 is about 1/3 to 2/3.
  • the implanted ions in the depth direction varies, if ions are implanted up to the current confinement layer 16, there is a possibility that the ions are implanted into the active layer 13 as well. This may cause a decrease in reliability. Therefore, it is desirable to perform annealing at about 500 ° C. for detachment of implanted ions from the active layer 13. In this case, if the ion implantation step is performed before the heating water vapor oxidation step of the current confinement layer 16, it is convenient that the implanted ions are also released from the active layer 13 at the time of the heat water vapor oxidation of the current confinement layer 16. Good.
  • the high resistance region 25 has a donut shape
  • the shape of the high resistance region 25 is not limited thereto.
  • the high resistance region 25 overlaps with a part of the oxidized portion 17 of the current confinement layer 16, but any shape may be used as long as it is separated from the unoxidized portion 18.
  • the cross-sectional shape of the through hole may be a polygon such as a quadrangle, or the high resistance region 25 may be divided into a plurality.
  • the current confinement layer 16 is formed inside the first low refractive index layer constituting the DBR layer 15. However, the current confinement layer 16 is located closer to the active layer 13 such as the inside of the cladding layer 14. It is also possible to arrange. Therefore, more generally speaking, the current confinement layer 16 is disposed in the DBR layer 15 or between the DBR layer 15 and the active layer 13.
  • FIG. 14 is a cross-sectional view schematically showing the configuration of the VCSEL according to the second embodiment.
  • the configuration of the VCSEL 2 shown in FIG. 14 is different from the VCSEL 1 shown in FIG. 3 in the distribution shape of the high resistance region 25. Since the other points are the same as those in FIG. 3, the same reference numerals are given to the same or corresponding parts, and the description will not be repeated.
  • the distribution shape of high resistance region 25 is a three-dimensional shape having a through hole as in the case of FIG. 3, and more specifically, a donut shape (torus shape).
  • the dimension of the cross-section of the through hole changes in a plurality of steps (in the case of FIG. 14, three steps) and increases as the distance from the active layer 13 increases.
  • This distributed shape can be realized, for example, by repeating ion implantation using a plurality of masks having different dimensions of the shielding portions corresponding to the through holes.
  • the distribution shape of the high resistance region 25 as described above prevents the current path from the anode electrode layer 19 to the unoxidized portion 18 of the current confinement layer 16 from being further hindered, so that an increase in device resistance can be further suppressed.
  • FIG. 15 is a cross-sectional view schematically showing the configuration of the VCSEL according to the third embodiment.
  • the configuration of the VCSEL 3 shown in FIG. 15 differs from the VCSEL 2 shown in FIG. 14 in that the cross-sectional dimension of the through hole of the high resistance region 25 continuously changes and becomes larger as the distance from the active layer 13 increases.
  • the current path from the anode electrode layer 19 to the unoxidized portion 18 of the current confinement layer 16 is further prevented, so that an increase in element resistance can be further suppressed.
  • Electrode layer anode electrode layer
  • 20 back electrode cathode electrode layer
  • 21 moisture-resistant film insulating film
  • 22 polyimide pattern 23 pad electrode, 25 high resistance region, 30 N-type doped region, 31 P-type doped region.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Geometry (AREA)
  • Semiconductor Lasers (AREA)

Abstract

Cette invention concerne un laser à cavité verticale émettant par la surface (1) qui comporte une première couche de miroir réfléchissant (11), une seconde couche de miroir réfléchissant (15), une couche active (13) et une couche de limitation de courant (16). La couche de limitation de courant (16) comprend une partie oxydée (17) et une partie non oxydée (18) qui est entourée par la partie oxydée (17). Une région à haute résistance (25) est formée dans une région adjacente à la partie oxydée (17) de la couche de limitation de courant (16) au moyen d'une implantation ionique. La région à haute résistance (25) est séparée de la partie non oxydée (18) de la couche de limitation de courant (16), quand on regarde dans la direction perpendiculaire à un substrat (10).
PCT/JP2014/067105 2013-09-03 2014-06-27 Laser à cavité verticale émettant par la surface et son procédé de fabrication WO2015033649A1 (fr)

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JPWO2018096850A1 (ja) * 2016-11-24 2019-10-17 ソニー株式会社 面発光レーザおよび電子機器
US10916917B2 (en) 2018-10-25 2021-02-09 Sumitomo Electric Industries, Ltd. Method of manufacturing surface emitting laser
US10998697B2 (en) 2018-10-25 2021-05-04 Sumitomo Electric Industries, Ltd. Method of manufacturing surface emitting laser
CN113013728A (zh) * 2021-02-26 2021-06-22 武汉仟目激光有限公司 垂直腔面发射激光器以及离子注入方法
US11522343B2 (en) 2019-06-28 2022-12-06 Sumitomo Electric Industries, Ltd. Surface-emitting laser and method of manufacturing the same
US11539188B2 (en) 2019-07-25 2022-12-27 Sumitomo Electric Industries, Ltd. Surface emitting laser and method of manufacturing the same

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JPH10256669A (ja) * 1997-03-14 1998-09-25 Mitsubishi Electric Corp 光変調器集積半導体レーザダイオード
US20030123514A1 (en) * 2001-12-28 2003-07-03 Cox James A. Vertical cavity surface emitting laser having a gain guide aperture interior to an oxide confinement layer
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JP2005044964A (ja) * 2003-07-28 2005-02-17 Ricoh Co Ltd 面発光レーザ素子および面発光レーザアレイおよび面発光レーザモジュールおよび電子写真システムおよび光インターコネクションシステムおよび光通信システムおよび面発光レーザ素子の製造方法
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JPH10256669A (ja) * 1997-03-14 1998-09-25 Mitsubishi Electric Corp 光変調器集積半導体レーザダイオード
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CHIH-HAO CHANG ET AL.: "Parasitics and Design Considerations on Oxide-Implant VCSELs", IEEE PHOTONICS TECHNOLOGY LETTERS, vol. 13, no. 12, December 2001 (2001-12-01), pages 1274 - 1276 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2018096850A1 (ja) * 2016-11-24 2019-10-17 ソニー株式会社 面発光レーザおよび電子機器
US10916917B2 (en) 2018-10-25 2021-02-09 Sumitomo Electric Industries, Ltd. Method of manufacturing surface emitting laser
US10998697B2 (en) 2018-10-25 2021-05-04 Sumitomo Electric Industries, Ltd. Method of manufacturing surface emitting laser
US11522343B2 (en) 2019-06-28 2022-12-06 Sumitomo Electric Industries, Ltd. Surface-emitting laser and method of manufacturing the same
US11539188B2 (en) 2019-07-25 2022-12-27 Sumitomo Electric Industries, Ltd. Surface emitting laser and method of manufacturing the same
CN113013728A (zh) * 2021-02-26 2021-06-22 武汉仟目激光有限公司 垂直腔面发射激光器以及离子注入方法

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