WO2015029462A1 - 電力増幅装置、及び電力増幅装置の制御方法 - Google Patents
電力増幅装置、及び電力増幅装置の制御方法 Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
- H03F1/0244—Stepped control
- H03F1/025—Stepped control by using a signal derived from the input signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0294—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using vector summing of two or more constant amplitude phase-modulated signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
- H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/222—A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/387—A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/20—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F2203/21—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F2203/211—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
- H03F2203/21103—An impedance adaptation circuit being added at the input of a power amplifier stage
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/20—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F2203/21—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F2203/211—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
- H03F2203/21139—An impedance adaptation circuit being added at the output of a power amplifier stage
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/20—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F2203/21—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F2203/211—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
- H03F2203/21163—An output signal dependant signal being measured by power measuring, e.g. by an inductive coupler, at the output of a power amplifier
Definitions
- Embodiments described herein relate generally to a power amplification device and a method for controlling the power amplification device.
- a Doherty amplifier that combines a carrier amplifier and a peak amplifier is used as a power amplification device that amplifies input power with high efficiency.
- the average output power level may be lowered (when the power is reduced).
- the power amplifying apparatus is operated in a state where the power efficiency is lowered from the peak point.
- the problem to be solved by the present invention is to provide a power amplifying device capable of maintaining high efficiency even in the case of a power reducing operation, and a method for controlling the power amplifying device.
- the power amplification device includes a Doherty amplifier, a voltage adjustment unit, and a central processing unit.
- the Doherty amplifier has a carrier amplifier and a peak amplifier, and outputs an output signal obtained by amplifying an input signal by the amplifiers and synthesizing the amplified signals.
- the voltage adjustment unit supplies a control voltage to each of the carrier amplifier and the peak amplifier.
- the central processing unit has a table that is determined according to the operation at the average output power of the Doherty amplifier, and stores control voltage value information for each carrier amplifier and peak amplifier constituting the Doherty amplifier.
- the central processing unit controls the voltage adjustment unit to supply the control voltage based on the control voltage value information stored in the table for each carrier amplifier and peak amplifier.
- the control method of the power amplifying device of the embodiment is a control method of the power amplifying device having a Doherty amplifier, a voltage adjusting unit, and a central processing unit.
- the Doherty amplifier has a carrier amplifier and a peak amplifier, and amplifies an input signal by each amplifier and outputs an output signal obtained by synthesizing the amplified signal.
- the voltage adjustment unit supplies a control voltage to each of the carrier amplifier and the peak amplifier.
- the central processing unit has a table that is determined according to the operation at the average output power of the Doherty amplifier, and stores control voltage value information for each carrier amplifier and peak amplifier constituting the Doherty amplifier.
- the central processing unit controls the voltage adjustment unit to supply a control voltage based on the control voltage stored in the table for each carrier amplifier and peak amplifier.
- the figure which shows the power efficiency of the power amplification apparatus 200 shown in FIG. The figure which shows the structure of the power amplification apparatus 100 of embodiment.
- FIG. 1 is a diagram showing a configuration of a power amplifying apparatus 200 using a general Doherty amplifier.
- a power amplifying apparatus 200 shown in FIG. 1 includes an input terminal 1, a matching circuit 4, a carrier amplifier 5, a matching circuit 6, a ⁇ / 4 line 7, a ⁇ / 4 line 8, a matching circuit 9, a peak amplifier 10, a matching circuit 11, A ⁇ / 4 line 13 and an output terminal 14 are provided.
- the input signal 2 input to the input terminal is input to the matching circuit 4 via the branch point 3.
- the matching circuit 4 is a circuit for matching the input signal 2 with the input side of the amplifying element constituting the carrier amplifier 5.
- the carrier amplifier 5 amplifies the input signal 2 and outputs it regardless of the power level of the input signal 2 because the amplifying element constituting it is biased from class A to class AB or class B.
- the matching circuit 6 is a circuit that matches the output of the amplifying element constituting the carrier amplifier 5 and the output of the carrier amplifier 5.
- the ⁇ / 4 line 7 functions as a circuit for impedance-converting the output of the carrier amplifier 5 when the input signal 2 is at a low power level.
- the input signal 2 branched at the branch point 3 is delayed by 90 degrees by the ⁇ / 4 line 8 and input to the matching circuit 9.
- the matching circuit 9 is a circuit for matching the input signal 2 whose phase is delayed by 90 degrees with the input side of the amplifying element constituting the carrier amplifier 5. Since the amplifying element constituting the peak amplifier 10 is biased to class C, the peak amplifier 10 becomes inactive when the input signal 2 is at a low power level, and becomes active when the input signal 2 is at a high power level, and amplifies the input signal 2. Output.
- the matching circuit 11 is a circuit that matches the output of the amplification element constituting the peak amplifier 10 and the output of the peak amplifier 10.
- the output of the ⁇ / 4 line 7 and the output of the matching circuit 11 are combined at the combining point 12.
- the ⁇ / 4 line 13 performs impedance conversion to match the output synthesized at the synthesis point 12 with the impedance of the load connected to the output terminal 14.
- the impedance-converted signal is output as an output signal 15 from the output terminal 14.
- linear power amplification is performed only by the carrier amplifier 5 when the input power of the input signal 2 is lower than a predetermined input power level in the input / output power characteristics.
- a linear power amplifying operation is performed by the peak amplifier 10 in addition to the carrier amplifier 5. .
- FIG. 2 is a diagram showing the power efficiency of the power amplifying apparatus 200 shown in FIG.
- the horizontal axis represents the output power level of the output signal 15, and the vertical axis represents the power efficiency.
- the carrier amplifier 5 and the peak amplifier 10 are in a state of being amplified at the saturation power level. In this case, the power efficiency 30 reaches a peak.
- the power amplifying apparatus 200 shown in FIG. 1 only the carrier amplifier 5 is used at an output level in which the output power level of the output signal 15 is backed off by a predetermined level from the saturated output power level 31 (this point is referred to as a turning point 35).
- the power efficiency 30 reaches a peak.
- the range of the output power level with high power efficiency can be increased.
- the definition of back-off is the difference between the average output power and saturation output power of the amplifier.
- the PAR Peak to Average Ratio
- the power amplification device can be used with high efficiency.
- the power amplifying apparatus 200 shown in FIG. 1 is used for a broadcast power amplifying apparatus, there is a case where the average output power level is lowered in actual operation (when the power reducing operation is performed). In this case, there is a problem that the power amplifying apparatus 200 is operated in a state where the power efficiency is lowered in the direction of the arrow in FIG. 2, that is, from a point where the power efficiency reaches a peak (for example, point 38 shown in FIG. 2). It was.
- FIG. 3 is a diagram illustrating a configuration of the power amplifying device 100 according to the embodiment.
- the power amplifying apparatus 100 of the embodiment includes a central processing unit (CPU unit) 21, an output monitor circuit 22, a voltage adjustment circuit 23 (voltage adjustment unit), and a voltage adjustment circuit. 24 (voltage adjustment unit).
- the central processing unit 21 acquires the average output power level of the output signal 15 in the power amplification device 100 via the output monitor circuit 22.
- the central processing unit 21 converts the control voltage applied by the voltage adjusting circuit 23 and the voltage adjusting circuit 24 to the amplifying element constituting the carrier amplifier 5 and the amplifying element constituting the peak amplifier 10 with this average output power level.
- the voltage adjustment circuit 23 converts the voltage level of the drain power source into a control voltage level determined by the central processing unit 21, and controls the converted voltage (control voltage) for the amplification elements constituting the carrier amplifier 5. Apply to terminal.
- the voltage adjustment circuit 24 converts the voltage level of the drain power source into a control voltage level determined by the central processing unit 21, and controls the converted voltage (control voltage) of the amplification elements constituting the peak amplifier 10. Apply to terminal.
- the drain voltage of each of the carrier amplifier 5 and the peak amplifier 10 can be set independently according to the average output voltage level of the output signal 15. Yes.
- the reason for controlling the drain voltages of the carry amplifier 5 and the peak amplifier 10 separately is as follows. This is because if the Doherty amplifier is a symmetric Doherty amplifier, individual differences between devices (power amplification elements) are corrected. Note that the symmetric Doherty amplifier is a Doherty amplifier that uses two amplifiers (carrier amplifier 5 and peak amplifier 10) having the same output characteristics and uses the same configuration for the matching circuit. In addition, if the Doherty amplifier is an asymmetric Doherty amplifier, the voltage reduction characteristics of the peak amplifier and the carrier amplifier are often different.
- the asymmetric Doherty amplifier is, for example, a Doherty amplifier having a configuration in which a plurality of peak amplifiers 10 are connected in parallel. As another example of the asymmetric Doherty amplifier, there is a Doherty amplifier that uses different types of power amplification elements in the peak amplifier and the carrier amplifier.
- an amplifying element is configured by a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), for example.
- the carrier amplifier 5 has input / output characteristics in which the saturation power level of the output signal of the carrier amplifier 5 decreases when the drain voltage (control voltage) applied to the drain terminal (control terminal) of the amplifying element decreases.
- the amplifying element is constituted by, for example, a MOSFET.
- the peak amplifier 10 has input / output characteristics in which the saturation power level of the output signal of the peak amplifier 10 decreases when the drain voltage applied to the drain terminal of the amplifier element decreases.
- the central processing unit 21 has a table that stores control voltages applied to the carrier amplifier 5 and the peak amplifier 10.
- a control voltage hereinafter referred to as control voltage Vd1
- control voltage Vd2 to be stored is stored.
- the following values are stored as the control voltages Vd1 and Vd2 according to the average output power level.
- control voltages Vd1_1 and Vd2_1 corresponding to the average output power of the output signal 15 in the rated operation of the power amplifying apparatus 100 are stored.
- the table included in the central processing unit 21 is a control in which the average output power of the output signal 15 in the power reducing operation of the power amplifying apparatus 100 and the control voltages Vd1_2 and Vd2_2 (control voltage value information) are paired.
- a plurality of sets of voltages are stored in advance in association with each other.
- Each set of control voltages is determined by experiment to correspond to a plurality of average output powers. For example, control voltages Vd1_2 and Vd2_2 corresponding to an average output power level of 200 W (watts) and control voltages Vd1_3 and Vd2_3 corresponding to an average output power level of 180 W are stored in the table in association with the average output power.
- FIG. 4 is a diagram showing the power efficiency of the power amplifying apparatus 100 shown in FIG.
- the horizontal axis represents the output power level of the output signal 15, and the vertical axis represents the power efficiency.
- the power efficiency 40 a indicated by a broken line indicates the power efficiency in the rated operation of the power amplifying apparatus 100.
- the power efficiency 40a there is a turning point where the power efficiency 40a reaches a peak at a point where the back-off amount, for example, 8 dB, is lowered from the saturated output power level 41a. Since this turning point is the average output power level 44a in the rated operation of the power amplifying apparatus 100, high-efficiency operation is possible.
- the power level of the input signal 2 is input at a lower power level than the rated operation.
- An average output power level of the output signal 15 measured by the output monitor circuit 22 is input to the central processing unit 21.
- the central processing unit 21 reads a set of control voltages in the reduction operation corresponding to the average output power level from a plurality of sets of control voltages stored in the table. For example, if the average output power level is 200 W, control voltages Vd1_2 and Vd2_2 corresponding to 200 W are read from the table.
- the central processing unit 21 controls the voltage adjustment circuits 23 and 24 to apply the control voltage to the carrier amplifier 5 and the peak amplifier 10. Since the drain voltages applied to the carrier amplifier 5 and the peak amplifier 10 are different in a state where this control voltage is applied, the turning point indicated by a point 45 in FIG. 4 and the back-off value can be matched.
- the power efficiency in the power reduction operation of the power amplifying apparatus 100 is the power efficiency 40 indicated by the solid line in the power efficiency shown in FIG. That is, the power amplifying apparatus 100 can perform the power reducing operation while setting the average output power at the turning point 45 at which the power efficiency reaches a peak.
- the power amplifying apparatus 200 does not have a configuration in which a voltage is individually applied by the carrier amplifier 5 and the peak amplifier 10 during the reduction operation. Therefore, referring to FIG.
- the power amplifying apparatus 200 when the power reducing operation is performed (for example, when the broken line 44 is operated as the average output power level), the power amplifying apparatus 200 is around the point 48 in the power efficiency 40 a indicating the power efficiency of the rated operation. Will work with. For this reason, the power reducing operation is performed in a state where the power efficiency is low.
- the power efficiency in the power reducing operation is the power efficiency 40 shown in FIG. 4 as described above. Therefore, the output power level at the turning point 45 (broken line 44) can be operated as the average output power level, and the operation can be performed with high power efficiency, that is, with high efficiency.
- control voltages Vd1_1 and Vd2_1 stored in the table are set to substantially the same voltage. This is because the back-off setting can be set to 8 dB, for example, by making the power amplification device 100 asymmetrical Doherty.
- the control voltages Vd1_1 and Vd2_1 may be set to different values when the output power-power efficiency characteristic at the turning point due to asymmetric Doherty is finely adjusted in rated operation.
- DESCRIPTION OF SYMBOLS 100,200 ... Power amplification apparatus 1 ... Input terminal, 2 ... Input signal, 4, 6, 9, 10 ... Matching circuit, 5 ... Carrier amplifier, 7, 8 ... ⁇ / 4 line, 10 ... Peak amplifier, 13 ... ⁇ / 4 line, 14 ... output terminal, 15 ... output signal, 21 ... central processing unit, 22 ... output monitor circuit, 23, 24 ... voltage adjustment circuit
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Abstract
Description
本発明が解決しようとする課題は、減力動作する場合においても高効率を維持することができる電力増幅装置、及び電力増幅装置の制御方法を提供することである。
図2に示すように、出力電力レベルが飽和出力電力レベル31の場合、キャリアアンプ5とピークアンプ10とが飽和電力レベルで増幅する状態となる。この場合に電力効率30がピークとなる。一方、図1に示す電力増幅装置200では、出力信号15の出力電力レベルが飽和出力電力レベル31から所定レベルだけバックオフした出力レベル(この点を転換点35とする)では、キャリアアンプ5のみが飽和電力レベルで増幅する状態となり、ピークアンプ10は増幅していない状態となる。この場合も電力効率30はピークとなる。このように、図1に示す電力増幅装置200では、電力効率がピークとなる出力電力レベルが2箇所あるため、電力効率が高い出力電力レベルの範囲を大きくできる。ここで、バックオフの定義は、増幅器の平均出力電力と飽和出力電力の差である。
図3は、実施形態の電力増幅装置100の構成を示す図である。
なお、図3において、図1に示す電力増幅装置200と同一の部分には同一の符号を付し、その説明を省略する。
実施形態の電力増幅装置100は、図1に示す電力増幅装置200に加えて、中央演算処理部(CPU部)21、出力モニタ回路22、電圧調整回路23(電圧調整部)、及び電圧調整回路24(電圧調整部)を備える。
中央演算処理部21は、電力増幅装置100における出力信号15の平均出力電力レベルを、出力モニタ回路22を介して取得する。そして、中央演算処理部21は、キャリアアンプ5を構成する増幅素子と、ピークアンプ10を構成する増幅素子とへ電圧調整回路23及び電圧調整回路24が印加する制御電圧を、この平均出力電力レベルに応じて決定する。
電圧調整回路23は、ドレイン電源の電圧レベルを、中央演算処理部21が決定する制御電圧のレベルに変換して、変換後の電圧(制御電圧)を、キャリアアンプ5を構成する増幅素子の制御端子へ印加する。
電圧調整回路24は、ドレイン電源の電圧レベルを、中央演算処理部21が決定する制御電圧のレベルに変換して、変換後の電圧(制御電圧)を、ピークアンプ10を構成する増幅素子の制御端子へ印加する。このように、実施形態の電力増幅装置100では、キャリアアンプ5、及びピークアンプ10各々のドレイン電圧を、出力信号15の平均出力電圧レベルに応じて独立に設定することが可能な構成となっている。
ドハティアンプが対称ドハティアンプであれば、デバイス(電力増幅素子)の個体差を補正するためである。なお、対称ドハティアンプとは、同一の出力特性を有するアンプを2つ(キャリアアンプ5、及びピークアンプ10)用い、整合回路も同一の構成を用いたドハティアンプである。
また、ドハティアンプが非対称ドハティアンプであれば、ピークアンプ、キャリアンプの減電圧特性が異なる場合が多いためである。なお、非対称ドハティアンプとは、例えば、ピークアンプ10を複数個並列接続する構成を有するドハティアンプである。非対称ドハティアンプの他の例として、ピークアンプとキャリアンプとにおいて異なる種類の電力増幅素子を使用しているドハティアンプなどがある。
ピークアンプ10は、増幅素子が、例えばMOSFETにより構成される。ピークアンプ10は、増幅素子のドレイン端子に印加されるドレイン電圧が下がった場合、ピークアンプ10の出力信号が有する飽和電力レベルが下がる入出力特性を有している。
まず、電力増幅装置100の定格動作での出力信号15の平均出力電力に対応した制御電圧Vd1_1、Vd2_1が記憶されている。
図4に示す電力効率のうち、破線で示す電力効率40aは、電力増幅装置100の定格動作における電力効率を示している。電力効率40aにおいて、飽和出力電力レベル41aからバックオフ分、例えば8dB下がったポイントにおいて、電力効率40aがピークとなっている転換点がある。この転換点が電力増幅装置100の定格動作における平均出力電力レベル44aであるので、高効率動作が可能となっている。
中央演算処理部21は、テーブルに記憶された制御電圧の複数の組から、この平均出力電力レベルに対応する、減力動作での一組の制御電圧を読み出す。例えば、平均出力電力レベルが200Wであれば、200Wに対応する制御電圧Vd1_2、Vd2_2が、テーブルから読み出される。中央演算処理部21は、電圧調整回路23、24を制御して、この制御電圧をキャリアアンプ5、及びピークアンプ10に印加させる。この制御電圧が印加された状態で、キャリアアンプ5とピークアンプ10に印加されるドレイン電圧が別々になるため、図4において点45で示す転換点とバックオフの値とを合わせることができる。
例えば、電力増幅装置200は、本実施形態と異なり、減力動作時にキャリアアンプ5とピークアンプ10とで個別に電圧を印加する構成を有さない。そのため、図4を参照すると、電力増幅装置200では、減力動作させる場合(例えば、破線44を平均出力電力レベルとして動作させる場合)、定格動作の電力効率を示す電力効率40aにおけるポイント48のあたりで動作することになる。そのため、電力効率の低い状態で減力動作することになってしまう。
これに対して、本実施形態の電力増幅装置100では、減力動作における電力効率は、上述の様に、図4に示す電力効率40である。そのため、転換点45における出力電力レベル(破線44)を平均出力電力レベルとして動作させることができ、電力効率の高い、すなわち高効率で動作させることができる。
例えば、テーブルに記憶される制御電圧Vd1_1、及びVd2_1は、ほぼ同じ電圧に設定されている。なぜなら、バックオフの設定は、電力増幅装置100を非対称ドハティ化することにより、例えば8dBに設定できるためである。ただし、定格動作において、非対称ドハティ化による転換点における出力電力-電力効率特性を微調整する場合などは、制御電圧Vd1_1、及びVd2_1は互いに異なる値に設定されていてもよい。
Claims (4)
- キャリアアンプとピークアンプとを有し、入力信号を前記各アンプにより増幅して増幅後の信号を合成した出力信号を出力するドハティアンプと、
前記キャリアアンプ及び前記ピークアンプ各々に制御電圧を供給する電圧調整部と、
前記ドハティアンプの平均出力電力における動作に応じて定められ、前記ドハティアンプを構成する前記キャリアアンプ及び前記ピークアンプ毎の制御電圧値情報を記憶するテーブルを有し、前記テーブルに記憶された制御電圧値情報に基づく制御電圧を前記キャリアアンプ及び前記ピークアンプ毎に供給させるよう前記電圧調整部を制御する中央演算処理部と、
を備える電力増幅装置。 - 更に、前記ドハティアンプの出力電力を検出する出力モニタ回路を備え、
前記中央演算処理部は、前記出力モニタ回路の検出結果及び前記テーブルに記憶された前記キャリアアンプおよび前記ピークアンプ毎の制御電圧値情報に基づいて、前記キャリアアンプ及び前記ピークアンプへそれぞれ制御電圧を供給させるよう前記電圧調整部を制御する請求項1に記載の電力増幅装置。 - 前記ドハティアンプは非対称ドハティ化されたドハティアンプである、請求項1または請求項2に記載の電力増幅装置。
- キャリアアンプとピークアンプとを有し、入力信号を前記各アンプにより増幅して増幅後の信号を合成した出力信号を出力するドハティアンプと、
前記キャリアアンプ及び前記ピークアンプ各々に制御電圧を供給する電圧調整部と、
前記ドハティアンプの平均出力電力における動作に応じて定められ、前記ドハティアンプを構成する前記キャリアアンプ及び前記ピークアンプ毎の制御電圧値情報を記憶するテーブルを有する中央演算処理部と、
を備える電力増幅装置の制御方法であって、
前記中央演算処理部が、前記テーブルに記憶された制御電圧に基づく制御電圧を前記キャリアアンプ及び前記ピークアンプ毎に供給させるよう前記電圧調整部を制御する電力増幅装置の制御方法。
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US14/915,016 US20160204743A1 (en) | 2013-08-28 | 2014-02-14 | Power amplification apparatus and control method of power amplification apparatus |
EP14840906.3A EP3041133A4 (en) | 2013-08-28 | 2014-02-14 | Power amplification device and control method for power amplification device |
CN201480046800.5A CN105493400A (zh) | 2013-08-28 | 2014-02-14 | 功率放大装置和功率放大装置的控制方法 |
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US10454427B2 (en) | 2017-11-01 | 2019-10-22 | Mitsubishi Electric Research Laboratories, Inc. | Power amplifier system and learning-based autotuning method thereof |
CN116802999A (zh) * | 2021-02-02 | 2023-09-22 | 株式会社村田制作所 | 功率放大模块 |
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EP3041133A1 (en) | 2016-07-06 |
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