WO2015027654A1 - Procédé de préparation de diode électroluminescente à haute tension à base de nitrure de gallium - Google Patents

Procédé de préparation de diode électroluminescente à haute tension à base de nitrure de gallium Download PDF

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Publication number
WO2015027654A1
WO2015027654A1 PCT/CN2013/091112 CN2013091112W WO2015027654A1 WO 2015027654 A1 WO2015027654 A1 WO 2015027654A1 CN 2013091112 W CN2013091112 W CN 2013091112W WO 2015027654 A1 WO2015027654 A1 WO 2015027654A1
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WIPO (PCT)
Prior art keywords
gallium nitride
layer
type gallium
emitting diode
based high
Prior art date
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PCT/CN2013/091112
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English (en)
Chinese (zh)
Inventor
王强
王磊
李国琪
涂招莲
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无锡华润华晶微电子有限公司
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Publication of WO2015027654A1 publication Critical patent/WO2015027654A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present invention relates to the field of light emitting diode technologies, and in particular, to a method for fabricating a gallium nitride based high voltage light emitting diode.
  • HVLED High Voltage Light Emitting Diode
  • FIG. 1 is a flow chart of a method for fabricating a gallium nitride-based high voltage light emitting diode in the prior art
  • FIGS. 2a-2d are wafer cross sections at different stages in a method for fabricating a gallium nitride based high voltage light emitting diode in the prior art.
  • N-type gallium nitride (GaN) buffer layer 22 sequentially forming an N-type gallium nitride (GaN) buffer layer 22, an N-type gallium nitride layer 23, a multiple quantum well layer (MQW) 24, and a P-type gallium nitride layer (P-GaN) on the substrate 21. 25, as shown in Figure 2a.
  • GaN N-type gallium nitride
  • MQW multiple quantum well layer
  • P-GaN P-type gallium nitride layer
  • a conductive layer 26 is formed, and patterned to form a pattern. That is, a transparent conductive layer (ITO) is evaporated on the surface of the P-type gallium nitride, and then the conductive layer 26 is patterned to form a pattern, as shown in Fig. 2b.
  • ITO transparent conductive layer
  • S130 patterning again to form an N-type gallium nitride platform, as shown in Figure 2b.
  • S140 performing photolithography and deep trench etching until the surface of the substrate 21 to form a trench.
  • the fabrication method first forms a transparent conductive layer 26 on the P-type gallium nitride layer, and then performs N-type gallium nitride etching, deep trench etching, and deep trench isolation, and then the electrode layer 28 and the surface passivation layer 29 are grown.
  • the transparent conductive layer 26 under such a manufacturing method is affected by factors such as temperature, growth time, chemical reaction and the like in the subsequent deep trench etching and material growth during deep trench isolation, resulting in the resistivity of the transparent conductive layer 26.
  • the abnormality causes the contact resistance between the transparent conductive layer 26 and the P-type gallium nitride layer 25 to become large, thereby causing an abnormality in the electrical parameters of the high-voltage light-emitting diode.
  • the embodiment of the invention provides a method for fabricating a gallium nitride-based high-voltage light-emitting diode, which can ensure the quality of the conductive layer film, thereby avoiding the abnormality of the resistivity of the conductive layer.
  • the embodiment of the invention discloses a method for fabricating a gallium nitride-based high-voltage light-emitting diode, comprising: sequentially forming an N-type gallium nitride buffer layer, an N-type gallium nitride layer, a multiple quantum well layer and a P-type on a substrate.
  • An electrode layer and a passivation layer are sequentially formed.
  • the patterning to form the N-type gallium nitride platform comprises:
  • Photolithography and etching are performed using a mask to form an N-type gallium nitride landing mask.
  • performing the photolithography and deep trench etching to the surface of the substrate to form the trench comprises: photolithography and etching using a mask up to the surface of the substrate.
  • the etching is an inductively coupled plasma etching or a reactive ion etching.
  • the mask is a hard mask.
  • the hard mask mask is formed of an aluminum or nickel material.
  • the height of the conductive layer is not greater than the height of the isolation layer.
  • the spacer layer is formed of a silicon dioxide material.
  • the conductive layer is composed of one of indium tin oxide and zinc oxide or a combination thereof or a laminate thereof.
  • the substrate is formed of sapphire, silicon or silicon nitride material.
  • the number of quantum wells of the multiple quantum well layer is 3-10.
  • the invention adopts a method of first performing deep trench etching and forming an isolation layer, and then forming a conductive layer, thereby ensuring that the conductive layer obtained by the growth is not subjected to deep trench etching and temperature and growth time in the process of forming the isolation layer,
  • the influence of factors such as chemical reaction ensures the quality of the conductive layer film and avoids the abnormality of the resistivity of the conductive layer, thereby avoiding high-voltage light emission due to excessive contact resistance between the conductive layer and the P-type gallium nitride layer.
  • the problem of abnormal electrical parameters of the diode is a method of first performing deep trench etching and forming an isolation layer, and then forming a conductive layer, thereby ensuring that the conductive layer obtained by the growth is not subjected to deep trench etching and temperature and growth time in the process of forming the isolation layer.
  • FIGS. 2a-2d are schematic cross-sectional views of wafers at different stages in a method for fabricating a gallium nitride-based high-voltage light-emitting diode of the prior art;
  • FIG. 3 is a flow chart of a method for fabricating a gallium nitride based high voltage light emitting diode according to a first embodiment of the present invention
  • FIGS. 4a to 4e are different stages of a method for fabricating a gallium nitride based high voltage light emitting diode according to a first embodiment of the present invention
  • FIG. 3 is a flow chart of a method for fabricating a gallium nitride-based high-voltage light-emitting diode of the present invention
  • FIGS. 4a to 4e are wafer cross-sections at different stages in a method for fabricating a gallium nitride-based high-voltage light-emitting diode according to a first embodiment of the present invention
  • schematic diagram As shown in FIG. 3 and FIG. 4a to FIG. 4e, a first embodiment of the present invention provides a method for fabricating a gallium nitride (GaN)-based high voltage light emitting diode (HVLED), comprising:
  • an N-type gallium nitride buffer layer 42, an N-type gallium nitride layer 43, a multi-quantum well layer 44, and a P-type gallium nitride layer 45 are sequentially formed on the substrate 41.
  • a wafer cross section of the N-type gallium nitride buffer layer 42, the N-type gallium nitride layer 43, the multiple quantum well layer 44, and the P-type gallium nitride layer 45 is sequentially formed as shown in Fig. 4a.
  • the substrate 41 may be formed of sapphire, silicon or silicon nitride material, and the quantum well number of the multiple quantum well layer 44 may be 3-10.
  • the formation of the N-type gallium nitride buffer layer 42, the N-type gallium nitride layer (N-GaN) 43, the multiple quantum well layer (MQW) 44, and the P-type gallium nitride layer 45 can be utilized in the field.
  • Known deposition or epitaxial growth techniques, and techniques used include, but are not limited to, physical vapor deposition (PVD) or chemical vapor deposition (CVD).
  • patterning to form an N-type gallium nitride platform comprises: photolithography and etching using a mask to form an N-type gallium nitride platform mask. That is, the growth of the N-type gallium nitride landing mask and the fabrication of the lithographic pattern are performed, and then the N-type gallium nitride layer 43, the multiple quantum well layer 44, and the P-type gallium nitride layer 45 are inductively coupled.
  • ICP Plasma
  • RIE reactive ion etching
  • FIG. 4b The wafer cross section of the gallium nitride platform is shown in Figure 4b.
  • the patterning process can utilize a pattern fabrication method well known in the art including, but not limited to, photolithography and etching, and "patterning" of embodiments of the present invention can be understood.
  • the growth of the deep trench etching mask and the fabrication of the photolithographic pattern are performed, and then deep trench etching is performed to the surface of the substrate 41 using inductively coupled plasma etching or reactive ion etching, where only a deep trench can be performed.
  • Other etching methods for etching can be employed, and are not limited to the two examples exemplified.
  • the deep trench etch mask usually uses a hard mask. Because the deep trench etch time is long, ordinary photoresist may be eroded, so usually a layer is obtained.
  • the hard mask is then subjected to deep trench etching, wherein the hard mask may be composed of a material such as aluminum or nickel.
  • the isolation layer 47 is formed first, and the wafer cross section of the isolation layer 47 is formed as shown in Fig. 4c, and then etched, thereby forming a predetermined region where the subsequent conductive layer is deposited.
  • the isolation layer may be formed of a silicon dioxide material, and the isolation layer 47 may be formed by using deposition or epitaxial growth techniques well known in the art, including but not limited to physical vapor deposition (PVD) or chemical vapor deposition (CVD). .
  • the conductive layer 46 is formed in a predetermined region etched by the isolation layer 47.
  • the height of the conductive layer 46 is not greater than (less than or equal to) the height of the isolation layer, and the height of the conductive layer is usually 500-6000A.
  • the isolation layer is generally between 3000-20000A.
  • the conductive layer is composed of one of indium tin oxide (ITO) and zinc oxide or a combination thereof or a laminate thereof.
  • the electrode layer 48 and the passivation layer 49 are formed, respectively, using a patterning process to form a corresponding pattern.
  • the formation of electrode layer 48 and passivation layer 49 may utilize formation or epitaxial growth techniques well known in the art, including but not limited to physical vapor phase formation (PVD) or chemical vapor phase formation (CVD).
  • the growth of the N-type gallium nitride mask, the deep trench etch mask, and the spacer material is typically performed using a plasma enhanced chemical weather deposition (PECVD) apparatus, a low pressure chemical weather deposition (LPCVD) apparatus, Equipment such as atmospheric pressure chemical vapor deposition (APCVD) equipment and oxidation furnace tubes.
  • PECVD plasma enhanced chemical weather deposition
  • LPCVD low pressure chemical weather deposition
  • APCVD atmospheric pressure chemical vapor deposition
  • the conductive layer is formed before the deep trench etching and the deep trench isolation processing, and the resistivity of the conductive layer film is easily caused.
  • the isolation layer is formed by deep trench etching, and then the conductive layer is formed.
  • the quality of the conductive layer film is ensured, and the resistance of the conductive layer is avoided.
  • the abnormality of the rate avoids the problem that the electrical parameters of the high-voltage light-emitting diode are abnormal due to excessive contact resistance between the conductive layer and the P-type gallium nitride layer.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Led Devices (AREA)

Abstract

La présente invention concerne un procédé de préparation de diode électroluminescente à haute tension à base de nitrure de gallium. Ledit procédé comprend : la formation séquentielle d'une couche tampon de nitrure de gallium de type N (42), d'une couche de nitrure de gallium de type N (43), d'une couche à puits quantiques multiples (44), et d'une couche de nitrure de gallium de type P (45) sur un substrat (41) ; la réalisation d'une mise en configuration pour former une plateforme de nitrure de gallium de type N ; la réalisation d'une photo-gravure et d'une gravure à tranchée profonde jusqu'à ce qu'une tranchée soit formée sur une surface du substrat ; la formation d'une couche d'isolation (47), et la mise en configuration de la couche d'isolation pour exposer une partie de la couche de nitrure de gallium de type P et de la couche de nitrure de gallium de type N ; la formation d'une couche conductrice (46) sur une partie de la couche de nitrure de gallium de type P exposée ; et la formation séquentielle d'une couche électrode (48) et d'une couche de passivation (49). Dans le procédé de préparation, la gravure à tranchée profonde est réalisée et une couche d'isolation est formée en premier, et puis une couche conductrice est formée, ainsi garantissant que, après que la couche conductrice est développée et formée, la couche conductrice soit empêchée d'être affectée par la gravure à tranchée profonde et des facteurs tels qu'une température, un temps de développement et une réaction chimique durant la formation de la couche d'isolation, et en outre garantissant la qualité d'un film de couche conductrice, et évitant l'exception de la résistivité électrique de la couche conductrice.
PCT/CN2013/091112 2013-08-29 2013-12-31 Procédé de préparation de diode électroluminescente à haute tension à base de nitrure de gallium WO2015027654A1 (fr)

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CN201310390690.1 2013-08-29
CN201310390690.1A CN104425663A (zh) 2013-08-29 2013-08-29 一种氮化镓基高压发光二极管的制作方法

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Cited By (1)

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CN106098892A (zh) * 2016-06-30 2016-11-09 华灿光电(苏州）有限公司 一种高压发光二极管芯片的制造方法

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CN105374909B (zh) * 2015-11-02 2018-05-29 华灿光电(苏州）有限公司 一种高压发光二极管的制造方法
CN105655463B (zh) * 2016-04-11 2018-09-18 杭州士兰明芯科技有限公司 一种led结构及其制作方法
CN106449906A (zh) * 2016-10-28 2017-02-22 合肥彩虹蓝光科技有限公司 一种高压led芯片深刻蚀工艺

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CN102867837A (zh) * 2012-09-13 2013-01-09 中国科学院半导体研究所 阵列式高压led器件的制作方法
CN103227250A (zh) * 2013-05-07 2013-07-31 中国科学院半导体研究所 柔性透明导电层互联的阵列式led器件制作方法

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WO2008031280A1 (fr) * 2006-09-13 2008-03-20 Helio Optoelectronics Corporation Structure de diode électroluminescente
CN103022276B (zh) * 2011-09-26 2015-08-26 比亚迪股份有限公司 一种ac led芯片的制备方法
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CN102790045A (zh) * 2011-05-18 2012-11-21 展晶科技(深圳)有限公司 发光二极管阵列及其制造方法
CN102867837A (zh) * 2012-09-13 2013-01-09 中国科学院半导体研究所 阵列式高压led器件的制作方法
CN103227250A (zh) * 2013-05-07 2013-07-31 中国科学院半导体研究所 柔性透明导电层互联的阵列式led器件制作方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106098892A (zh) * 2016-06-30 2016-11-09 华灿光电(苏州）有限公司 一种高压发光二极管芯片的制造方法
CN106098892B (zh) * 2016-06-30 2018-08-21 华灿光电(苏州）有限公司 一种高压发光二极管芯片的制造方法

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