WO2015027654A1 - Method for preparing gallium nitride-based high-voltage light-emitting diode - Google Patents
Method for preparing gallium nitride-based high-voltage light-emitting diode Download PDFInfo
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- WO2015027654A1 WO2015027654A1 PCT/CN2013/091112 CN2013091112W WO2015027654A1 WO 2015027654 A1 WO2015027654 A1 WO 2015027654A1 CN 2013091112 W CN2013091112 W CN 2013091112W WO 2015027654 A1 WO2015027654 A1 WO 2015027654A1
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- gallium nitride
- layer
- type gallium
- emitting diode
- based high
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- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 85
- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 83
- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 38
- 238000002955 isolation Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000000059 patterning Methods 0.000 claims abstract description 14
- 238000002161 passivation Methods 0.000 claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 claims description 19
- 238000000206 photolithography Methods 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 5
- 238000009616 inductively coupled plasma Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052594 sapphire Inorganic materials 0.000 claims description 3
- 239000010980 sapphire Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000011787 zinc oxide Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 7
- 238000006243 chemical reaction Methods 0.000 abstract description 5
- 238000001259 photo etching Methods 0.000 abstract 1
- 238000002360 preparation method Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 7
- 230000005856 abnormality Effects 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
Definitions
- the present invention relates to the field of light emitting diode technologies, and in particular, to a method for fabricating a gallium nitride based high voltage light emitting diode.
- HVLED High Voltage Light Emitting Diode
- FIG. 1 is a flow chart of a method for fabricating a gallium nitride-based high voltage light emitting diode in the prior art
- FIGS. 2a-2d are wafer cross sections at different stages in a method for fabricating a gallium nitride based high voltage light emitting diode in the prior art.
- N-type gallium nitride (GaN) buffer layer 22 sequentially forming an N-type gallium nitride (GaN) buffer layer 22, an N-type gallium nitride layer 23, a multiple quantum well layer (MQW) 24, and a P-type gallium nitride layer (P-GaN) on the substrate 21. 25, as shown in Figure 2a.
- GaN N-type gallium nitride
- MQW multiple quantum well layer
- P-GaN P-type gallium nitride layer
- a conductive layer 26 is formed, and patterned to form a pattern. That is, a transparent conductive layer (ITO) is evaporated on the surface of the P-type gallium nitride, and then the conductive layer 26 is patterned to form a pattern, as shown in Fig. 2b.
- ITO transparent conductive layer
- S130 patterning again to form an N-type gallium nitride platform, as shown in Figure 2b.
- S140 performing photolithography and deep trench etching until the surface of the substrate 21 to form a trench.
- the fabrication method first forms a transparent conductive layer 26 on the P-type gallium nitride layer, and then performs N-type gallium nitride etching, deep trench etching, and deep trench isolation, and then the electrode layer 28 and the surface passivation layer 29 are grown.
- the transparent conductive layer 26 under such a manufacturing method is affected by factors such as temperature, growth time, chemical reaction and the like in the subsequent deep trench etching and material growth during deep trench isolation, resulting in the resistivity of the transparent conductive layer 26.
- the abnormality causes the contact resistance between the transparent conductive layer 26 and the P-type gallium nitride layer 25 to become large, thereby causing an abnormality in the electrical parameters of the high-voltage light-emitting diode.
- the embodiment of the invention provides a method for fabricating a gallium nitride-based high-voltage light-emitting diode, which can ensure the quality of the conductive layer film, thereby avoiding the abnormality of the resistivity of the conductive layer.
- the embodiment of the invention discloses a method for fabricating a gallium nitride-based high-voltage light-emitting diode, comprising: sequentially forming an N-type gallium nitride buffer layer, an N-type gallium nitride layer, a multiple quantum well layer and a P-type on a substrate.
- An electrode layer and a passivation layer are sequentially formed.
- the patterning to form the N-type gallium nitride platform comprises:
- Photolithography and etching are performed using a mask to form an N-type gallium nitride landing mask.
- performing the photolithography and deep trench etching to the surface of the substrate to form the trench comprises: photolithography and etching using a mask up to the surface of the substrate.
- the etching is an inductively coupled plasma etching or a reactive ion etching.
- the mask is a hard mask.
- the hard mask mask is formed of an aluminum or nickel material.
- the height of the conductive layer is not greater than the height of the isolation layer.
- the spacer layer is formed of a silicon dioxide material.
- the conductive layer is composed of one of indium tin oxide and zinc oxide or a combination thereof or a laminate thereof.
- the substrate is formed of sapphire, silicon or silicon nitride material.
- the number of quantum wells of the multiple quantum well layer is 3-10.
- the invention adopts a method of first performing deep trench etching and forming an isolation layer, and then forming a conductive layer, thereby ensuring that the conductive layer obtained by the growth is not subjected to deep trench etching and temperature and growth time in the process of forming the isolation layer,
- the influence of factors such as chemical reaction ensures the quality of the conductive layer film and avoids the abnormality of the resistivity of the conductive layer, thereby avoiding high-voltage light emission due to excessive contact resistance between the conductive layer and the P-type gallium nitride layer.
- the problem of abnormal electrical parameters of the diode is a method of first performing deep trench etching and forming an isolation layer, and then forming a conductive layer, thereby ensuring that the conductive layer obtained by the growth is not subjected to deep trench etching and temperature and growth time in the process of forming the isolation layer.
- FIGS. 2a-2d are schematic cross-sectional views of wafers at different stages in a method for fabricating a gallium nitride-based high-voltage light-emitting diode of the prior art;
- FIG. 3 is a flow chart of a method for fabricating a gallium nitride based high voltage light emitting diode according to a first embodiment of the present invention
- FIGS. 4a to 4e are different stages of a method for fabricating a gallium nitride based high voltage light emitting diode according to a first embodiment of the present invention
- FIG. 3 is a flow chart of a method for fabricating a gallium nitride-based high-voltage light-emitting diode of the present invention
- FIGS. 4a to 4e are wafer cross-sections at different stages in a method for fabricating a gallium nitride-based high-voltage light-emitting diode according to a first embodiment of the present invention
- schematic diagram As shown in FIG. 3 and FIG. 4a to FIG. 4e, a first embodiment of the present invention provides a method for fabricating a gallium nitride (GaN)-based high voltage light emitting diode (HVLED), comprising:
- an N-type gallium nitride buffer layer 42, an N-type gallium nitride layer 43, a multi-quantum well layer 44, and a P-type gallium nitride layer 45 are sequentially formed on the substrate 41.
- a wafer cross section of the N-type gallium nitride buffer layer 42, the N-type gallium nitride layer 43, the multiple quantum well layer 44, and the P-type gallium nitride layer 45 is sequentially formed as shown in Fig. 4a.
- the substrate 41 may be formed of sapphire, silicon or silicon nitride material, and the quantum well number of the multiple quantum well layer 44 may be 3-10.
- the formation of the N-type gallium nitride buffer layer 42, the N-type gallium nitride layer (N-GaN) 43, the multiple quantum well layer (MQW) 44, and the P-type gallium nitride layer 45 can be utilized in the field.
- Known deposition or epitaxial growth techniques, and techniques used include, but are not limited to, physical vapor deposition (PVD) or chemical vapor deposition (CVD).
- patterning to form an N-type gallium nitride platform comprises: photolithography and etching using a mask to form an N-type gallium nitride platform mask. That is, the growth of the N-type gallium nitride landing mask and the fabrication of the lithographic pattern are performed, and then the N-type gallium nitride layer 43, the multiple quantum well layer 44, and the P-type gallium nitride layer 45 are inductively coupled.
- ICP Plasma
- RIE reactive ion etching
- FIG. 4b The wafer cross section of the gallium nitride platform is shown in Figure 4b.
- the patterning process can utilize a pattern fabrication method well known in the art including, but not limited to, photolithography and etching, and "patterning" of embodiments of the present invention can be understood.
- the growth of the deep trench etching mask and the fabrication of the photolithographic pattern are performed, and then deep trench etching is performed to the surface of the substrate 41 using inductively coupled plasma etching or reactive ion etching, where only a deep trench can be performed.
- Other etching methods for etching can be employed, and are not limited to the two examples exemplified.
- the deep trench etch mask usually uses a hard mask. Because the deep trench etch time is long, ordinary photoresist may be eroded, so usually a layer is obtained.
- the hard mask is then subjected to deep trench etching, wherein the hard mask may be composed of a material such as aluminum or nickel.
- the isolation layer 47 is formed first, and the wafer cross section of the isolation layer 47 is formed as shown in Fig. 4c, and then etched, thereby forming a predetermined region where the subsequent conductive layer is deposited.
- the isolation layer may be formed of a silicon dioxide material, and the isolation layer 47 may be formed by using deposition or epitaxial growth techniques well known in the art, including but not limited to physical vapor deposition (PVD) or chemical vapor deposition (CVD). .
- the conductive layer 46 is formed in a predetermined region etched by the isolation layer 47.
- the height of the conductive layer 46 is not greater than (less than or equal to) the height of the isolation layer, and the height of the conductive layer is usually 500-6000A.
- the isolation layer is generally between 3000-20000A.
- the conductive layer is composed of one of indium tin oxide (ITO) and zinc oxide or a combination thereof or a laminate thereof.
- the electrode layer 48 and the passivation layer 49 are formed, respectively, using a patterning process to form a corresponding pattern.
- the formation of electrode layer 48 and passivation layer 49 may utilize formation or epitaxial growth techniques well known in the art, including but not limited to physical vapor phase formation (PVD) or chemical vapor phase formation (CVD).
- the growth of the N-type gallium nitride mask, the deep trench etch mask, and the spacer material is typically performed using a plasma enhanced chemical weather deposition (PECVD) apparatus, a low pressure chemical weather deposition (LPCVD) apparatus, Equipment such as atmospheric pressure chemical vapor deposition (APCVD) equipment and oxidation furnace tubes.
- PECVD plasma enhanced chemical weather deposition
- LPCVD low pressure chemical weather deposition
- APCVD atmospheric pressure chemical vapor deposition
- the conductive layer is formed before the deep trench etching and the deep trench isolation processing, and the resistivity of the conductive layer film is easily caused.
- the isolation layer is formed by deep trench etching, and then the conductive layer is formed.
- the quality of the conductive layer film is ensured, and the resistance of the conductive layer is avoided.
- the abnormality of the rate avoids the problem that the electrical parameters of the high-voltage light-emitting diode are abnormal due to excessive contact resistance between the conductive layer and the P-type gallium nitride layer.
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Abstract
A method for preparing a gallium nitride-based high-voltage light-emitting diode comprises: sequentially forming an N-type gallium nitride buffer layer (42), an N-type gallium nitride layer (43), a multi-quantum well layer (44), and a P-type gallium nitride layer (45) on a substrate (41); performing patterning to form an N-type gallium nitride platform; performing photoetching and deep trench etching until a trench is formed on a surface of the substrate; forming an isolation layer (47), and patterning the isolation layer to expose part of the P-type gallium nitride layer and the N-type gallium nitride layer; forming a conducting layer (46) on part of the exposed P-type gallium nitride layer; and sequentially forming an electrode layer (48) and a passivation layer (49). In the preparation method, deep trench etching is performed and an isolation layer is formed first, and then a conducting layer is formed, thereby ensuring that after the conducting layer is grown and formed, the conducting layer is prevented from being affected by deep trench etching and factors such as a temperature, growth time and a chemical reaction during the formation of the isolation layer, and further, ensuring the quality of a conducting layer film, and avoiding the exception of the electrical resistivity of the conducting layer.
Description
说 明 书 一种氮化镓基高压发光二极管的制作方法 本专利申请要求于 2013年 08月 29日提交的、 申请号为 201310390690.1、 申请人为无锡华润华晶微电子有限公司、 发明名称为"一种氮化镓基高压发光二 极管的制作方法"的中国专利申请的优先权， 该申请的全文以引用的方式并入本 申请中。 The present invention claims to be filed on August 29, 2013, the application number is 201310390690.1, the applicant is Wuxi Huarun Huajing Microelectronics Co., Ltd., and the invention name is "a nitrogen The priority of the Chinese Patent Application for the Manufacture of a Gallium-Based High-Voltage Light Emitting Diode is incorporated herein by reference.
技术领域 Technical field
本发明涉及发光二极管技术领域， 尤其涉及一种氮化镓基高压发光二极管 的制作方法。 The present invention relates to the field of light emitting diode technologies, and in particular, to a method for fabricating a gallium nitride based high voltage light emitting diode.
背景技术 Background technique
近几年由于技术与效率的进步， 发光二极管 （Light Emitting Diode, LED ) 的应用范围越来越广。 随着 LED应用的升级， 市场对于 LED 的需求朝向具备 更大功率及更高亮度的 LED, 即高功率 LED 方向发展。 对于实现高功率 LED, 目前氮化镓 ( GaN )基高压发光二极管 （High Voltage Light Emitting Diode, HVLED ) 的制造方法成为解决方案之一。 In recent years, due to advances in technology and efficiency, the application range of Light Emitting Diodes (LEDs) has become wider and wider. With the upgrade of LED applications, the market demand for LEDs is moving toward LEDs with higher power and higher brightness, that is, high-power LEDs. For the realization of high-power LEDs, the current manufacturing method of GaN-based High Voltage Light Emitting Diode (HVLED) is one of the solutions.
图 1是现有技术中的氮化镓基高压发光二极管的制作方法的流程图， 图 2a- 图 2d是现有技术中的氮化镓基高压发光二极管的制作方法中不同阶段的晶圆截 面示意图。 如图 1以及图 2a-图 2d所示， 现有技术中的氮化镓基高压发光二极 管的制作方法包含以下步骤： 1 is a flow chart of a method for fabricating a gallium nitride-based high voltage light emitting diode in the prior art, and FIGS. 2a-2d are wafer cross sections at different stages in a method for fabricating a gallium nitride based high voltage light emitting diode in the prior art. schematic diagram. As shown in FIG. 1 and FIG. 2a to FIG. 2d, the prior art method for fabricating a gallium nitride based high voltage light emitting diode comprises the following steps:
S110, 在衬底 21上依次形成 N型氮化镓（GaN )緩冲层 22, N型氮化镓层 23 , 多量子阱层（MQW ) 24以及 P型氮化镓层 ( P-GaN ) 25, 如图 2a所示。 S110, sequentially forming an N-type gallium nitride (GaN) buffer layer 22, an N-type gallium nitride layer 23, a multiple quantum well layer (MQW) 24, and a P-type gallium nitride layer (P-GaN) on the substrate 21. 25, as shown in Figure 2a.
S120, 形成导电层 26, 并且通过图案化以形成图形。 也就是在 P型氮化镓 表面蒸镀一层透明导电层（ITO ), 然后对导电层 26进行图案化以形成图形， 如 图 2b所示。 S120, a conductive layer 26 is formed, and patterned to form a pattern. That is, a transparent conductive layer (ITO) is evaporated on the surface of the P-type gallium nitride, and then the conductive layer 26 is patterned to form a pattern, as shown in Fig. 2b.
S130, 再次进行图案化以形成 N型氮化镓平台， 如图 2b所示。
S140, 进行光刻和深沟刻蚀直至所述衬底 21的表面以形成沟槽。 S130, patterning again to form an N-type gallium nitride platform, as shown in Figure 2b. S140, performing photolithography and deep trench etching until the surface of the substrate 21 to form a trench.
S150, 形成隔离层 27, 然后对所述隔离层 27进行图案化， 如图 2c所示。 S150, forming an isolation layer 27, and then patterning the isolation layer 27, as shown in Fig. 2c.
S160, 依次形成电极层 28和钝化层 29, 如图 2d所示。 S160, an electrode layer 28 and a passivation layer 29 are sequentially formed, as shown in Fig. 2d.
该制作方法先在 P型氮化镓层上形成透明导电层 26, 再进行 N型氮化镓刻 蚀、 深沟刻蚀和深沟隔离， 然后生长电极层 28和表面钝化层 29。 这种制造方法 下的透明导电层 26会受到后面的深沟刻蚀和在深沟隔离的材料生长过程中的温 度、 生长时间、 化学反应等因素的影响， 造成透明导电层 26的电阻率的异常， 从而使透明导电层 26与 P型氮化镓层 25之间的接触电阻变大， 因此引起高压 发光二极管的电学参数异常。 The fabrication method first forms a transparent conductive layer 26 on the P-type gallium nitride layer, and then performs N-type gallium nitride etching, deep trench etching, and deep trench isolation, and then the electrode layer 28 and the surface passivation layer 29 are grown. The transparent conductive layer 26 under such a manufacturing method is affected by factors such as temperature, growth time, chemical reaction and the like in the subsequent deep trench etching and material growth during deep trench isolation, resulting in the resistivity of the transparent conductive layer 26. The abnormality causes the contact resistance between the transparent conductive layer 26 and the P-type gallium nitride layer 25 to become large, thereby causing an abnormality in the electrical parameters of the high-voltage light-emitting diode.
发明内容 Summary of the invention
有鉴于此， 本发明实施例提出一种氮化镓基高压发光二极管的制作方法， 能够保证导电层薄膜的质量， 从而避免导电层的电阻率的异常。 In view of this, the embodiment of the invention provides a method for fabricating a gallium nitride-based high-voltage light-emitting diode, which can ensure the quality of the conductive layer film, thereby avoiding the abnormality of the resistivity of the conductive layer.
本发明实施例公开了一种氮化镓基高压发光二极管的制作方法， 包含： 在衬底上依次形成 N型氮化镓緩冲层， N型氮化镓层， 多量子阱层以及 P 型氮化镓层； The embodiment of the invention discloses a method for fabricating a gallium nitride-based high-voltage light-emitting diode, comprising: sequentially forming an N-type gallium nitride buffer layer, an N-type gallium nitride layer, a multiple quantum well layer and a P-type on a substrate. Gallium nitride layer;
进行图案化以形成 N型氮化镓平台； Patterning to form an N-type gallium nitride platform;
进行光刻和深沟刻蚀直至所述衬底的表面以形成沟槽； Photolithography and deep trench etching to the surface of the substrate to form trenches;
形成隔离层， 并对所述隔离层进行图像化以露出部分 P型氮化镓层和 N型 氮化镓层； Forming an isolation layer, and patterning the isolation layer to expose a portion of the P-type gallium nitride layer and the N-type gallium nitride layer;
在露出的部分 P型氮化镓层上形成导电层； 以及 Forming a conductive layer on the exposed portion of the P-type gallium nitride layer;
依次形成电极层和钝化层。 An electrode layer and a passivation layer are sequentially formed.
优选地， 所述进行图案化以形成 N型氮化镓平台包含： Preferably, the patterning to form the N-type gallium nitride platform comprises:
利用掩模进行光刻和蚀刻以形成 N型氮化镓平台掩模。 Photolithography and etching are performed using a mask to form an N-type gallium nitride landing mask.
优选地， 所述进行光刻和深沟刻蚀至所述衬底的表面以形成沟槽包含： 利用掩模进行光刻和蚀刻直至所述衬底的表面。 Preferably, performing the photolithography and deep trench etching to the surface of the substrate to form the trench comprises: photolithography and etching using a mask up to the surface of the substrate.
优选地， 所述蚀刻为感应耦合等离子体蚀刻或反应离子刻蚀。
优选地， 所述掩模为硬掩模。 Preferably, the etching is an inductively coupled plasma etching or a reactive ion etching. Preferably, the mask is a hard mask.
优选地， 所述硬掩膜掩模由铝或镍材料所形成。 Preferably, the hard mask mask is formed of an aluminum or nickel material.
优选地， 所述导电层的高度不大于所述隔离层的高度。 Preferably, the height of the conductive layer is not greater than the height of the isolation layer.
优选地， 所述隔离层由二氧化硅材料形成。 Preferably, the spacer layer is formed of a silicon dioxide material.
优选地， 所述导电层由氧化铟锡和氧化锌中的一种材料或其组合或其叠层 所组成。 Preferably, the conductive layer is composed of one of indium tin oxide and zinc oxide or a combination thereof or a laminate thereof.
优选地， 所述衬底由蓝宝石， 硅或氮化硅材料形成。 Preferably, the substrate is formed of sapphire, silicon or silicon nitride material.
优选地， 所述多量子阱层的量子阱数为 3-10。 Preferably, the number of quantum wells of the multiple quantum well layer is 3-10.
本发明通过先进行深沟刻蚀和形成隔离层， 再形成导电层的方法， 从而保 证了生长获得的导电层不会受到深沟刻蚀和在形成隔离层的过程中的温度、 生 长时间、 化学反应等因素的影响， 从而保证了导电层薄膜的质量， 避免了导电 层的电阻率的异常， 因此避免了由于导电层与 P型氮化镓层之间的接触电阻过 大而引起高压发光二极管的电学参数异常的问题。 The invention adopts a method of first performing deep trench etching and forming an isolation layer, and then forming a conductive layer, thereby ensuring that the conductive layer obtained by the growth is not subjected to deep trench etching and temperature and growth time in the process of forming the isolation layer, The influence of factors such as chemical reaction ensures the quality of the conductive layer film and avoids the abnormality of the resistivity of the conductive layer, thereby avoiding high-voltage light emission due to excessive contact resistance between the conductive layer and the P-type gallium nitride layer. The problem of abnormal electrical parameters of the diode.
附图说明 DRAWINGS
图 1是现有技术的氮化镓基高压发光二极管的制作方法的流程图； 图 2a-图 2d是现有技术的氮化镓基高压发光二极管的制作方法中不同阶段 的晶圆截面示意图； 1 is a flow chart of a method for fabricating a gallium nitride-based high-voltage light-emitting diode of the prior art; and FIGS. 2a-2d are schematic cross-sectional views of wafers at different stages in a method for fabricating a gallium nitride-based high-voltage light-emitting diode of the prior art;
图 3是本发明第一实施例的氮化镓基高压发光二极管的制作方法的流程图； 图 4a-图 4e是本发明第一实施例的氮化镓基高压发光二极管的制作方法中 不同阶段的晶圆截面示意图。 3 is a flow chart of a method for fabricating a gallium nitride based high voltage light emitting diode according to a first embodiment of the present invention; and FIGS. 4a to 4e are different stages of a method for fabricating a gallium nitride based high voltage light emitting diode according to a first embodiment of the present invention; Schematic diagram of the wafer cross section.
具体实施方式 detailed description
下面结合附图并通过具体实施方式来进一步说明本发明的技术方案。 可以 理解的是， 此处所描述的具体实施例仅仅用于解释本发明， 而非对本发明的限 定。 另外还需要说明的是， 为了便于描述， 附图中仅示出了与本发明相关的部 分而非全部内容。
图 3是本发明的氮化镓基高压发光二极管的制作方法的流程图； 图 4a-图 4e 是本发明第一实施例的氮化镓基高压发光二极管的制作方法中不同阶段的晶圆 截面示意图。 如图 3和图 4a-图 4e所示， 本发明第一实施例提供了一种氮化镓 ( GaN )基高压发光二极管 （HVLED ) 的制作方法， 包含： The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. It should also be noted that, for ease of description, only some, but not all, of the present invention are shown in the drawings. 3 is a flow chart of a method for fabricating a gallium nitride-based high-voltage light-emitting diode of the present invention; FIGS. 4a to 4e are wafer cross-sections at different stages in a method for fabricating a gallium nitride-based high-voltage light-emitting diode according to a first embodiment of the present invention; schematic diagram. As shown in FIG. 3 and FIG. 4a to FIG. 4e, a first embodiment of the present invention provides a method for fabricating a gallium nitride (GaN)-based high voltage light emitting diode (HVLED), comprising:
S310, 在衬底 41上依次形成 N型氮化镓緩冲层 42, N型氮化镓层 43 , 多 量子阱层 44以及 P型氮化镓层 45。 S310, an N-type gallium nitride buffer layer 42, an N-type gallium nitride layer 43, a multi-quantum well layer 44, and a P-type gallium nitride layer 45 are sequentially formed on the substrate 41.
依次形成 N型氮化镓緩冲层 42, N型氮化镓层 43 , 多量子阱层 44以及 P 型氮化镓层 45后的晶圆截面如图 4a所示。 其中， 所述衬底 41可以由蓝宝石、 硅或氮化硅材料形 所述多量子阱层 44的量子阱数可以为 3-10。在该步骤中， N型氮化镓緩冲层 42, N型氮化镓层（N-GaN ) 43 , 多量子阱层（MQW ) 44 以及 P型氮化镓层 45的形成可以利用本领域公知的沉积或外延生长技术， 并且 所用技术包括但不限于物理气相沉积（PVD )或化学气相沉积（CVD ) 。 A wafer cross section of the N-type gallium nitride buffer layer 42, the N-type gallium nitride layer 43, the multiple quantum well layer 44, and the P-type gallium nitride layer 45 is sequentially formed as shown in Fig. 4a. Wherein, the substrate 41 may be formed of sapphire, silicon or silicon nitride material, and the quantum well number of the multiple quantum well layer 44 may be 3-10. In this step, the formation of the N-type gallium nitride buffer layer 42, the N-type gallium nitride layer (N-GaN) 43, the multiple quantum well layer (MQW) 44, and the P-type gallium nitride layer 45 can be utilized in the field. Known deposition or epitaxial growth techniques, and techniques used include, but are not limited to, physical vapor deposition (PVD) or chemical vapor deposition (CVD).
S320, 进行图案化以形成 N型氮化镓平台。 S320, patterning to form an N-type gallium nitride platform.
在该步骤中， 优选地， 进行图案化以形成 N型氮化镓平台包含： 利用掩模 进行光刻和蚀刻以形成 N型氮化镓平台掩模。 也就是说， 进行所述 N型氮化镓 平台掩模的生长以及光刻图形的制作， 然后对 N型氮化镓层 43, 多量子阱层 44 以及 P型氮化镓层 45进行感应耦合等离子体（ ICP )蚀刻或反应离子刻蚀（ RIE ) 以形成 N 型氮化镓平台， 此处只要能进行深沟蚀刻的其他蚀刻方法都可以采 用， 不仅限于举例的这两种方式形成 N型氮化镓平台的晶圆截面如图 4b所示。 其中， 图案化工艺可以利用本领域公知的图案制造方法， 该方法包括但不限于 光刻和蚀刻， 本发明的实施例的"图案化 "皆可理解为此。 In this step, preferably, patterning to form an N-type gallium nitride platform comprises: photolithography and etching using a mask to form an N-type gallium nitride platform mask. That is, the growth of the N-type gallium nitride landing mask and the fabrication of the lithographic pattern are performed, and then the N-type gallium nitride layer 43, the multiple quantum well layer 44, and the P-type gallium nitride layer 45 are inductively coupled. Plasma (ICP) etching or reactive ion etching (RIE) to form an N-type gallium nitride platform, as long as other etching methods capable of deep trench etching can be used, not limited to the two examples of forming an N-type The wafer cross section of the gallium nitride platform is shown in Figure 4b. Wherein, the patterning process can utilize a pattern fabrication method well known in the art including, but not limited to, photolithography and etching, and "patterning" of embodiments of the present invention can be understood.
S330, 进行光刻和深沟刻蚀直至所述衬底的表面以形成沟槽。 S330, performing photolithography and deep trench etching to the surface of the substrate to form a trench.
在该步骤中， 进行光刻和深沟刻蚀直至所述衬底的表面以形成沟槽包含： 利用掩模进行光刻和蚀刻至所述衬底的表面。 通常进行深沟刻蚀掩模的生长以 及光刻图形的制作， 然后使用感应耦合等离子体蚀刻或反应离子刻蚀进行深沟 刻蚀直至所述衬底 41的表面， 此处只要能进行深沟蚀刻的其他蚀刻方法都可以 采用， 不仅限于举例的这两种方式。 所述深沟刻蚀掩模通常使用硬掩模， 因为 深沟蚀刻的时间较长， 普通的光刻胶可能会被侵蚀， 所以通常先生长得到一层
硬掩模， 然后再进行深沟蚀刻， 其中， 硬掩模可以由铝或镍等材料所组成。 In this step, photolithography and deep trench etching are performed until the surface of the substrate to form a trench comprises: photolithography and etching to a surface of the substrate using a mask. Generally, the growth of the deep trench etching mask and the fabrication of the photolithographic pattern are performed, and then deep trench etching is performed to the surface of the substrate 41 using inductively coupled plasma etching or reactive ion etching, where only a deep trench can be performed. Other etching methods for etching can be employed, and are not limited to the two examples exemplified. The deep trench etch mask usually uses a hard mask. Because the deep trench etch time is long, ordinary photoresist may be eroded, so usually a layer is obtained. The hard mask is then subjected to deep trench etching, wherein the hard mask may be composed of a material such as aluminum or nickel.
S340, 形成隔离层 47, 对所述隔离层 47进行图案化以露出部分 P型氮化镓 层 45和 N型氮化镓层 43。 S340, forming an isolation layer 47, and patterning the isolation layer 47 to expose a portion of the P-type gallium nitride layer 45 and the N-type gallium nitride layer 43.
在该步骤中， 先形成隔离层 47, 所形成隔离层 47的晶圆截面如图 4c所示， 然后进行蚀刻， 这样便制作出后续导电层沉积的预定区域。 其中， 所述隔离层 可以由二氧化硅材料形成， 隔离层 47的形成可以利用本领域公知的沉积或外延 生长技术， 所用技术包括但不限于物理气相沉积 （PVD ) 或化学气相沉积 ( CVD ) 。 In this step, the isolation layer 47 is formed first, and the wafer cross section of the isolation layer 47 is formed as shown in Fig. 4c, and then etched, thereby forming a predetermined region where the subsequent conductive layer is deposited. Wherein, the isolation layer may be formed of a silicon dioxide material, and the isolation layer 47 may be formed by using deposition or epitaxial growth techniques well known in the art, including but not limited to physical vapor deposition (PVD) or chemical vapor deposition (CVD). .
S350, 在露出的部分 P型氮化镓层上形成导电层 46。 S350, forming a conductive layer 46 on the exposed portion of the P-type gallium nitride layer.
在该步骤中， 在隔离层 47蚀刻出的预定区域中形成导电层 46, 优选地， 导 电层 46 的高度不大于 （小于或等于） 隔离层的高度， 通常导电层的高度在 500-6000A之间， 隔离层一般在 3000-20000A之间。 其中， 所述导电层由氧化铟 锡（ITO )和氧化锌中的一种材料或其组合或其叠层所组成。 In this step, the conductive layer 46 is formed in a predetermined region etched by the isolation layer 47. Preferably, the height of the conductive layer 46 is not greater than (less than or equal to) the height of the isolation layer, and the height of the conductive layer is usually 500-6000A. The isolation layer is generally between 3000-20000A. Wherein, the conductive layer is composed of one of indium tin oxide (ITO) and zinc oxide or a combination thereof or a laminate thereof.
S360, 依次形成电极层 48和钝化层 49。 S360, an electrode layer 48 and a passivation layer 49 are sequentially formed.
在该步骤中， 形成电极层 48和钝化层 49, 分别使用图案化工艺以形成相应 的图形。 电极层 48和钝化层 49的形成可以利用本领域公知的形成或外延生长 技术， 所用技术包括但不限于物理气相形成（PVD )或化学气相形成（CVD ) 。 In this step, the electrode layer 48 and the passivation layer 49 are formed, respectively, using a patterning process to form a corresponding pattern. The formation of electrode layer 48 and passivation layer 49 may utilize formation or epitaxial growth techniques well known in the art, including but not limited to physical vapor phase formation (PVD) or chemical vapor phase formation (CVD).
在该实施例中， N型氮化镓掩模、 深沟刻蚀掩模和隔离层材料的生长通常 采用等离子体增强化学气象淀积（ PECVD )设备、 低压化学气象淀积（ LPCVD ) 设备、 常压化学气相淀积（APCVD )设备和氧化炉管等设备。 In this embodiment, the growth of the N-type gallium nitride mask, the deep trench etch mask, and the spacer material is typically performed using a plasma enhanced chemical weather deposition (PECVD) apparatus, a low pressure chemical weather deposition (LPCVD) apparatus, Equipment such as atmospheric pressure chemical vapor deposition (APCVD) equipment and oxidation furnace tubes.
现有技术中导电层形成在深沟刻蚀和深沟隔离加工之前， 容易造成导电层 薄膜的电阻率异常， 而本发明实施例通过先进行深沟刻蚀形成隔离层， 再形成 导电层， 以保证在生长获得的导电层不会受到深沟刻蚀和形成隔离层的过程中 的温度、 生长时间、 化学反应等因素的影响， 从而保证了导电层薄膜的质量， 避免了导电层的电阻率的异常， 因此避免了由于导电层与 P型氮化镓层之间的 接触电阻过大而引起高压发光二极管的电学参数异常的问题。 In the prior art, the conductive layer is formed before the deep trench etching and the deep trench isolation processing, and the resistivity of the conductive layer film is easily caused. In the embodiment of the present invention, the isolation layer is formed by deep trench etching, and then the conductive layer is formed. In order to ensure that the conductive layer obtained during growth is not affected by factors such as temperature, growth time and chemical reaction during deep trench etching and isolation layer formation, the quality of the conductive layer film is ensured, and the resistance of the conductive layer is avoided. The abnormality of the rate avoids the problem that the electrical parameters of the high-voltage light-emitting diode are abnormal due to excessive contact resistance between the conductive layer and the P-type gallium nitride layer.
而且， 如果本发明实施例中对掩模和隔离层材料采用了更高质量的制作方 法， 并且反应温度高， 时间长， 与会严重影响高压发光二极管的电学参数的现
有技术的方法相比， 该实施例的效果将更加显著。 Moreover, if a higher quality fabrication method is adopted for the mask and the spacer material in the embodiment of the present invention, and the reaction temperature is high and the time is long, the electrical parameters of the high voltage LED may be seriously affected. The effect of this embodiment will be more significant than the technical method.
以上仅为本发明的较佳实施例， 并不用以限制本发明， 凡在本发明的精神 和原则之内， 所作的任何修改、 等同替换、 改进等， 均应包含在本发明的保护 范围之内。
The above are only the preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalents, improvements, etc., which are within the spirit and scope of the present invention, should be included in the scope of the present invention. Inside.
Claims
1、 一种氮化镓基高压发光二极管的制作方法， 包含： 1. A method for manufacturing a gallium nitride-based high-voltage light-emitting diode, including:
在衬底上依次形成 N型氮化镓緩冲层， N型氮化镓层， 多量子阱层以及 P 型氮化镓层； Form an N-type gallium nitride buffer layer, an N-type gallium nitride layer, a multiple quantum well layer and a P-type gallium nitride layer in sequence on the substrate;
对所述 N型氮化镓层， 所述多量子阱层以及所述 P型氮化镓层进行图案化 以形成 N型氮化镓平台； Pattern the N-type gallium nitride layer, the multiple quantum well layer and the P-type gallium nitride layer to form an N-type gallium nitride platform;
进行光刻和深沟刻蚀直至所述衬底的表面以形成沟槽； Perform photolithography and deep trench etching to the surface of the substrate to form trenches;
形成隔离层， 并对所述隔离层进行图案化以露出部分 P型氮化镓层和 N型 氮化镓层； Form an isolation layer, and pattern the isolation layer to expose part of the P-type gallium nitride layer and the N-type gallium nitride layer;
在露出的部分 P型氮化镓层上形成导电层； 以及 forming a conductive layer on the exposed portion of the P-type gallium nitride layer; and
依次形成电极层和钝化层。 The electrode layer and passivation layer are formed in sequence.
2、 根据权利要求 1所述的氮化镓基高压发光二极管的制作方法， 所述进行 图案化以形成 N型氮化镓平台包含： 2. The method for manufacturing a gallium nitride-based high-voltage light-emitting diode according to claim 1, wherein the patterning to form an N-type gallium nitride platform includes:
利用掩模进行光刻和蚀刻以形成 N型氮化镓平台掩模。 Photolithography and etching are performed using the mask to form an N-type gallium nitride mesa mask.
3、 根据权利要求 1所述的氮化镓基高压发光二极管的制作方法， 所述进行 光刻和深沟刻蚀至所述衬底的表面以形成沟槽包含： 3. The method for manufacturing a gallium nitride-based high-voltage light-emitting diode according to claim 1, wherein performing photolithography and deep trench etching to the surface of the substrate to form trenches includes:
利用掩模进行光刻和蚀刻直至所述衬底的表面。 Photolithography and etching are performed using a mask down to the surface of the substrate.
4、 根据权利要求 2或 3所述的氮化镓基高压发光二极管的制作方法， 所述 蚀刻为感应耦合等离子体蚀刻或反应离子刻蚀。 4. The method for manufacturing a gallium nitride-based high-voltage light-emitting diode according to claim 2 or 3, wherein the etching is inductively coupled plasma etching or reactive ion etching.
5、 根据权利要求 2或 3所述的氮化镓基高压发光二极管的制作方法， 所述 掩模为硬掩模。 5. The method for manufacturing a gallium nitride-based high-voltage light-emitting diode according to claim 2 or 3, wherein the mask is a hard mask.
5、 根据权利要求 1所述的氮化镓基高压发光二极管的制作方法， 所述硬掩 膜掩模由铝或镍材料所形成。 5. The method of manufacturing a gallium nitride-based high-voltage light-emitting diode according to claim 1, wherein the hard mask is made of aluminum or nickel material.
6、 根据权利要求 1 所述的氮化镓基高压发光二极管的制作方法， 所述导 电层的高度不大于所述隔离层的高度。 6. The method of manufacturing a gallium nitride-based high-voltage light-emitting diode according to claim 1, wherein the height of the conductive layer is not greater than the height of the isolation layer.
7、 根据权利要求 1所述的氮化镓基高压发光二极管的制作方法， 所述隔离 层由二氧化硅材料形成。 7. The method of manufacturing a gallium nitride-based high-voltage light-emitting diode according to claim 1, wherein the isolation layer is formed of silicon dioxide material.
8、 根据权利要求 1所述的氮化镓基高压发光二极管的制作方法， 所述导电 层由氧化铟锡和氧化锌中的一种材料或其组合或其叠层所组成。
8. The method for manufacturing a gallium nitride-based high-voltage light-emitting diode according to claim 1, wherein the conductive layer is composed of a material selected from indium tin oxide and zinc oxide, a combination thereof, or a stack thereof.
9、 根据权利要求 1所述的氮化镓基高压发光二极管的制作方法， 所述衬底 由蓝宝石， 硅或氮化硅材料形成。 9. The method of manufacturing a gallium nitride-based high-voltage light-emitting diode according to claim 1, wherein the substrate is made of sapphire, silicon or silicon nitride material.
10、 根据权利要求 1 所述的氮化镓基高压发光二极管的制作方法， 所述多 量子阱层的量子阱数为 3-10。
10. The method for manufacturing a gallium nitride-based high-voltage light-emitting diode according to claim 1, wherein the number of quantum wells in the multi-quantum well layer is 3-10.
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| CN105655463B (en) * | 2016-04-11 | 2018-09-18 | 杭州士兰明芯科技有限公司 | A kind of LED structure and preparation method thereof |
| CN106449906A (en) * | 2016-10-28 | 2017-02-22 | 合肥彩虹蓝光科技有限公司 | High-pressure LED chip deep-etching process |
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| CN102790045A (en) * | 2011-05-18 | 2012-11-21 | 展晶科技(深圳)有限公司 | Light emitting diode array and manufacturing method thereof |
| CN102867837A (en) * | 2012-09-13 | 2013-01-09 | 中国科学院半导体研究所 | Manufacture method of array type high-voltage LED device |
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