WO2015027609A1 - Substrat en réseau, procédé de fabrication associé et dispositif d'affichage - Google Patents

Substrat en réseau, procédé de fabrication associé et dispositif d'affichage Download PDF

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Publication number
WO2015027609A1
WO2015027609A1 PCT/CN2013/088834 CN2013088834W WO2015027609A1 WO 2015027609 A1 WO2015027609 A1 WO 2015027609A1 CN 2013088834 W CN2013088834 W CN 2013088834W WO 2015027609 A1 WO2015027609 A1 WO 2015027609A1
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Prior art keywords
black matrix
layer
thin film
film transistor
common electrode
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PCT/CN2013/088834
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English (en)
Chinese (zh)
Inventor
姜清华
秦锋
李小和
刘永
邵贤杰
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合肥京东方光电科技有限公司
京东方科技集团股份有限公司
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Publication of WO2015027609A1 publication Critical patent/WO2015027609A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the TFT-LCD is composed of a liquid crystal display panel, a driving circuit, and a backlight module, and the liquid crystal display panel is an important part of the TFT-LCD.
  • the liquid crystal display panel is formed by injecting liquid crystal between the array substrate and the color filter substrate, sealing with a sealant around the frame, and then applying a polarizing plate having polarization directions perpendicular to each other on the array substrate and the color filter substrate.
  • a matrix array of thin film transistors, pixel electrodes and peripheral circuits are formed on the array substrate.
  • the color filter substrate (Color Filter, CF, ) is composed of red (R), green (G), and blue (B) three primary color resins, and is formed with a transparent common electrode.
  • the prior art liquid crystal panel is provided with a black matrix on the color filter substrate.
  • the width of the black matrix is the sum of the width of the light leakage region and the accuracy error of the box.
  • the width dl of the black matrix disposed on the color filter substrate is generally large, resulting in TFT.
  • - LCD has defects such as low aperture ratio and low display brightness.
  • FIG. 1 is a cross-sectional structural view of the display panel for reducing the resistance of the common electrode layer in the prior art.
  • the transparent conductive common electrode layer 20 is directly placed on the metal layer 11 in the same layer as the gate electrode 10, so that the material used for the metal layer 11 disposed in the same layer as the gate electrode 10 is generally chromium (Cr) or tungsten (W).
  • the common electrode layer 20 is generally indium tin oxide, indium oxide, alumina, etc., the former The resistivity is much smaller than the resistivity of the latter, so the total resistance of the two in parallel is higher than the resistance of the common electrode layer. To be much smaller, the resistance value of the common electrode layer can be effectively reduced, thereby reducing the voltage difference of the common electrode between the pixels.
  • the metal layer 11 in the same layer as the gate electrode 10 is a non-transparent metal, it causes a large loss in the aperture ratio of the pixel.
  • FIG. 2 is a schematic plan view of the display panel shown in FIG. 1 and 2, the display panel includes: a TFT array substrate, a color filter substrate, and a liquid crystal layer (not shown) disposed between the array substrate and the color filter substrate, wherein
  • the array substrate includes: a gate electrode 10, a metal layer 11 and a gate line 12 of the same material disposed in the same layer as the gate electrode 10, a transparent conductive common electrode layer 20, and the common electrode layer 20 covers the metal layer a first insulating layer 30, an active layer 40, a data line layer 50 (including: a data line 501, a source 502 and a drain 503), and a pixel electrode layer 60; wherein the gate 10, the first The insulating layer 30, the active layer 40, the data line layer 50 constitute a thin film transistor, the gate line 12 is used to provide an on signal to the thin film transistor, and the data line 501 is used to supply a data signal to the pixel electrode 60; wherein the pixel electrode 60 is also A
  • the pixel electrode 60 is generally designed as a planar hollow structure, as shown in FIG.
  • the data electrode layer 50 may be formed by patterning process, and then the pixel electrode layer 60 may be formed.
  • the pixel electrode layer 60 may be formed by a patterning process to form the data line layer 50.
  • the patterning process here mainly includes forming. Film, exposure and etching processes.
  • the array substrate further includes a protective layer 70 disposed over the thin film transistor and the pixel electrode 60, the protective layer 70 for protecting the thin film transistor from corrosion.
  • the display panel further includes a black matrix 80 disposed on the color filter substrate 200, the black matrix 80 for shielding a light leakage region.
  • a broken line AA, and a broken line BB the area defined is a non-display area of the pixel unit, a cylinder is referred to as a non-display area), a broken line BB, and a broken line CC.
  • the defined area is the display area of the pixel unit (the cartridge is referred to as a display area).
  • the materials used are generally metals such as Cr, W, Ti, Ta, Mo, Al, Cu, and alloys thereof, so that the metal
  • the parallel connection of the layer 11 and the common electrode layer 20 can reduce the resistance of the common electrode layer 20 to a certain extent, but due to the limitation of the width dl of the black matrix 80 on the color filter substrate, and to prevent the metal layer 11 and the gate electrode 10 from being A short circuit occurs, and the interval between the metal layer 11 and the gate electrode 10 is about 5 micrometers (um), so the width d2 of the metal layer 11 is very limited, and thus the common electrode layer is lowered.
  • the resistance effect of 20 is not very significant, but the manner of reducing the resistance of the common electrode layer 20 by increasing the length of d2 causes d2 to enter the inside of the display region, resulting in a decrease in pixel aperture ratio. Summary of the invention
  • An embodiment of the present invention provides an array substrate including a substrate substrate, gate lines arranged on the substrate substrate, data lines, and pixel units arranged in a matrix defined by the gate lines and the data lines.
  • Each of the pixel units is provided with a thin film transistor, a pixel electrode and a common electrode layer, the thin film transistor includes a gate, a first insulating layer, an active layer, a source and a drain, wherein the array substrate further includes :
  • a conductive black matrix disposed in a non-display area of the pixel unit, the black matrix being electrically connected to the common electrode layer;
  • a second insulating layer for insulating the black matrix and the common electrode layer from the thin film transistor.
  • a portion of the black matrix forms a direct surface contact with a portion of the common electrode layer.
  • the black matrix is disposed between the thin film transistor and the substrate substrate or disposed above the thin film transistor, and the second insulating layer is disposed on the thin film transistor and the black matrix between.
  • the material of the black matrix is a non-transparent metal material.
  • the black matrix is located above the common electrode layer, or the black matrix is located below the common electrode layer.
  • a projected overlap region of the black matrix and the common electrode layer on the base substrate does not overlap with a projection of the gate on the base substrate.
  • the array substrate further includes a passivation layer covering the thin film transistor and the pixel electrode.
  • the thin film transistor is a top gate type thin film transistor.
  • the thin film transistor is a bottom gate type thin film transistor.
  • Another embodiment of the present invention provides a display device comprising the array substrate of any of the above.
  • Another embodiment of the present invention provides a method for preparing an array substrate, including: Forming a common electrode layer of a pixel unit and a conductive black matrix on the substrate of the substrate, the black matrix is electrically connected to the common electrode layer, and the black matrix is disposed in a non-display area of the pixel unit; Forming a second insulating layer of the pixel unit on the substrate of the substrate, for insulating the black matrix and the common electrode layer from the thin film transistor to be formed;
  • a thin film transistor and a pixel electrode of the pixel unit are formed on a substrate of a village.
  • a portion of the black matrix forms a direct surface contact with a portion of the common electrode layer.
  • the black matrix is disposed between the thin film transistor and the substrate, the second insulating layer is disposed between the thin film transistor and the black matrix, and the substrate is Forming the common electrode layer and the conductive black matrix on the pixel unit: forming the black matrix on the substrate substrate; and forming a common electrode layer over the black matrix; or, on the substrate substrate Forming a common electrode layer thereon; and forming a black matrix over the common electrode layer; wherein the black matrix covers a non-display area of the pixel unit.
  • forming the thin film transistor and the pixel electrode of the pixel unit on the substrate of the substrate includes: forming a gate and a gate line of the thin film transistor over the second insulating layer; Forming a first insulating layer over the gate line; forming an active layer over the first insulating layer; and forming a source, a drain, and a pixel electrode of the thin film transistor over the active layer.
  • forming the thin film transistor and the pixel electrode of the pixel unit on the substrate of the substrate includes: forming a source, a drain, and a pixel electrode of the thin film transistor over the second insulating layer; An active layer is formed over the source, the drain, and the pixel electrode; a first insulating layer is formed over the active layer; and a gate and a gate line of the thin film transistor are formed over the first insulating layer .
  • the preparation method further includes: forming a passivation layer over the thin film transistor and the pixel electrode, the passivation layer covering a top surface of the thin film transistor and the pixel electrode.
  • FIG. 1 is a schematic cross-sectional view showing a pixel unit of a display panel in the prior art
  • 2 is a plan view showing a planar structure of a pixel unit of the display panel shown in FIG. 1
  • FIG. 3 is a plan view showing a planar structure of the pixel electrode of FIG.
  • FIG. 4 is a schematic cross-sectional view showing a pixel unit of an array substrate according to a first embodiment of the present invention
  • FIG. 5 is a schematic plan view showing a planar structure of a pixel unit of the array substrate shown in FIG. 4;
  • FIG. 6 is a schematic cross-sectional view showing a pixel unit of an array substrate according to a second embodiment of the present invention.
  • FIG. 7 is a schematic cross-sectional view of a pixel unit of an array substrate according to a third embodiment of the present invention.
  • FIG. 8 is a schematic cross-sectional view showing a pixel unit of an array substrate according to a fourth embodiment of the present invention.
  • FIG. 9 is a cross-sectional structural view of an array substrate fabricated by completing a black matrix and a common electrode layer according to an embodiment of the invention.
  • FIG. 10 is a schematic cross-sectional structural view of an array substrate on which a second insulating layer is formed;
  • FIG. 11 is a schematic cross-sectional view showing an array substrate on which a thin film transistor is formed
  • FIG. 12 is a schematic cross-sectional structural view of an array substrate on which pixel electrodes are formed
  • Figure 13 is a schematic cross-sectional view showing the array substrate after the black matrix and the common electrode layer are formed in the process of preparing the array substrate provided in the second embodiment.
  • the embodiment of the invention provides an array substrate, a preparation method thereof and a display panel, which can reduce the voltage difference of the common electrode layer between different pixel units and increase the aperture ratio of the pixel.
  • a first embodiment of the present invention provides an array substrate including a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other thereby defining pixel units arranged in a matrix, each of the pixel units being included as a switch
  • the gate of the thin film transistor of each pixel is electrically connected or integrally formed with the corresponding gate line
  • the source is electrically connected or integrally formed with the corresponding data line
  • the drain is electrically connected or integrated with the corresponding pixel electrode. to make.
  • the following description is mainly made for a single or a plurality of pixel units, but other pixel units may have the same structure and may be formed identically.
  • FIG. 4 is a cross-sectional structural view of a pixel unit of the array substrate according to the first embodiment of the present invention
  • FIG. 5 is a schematic plan view of a pixel unit of the array substrate shown in FIG. 4 and FIG. 5, it can be seen that the array substrate includes: a substrate substrate 1001, a black matrix 80, a common electrode layer 20, a second insulating layer 90, a gate electrode 10, a gate line 12, and a first pixel unit.
  • the black matrix 80 is located above the base substrate 1001, the material of the black matrix is a non-transparent metal material, and the black matrix made of a non-transparent metal material can have both conductive function and shading. Function, and the resistance of the metal material is much smaller than that used to make use of other non-transparent conductive materials.
  • the black matrix 80 has a width d3 covering a non-display area of the pixel unit for preventing transmission of light in the non-display area; since the black matrix 80 is disposed on the array substrate, the black matrix is designed. At 80 o'clock, there is no need to consider the accuracy error of the box, which is beneficial to reducing the size of the black matrix and increasing the aperture ratio of the pixel;
  • the black matrix 80 can also cover the channel region of the active layer 40, so that the light from the backlight to be irradiated to the active layer 40 is completely blocked, thereby reducing the leakage current of the active layer.
  • the common electrode layer 20 is located above the layer where the black matrix 80 is located, and is electrically connected to the black matrix 80.
  • the material of the common electrode layer 20 is transparent, for example, indium tin oxide, indium oxide or alumina. Oxide.
  • the width of the electrical connection portion of the black matrix 80 and the common electrode layer 20 is d4, and the coverage area of the electrical connection portion does not overlap with the coverage area of the gate 10 for preventing the common electrode layer 20
  • a coupling capacitor is formed between the gate 10 and the gate 10 so as not to affect the performance of the thin film transistor.
  • a covered area of a structure e.g., an electrical connection portion or a gate of the black matrix and the common electrode layer
  • the resistance of the conductive black matrix 80 is in parallel with the resistance of the common electrode layer 20, since the resistance value of the electrical connection portion is much smaller than the The resistance of the common electrode layer 20, therefore, the resistance of the total resistance after the parallel connection is much smaller than the resistance of the common electrode layer 20, thereby causing the voltage difference caused by the resistance of the common electrode layer 20. Reduced.
  • the second insulating layer 90 is disposed between the layer where the common electrode layer 20 is located and the layer where the gate electrode 10 and the gate line 12 are located, the coverage area of the second insulating layer and the black matrix and the The coverage areas of the common electrode layer overlap, that is, the second insulating layer covers the upper regions of the black matrix 80 and the common electrode layer 20 for the gate 10 of the thin film transistor and the black matrix 80
  • the common electrode layer 20 is insulated. Therefore, in the array substrate, it is not necessary to set the interval between the common electrode layer 20 and the gate line 10 to be larger than a predetermined distance due to the presence of the second insulating layer 90. It is advantageous to further reduce the size of the black matrix and increase the aperture ratio of the pixel.
  • the gate electrode 10 is disposed in the same layer as the gate line 12, and is located between the first insulating layer 30 and the second insulating layer 90, and the gate electrode 10 and the gate line 12 are made of the same material.
  • the material to be produced is generally a non-transparent metal such as Cr, W, Ti, Ta, Mo, Al, Cu, or the like.
  • the first insulating layer 30 is located above the gate 10 and the gate line 12, for example, covering the upper surface of the gate 10 and the gate line 12; in this embodiment, the material of the first insulating layer 30 is fabricated.
  • the thickness is, for example, about 20,000 angstroms.
  • the first insulating layer 30 can also be made of other insulating layer materials, and the thickness can also be determined according to actual needs.
  • the active layer 40 is located above the first insulating layer 30;
  • the data line 501, the source 502 and the drain 503 are disposed in the same layer, are located above the layer of the active layer 40, and are made of the same material;
  • the data line 501 is electrically connected to the source 502 and intersects with the gate line 12; the source 502 and the drain 503 are located on opposite sides of the active layer 40.
  • the pixel electrode 60 is disposed in the same layer as the data line 501, the source 502, and the drain 503, and the pixel electrode 60 is electrically connected to the drain 503.
  • the pixel electrode is, for example, indium tin oxide or indium oxide.
  • the transparent electrode material is made of a transparent oxide material such as alumina or alumina, and the pixel electrode has a slit shape.
  • the array substrate further includes, for example, a passivation layer 70 over the data line 501, the source 502, and the drain 503, the passivation layer 70 is for protecting the thin film transistor from being etched; the passivation layer 70 is for example It is formed using a transparent insulating material such as silicon nitride or silicon oxide.
  • the pixel unit in the conventional display panel shown in FIG. 2 and the pixel unit in the array substrate according to the embodiment of the present invention shown in FIGS. 4 and 5 are compared as an example to more clearly explain the implementation according to the present invention.
  • FIG. 1 and 2 are schematic cross-sectional structural views and planar structures of a pixel unit in a conventional display panel Schematic, the material and film thickness data of each layer of film are shown in Table 1;
  • FIG. 4 and FIG. 5 are schematic diagrams showing a cross-sectional structure and a planar structure of a pixel unit in an array substrate according to a first embodiment of the present invention.
  • materials and film thickness data of each layer film see Table 2; Material and film thickness data of each layer of the film in the array substrate provided in the examples
  • the pixel units shown in FIG. 2 and FIG. 5 are both 5.2-inch pixel structures with a resolution of 480 272, the pixel unit size is 80 X 240 um, the gate line 12 line width is 6 um, and the data line 501 line width is 4um.
  • the gate line capacitance of the pixel unit is increased from the original 5.91 10" 14 F to 3.72 10" 13 F, each data line capacitance from the original pixel unit 9.56 10 "14 F increases to 2.19 10" 13 F, the capacitance increases adds latency gate line and the data line, leading to reduce the charging time of the pixel unit, is This requires an increase in the charging current. Therefore, in the array substrate provided in the first embodiment, the width and length of the thin film transistor need to be respectively designed to be 17 um, 5 um for increasing the charging current to ensure normal display of the pixel unit.
  • the black matrix in parallel with the common electrode layer in the pixel unit
  • the gate line layer is of a non-same layer design, and there is no need to set a large interval between the black matrix and the gate line layer, and it is not necessary to consider the accuracy error of the box, so that the aperture ratio of the pixel unit is increased as a whole, the whole The aperture ratio of the pixel is increased from 72% to 75.5%.
  • the second embodiment of the present invention further provides an array substrate, the cross-sectional structure of which is shown in FIG. 6.
  • the array substrate and the array substrate provided by the first embodiment of the present invention shown in FIG. The structure is basically the same, the difference between the two is: in the array substrate shown in FIG. 4, the black matrix 80 is located between the base substrate 1001 and the common electrode layer 20; and in the array substrate shown in FIG. The black matrix 80 is located between the second insulating layer 90 and the common electrode layer 20.
  • the third embodiment of the present invention further provides an array substrate, and the cross-sectional structure thereof is as shown in FIG. 7.
  • the array substrate and the array substrate shown in FIG. 4 have basically the same structure, and the difference between the two.
  • the following is an array substrate in which the thin film transistor is a bottom gate structure as shown in FIG. 4, and an array substrate in which the thin film transistor is a top gate structure as shown in FIG. 7, in one example, in the array substrate shown in FIG.
  • the data line 501, the source 502 and the drain 503 are located above the second insulating layer 90, and the active layer 40 is located in the pattern including the data line 501, the source 502 and the drain 503.
  • the first insulating layer 30 is located above the active layer 40, and the gate 10 and the gate line 12 are located above the first insulating layer 30. Moreover, since the pixel electrode 60 is disposed in the same layer as the data line 501, the source 502, and the drain 503, the array substrate shown in FIG. The pixel electrode 60 is disposed between the first insulating layer 30 and the second insulating layer 90.
  • the fourth embodiment of the present invention further provides an array substrate, and the cross-sectional structure thereof is as shown in FIG. 8.
  • the array substrate and the array substrate shown in FIG. 7 have basically the same structure. The difference is: in the array substrate shown in FIG. 7, the black matrix 80 is located between the base substrate 1001 and the common electrode layer 20; and in the array substrate shown in FIG. 8, the black matrix 80 is located at the second insulating layer 90. And between the common electrode layer 20.
  • the array substrate provided in the first embodiment, the second embodiment, the third embodiment, and the fourth embodiment includes a black matrix having conductivity disposed above the substrate, the black matrix and the common electrode layer. Electrically connected, the resistance of the black matrix of the electrical connection portion is paralleled with the resistance of the common electrode layer, so that the total resistance of the electrical connection portion after the parallel connection is smaller than the resistance of the common electrode layer of the electrical connection portion, effectively reducing the resistance of the common electrode layer Value, thereby reducing the voltage difference of the common electrode layer between different pixel units; meanwhile, since the black matrix is disposed on the array substrate, it is not necessary to consider the accuracy error of the box, which is advantageous for reducing the width dimension of the black matrix and improving The aperture ratio of the pixel; at the same time, the array substrate is further provided with a second insulating layer for insulating the gate from the black matrix and the common electrode, so there is no need to be disposed between the common electrode layer and the gate A larger separation distance is used to prevent the gate from being short-circuited with the common
  • the black matrix may also be disposed above the thin film transistor.
  • the second insulating layer is disposed above the thin film crystal, and the black matrix is disposed above the second insulating layer.
  • the common electrode layer is disposed above/below the black matrix and electrically connected to the black matrix
  • the passivation layer is disposed above the common electrode layer and the black matrix
  • the pixel electrode is disposed at the passivation Above the layer, wherein the pixel electrode is in a slit shape, and the common electrode is in a plate shape or a slit shape;
  • the second insulating layer is disposed above the thin film transistor
  • the pixel electrode is disposed under the second insulating layer
  • the common electrode layer is disposed above the thin film transistor
  • the black matrix is disposed on the second insulating layer
  • the passivation layer is disposed above the black matrix and the common electrode layer; wherein the common electrode is slit-shaped,
  • the pixel electrode has a plate shape or a slit shape.
  • a method for fabricating an array substrate according to a fifth embodiment of the present invention comprising: forming a pattern including a common electrode layer and a black matrix having electrical conductivity on the base substrate, the black matrix and the common electrode Layer electrical connection, the black matrix is disposed in a non-display area of the pixel unit area;
  • a pattern including a thin film transistor and a pixel electrode is formed on the substrate of the substrate.
  • the array substrate prepared by the method includes a black matrix having electrical conductivity disposed above the substrate, the black matrix being electrically connected to the common electrode layer, and the electrical resistance of the black matrix of the electrical connection portion and the common electrode layer
  • the resistors are connected in parallel such that the total resistance after the parallel connection is smaller than the resistance of the common electrode layer, effectively reducing the resistance value of the common electrode layer, thereby reducing the voltage difference of the common electrode layer between different pixel units; meanwhile, due to the black
  • the matrix is disposed on the array substrate, and the accuracy of the box is not required to be considered, and the second insulating layer is disposed in the array substrate for insulating the gate from the black matrix and the common electrode, so A large separation distance is set between the common electrode and the gate electrode. Therefore, the width of the black matrix is smaller than that of the prior art black matrix, which is advantageous for increasing the aperture ratio of the pixel unit.
  • the method for preparing a pixel unit of the array substrate according to the embodiment of the present invention is as follows.
  • a pattern including a black matrix 80 and a common electrode layer 20 is formed on the substrate substrate 1001; in one example, the step includes:
  • the patterning process includes, for example: First, a non-transparent metal film for forming a black matrix is formed on the substrate substrate 1001 (such as sputtering or coating); then, a photoresist is coated on the metal film; A photoresist having a pattern including a black matrix exposes the photoresist; finally, after development and etching, a pattern including the black matrix 80 is formed.
  • the preparation process of the film layer formed by the patterning process is the same as that, and will not be described in detail later.
  • An indium tin oxide transparent conductive film is deposited by magnetron sputtering on the substrate substrate 1001 including the pattern of the black matrix 80, and a pattern including the common electrode layer 20 is formed by a patterning process;
  • the electrode layer 20 is electrically connected to the black matrix, and the width of the electrical connection portion is d4. Since the interval between the common electrode layer and the gate electrode is not required to be considered, the width of the electrical connection portion is wide.
  • the degree d4 is larger than the width d2 of the electrical connection portion of the metal layer and the common electrode line in the prior art.
  • a second insulating layer 90 (for example, a silicon nitride (SiN x ) or silicon oxide (SiO x ) layer) is deposited over the pattern including the black matrix 80 and the common electrode layer 20,
  • the second gate insulating layer 90 is for covering the upper regions of the black matrix 80 and the common electrode layer 20 for insulating the black matrix 80 and the common electrode layer 20 from the thin film transistor to be formed.
  • a pattern including a thin film transistor is formed over the second insulating layer 90.
  • the step specifically includes:
  • Step 31 depositing a metal thin film on the deposition above the second insulating layer 90, and then performing a patterning process to form a pattern including the gate electrode 10 and the gate line 12 (see FIG. 5) for forming a metal
  • the material of the film is a non-transparent metal such as Cr, W, Ti, Ta, Mo, Al, Cu or the like;
  • Step 32 depositing a first insulating layer 30 (for example, a silicon nitride (SiN x ) or silicon oxide (SiO x ) layer) over the pattern including the gate 10 and the gate line 12, the first gate insulating Layer 30 is for covering an upper region of the gate line and the gate for insulating the gate line and the gate from other layers to be formed;
  • a first insulating layer 30 for example, a silicon nitride (SiN x ) or silicon oxide (SiO x ) layer
  • Step 33 depositing an amorphous silicon semiconductor material over the first insulating layer 30, and then forming a pattern including the active layer 40 by a patterning process;
  • Step 34 forming a source/drain metal film over the pattern including the active layer 40, and then forming a pattern including the data line 501, the source 502, and the drain 503 by a patterning process.
  • a layer of indium tin oxide transparent conductive film is deposited on the first insulating layer 30 by magnetron sputtering, and a pattern including the pixel electrode 60 is formed by a patterning process, the pixel electrode 60 and the The data line 501, the source 502, and the drain 503 are disposed in the same layer, and the pixel electrode 60 is electrically connected to the drain 503.
  • Step 35 Referring to FIG. 4, a silicon nitride or silicon oxide layer is deposited over the pattern including the pixel electrode to form a passivation layer 70 for protecting the thin film transistor from corrosion.
  • the pixel unit of the array substrate shown in FIG. 4 according to the first embodiment of the present invention is formed.
  • the thin film transistor may be formed first to form the pixel electrode, or the pixel electrode may be formed first to form the thin film transistor.
  • the pixel unit of the array substrate provided by the second embodiment of the present invention, the preparation method and the preparation thereof The method for the pixel unit of the array substrate provided by the first embodiment of the present invention is similar, except that, in FIG. 13, in the process of fabricating the pixel unit of the array substrate provided by the second embodiment of the present invention, the substrate is The step of forming a pattern including a black matrix and a common electrode layer on the substrate includes, for example:
  • the common electrode layer 20 is electrically connected to the black matrix, and the width of the electrical connection portion is d4. Since the spacing between the common electrode layer and the gate electrode is not required to be considered, the width d4 of the electrical connection portion is greater than There is a technique in which the width d2 of the electrical connection portion of the metal layer and the common electrode line.
  • the method for preparing the pixel unit of the array substrate provided by the third embodiment of the present invention is similar to the method for preparing the pixel unit of the array substrate provided by the first embodiment of the present invention, except that, referring to FIG. 7, the present invention is fabricated.
  • the step of forming the pattern including the thin film transistor and the pixel electrode includes, for example:
  • the material for forming the metal thin film It is a non-transparent metal such as Cr, W, Ti, Ta, Mo, Al, Cu, or the like.
  • the pixel unit of the array substrate provided by the fourth embodiment of the present invention, the preparation method and the preparation thereof The method for the pixel unit of the array substrate provided by the third embodiment of the present invention is similar, except that, in the process of preparing the pixel unit of the array substrate provided by the fourth embodiment of the present invention, the substrate is in the process of preparing the pixel unit of the array substrate provided by the fourth embodiment of the present invention.
  • the step of forming a pattern including a black matrix and a common electrode layer on the substrate includes, for example:
  • the common electrode layer 20 is electrically connected to the black matrix, and the width of the electrical connection portion is d4. Since the spacing between the common electrode layer and the gate electrode is not required to be considered, the width d4 of the electrical connection portion is greater than There is a technique in which the width d2 of the electrical connection portion of the metal layer and the common electrode line.
  • the patterning process may include only a photolithography process, or may include a photolithography process and an etching process, and may also include printing, inkjet, and the like for forming a predetermined schedule.
  • the process of patterning; the lithography process refers to a process of forming a pattern by using a photoresist, a mask, an exposure machine, or the like, including a process of film formation, exposure, development, and the like.
  • the corresponding patterning process can be selected in accordance with the structure formed in the present invention.
  • an array substrate disposed above a thin film transistor is disposed for a black matrix, a common electrode layer, and a second insulating layer, and the manufacturing method thereof includes:
  • a pattern including a thin film transistor is formed on the base substrate, and a pattern including the pixel electrode and the second insulating layer are sequentially formed over the pattern including the thin film transistor, and a common electrode is formed over the second insulating layer A pattern of a layer and a black matrix, wherein a passivation layer is formed over the pattern including the common electrode layer and the black matrix, wherein the pixel electrode has a slit shape or a plate shape, and the common electrode layer has a slit shape.
  • the array substrate provided by the embodiment of the present invention includes a black matrix having conductivity disposed above the substrate, the black matrix and the common electrode layer being electrically connected, and the black matrix of the electrical connection portion.
  • the resistance is paralleled with the resistance of the common electrode layer, so that the total resistance of the electrically connected portions after the parallel connection is smaller than the resistance of the common electrode layer of the electrical connection portion, effectively reducing the resistance value of the common electrode layer, thereby reducing different pixel units
  • the voltage difference between the common electrode layers at the same time, since the black matrix is disposed on the array substrate, it is not necessary to consider the accuracy error of the box, which is advantageous for reducing the width dimension of the black matrix and increasing the aperture ratio of the pixel;
  • a second insulating layer is further disposed in the substrate for insulating the gate from the black matrix and the common electrode, so that a large separation distance between the common electrode layer and the gate is not required for preventing the gate
  • the short circuit of the pole and the common electrode layer is advantageous for further reducing the size of

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un substrat en réseau et un procédé associé, ainsi qu'un dispositif d'affichage. Le substrat en réseau selon l'invention contient, dans une unité de pixels : une matrice noire électriquement conductrice (80) disposée dans une zone de non-affichage de l'unité de pixels, ladite matrice (80) étant connectée électriquement à une couche d'électrode commune (20) ; et une deuxième couche d'isolation (90) destinée à isoler la matrice noire (80) et la couche d'électrode commune (20) d'un transistor en couches minces.
PCT/CN2013/088834 2013-08-28 2013-12-09 Substrat en réseau, procédé de fabrication associé et dispositif d'affichage WO2015027609A1 (fr)

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CN106200159A (zh) * 2016-07-07 2016-12-07 京东方科技集团股份有限公司 一种显示面板、显示装置及显示装置的显示调节方法
CN105974687B (zh) * 2016-07-20 2020-01-03 深圳市华星光电技术有限公司 一种阵列基板以及液晶显示器
CN105974691B (zh) * 2016-07-25 2019-05-07 深圳市华星光电技术有限公司 一种ffs模式的阵列基板及其制备方法
CN105974659B (zh) * 2016-07-29 2020-07-07 上海中航光电子有限公司 阵列基板及显示面板
JP6322247B2 (ja) * 2016-09-16 2018-05-09 Ｎｉｓｓｈａ株式会社 圧力センサ
CN106855670A (zh) * 2017-02-28 2017-06-16 厦门天马微电子有限公司 阵列基板、显示面板和显示装置
CN108628046B (zh) * 2017-03-23 2021-04-27 京东方科技集团股份有限公司 像素单元及其制造方法、阵列基板和显示装置
CN109801943B (zh) * 2019-01-09 2021-02-12 昆山国显光电有限公司 显示面板和显示装置
CN110061013B (zh) * 2019-04-23 2021-06-01 武汉华星光电技术有限公司 阵列基板及其制备方法
US11402711B2 (en) * 2019-07-16 2022-08-02 Fuzhou Boe Optoelectronics Technology Co., Ltd. Array substrate, display panel, display device and manufacturing method for array substrate
CN111539340B (zh) * 2020-04-26 2022-08-05 厦门天马微电子有限公司 一种显示面板、显示装置及驱动方法
CN111522181B (zh) * 2020-04-27 2023-05-05 深圳市华星光电半导体显示技术有限公司 一种阵列基板、显示面板及其制备方法
CN112379552A (zh) * 2020-12-03 2021-02-19 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法
CN113552751B (zh) * 2021-07-21 2023-11-07 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板、显示装置

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