WO2015021708A1 - 阵列基板及其制造方法、显示面板和显示装置 - Google Patents

阵列基板及其制造方法、显示面板和显示装置 Download PDF

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WO2015021708A1
WO2015021708A1 PCT/CN2013/088312 CN2013088312W WO2015021708A1 WO 2015021708 A1 WO2015021708 A1 WO 2015021708A1 CN 2013088312 W CN2013088312 W CN 2013088312W WO 2015021708 A1 WO2015021708 A1 WO 2015021708A1
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Prior art keywords
pattern
thin film
film transistor
amorphous silicon
temperature polysilicon
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English (en)
French (fr)
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李月
董学
薛海林
陈小川
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Priority to US14/389,115 priority Critical patent/US9508757B2/en
Publication of WO2015021708A1 publication Critical patent/WO2015021708A1/zh
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    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
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    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
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    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
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    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
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    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/425—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer having different crystal properties in different TFTs or within an individual TFT
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    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
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Definitions

  • the pixel region has a problem of excessive leakage current; when the array substrate is fabricated by using amorphous silicon (a-Si) technology, the patterned structure of the peripheral region is made.
  • a-Si amorphous silicon
  • An object of the present invention is to provide an array substrate and a method of fabricating the same, a display panel and a display device for reducing leakage current in a pixel region and realizing a narrow bezel design of the display panel and the display device.
  • the present invention provides an array substrate, including: a substrate substrate; and a pixel region and a peripheral region formed on the substrate substrate, wherein the peripheral region is located at a periphery of the pixel region,
  • the pixel region includes an amorphous silicon thin film transistor, and the peripheral region includes a low temperature polysilicon structure.
  • the low temperature polysilicon structure comprises a low temperature polysilicon thin film transistor.
  • the low temperature polysilicon thin film transistor is a top gate type low temperature polysilicon thin film crystal Tube.
  • the array substrate further includes: a buffer layer on the substrate, under the amorphous silicon thin film transistor and the low temperature polysilicon structure, and covering the entire substrate substrate.
  • the present invention also provides a display device comprising: the above display panel.
  • the present invention further provides a method for fabricating an array substrate, comprising the steps of: forming a pixel region and a peripheral region on a substrate, wherein the peripheral region is located at a periphery of the pixel region, The pixel region forms an amorphous silicon thin film transistor, and a low temperature polysilicon structure is formed in the peripheral region.
  • the low temperature polysilicon structure comprises a low temperature polysilicon thin film transistor.
  • the method for manufacturing the array substrate includes: forming a gate of the amorphous silicon thin film transistor on a base substrate of the pixel region; forming a gate above a gate of the amorphous silicon thin film transistor An insulating layer covering the entire base substrate; forming an amorphous silicon active layer pattern in the pixel region and forming a low temperature polysilicon pattern in the peripheral region over the gate insulating layer; Forming a gate insulating pattern over the pattern; forming a gate of the low temperature polysilicon thin film transistor over the gate insulating pattern; doping the low temperature polysilicon pattern to form the low temperature polysilicon active layer pattern; A source and a drain of the amorphous silicon thin film transistor are formed over the amorphous silicon active layer pattern, and a source drain pattern of the low temperature polysilicon thin film transistor is formed over the low temperature polysilicon active layer pattern.
  • the step of forming the low temperature polysilicon pattern comprises: forming an amorphous silicon material layer over the gate insulating layer, the amorphous silicon material layer covering the entire substrate; illuminating the pixel region by the UV substrate to The amorphous silicon material layer of the peripheral region is subjected to laser crystallization treatment to form a low temperature polysilicon material layer in the peripheral region; the amorphous silicon material layer located in the pixel region and the low temperature polysilicon material layer located in the peripheral region Performing a patterning process to form an amorphous silicon pattern in the pixel region and forming a low temperature polysilicon pattern in the peripheral region; forming an N+ amorphous silicon pattern over the amorphous silicon pattern of the pixel region, thereby forming the pixel region An amorphous silicon active layer pattern is formed.
  • the present invention has the following advantageous effects.
  • the display panel and the display device provided by the present invention since the pixel region of the array substrate adopts an a-si thin film transistor, the leakage current of the pixel region existing in the LTPS array substrate in the prior art is overcome. The problem is that the leakage current in the pixel region is reduced. At the same time, since the peripheral region of the array substrate adopts the LTPS structure, the narrow frame design of the display panel and the display device is realized. DRAWINGS
  • FIG. 1 is a schematic structural view of an array substrate according to an embodiment of the present invention.
  • 2 is a flow chart showing a method of fabricating an array substrate according to Embodiment 4 of the present invention.
  • Fig. 3a is a schematic view showing the gate electrode forming the a-Si thin film transistor in the fourth embodiment.
  • Fig. 3c is a schematic view showing the formation of an a-Si material layer in the fourth embodiment.
  • Figure 3d is a schematic illustration of the formation of a layer of LTPS material in Example 4.
  • Fig. 3e is a schematic view showing the formation of an a-Si active layer pattern and an LTPS pattern in the fourth embodiment.
  • Fig. 3f is a schematic view showing the formation of a gate insulating pattern in the fourth embodiment.
  • Fig. 3g is a schematic view showing the gate electrode forming the LTPS thin film transistor in the fourth embodiment.
  • Figure 3h is a schematic diagram of the formation of an LDD pattern in the fourth embodiment.
  • Fig. 3i is a schematic view showing the formation of an n-type doping pattern in the fourth embodiment.
  • Fig. 3j is a schematic view showing the formation of a p-type doping pattern in the fourth embodiment.
  • Fig. 3k is a schematic view showing the formation of an ILD pattern in the fourth embodiment.
  • FIG. 31 is a source and drain of an a-Si thin film transistor and an LTPS film formed in the fourth embodiment. Schematic diagram of the source and drain patterns of a transistor.
  • the array substrate includes: a substrate substrate 1; and a pixel region and a peripheral region formed on the substrate substrate 1, and the peripheral region is located at a periphery of the pixel region.
  • the pixel region includes an amorphous silicon (a-si) thin film transistor, and the peripheral region includes a low temperature polysilicon (LTPS) structure.
  • a-si amorphous silicon
  • LTPS low temperature polysilicon
  • FIG. 1 Only a partial structure of the pixel area and the peripheral area is shown in FIG. 1. It should be clear to those skilled in the art that the pixel area and the peripheral area shown in FIG. 1 should not be understood as a structure of a pixel area and The limitation of the structure of the peripheral region; in addition, the broken line in Fig. 1 is only a part of the structure of the array substrate, which can clearly show the pixel area and the peripheral area.
  • the a-Si thin film transistor is a bottom gate type a-Si thin film transistor
  • the LTPS structure includes an LTPS thin film transistor.
  • the LTPS thin film transistor is a top gate type LTPS thin film transistor.
  • the a-Si thin film transistor may alternatively be a top gate type thin film transistor, and the LTPS thin film transistor may also be a bottom gate type LTPS thin film transistor.
  • the a-Si thin film transistor includes an a-Si active layer pattern
  • the LTPS thin film transistor includes an LTPS active layer pattern.
  • the a-Si active layer pattern and the LTPS active layer pattern are formed in the same layer, i.e., at substantially the same level.
  • a buffer layer 2 is formed on the base substrate 1, and the buffer layer 2 is disposed on the base substrate 1, under the a-Si thin film transistor and the LTPS thin film transistor, and covers the entire base substrate 1.
  • the buffer layer 2 can effectively improve the performance of the LTPS thin film transistor.
  • the pixel region includes a pixel unit defined by a gate line and a data line, and the pixel unit includes an a-Si thin film transistor and a pixel electrode 3 connected to the a-Si thin film transistor.
  • the a-Si thin film transistor is a bottom gate type a-Si thin film transistor.
  • the a-Si thin film transistor includes a gate electrode 4, an a-Si active layer pattern 5, a source electrode 6, and a drain electrode 7.
  • Gate 4 Formed on the buffer layer 2, the a-Si active layer pattern 5 is formed over the gate electrode 4, and the source electrode 6 and the drain electrode 7 are both formed on the a-Si active layer pattern 5, the drain electrode 7 and the pixel electrode. 3 connections.
  • the array substrate further includes a gate insulating layer 8 located above the gate electrode 4 and below the a-Si active layer pattern 5, and covering the entire substrate substrate 1, BP, the gate insulating layer 8 is spread over the pixel region and The surrounding area.
  • the gate insulating layer 8 can be used to protect the gate 4 of the pixel region and enhance the performance of the LTPS thin film transistor.
  • the array substrate may further include a passivation layer 9 over the source 6 and the drain 7, and covering the entire substrate 1, BP, and the passivation layer 9 is spread over the pixel region and the peripheral region.
  • a via hole is disposed on the passivation layer 9 above the drain electrode 7, and the pixel electrode 3 is filled in the via hole to realize the connection between the pixel electrode 3 and the drain electrode 7.
  • the peripheral region includes the LTPS thin film transistor 10 and the LTPS thin film transistor 11.
  • the LTPS thin film transistor 10 includes an LTPS active layer pattern 101, a gate electrode 102, a source drain pattern 103, and a source drain pattern 104.
  • the LTPS active layer pattern 101 is over the gate insulating layer 8
  • the source drain pattern 103 and the source drain pattern 104 are over the LTPS active layer pattern 101
  • the gate 102 is over the LTPS active layer pattern 101 and at the source.
  • the LTPS active layer pattern 101 includes an LTPS sub-pattern 1011, an n-type doped pattern 1012 and an n-type doped pattern 1013 on both sides of the LTPS sub-pattern 1011.
  • the LTPS thin film transistor 11 includes an LTPS active layer pattern 111, a gate electrode 112, a source drain pattern 113, and a source drain pattern 114.
  • the LTPS active layer pattern 111 is over the gate insulating layer 8
  • the source drain pattern 113 and the source drain pattern 114 are over the LTPS active layer pattern 111
  • the gate 112 is over the LTPS active layer pattern 111 and at the source.
  • the LTPS active layer pattern 111 includes an LTPS sub-pattern 1111, a P-type doped pattern 1112 and a p-type doped pattern 1113 on both sides of the LTPS sub-pattern 1111.
  • the array substrate further includes a gate insulating pattern 12 over the LTPS active layer pattern 101 and the LTPS active layer pattern 111 and under the gate 102 and the gate 112.
  • the array substrate also includes an inner layer (Inter Layer Dielectric, ILD) graphic 13.
  • ILD Inter Layer Dielectric
  • the gate insulating pattern 12 and the ILD pattern 13 are provided with a plurality of via holes, and the source and drain patterns 103 are filled in the via holes to realize the connection of the source drain pattern 103 and the n-type doping pattern 1012, and the source drain pattern 104 is filled in In the via hole, the source-drain pattern 104 and the n-type doping pattern 1013 are connected, and the source-drain pattern 113 is filled in the via hole to realize the connection of the source-drain pattern 113 and the p-type doping pattern 1112, and the source and drain.
  • the pole pattern 114 is filled in the via to achieve the connection of the source drain pattern 114 and the p-type doping pattern 1113.
  • the LTPS active layer pattern 101 and the LTPS active layer pattern 111 are integrally formed, and the source and drain patterns 104 and the source and drain patterns 113 are integrally formed.
  • the source drain pattern 104 and the source drain pattern 113 may also be separately disposed, that is, the source drain pattern 104 and the source drain pattern 113 are not in contact; the LTPS active layer pattern 101 and the LTPS active layer pattern 111 are also It can be set separately, that is, the LTPS active layer pattern 101 and the LTPS active layer pattern 111 are not in contact.
  • the source drain pattern 103 may be a drain
  • the source drain pattern 104 may be a source
  • the source drain pattern 113 may be a source
  • the source drain pattern 114 may be a drain. pole.
  • the LTPS active layer pattern 101 since the LTPS active layer pattern 101 includes an n-type doping pattern 1012 and an n-type doping pattern 1013, the LTPS active layer pattern 111 includes a p-type doping pattern 1112 and a p-type doping pattern 1113, and thus LTPS
  • the thin film transistor 10 and the LTPS thin film transistor 11 constitute a Complementary Metal Oxide Semiconductor (hereinafter referred to as CMOS).
  • CMOS Complementary Metal Oxide Semiconductor
  • the LTPS active layer patterns of all the LTPS thin film transistors of the peripheral region may each include only the n-type doped pattern, or the LTPS active layer patterns of all the LTPS thin film transistors of the peripheral region may include only P-doped pattern.
  • the LTPS structure may also include metal lines.
  • the metal line is over the LTPS active layer pattern of the LTPS thin film transistor.
  • the metal wires may include metal test wires and/or metal leads. This situation is no longer specifically drawn.
  • the array substrate provided in this embodiment includes a substrate substrate and a pixel region and a peripheral region formed on the substrate, the peripheral region is located at a periphery of the pixel region, the pixel region includes an a-Si thin film transistor, and the peripheral region includes an LTPS structure. Since the pixel region adopts the a-si thin film transistor, the problem of excessive leakage current in the pixel region of the LTPS array substrate in the prior art is overcome, the leakage current in the pixel region is reduced, and at the same time, since the peripheral region adopts the LTPS structure, Therefore, a narrow bezel design of the display panel and the display device is realized.
  • Embodiment 2 of the present invention provides a display panel including an array substrate.
  • the array substrate may be the array substrate in the first embodiment, which is not described in detail herein.
  • the display panel may be a display panel of an Advanced Super Dimension Switch (ADS) device.
  • ADS Advanced Super Dimension Switch
  • Embodiment 3 of the present invention provides a display device including the above display panel.
  • the display device can be, for example, a display, a portable computer, a television, a handy phone, or the like.
  • a fourth embodiment of the present invention provides a method for fabricating an array substrate, the method comprising: forming a pixel region and a peripheral region on a substrate, wherein the peripheral region is located at a periphery of the pixel region, and forming an a-Si film in the pixel region The transistor and the LTPS structure are formed in the peripheral region.
  • the LTPS structure comprises an LTPS thin film transistor.
  • the gate of the amorphous silicon thin film transistor, the amorphous silicon active layer pattern, the source and the drain are formed in the pixel region, and the low temperature polysilicon active of the LTPS thin film transistor is formed in the peripheral region a layer pattern, a gate and a source/drain pattern, wherein the amorphous silicon active layer pattern and the low temperature polysilicon active layer pattern are formed in the same layer, that is, at substantially the same level.
  • the a-Si thin film transistor is formed in the pixel region, the problem of excessive leakage current in the pixel region existing in the LTPS array substrate in the prior art is overcome, and the leakage of the pixel region is reduced.
  • the LTPS structure is formed in the peripheral region, the narrow bezel design of the display panel and the display device is realized.
  • an a-Si thin film transistor is used as a bottom gate type a-Si thin film transistor and an LTPS thin film transistor is a top gate type LTPS thin film transistor as an example.
  • Step 101 Form a gate of the a-Si thin film transistor on the base substrate.
  • Fig. 3a is a schematic view showing the gate electrode forming the a-Si thin film transistor in the fourth embodiment.
  • a gate metal layer is formed on the base substrate 1, and a gate metal layer is patterned to form a gate electrode 4 on the base substrate 1.
  • a buffer layer 2 may be formed on the substrate substrate 1, and the buffer layer 2 is located under the gate electrode 4 and covers the entire substrate substrate 1.
  • FIG. 3b is a schematic view showing the formation of a gate insulating layer in the fourth embodiment.
  • a gate insulating layer 8 is formed over the gate electrode 4, for example, by a chemical vapor deposition method, and the gate insulating layer 8 covers the entire substrate substrate 1.
  • Step 103 above the gate insulating layer 8, forming an a-Si active layer pattern in the pixel region and forming an LTPS pattern in the peripheral region.
  • Sub-step 1031 forming an a-Si material layer over the gate insulating layer.
  • Fig. 3c is a schematic view showing the formation of an a-Si material layer in the fourth embodiment. As shown in Fig. 3c, an a-Si material layer 14 is formed on the gate insulating layer 8, for example, by a chemical vapor deposition method.
  • Sub-step 1032 illuminating the pixel region by a UV substrate (i.e., a UV-resistant glass substrate) to perform laser crystallization treatment on the a-Si material layer located in the peripheral region, thereby forming an LTPS material layer in the peripheral region.
  • a UV substrate i.e., a UV-resistant glass substrate
  • Figure 3d is a schematic illustration of the formation of a layer of LTPS material in Example 4. As shown in Figure 3d, through
  • the UV substrate occludes the pixel region to laser crystallization the a-Si material layer located in the peripheral region to form the LTPS material layer 15 in the peripheral region.
  • Sub-step 1033 patterning the a-Si material layer located in the pixel region and the LTPS material layer located in the peripheral region to form an a-Si pattern in the pixel region and an LTPS pattern in the peripheral region.
  • Fig. 3e is a schematic view showing the formation of an a-Si active layer pattern and an LTPS pattern in the fourth embodiment.
  • an a-Si pattern 51 is formed in the pixel region by the patterning process and an LTPS pattern 16 is formed in the peripheral region.
  • an N+ a-Si material layer is formed over the a-Si pattern 51 by, for example, a chemical vapor deposition method, and the N+ a-Si material layer is patterned to form an N+ a-Si pattern on the a_Si pattern 51.
  • N+ a-Si pattern 53 thereby forming a pattern including a_Si
  • N+ a-Si pattern 52 and N+ a-Si pattern 53 a_Si active layer pattern 5.
  • Step 104 Form a gate insulating pattern over the LTPS pattern.
  • Fig. 3f is a schematic view showing the formation of a gate insulating pattern in the fourth embodiment.
  • a gate insulating layer is formed over the LTPS pattern 16 by, for example, a chemical vapor deposition method, and the gate insulating layer is patterned to form a gate insulating pattern 12 over the LTPS pattern 16.
  • the material of 12 can be SiNx.
  • Step 105 Form a gate of the LTPS thin film transistor over the gate insulating pattern.
  • Fig. 3g is a schematic view showing the gate electrode forming the LTPS thin film transistor in the fourth embodiment.
  • a gate metal layer is formed over the gate insulating pattern 12 by, for example, a physical vapor deposition method, and a gate metal layer is patterned to form a gate electrode 102 and a gate electrode 112 on the gate insulating pattern 12. .
  • Step 106 Doping the LTPS pattern to form an LTPS active layer pattern.
  • step 106 specifically includes the following sub-steps.
  • the LDD pattern 161 is n-type doped to form an n-type doped pattern 1012 and an n-type doped pattern 1013, as shown in Figure 3i.
  • Fig. 3i is a schematic view showing the formation of an n-type doping pattern in the fourth embodiment.
  • a photoresist layer is coated on the pixel region and the peripheral region, and a photoresist pattern covering the undoped region is formed by patterning to protect each structural pattern of the undoped region; then, the LDD pattern is 161. The n-type doping is performed; finally, the photoresist pattern is removed.
  • Sub-step 1063 p-doping the LDD pattern 161 to form a p-type doping pattern 1112 and a p-type doping pattern 1113, as shown in Figure 3j.
  • Fig. 3j is a schematic view showing the formation of a p-type doping pattern in the fourth embodiment.
  • a photoresist layer is coated on the pixel region and the peripheral region, and a photoresist pattern covering the undoped region is formed by patterning to protect each structural pattern of the undoped region; then, the LDD pattern is 161. P-type doping is performed; finally, the photoresist pattern is removed.
  • the LTPS active layer pattern 101 formed by the step 106 includes an LTPS sub-pattern 1011, an n-type doping pattern 1012 and an n-type doping pattern 1013 located on both sides of the LTPS sub-pattern 1011.
  • the formed LTPS active layer pattern 111 includes an LTPS sub-pattern 1111 and is located at LTPS.
  • Fig. 3k is a schematic view showing the formation of an ILD pattern in the fourth embodiment. As shown in FIG. 3k, an ILD material layer is deposited over the gate 102 and the gate 112, and the ILD material layer is patterned to form an ILD pattern 13.
  • Step 108 Dehydrogenating the LTPS active layer pattern.
  • Step 109 forming a source and a drain of the a-Si thin film transistor over the a-Si active layer pattern, and forming a source-drain pattern of the LTPS thin film transistor over the LTPS active layer pattern.
  • FIG. 31 is a view showing the source and drain electrodes of the a-Si thin film transistor and the source and drain patterns of the LTPS thin film transistor in the fourth embodiment.
  • step 109 specifically includes:
  • the method further includes: forming a plurality of via holes on the ILD pattern, so that the source drain pattern 103 is filled in the via holes to realize connection of the source drain pattern 103 and the n-type doping pattern 1012, the source The drain pattern 104 is filled in the via hole to connect the source drain pattern 104 and the n-type doping pattern 1013, and the source drain pattern 113 is filled in the via hole to implement the source drain pattern 113 and the p-type doping pattern 1112.
  • the connection, and the source drain pattern 114 are filled in the via to achieve the connection of the source drain pattern 114 and the p-type doping pattern 1113.
  • Step 110 forming a passivation layer (PVX) over the source and drain of the a-Si thin film transistor and the source-drain pattern of the LTPS thin film transistor.
  • PVX passivation layer
  • Figure 3m is a schematic view showing the formation of a passivation layer in the fourth embodiment.
  • a source 6 and a drain 7 of the a_Si thin film transistor and a source/drain pattern 103, a source/drain pattern 104, a source/drain pattern 113, and a source/drain pattern 114 of the LTPS thin film transistor are formed.
  • a passivation layer 9 covering the entire array substrate.
  • the step 111 may specifically include: forming a via hole on the passivation layer 9 over the drain electrode 7 of the a-Si thin film transistor; then forming a pixel electrode material layer on the passivation layer 9; Patterning the pixel electrode material layer to form the pixel electrode 3, thereby
  • the pixel electrode 3 is filled in the via hole to achieve connection with the drain electrode 7.
  • the patterning process of the present invention may include: processing steps of photoresist coating, exposure, development, etching, photoresist stripping, and the like.
  • the manufacturing method of the array substrate provided in this embodiment includes forming a pixel region and a peripheral region on the substrate, the peripheral region is located at the periphery of the pixel region, forming an a-Si thin film transistor in the pixel region, and forming an LTPS structure in the peripheral region. Since the pixel region adopts the a-si thin film transistor, the problem of excessive leakage current in the pixel region of the LTPS array substrate in the prior art is overcome, the leakage current in the pixel region is reduced, and at the same time, since the peripheral region adopts the LTPS structure, Therefore, a narrow bezel design of the display panel and the display device is realized.

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Abstract

一种阵列基板及其制造方法、显示面板和显示装置，该阵列基板包括：衬底基板（1）；以及形成于衬底基板（1）上的像素区和周边区，其中，所述周边区位于所述像素区周边，所述像素区包括非晶硅薄膜晶体管，所述周边区包括低温多晶硅结构。由于阵列基板的像素区采用了非晶硅薄膜晶体管，因此克服了现有技术中低温多晶硅阵列基板中存在的像素区漏电流过大的问题，降低了像素区的漏电流，同时，由于阵列基板的周边区采用了低温多晶硅结构，因此实现了显示面板及显示装置的窄边框设计。

Description

阵列基板及其制造方法、 显示面板和显示装置 技术领域
本发明涉及显示技术领域， 特别涉及阵列基板及其制造方法、 显示 面板和显示装置。 背景技术
在显示技术领域，非晶硅（a-Si )技术和低温多晶硅（Low Temperature Poly-silicon, 简称： LTPS)技术应用较为广泛。其中， 随着显示技术的 发展， LTPS技术凭借其高效能和高清晰的特点，得到了越来越广泛的应用。
现有技术中， 当采用 LTPS技术制成阵列基板时， 其像素区存在漏电 流过大的问题； 当采用非晶硅（a-Si )技术制成阵列基板时， 其周边区的 构图结构使得包括该阵列基板的显示面板及显示装置难以实现窄边框设 计。
综上所述， 现有技术中还没有一种在降低像素区漏电流的同时能够 使得显示面板及显示装置实现窄边框设计的技术方案。 发明内容
本发明的目的是提供一种阵列基板及其制造方法、 显示面板和显示 装置， 用于降低像素区的漏电流， 并实现显示面板及显示装置的窄边框设 计。
为实现上述目的， 本发明提供了一种阵列基板， 包括： 衬底基板； 以及形成于所述衬底基板上的像素区和周边区， 其中， 所述周边区位于所 述像素区的周边， 所述像素区包括非晶硅薄膜晶体管， 所述周边区包括低 温多晶硅结构。
可选地， 所述非晶硅薄膜晶体管为底栅型非晶硅薄膜晶体管。
可选地， 所述低温多晶硅结构包括低温多晶硅薄膜晶体管。
可选地， 所述低温多晶硅薄膜晶体管为顶栅型低温多晶硅薄膜晶体 管。
可选地， 所述阵列基板还包括： 缓冲层， 其位于所述衬底基板上、 及所述非晶硅薄膜晶体管和所述低温多晶硅结构下方，且覆盖整个衬底基 板。
可选地， 所述非晶硅薄膜晶体管包括非晶硅有源层图形， 所述低温 多晶硅薄膜晶体管包括低温多晶硅有源层图形，所述非晶硅有源层图形和 所述低温多晶硅有源层图形同层形成。
为实现上述目的， 本发明还提供了一种显示面板， 包括： 上述阵列 基板。
为实现上述目的， 本发明还提供了一种显示装置， 包括： 上述显示 面板。
为实现上述目的， 本发明还提供了一种阵列基板的制造方法， 包括 步骤： 在衬底基板上形成像素区和周边区， 其中， 所述周边区位于所述像 素区的周边， 在所述像素区形成非晶硅薄膜晶体管， 在所述周边区形成低 温多晶硅结构。
可选地， 所述低温多晶硅结构包括低温多晶硅薄膜晶体管。
可选地， 在所述像素区形成所述非晶硅薄膜晶体管的栅极、 非晶硅 有源层图形、源极和漏极， 以及在所述周边区形成所述低温多晶硅薄膜晶 体管的低温多晶硅有源层图形、 栅极和源漏极图形， 其中， 所述非晶硅有 源层图形和所述低温多晶硅有源层图形同层形成。
可选地， 所述阵列基板的制造方法包括： 在所述像素区的衬底基板 上形成所述非晶硅薄膜晶体管的栅极；在所述非晶硅薄膜晶体管的栅极的 上方形成栅绝缘层，该栅绝缘层覆盖整个衬底基板；在所述栅绝缘层上方， 在所述像素区形成非晶硅有源层图形以及在所述周边区形成低温多晶硅 图形； 在所述低温多晶硅图形的上方形成栅绝缘图形； 在所述栅绝缘图形 的上方形成所述低温多晶硅薄膜晶体管的栅极；对所述低温多晶硅图形进 行掺杂处理， 形成所述低温多晶硅有源层图形； 在所述非晶硅有源层图形 的上方形成所述非晶硅薄膜晶体管的源极和漏极， 以及在所述低温多晶硅 有源层图形的上方形成所述低温多晶硅薄膜晶体管的源漏极图形。
可选地， 在所述像素区形成非晶硅有源层图形以及在所述周边区形
2 成低温多晶硅图形的步骤包括： 在所述栅绝缘层的上方形成非晶硅材料 层， 该非晶硅材料层覆盖整个衬底基板； 通过 UV基板对所述像素区进行 遮挡， 以对位于所述周边区的非晶硅材料层进行激光晶化处理， 从而在所 述周边区形成低温多晶硅材料层；对位于所述像素区的非晶硅材料层和位 于所述周边区的低温多晶硅材料层进行构图处理， 以在所述像素区形成非 晶硅图形以及在所述周边区形成低温多晶硅图形；在所述像素区的非晶硅 图形上方形成 N+非晶硅图形， 从而在所述像素区形成非晶硅有源层图形。
本发明具有以下有益效果。
本发明提供的阵列基板及其制造方法、 显示面板和显示装置中， 由 于阵列基板的像素区采用了 a-si 薄膜晶体管， 因此克服了现有技术中 LTPS阵列基板存在的像素区漏电流过大的问题， 降低了像素区的漏电流， 同时， 由于阵列基板的周边区采用了 LTPS结构， 因此实现了显示面板及 显示装置的窄边框设计。 附图说明
图 1为根据本发明的实施例一提供的一种阵列基板的结构示意图。 图 2为根据本发明的实施例四提供的一种阵列基板的制造方法的流 程图。
图 3a为实施例四中形成 a-Si薄膜晶体管的栅极的示意图。
图 3b为实施例四中形成栅绝缘层的示意图。
图 3c为实施例四中形成 a-Si材料层的示意图。
图 3d为实施例四中形成 LTPS材料层的示意图。
图 3e为实施例四中形成 a-Si有源层图形和 LTPS图形的示意图。 图 3f为实施例四中形成栅绝缘图形的示意图。
图 3g为实施例四中形成 LTPS薄膜晶体管的栅极的示意图。
图 3h为实施例四中形成 LDD图形的示意图。
图 3i为实施例四中形成 n型掺杂图形的示意图。
图 3j为实施例四中形成 p型掺杂图形的示意图。
图 3k为实施例四中形成 ILD图形的示意图。
图 31为实施例四中形成 a-Si薄膜晶体管的源极和漏极及 LTPS薄膜 晶体管的源漏极图形的示意图。
图 3m为实施例四中形成钝化层的示意图。 具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案， 下面结合附 图对本发明提供的阵列基板及其制造方法、显示面板和显示装置进行详细 描述。
图 1 为根据本发明的实施例一提供的一种阵列基板的结构示意图。 如图 1所示， 该阵列基板包括： 衬底基板 1; 以及形成于衬底基板 1上的 像素区和周边区， 周边区位于像素区的周边。 像素区包括非晶硅（a-si ) 薄膜晶体管， 周边区包括低温多晶硅（LTPS)结构。
需要说明的是， 图 1 中仅示出了像素区和周边区的部分结构， 本领 域技术人员应当清楚， 图 1中所示出的像素区和周边区不应被理解为对像 素区结构和周边区结构的限制； 另外， 图 1中的虚线仅为了能够清楚地表 示出像素区和周边区， 并非阵列基板结构的一部分。
本实施例中， 优选地， a-Si薄膜晶体管为底栅型 a-Si薄膜晶体管， LTPS结构包括 LTPS薄膜晶体管。其中， 优选地， LTPS薄膜晶体管为顶栅 型 LTPS薄膜晶体管。
在实际应用中， 可选地， a-Si薄膜晶体管还可以为顶栅型薄膜晶体 管， 而 LTPS薄膜晶体管还可以为底栅型 LTPS薄膜晶体管。
本实施例中， a-Si薄膜晶体管包括 a-Si有源层图形， LTPS薄膜晶 体管包括 LTPS有源层图形。优选地， a-Si有源层图形和 LTPS有源层图形 同层形成， 即设置在大致相同的水平高度上。
可选地，衬底基板 1上形成有缓冲层 2，缓冲层 2位于衬底基板 1上、 及 a-Si薄膜晶体管和 LTPS薄膜晶体管下方， 且覆盖整个衬底基板 1。 缓 冲层 2可有效提高 LTPS薄膜晶体管的性能。
本实施例中， 具体地， 像素区包括栅线和数据线限定的像素单元， 像素单元包括 a-Si薄膜晶体管和与该 a-Si薄膜晶体管连接的像素电极 3。 本实施例中， a-Si薄膜晶体管为底栅型 a-Si薄膜晶体管。 具体地， a-Si 薄膜晶体管包括栅极 4、 a-Si有源层图形 5、 源极 6和漏极 7。 栅极 4形 成于缓冲层 2之上， a-Si有源层图形 5形成于栅极 4上方，源极 6和漏极 7均形成于 a-Si有源层图形 5之上，漏极 7与像素电极 3连接。其中， a_Si 有源层图形 5包括 a-Si图形 51和位于 a-Si图形 51之上的 N+ a-Si图形 52和 N+ a_Si图形 53， 源极 6位于 N+ a_Si图形 53之上， 漏极 7位于 N+ a-Si图形 52之上。 N+ a-Si图形 53可减小源极 6与 a_Si有源层图形 5 之间的接触电阻， N+ a-Si图形 52可减小漏极 7与 a_Si有源层图形 5之 间的接触电阻。 阵列基板还包括栅绝缘层 8， 栅绝缘层 8位于栅极 4的上 方、及 a-Si有源层图形 5的下方， 且覆盖整个衬底基板 1， BP, 栅绝缘层 8遍布像素区和周边区。栅绝缘层 8可用于保护像素区的栅极 4并提升 LTPS 薄膜晶体管的性能。 阵列基板还可以包括钝化层 9， 钝化层 9位于源极 6 和漏极 7的上方， 且覆盖整个衬底基板 1， BP, 钝化层 9遍布像素区和周 边区。 漏极 7上方的钝化层 9上设置有过孔， 像素电极 3填充于过孔中， 以实现像素电极 3与漏极 7之间的连接。
本实施例中， 具体地， 周边区包括 LTPS薄膜晶体管 10和 LTPS薄膜 晶体管 11。
LTPS薄膜晶体管 10包括 LTPS有源层图形 101、栅极 102、源漏极图 形 103和源漏极图形 104。 LTPS有源层图形 101位于栅绝缘层 8之上， 源 漏极图形 103和源漏极图形 104位于 LTPS有源层图形 101之上，栅极 102 位于 LTPS有源层图形 101上方、及处于源漏极图形 103和源漏极图形 104 之间。 LTPS有源层图形 101包括 LTPS子图形 1011、位于 LTPS子图形 1011 两侧的 n型掺杂图形 1012和 n型掺杂图形 1013。
LTPS薄膜晶体管 11包括 LTPS有源层图形 111、栅极 112、源漏极图 形 113和源漏极图形 114。 LTPS有源层图形 111位于栅绝缘层 8之上， 源 漏极图形 113和源漏极图形 114位于 LTPS有源层图形 111之上，栅极 112 位于 LTPS有源层图形 111上方、及处于源漏极图形 113和源漏极图形 114 之间。 LTPS有源层图形 111包括 LTPS子图形 1111、位于 LTPS子图形 1111 两侧的 P型掺杂图形 1112和 p型掺杂图形 1113。
阵列基板还包括栅绝缘图形 12， 栅绝缘图形 12位于 LTPS有源层图 形 101和 LTPS有源层图形 111之上， 且位于栅极 102和栅极 112之下。 阵列基板还包括内保护层 （Inter Layer Dielectric, 简称： ILD) 图形 13， ILD图形 13位于栅极 102和栅极 112之上。 栅绝缘图形 12和 ILD图 形 13上设置有多个过孔， 源漏极图形 103填充于过孔中以实现源漏极图 形 103和 n型掺杂图形 1012的连接， 源漏极图形 104填充于过孔中以实 现源漏极图形 104和 n型掺杂图形 1013的连接， 源漏极图形 113填充于 过孔中以实现源漏极图形 113和 p型掺杂图形 1112的连接， 以及源漏极 图形 114填充于过孔中以实现源漏极图形 114和 p型掺杂图形 1113的连 接。本实施例中， LTPS有源层图形 101和 LTPS有源层图形 111一体成型， 源漏极图形 104和源漏极图形 113—体成型。在实际应用中，源漏极图形 104和源漏极图形 113还可以单独设置， 即源漏极图形 104和源漏极图形 113不接触； LTPS有源层图形 101和 LTPS有源层图形 111也可以单独设 置， 即 LTPS有源层图形 101和 LTPS有源层图形 111不接触。作为一种优 选方案， 可以设置成源漏极图形 103为漏极， 而源漏极图形 104为源极， 或者替代地设置成源漏极图形 113为源极， 而源漏极图形 114为漏极。
本实施例中，由于 LTPS有源层图形 101包括 n型掺杂图形 1012和 n 型掺杂图形 1013， LTPS有源层图形 111包括 p型掺杂图形 1112和 p型掺 杂图形 1113，因此 LTPS薄膜晶体管 10和 LTPS薄膜晶体管 11组成互补金 属氧化物半导体 (Complementary Metal Oxide Semiconductor, 以下简 称： CMOS) ， CMOS的优点在于其功耗低。
在实际应用中， 可选地， 周边区的所有 LTPS薄膜晶体管的 LTPS有 源层图形可以均仅包括 n型掺杂图形， 或者周边区的所有 LTPS薄膜晶体 管的 LTPS有源层图形可以均仅包括 p型掺杂图形。
在实际应用中， 可选地， LTPS结构还可以包括金属线。 优选地， 金 属线位于 LTPS薄膜晶体管的 LTPS有源层图形之上。金属线可包括金属测 试线和 /或金属引线。 此种情况不再具体画出。
本实施例提供的阵列基板包括衬底基板及形成于衬底基板上的像素 区和周边区， 周边区位于像素区的周边， 像素区包括 a-si薄膜晶体管， 周边区包括 LTPS结构。 由于像素区采用了 a-si薄膜晶体管， 因此克服了 现有技术中 LTPS阵列基板存在的像素区漏电流过大的问题， 降低了像素 区的漏电流， 同时， 由于周边区采用了 LTPS结构， 因此实现了显示面板 及显示装置的窄边框设计。 本发明的实施例二提供了一种显示面板， 该显示面板包括阵列基板。 其中， 阵列基板可采用上述实施例一中的阵列基板， 此处不再具体描述。 优选地， 显示面板可以为高级超维场转换 （Advanced Super Dimension Switch, 简称： ADS)装置的显示面板。
本发明的实施例三提供了一种显示装置， 其包括上述显示面板。 显 示装置可以为例如显示器、 便携式电脑、 电视、 手持电话等。
本发明的实施例四提供了一种阵列基板的制造方法， 该方法包括： 在衬底基板上形成像素区和周边区， 其中， 周边区位于像素区的周边， 在 像素区形成 a-Si薄膜晶体管以及在周边区形成 LTPS结构。
本实施例中， 优选地， LTPS结构包括 LTPS薄膜晶体管。其中， 在所 述像素区形成所述非晶硅薄膜晶体管的栅极、非晶硅有源层图形、源极和 漏极， 以及在所述周边区形成所述 LTPS薄膜晶体管的低温多晶硅有源层 图形、 栅极和源漏极图形， 其中， 所述非晶硅有源层图形和所述低温多晶 硅有源层图形同层形成， 即设置在大致相同的水平高度上。
本实施例提供的阵列基板的制造方法中， 由于在像素区形成 a-si薄 膜晶体管， 因此克服了现有技术中 LTPS阵列基板存在的像素区漏电流过 大的问题， 降低了像素区的漏电流， 同时， 由于在周边区形成 LTPS结构， 因此实现了显示面板及显示装置的窄边框设计。
下面通过实施例四对本发明提供的阵列基板的制造方法进行详细描 述。 本实施例以 a-Si薄膜晶体管为底栅型 a-Si薄膜晶体管以及 LTPS薄 膜晶体管为顶栅型 LTPS薄膜晶体管为例进行描述。
图 2为根据本发明的实施例四提供的一种阵列基板的制造方法的流 程图。 如图 2所示， 该方法包括以下步骤。
步骤 101、 在衬底基板上形成 a-Si薄膜晶体管的栅极。
图 3a为实施例四中形成 a-Si薄膜晶体管的栅极的示意图。 如图 3a 所示， 在衬底基板 1上形成栅极金属层， 对栅极金属层进行构图处理， 以 在衬底基板 1上形成栅极 4。 可选地， 在形成栅极 4之前， 还可以在衬底 基板 1上形成缓冲层 2， 该缓冲层 2位于栅极 4的下方， 且覆盖整个衬底 基板 1。
步骤 102、 在 a-Si薄膜晶体管的栅极的上方形成栅绝缘层。 图 3b为实施例四中形成栅绝缘层的示意图。 如图 3b所示， 例如通 过化学气相淀积方法在栅极 4的上方形成栅绝缘层 8， 栅绝缘层 8覆盖整 个衬底基板 1。
步骤 103、 在栅绝缘层 8的上方， 在像素区形成 a-Si有源层图形以 及在周边区形成 LTPS图形。
本实施例中， 步骤 103具体包括以下子步骤。
子步骤 1031、 在栅绝缘层的上方形成 a-Si材料层。
图 3c为实施例四中形成 a-Si材料层的示意图。 如图 3c所示， 例如 通过化学气相淀积方法在栅绝缘层 8上形成 a-Si材料层 14。
子步骤 1032、 通过 UV基板（glass) (即， 防紫外线玻璃基板）对 像素区进行遮挡， 以对位于周边区的 a-Si材料层进行激光晶化处理， 从 而在周边区形成 LTPS材料层。
图 3d为实施例四中形成 LTPS材料层的示意图。 如图 3d所示， 通过
UV基板（glass)对像素区进行遮挡， 以对位于周边区的 a-Si材料层进行 激光晶化处理， 从而在周边区形成 LTPS材料层 15。
子步骤 1033、 对位于像素区的 a-Si材料层和位于周边区的 LTPS材 料层进行构图处理， 以在像素区形成 a-Si图形以及在周边区形成 LTPS图 形。
子步骤 1034、 在 a-Si图形上方形成 N+ a-Si图形， 从而形成像素区 的 a-Si有源层图形。
图 3e为实施例四中形成 a-Si有源层图形和 LTPS图形的示意图。如 图 3e所示， 通过构图处理在像素区形成 a-Si图形 51以及在周边区形成 LTPS图形 16。 可选地， 例如通过化学气相淀积方法在 a-Si图形 51上方 形成 N+ a-Si材料层， 对 N+ a-Si材料层进行构图处理， 以在 a_Si图形 51上形成 N+ a-Si图形 52和 N+ a-Si图形 53， 从而形成包括 a_Si图形
51、 N+ a-Si图形 52和 N+ a-Si图形 53的 a_Si有源层图形 5。
步骤 104、 在 LTPS图形的上方形成栅绝缘图形。
图 3f 为实施例四中形成栅绝缘图形的示意图。 如图 3f 所示， 例如 通过化学气相淀积方法在 LTPS图形 16上方形成栅绝缘层，对栅绝缘层进 行构图处理， 以在 LTPS图形 16的上方形成栅绝缘图形 12。 栅绝缘图形
8 12的材料可以为 SiNx。
步骤 105、 在栅绝缘图形的上方形成 LTPS薄膜晶体管的栅极。
图 3g为实施例四中形成 LTPS薄膜晶体管的栅极的示意图。 如图 3g 所示， 例如通过物理气相淀积方法在栅绝缘图形 12的上方形成栅极金属 层， 对栅极金属层进行构图处理， 以在栅绝缘图形 12上形成栅极 102和 栅极 112。
步骤 106、 对 LTPS图形进行掺杂处理， 以形成 LTPS有源层图形。 本实施例中， 步骤 106具体包括以下子步骤。
子步骤 1061、对 LTPS图形 16进行轻掺杂漏区（Lightly Doped Drain region, 简称： LDD)掺杂， 形成 LDD图形 161以及位于栅极 102下方的 LTPS子图形 1011和位于栅极 112下方的 LTPS子图形 1111，如图 3h所示。 图 3h为实施例四中形成 LDD图形的示意图。
具体地， 在像素区和周边区上涂覆一层光刻胶， 通过构图处理形成 覆盖像素区的光刻胶图形， 以保护像素区的各结构图形； 然后， 对 LTPS 图形 16进行 LDD掺杂； 最后， 去除光刻胶图形。
子步骤 1062、 对 LDD图形 161进行 n型掺杂， 以形成 n型掺杂图形 1012和 n型掺杂图形 1013， 如图 3i所示。 图 3i为实施例四中形成 n型 掺杂图形的示意图。
具体地， 在像素区和周边区上涂覆一层光刻胶， 通过构图处理形成 覆盖非掺杂区的光刻胶图形，以保护非掺杂区的各结构图形；然后，对 LDD 图形 161进行 n型掺杂； 最后， 去除光刻胶图形。
子步骤 1063、 对 LDD图形 161进行 p型掺杂， 以形成 p型掺杂图形 1112和 p型掺杂图形 1113， 如图 3j所示。 图 3j为实施例四中形成 p型 掺杂图形的示意图。
具体地， 在像素区和周边区上涂覆一层光刻胶， 通过构图处理形成 覆盖非掺杂区的光刻胶图形，以保护非掺杂区的各结构图形；然后，对 LDD 图形 161进行 p型掺杂； 最后， 去除光刻胶图形。
综上所述， 通过步骤 106形成的 LTPS有源层图形 101包括 LTPS子 图形 1011、 位于 LTPS子图形 1011两侧的 n型掺杂图形 1012和 n型掺杂 图形 1013。形成的 LTPS有源层图形 111包括 LTPS子图形 1111、位于 LTPS 子图形 1111两侧的 p型掺杂图形 1112和 p型掺杂图形 1113。
步骤 107、 在 LTPS薄膜晶体管的栅极的上方形成 ILD图形。
图 3k为实施例四中形成 ILD图形的示意图。 如图 3k所示， 在栅极 102和栅极 112的上方沉积 ILD材料层， 对 ILD材料层进行构图处理， 以 形成 ILD图形 13。
步骤 108、 对 LTPS有源层图形进行去氢处理。
步骤 109、在 a-Si有源层图形的上方形成 a-Si薄膜晶体管的源极和 漏极，以及在 LTPS有源层图形的上方形成 LTPS薄膜晶体管的源漏极图形。
图 31为实施例四中形成 a-Si薄膜晶体管的源极和漏极以及 LTPS薄 膜晶体管的源漏极图形的示意图。 如图 31所示， 步骤 109具体包括： 在
ILD图形上方形成源漏极金属层， 对源漏极金属层进行构图处理， 以形成 a-Si薄膜晶体管的源极 6和漏极 7、 以及 LTPS薄膜晶体管的源漏极图形 103、 源漏极图形 104、 源漏极图形 113和源漏极图形 114。进一步地， 在 执行步骤 109之前还包括： 在 ILD图形上形成多个过孔， 从而源漏极图形 103填充于过孔中以实现源漏极图形 103和 n型掺杂图形 1012的连接，源 漏极图形 104填充于过孔中以实现源漏极图形 104和 n型掺杂图形 1013 的连接，源漏极图形 113填充于过孔中以实现源漏极图形 113和 p型掺杂 图形 1112的连接， 以及源漏极图形 114填充于过孔中以实现源漏极图形 114和 p型掺杂图形 1113的连接。
步骤 110、在 a-Si薄膜晶体管的源极和漏极以及 LTPS薄膜晶体管的 源漏极图形的上方形成钝化层 （PVX) 。
图 3m为实施例四中形成钝化层的示意图。 如图 3m所示， 在 a_Si薄 膜晶体管的源极 6和漏极 7、 以及 LTPS薄膜晶体管的源漏极图形 103、源 漏极图形 104、 源漏极图形 113和源漏极图形 114的上方形成钝化层 9， 该钝化层 9覆盖整个阵列基板。
步骤 111、在像素区， 在钝化层的上方形成像素电极， 该像素电极与 像素区的漏极连接。
如图 1所示， 步骤 111具体可包括： 在钝化层 9上形成过孔， 过孔 位于 a-Si薄膜晶体管的漏极 7上方； 然后， 在钝化层 9上形成像素电极 材料层； 对该像素电极材料层进行构图处理， 以形成像素电极 3， 从而该
10 像素电极 3被填充于过孔中以实现与漏极 7的连接。
优选地， 本发明所述的构图处理可包括： 光刻胶涂覆、 曝光、 显影、 刻蚀、 光刻胶剥离等处理步骤。
需要说明的是， 本实施例中各步骤的执行顺序可根据实际需要进行 变更。
本实施例提供的阵列基板的制造方法包括在衬底基板上形成像素区 和周边区， 周边区位于像素区的周边， 在像素区形成 a-Si薄膜晶体管， 在周边区形成 LTPS结构。 由于像素区采用了 a-si薄膜晶体管， 因此克服 了现有技术中 LTPS阵列基板存在的像素区漏电流过大的问题， 降低了像 素区的漏电流， 同时， 由于周边区采用了 LTPS结构， 因此实现了显示面 板及显示装置的窄边框设计。
可以理解的是， 以上实施方式仅仅是为了说明本发明的原理而采用 的示例性实施方式， 然而本发明并不局限于此。本发明的实施例可以省略 上述技术特征中的一些技术特征， 仅解决现有技术中存在的部分技术问 题， 而且， 所公开的技术特征可以进行任意组合。对于本领域内的普通技 术人员而言， 在不脱离本发明的精神和实质的情况下， 可以做出各种变型 和改进， 这些变型和改进也视为本发明的保护范围。本发明的保护范围由 所附权利要求限定。
11

Claims

权 利 要 求 书
1、 一种阵列基板， 包括：
衬底基板； 以及
形成于所述衬底基板上的像素区和周边区， 其中， 所述周边区位于 所述像素区的周边， 所述像素区包括非晶硅薄膜晶体管， 所述周边区包括 低温多晶硅结构。
2、 根据权利要求 1所述的阵列基板， 其特征在于， 所述非晶硅薄膜 晶体管为底栅型非晶硅薄膜晶体管。
3、 根据权利要求 1所述的阵列基板， 其特征在于， 所述低温多晶硅 结构包括低温多晶硅薄膜晶体管。
4、 根据权利要求 3所述的阵列基板， 其特征在于， 所述低温多晶硅 薄膜晶体管为顶栅型低温多晶硅薄膜晶体管。
5、 根据权利要求 3所述的阵列基板， 其特征在于， 所述非晶硅薄膜 晶体管包括非晶硅有源层图形，所述低温多晶硅薄膜晶体管包括低温多晶 硅有源层图形，所述非晶硅有源层图形和所述低温多晶硅有源层图形同层 形成。
6、 根据权利要求 1所述的阵列基板， 其特征在于， 还包括： 缓冲层， 其位于所述衬底基板上、 及所述非晶硅薄膜晶体管和所述 低温多晶硅结构下方， 且覆盖整个衬底基板。
7、 一种显示面板， 其特征在于， 包括： 权利要求 1至 6中任一项所 述的阵列基板。
8、一种显示装置，其特征在于，包括：权利要求 7所述的显示面板。
9、 一种阵列基板的制造方法， 其特征在于， 包括步骤：
在衬底基板上形成像素区和周边区， 其中， 所述周边区位于所述像 素区的周边，在所述像素区形成非晶硅薄膜晶体管以及在所述周边区形成 低温多晶硅结构。
10、 根据权利要求 9所述的阵列基板的制造方法， 其特征在于， 所 述低温多晶硅结构包括低温多晶硅薄膜晶体管。
11、 根据权利要求 10所述的阵列基板的制造方法， 其特征在于， 在 所述像素区形成所述非晶硅薄膜晶体管的栅极、非晶硅有源层图形、源极 和漏极， 以及在所述周边区形成所述低温多晶硅薄膜晶体管的低温多晶硅 有源层图形、 栅极和源漏极图形， 其中， 所述非晶硅有源层图形和所述低 温多晶硅有源层图形同层形成。
12、 根据权利要求 11所述的阵列基板的制造方法， 其特征在于， 包 括：
在所述像素区的衬底基板上形成所述非晶硅薄膜晶体管的栅极； 在所述非晶硅薄膜晶体管的栅极的上方形成栅绝缘层， 该栅绝缘层 覆盖整个衬底基板；
在所述栅绝缘层上方， 在所述像素区形成非晶硅有源层图形以及在 所述周边区形成低温多晶硅图形；
在所述低温多晶硅图形的上方形成栅绝缘图形；
在所述栅绝缘图形的上方形成所述低温多晶硅薄膜晶体管的栅极； 对所述低温多晶硅图形进行掺杂处理， 形成所述低温多晶硅有源层 图形；
在所述非晶硅有源层图形的上方形成所述非晶硅薄膜晶体管的源极 和漏极， 以及在所述低温多晶硅有源层图形的上方形成所述低温多晶硅薄 膜晶体管的源漏极图形。
13
13、 根据权利要求 12所述的阵列基板的制造方法， 其特征在于， 在 所述像素区形成非晶硅有源层图形以及在所述周边区形成低温多晶硅图 形的步骤包括：
在所述栅绝缘层的上方形成非晶硅材料层， 该非晶硅材料层覆盖整 个衬底基板；
通过防紫外线基板对所述像素区进行遮挡， 以对位于所述周边区的 非晶硅材料层进行激光晶化处理，从而在所述周边区形成低温多晶硅材料 层；
对位于所述像素区的非晶硅材料层和位于所述周边区的低温多晶硅 材料层进行构图处理， 以在所述像素区形成非晶硅图形以及在所述周边区 形成低温多晶硅图形；
在所述像素区的非晶硅图形上方形成 N+非晶硅图形， 从而在所述像 素区形成非晶硅有源层图形。
14
PCT/CN2013/088312 2013-08-16 2013-12-02 阵列基板及其制造方法、显示面板和显示装置 Ceased WO2015021708A1 (zh)

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