WO2015014053A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

Info

Publication number
WO2015014053A1
WO2015014053A1 PCT/CN2013/088109 CN2013088109W WO2015014053A1 WO 2015014053 A1 WO2015014053 A1 WO 2015014053A1 CN 2013088109 W CN2013088109 W CN 2013088109W WO 2015014053 A1 WO2015014053 A1 WO 2015014053A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate insulating
pixel electrode
data line
layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2013/088109
Other languages
English (en)
French (fr)
Inventor
郭建
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing BOE Optoelectronics Technology Co Ltd
Original Assignee
Beijing BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing BOE Optoelectronics Technology Co Ltd filed Critical Beijing BOE Optoelectronics Technology Co Ltd
Publication of WO2015014053A1 publication Critical patent/WO2015014053A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/42—Materials having a particular dielectric constant

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • a conventional liquid crystal display panel includes an array substrate, a color filter substrate, and a liquid crystal disposed between the array substrate and the color filter substrate.
  • the array substrate in the liquid crystal display comprises: a transparent substrate 1 and a gate metal layer, a gate insulating layer 7, a passivation layer 8, a source/drain metal layer, and a transparent conductive layer sequentially disposed on the transparent substrate 1.
  • the gate metal layer includes: a gate line 2 and a gate 31.
  • the source/drain metal layer includes: a data line 4, a common electrode line 6, a source 32 and a drain 33, and the transparent conductive layer comprises: a pixel electrode 5. As shown in FIG.
  • Embodiments of the present invention provide an array substrate, a method of fabricating the same, and a display device.
  • the array substrate can reduce the capacitance between the common electrode line and the pixel electrode, and reduce the interference of the common electrode line to the pixel electrode.
  • An embodiment of the present invention provides an array substrate, including: a substrate substrate, and a gate insulating layer, a pixel electrode layer, and a data line metal layer disposed on the substrate of the substrate, wherein the data line metal layer includes a data line, and the pixel electrode
  • the layer includes a pixel electrode; a thickness of a region of the gate insulating layer corresponding to the pixel electrode and the data line is smaller than a thickness of a region of the gate insulating layer corresponding to the pixel electrode and/or a thickness of a region of the gate insulating layer corresponding to the data line.
  • the gate insulating layer is located below the data line and the pixel electrode.
  • the gate insulating layer is located above the data line and the pixel electrode.
  • the gate insulating layer is located above the pixel electrode and under the data line.
  • the gate insulating layer is located below the pixel electrode and above the data line.
  • the thickness of the gate insulating layer between the pixel electrode and the data line is the gate insulating layer and The thickness of the region corresponding to the pixel electrode and/or the thickness of the region corresponding to the gate insulating layer and the data line
  • the thickness of the region where the gate insulating layer is located between the pixel electrode and the data line is 1/2 of the thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • the embodiment of the invention provides a display device, which comprises the array substrate provided by the embodiment of the invention.
  • the embodiment of the present invention provides a method for fabricating an array substrate, including: forming a gate insulating layer, a pixel electrode layer, and a data line metal layer on a substrate substrate, wherein the data line metal layer includes a data line, and the pixel electrode layer includes a pixel
  • Forming a gate insulating layer on the substrate of the substrate comprises: forming a gate insulating film on the substrate of the substrate, and etching the gate insulating film such that a thickness of a region between the pixel insulating layer corresponding to the pixel electrode and the data line is smaller than The thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • the gate insulating layer is located below the data line and the pixel electrode.
  • the gate insulating film and the pixel electrode layer are formed on the substrate substrate in this order, the gate insulating film is etched before the data line metal layer is formed on the substrate substrate.
  • the gate insulating film and the data line metal layer are sequentially formed on the substrate of the substrate, the gate insulating film is etched before the pixel electrode layer is formed on the substrate.
  • the gate is insulated.
  • the film is etched.
  • the gate insulating layer is located above the data line and the pixel electrode.
  • a gate insulating film is formed on the substrate, and the gate insulating film on the substrate is etched.
  • the gate insulating layer is located above the pixel electrode and under the data line.
  • the gate insulating film, and the data line metal layer are sequentially formed on the substrate of the substrate, the gate insulating film is etched.
  • the gate insulating film is etched before the data line metal layer is formed on the substrate substrate.
  • the gate insulating layer is located below the pixel electrode and above the data line.
  • a data line metal layer, a gate insulating film, and a pixel electrode are sequentially formed on the substrate of the substrate. After the layer, the gate insulating film is etched.
  • the gate insulating film is etched before the pixel electrode layer is formed on the substrate.
  • the thickness of the region where the gate insulating layer is located between the pixel electrode and the data line is 1/5-4 of the thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line. 5.
  • the thickness of the region where the gate insulating layer is located between the pixel electrode and the data line is 1/2 of the thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • FIG. 1 is a schematic top plan view of a conventional array substrate pixel unit
  • Figure 2 is a partial cross-sectional structural view of Figure 1;
  • FIG. 3 is a schematic partial cross-sectional structural view of a pixel unit of an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic partial cross-sectional structural view of another array substrate pixel unit according to an embodiment of the present invention.
  • FIG. 5 is a schematic partial cross-sectional structural view of another array substrate pixel unit according to an embodiment of the present invention.
  • FIG. 6 is a schematic partial cross-sectional structural view of another array substrate pixel unit according to an embodiment of the present invention.
  • FIG. 7 is a schematic partial cross-sectional structural view of another array substrate pixel unit according to an embodiment of the present invention.
  • FIG. 8 is a schematic partial cross-sectional structural view of another array substrate pixel unit according to an embodiment of the present invention.
  • FIG. 9 is a schematic partial cross-sectional structural view of another array substrate pixel unit according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 13 is a schematic view showing the etching of the gate insulating film formed on the substrate of the substrate in the manufacturing method shown in FIG.
  • FIG. 14 is a schematic diagram of forming a data line on a substrate of the substrate in the manufacturing method shown in FIG. 10;
  • FIG. 15 is a schematic diagram of another method for fabricating an array substrate according to an embodiment of the present invention;
  • FIG. 17 is a schematic view showing the etching of the gate insulating film formed on the substrate of the substrate in the manufacturing method shown in FIG. 15;
  • FIG. 14 is a schematic diagram of forming a data line on a substrate of the substrate in the manufacturing method shown in FIG. 10;
  • FIG. 15 is a schematic diagram of another method for fabricating an array substrate according to an embodiment of the present invention;
  • FIG. 17 is a schematic view showing the etching of the gate insulating film formed on the substrate of the substrate in the manufacturing method shown in FIG. 15;
  • FIG. 18 is a schematic diagram of forming a pixel electrode on a substrate of the substrate in the manufacturing method shown in FIG. 15;
  • FIG. 19 is a schematic diagram of another method for fabricating an array substrate according to an embodiment of the present invention;
  • FIG. A schematic diagram of forming a pixel electrode and a data line on a substrate of a village;
  • FIG. 21 is a schematic view showing the etching of the gate insulating film formed on the substrate of the substrate in the manufacturing method shown in FIG. 19;
  • FIG. 22 is a schematic diagram of another method for fabricating an array substrate according to an embodiment of the present invention
  • FIG. 23 is a schematic diagram of another method for fabricating an array substrate according to an embodiment of the present invention
  • FIG. 25 is a schematic diagram of another method for fabricating an array substrate according to an embodiment of the present invention
  • FIG. 26 is a schematic diagram of another method for fabricating an array substrate according to an embodiment of the present invention.
  • 1-village substrate 2-gate line; 3-thin film transistor; 31-gate; 32-source; 33-drain; 4-data line; 5-pixel electrode; 6- common electrode line; Insulation layer; 70-gate insulating film; 8-passivation layer.
  • An embodiment of the present invention provides an array substrate, as shown in FIG. 3 to FIG. 9, including a gate insulating layer 7, a pixel electrode layer, and a data line metal layer disposed on a substrate of the substrate, wherein the data line metal layer includes data.
  • the pixel electrode layer includes the pixel electrode 5; the thickness of the region of the gate insulating layer 7 corresponding to the pixel electrode 5 and the data line 4 is smaller than the thickness of the region of the gate insulating layer 7 corresponding to the pixel electrode 5 and/or the gate insulating layer 7 The thickness of the area corresponding to the data line 4.
  • the gate insulating layer is generally first deposited with a gate insulating film during the fabrication process, and then the gate insulating film is etched, wherein the thickness of the deposited gate insulating film is the same.
  • the thickness of the region between the pixel electrode and the data line formed by the gate insulating layer formed after the etching is smaller than the thickness of the region corresponding to the gate insulating layer and the pixel electrode. And/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • the array substrate in the drawings of the present invention is a partially enlarged view, and the present invention is not submerged for the sake of clarity. Only the film or layer structure related to the present invention is shown in the drawings, and other structures are omitted, which does not indicate that the present invention only Including these layers or structures, embodiments of the invention may also include other desired film layers or structural features.
  • the thickness of the region between the pixel insulating layer corresponding to the pixel electrode and the data line is smaller than the thickness of the region corresponding to the pixel insulating layer and the pixel electrode and/or the thickness of the region corresponding to the gate insulating layer and the data line, and may be corresponding to the gate insulating layer.
  • a thickness of a region between the pixel electrode and the data line is smaller than a thickness of a region of the gate insulating layer corresponding to the pixel electrode; and a thickness of a region between the pixel electrode and the data line corresponding to the gate insulating layer may be smaller than a gate insulating layer corresponding to the data line.
  • the "upper” and “lower” are based on the order of fabricating the film or the layer structure, for example, the film or layer structure which is previously produced may be “below”, and the film or layer which is fabricated later.
  • the structure is "on,,.
  • film refers to a film formed by deposition or other processes on a substrate using a certain material. If the “film” does not require a patterning process throughout the manufacturing process, the “film” may also be referred to as a “layer”; if the “film” requires a patterning process throughout the manufacturing process, it is referred to as "before the patterning process”.
  • the gate insulating layer may be formed by depositing a SiNx (silicon nitride) film on the transparent substrate 1 and etching the formed silicon nitride film to obtain the gate insulating layer. Of course, the formed silicon nitride film may be etched by other purposes such as via etching.
  • the gate insulating film is etched such that a thickness of a region between the pixel insulating layer corresponding to the pixel electrode and the data line is smaller than a thickness of the region corresponding to the gate insulating layer and the pixel electrode and/or a gate insulating layer The thickness of the area corresponding to the data line.
  • An embodiment of the present invention provides an array substrate, wherein a thickness of a region between a pixel electrode and a data line of the gate insulating layer on the array substrate is smaller than a thickness of a region corresponding to the gate insulating layer and the pixel electrode, and/or a gate insulating layer
  • the thickness of the region corresponding to the data line therefore, the storage capacitor formed between the pixel electrode and the data line is almost generated by the insulating layer or the passivation layer, and the interlayer capacitance is small, which can ensure the normality of the electrode signal and improve the display effect.
  • the gate insulating layer is located below the data line and the pixel electrode.
  • the array substrate includes a gate, an active layer, a source layer and a drain, wherein the gate, the source and the drain are three electrodes of the thin film transistor, and the source and the drain are disposed and insulated in the same layer. .
  • An insulating film layer between the active layer and the gate is insulated from the source and the drain.
  • thin film transistors are classified into two types according to the positional relationship between the active layer and the gate: one type is that the gate is under the active layer (and the source and the drain), and this type is called a bottom gate type thin film transistor; One type is that the gate is on the active layer (and the source and drain), and this type is called a top-gate thin film transistor.
  • the above-described top gate type thin film transistor and bottom gate type thin film transistor have their source and drain electrodes disposed in the same layer.
  • there is a side gate type thin film transistor having a source and a drain which are adjacent to the substrate in the direction of the vertical substrate and one away from the substrate.
  • the thin film transistor on the array substrate is a bottom gate type thin film transistor, which may be as shown in FIGS.
  • the thickness of the region of the gate insulating layer 7 corresponding to the pixel electrode 5 and the data line 4 is smaller than the thickness of the region of the gate insulating layer 7 corresponding to the pixel electrode 5 and the gate insulating layer 7 corresponds to the data line 4.
  • the thickness of the area As shown in FIG. 4, the thickness of the region of the gate insulating layer 7 corresponding to the pixel electrode 5 and the data line 4 is smaller than the thickness of the region of the gate insulating layer 7 corresponding to the pixel electrode 5. As shown in FIG.
  • the thickness of the region between the pixel electrode 5 and the data line 4 of the gate insulating layer 7 is smaller than that of the gate insulating layer 7 and the data.
  • the gate insulating layer is located above the data line and the pixel electrode, and the thin film transistor on the array substrate is a top gate type thin film transistor.
  • the thickness of the region between the pixel electrode 5 and the data line 4 of the gate insulating layer 7 is smaller than the thickness of the region corresponding to the gate insulating layer 7 and the pixel electrode 5, and the gate insulating layer 7 and the data.
  • the gate insulating layer is located above the pixel electrode and below the data line.
  • the gate insulating layer 7 is located above the pixel electrode 5 and below the data line 4.
  • the thickness of the region between the pixel insulating layer 7 and the data line 4 of the gate insulating layer 7 is smaller than the thickness of the region of the gate insulating layer 7 corresponding to the pixel electrode 5 and the thickness of the region of the gate insulating layer 7 corresponding to the data line 4.
  • the thickness of the region between the pixel insulating layer corresponding to the pixel electrode and the data line may be smaller than the gate insulating layer and the pixel electrode.
  • the thickness of the corresponding region or the thickness of the region corresponding to the data line of the gate insulating layer is exemplified by way of example only in FIG. 8 in the embodiment of the present invention.
  • the gate insulating layer is located below the pixel electrode and above the data line.
  • the gate insulating layer 7 is located below the pixel electrode 5 and above the data line 4.
  • the thickness of the region between the pixel insulating layer 7 and the data line 4 of the gate insulating layer 7 is smaller than the thickness of the region of the gate insulating layer 7 corresponding to the pixel electrode 5 and the thickness of the region of the gate insulating layer 7 corresponding to the data line 4.
  • the thickness of the region between the pixel insulating layer corresponding to the pixel electrode and the data line may be smaller than the gate insulating layer and the pixel electrode.
  • the thickness of the corresponding region or the thickness of the region corresponding to the data line of the gate insulating layer is exemplified in the embodiment of the present invention by way of example only in FIG.
  • the thickness of the region of the gate insulating layer between the pixel electrode and the data line is 1/5 of a thickness of a region of the gate insulating layer corresponding to the pixel electrode and/or a thickness of a region corresponding to the gate insulating layer and the data line. 4/5.
  • the thickness of the region where the gate insulating layer is located between the pixel electrode and the data line is 1/2 of the thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • the embodiment of the present invention further provides a display device, including the array substrate according to any one of the embodiments of the present invention.
  • the display device may be a liquid crystal display, an electronic paper, or an OLED (Organic) Display devices such as Light-Emitting Diode (OLED) displays, and any products or components having display functions such as televisions, digital cameras, mobile phones, and tablets including these display devices.
  • OLED Organic LED
  • the embodiment of the invention further provides a method for fabricating an array substrate, comprising: forming a gate insulating layer, a pixel electrode layer, and a data line metal layer on a substrate substrate, wherein the data line metal layer comprises a data line, and the pixel electrode layer comprises a pixel
  • Forming a gate insulating layer on the substrate of the substrate comprises: forming a gate insulating film on the substrate of the substrate and etching the gate insulating film such that a thickness of a region between the pixel insulating layer corresponding to the pixel electrode and the data line is smaller than a gate The thickness of the region of the insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • the order of making each layer or film on the array substrate may be different according to the arrangement on the array substrate.
  • the thin film transistor on the array substrate is a top gate thin film transistor and the thin film transistor on the array substrate is different in the fabrication method of the bottom gate thin film transistor, and the fabrication method of the same thin film transistor array substrate is also different. A method of fabricating an array substrate including these two types of thin film transistors will be described in detail below.
  • the gate insulating layer 7 is formed under the data line 4 and the pixel electrode 5.
  • an embodiment of the present invention provides a method for fabricating an array substrate, including:
  • Step S101 forming a gate insulating film on the substrate of the village.
  • a gate insulating film 70 is formed on the substrate 1 on the substrate.
  • the substrate substrate shown may be a transparent substrate or a substrate formed with another film or layer structure.
  • the substrate substrate shown may be a substrate on which a gate metal layer is formed, such as a glass, plastic, or quartz substrate.
  • the method of forming the film or layer structure may be a conventional manner of forming a film or layer structure in the art, such as deposition, sputtering, or the like.
  • Step S102 forming a pixel electrode layer on the substrate of the village.
  • the pixel electrode layer shown includes a pixel electrode, and as shown in Fig. 12, a pixel electrode 5 is formed on the substrate 1 on which the gate insulating film 70 is formed.
  • the gate insulating film is etched, and the gate insulating layer 7 formed after etching is as shown in FIG. Shown.
  • the etching of the gate insulating film can be performed by dry etching. Of course, other etching methods can also be used.
  • the thickness of the region of the gate insulating layer between the pixel electrode and the data line is 1/5 of a thickness of a region of the gate insulating layer corresponding to the pixel electrode and/or a thickness of a region corresponding to the gate insulating layer and the data line. 4/5.
  • the thickness of the region where the gate insulating layer is located between the pixel electrode and the data line is 1/2 of the thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • Step S104 forming a data line metal layer on the substrate of the village.
  • the substrate after the data line metal layer formed on the substrate 1 is as shown in Fig. 14.
  • the data line metal layer includes: a data line 4 and a source and a drain (not shown).
  • a source and a drain of the thin film transistor may be formed while forming a data line metal layer to form a data line. pole.
  • the fabrication of the array substrate is not limited to the above steps, and may further include other steps according to the film or layer structure on the array substrate, and only the film or layer structure related to the present invention is used in the embodiment of the present invention.
  • the fabrication is described as an example to make the description clearer, and other film or layer structures can be specifically fabricated according to the specific conditions of the array substrate.
  • a passivation layer 8 may be disposed on the array substrate, and a passivation layer 8 is formed after the above steps.
  • the gate insulating film and the data line metal layer are sequentially formed on the substrate of the substrate, the gate insulating film is etched before the pixel electrode layer is formed on the substrate.
  • the production methods shown include:
  • Step S201 forming a gate insulating film on the substrate of the village.
  • the formation of the gate insulating film on the substrate of the substrate can be carried out by referring to the above step S101.
  • the data line metal layer shown includes a data line, a source and a drain, and as shown in Fig. 16, a data line 4 is formed on the substrate substrate 1.
  • the data line metal layer includes: a data line 4 and a source and a drain (not shown).
  • a source and a drain of the thin film transistor may be formed while forming a data line metal layer to form a data line. pole.
  • Step S203 etching the gate insulating film.
  • the gate insulating layer 7 formed by etching the gate insulating film is as shown in FIG.
  • the etching of the gate insulating film can be performed by dry etching.
  • other etching methods can also be used.
  • the thickness of the region of the gate insulating layer between the pixel electrode and the data line is a gate insulating layer and a pixel electrode pair.
  • the thickness of the area to be applied and/or the thickness of the area corresponding to the gate insulating layer and the data line is 1/5 to 4/5.
  • the thickness of the region where the gate insulating layer is located between the pixel electrode and the data line is 1/2 of the thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • Step S204 forming a pixel electrode layer on the substrate of the village.
  • the array substrate after the pixel electrode 5 is formed on the substrate 1 is as shown in Fig. 18. It should be noted that the fabrication of the array substrate is not limited to the above steps, and may further include other steps according to the film or layer structure on the array substrate. In the embodiment of the present invention, only the film or layer structure related to the present invention is fabricated. For example, the description will be made to make the description clearer, and other film or layer structures are specifically fabricated according to the specific conditions of the array substrate. For example, a passivation layer 8 may be disposed on the array substrate, and the array substrate formed after the above steps is as shown in FIG.
  • the gate is The insulating film is etched. It should be noted that the order in which the pixel electrode layer and the data line metal layer are formed may be interchanged. For example, as shown in FIG. 19, the manufacturing method includes:
  • Step S301 forming a gate insulating film on the substrate of the village.
  • the step S101 can be referred to by forming a gate insulating film on the substrate of the substrate.
  • Step S302 forming a pixel electrode layer and a data line metal layer on the substrate of the village.
  • the pixel electrode layer and the data line metal layer are formed on the substrate of the substrate, and the data electrode metal layer may be formed after the pixel electrode layer is formed on the array substrate or after the data line metal layer is formed on the array substrate.
  • a pixel electrode is formed again, and a pixel electrode layer or a data line metal layer is formed on the substrate of the substrate as shown in FIG.
  • Step S303 etching the gate insulating film.
  • the gate insulating layer 7 formed by etching the gate insulating film is as shown in Fig.21.
  • the thickness of the region of the gate insulating layer between the pixel electrode and the data line is 1/5 of the thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region corresponding to the gate insulating layer and the data line. 4/5.
  • the thickness of the region where the gate insulating layer is located between the pixel electrode and the data line is 1/2 of the thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • the fabrication of the array substrate is not limited to the above steps, according to the array substrate.
  • the film or layer structure may further include other steps.
  • only the film or layer structure related to the present invention is described as an example.
  • Other film or layer structures are specifically fabricated according to the specific conditions of the array substrate.
  • a passivation layer 8 may be disposed on the array substrate, and the array substrate formed after the above steps is as shown in FIG. 3.
  • the gate insulating layer 7 is located above the data line 4 and the pixel electrode 5.
  • the manufacturing method includes:
  • Step S401 forming a data line metal layer and a pixel electrode layer on the substrate of the village.
  • the pixel electrode layer or the data line metal layer is formed on the substrate of the substrate, and the data electrode metal layer is formed after the pixel electrode layer is formed on the array substrate, or the data line metal layer is formed on the array substrate. Pixel electrode.
  • Step S402 forming a gate insulating film on the substrate of the village.
  • Step S403 etching the gate insulating film on the substrate of the village.
  • the fabrication of the array substrate is not limited to the above steps, and may further include other steps according to the film or layer structure on the array substrate.
  • the film or layer structure related to the present invention is fabricated.
  • other film or layer structures are specifically fabricated according to the specific conditions of the array substrate.
  • a passivation layer 8 may be disposed on the array substrate, and the array substrate formed after the above steps is as shown in FIGS. 6 and 7.
  • the gate insulating layer 7 is located above the pixel electrode 5 and below the data line 4.
  • the manufacturing method includes:
  • Step S501 forming a pixel electrode layer on the substrate of the village.
  • the formation of the pixel electrode layer on the substrate of the substrate may be as in other embodiments of the present invention, and is not described herein.
  • Step S502 forming a gate insulating film on the substrate of the village.
  • Step S503 forming a data line metal layer on the substrate of the village.
  • the formation of the data line metal layer on the substrate of the substrate may be as in other embodiments of the present invention and will not be described herein.
  • Step S504 etching the gate insulating film.
  • the etching of the gate insulating film can be performed by dry etching. Of course, it can also use other etching methods.
  • the thickness of the region of the gate insulating layer between the pixel electrode and the data line is 1/5 of a thickness of a region of the gate insulating layer corresponding to the pixel electrode and/or a thickness of a region corresponding to the gate insulating layer and the data line. 4/5.
  • the thickness of the region of the gate insulating layer between the pixel electrode and the data line is 1/2 of the thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • the fabrication of the array substrate is not limited to the above steps, and may further include other steps according to the film or layer structure on the array substrate.
  • the film or layer structure related to the present invention is fabricated.
  • other film or layer structures are specifically fabricated according to the specific conditions of the array substrate.
  • the manufacturing method includes:
  • Step S601 forming a pixel electrode layer on the substrate of the village.
  • the formation of the pixel electrode layer on the substrate of the substrate may be as in other embodiments of the present invention, and is not described herein.
  • Step S602 forming a gate insulating film on the substrate of the village.
  • the formation of the gate insulating film on the substrate of the substrate may be as in other embodiments of the present invention, and will not be described herein.
  • Step S603 etching the gate insulating film.
  • the etching of the gate insulating film can be performed by dry etching.
  • the thickness of the region of the gate insulating layer between the pixel electrode and the data line is 1/5 of a thickness of a region of the gate insulating layer corresponding to the pixel electrode and/or a thickness of a region corresponding to the gate insulating layer and the data line. 4/5.
  • the thickness of the region where the gate insulating layer is located between the pixel electrode and the data line is 1/2 of the thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • Step S604 forming a data line metal layer on the substrate of the village.
  • the formation of the data line metal layer on the substrate of the substrate may be as in other embodiments of the present invention and will not be described herein.
  • the fabrication of the array substrate is not limited to the above steps, and may further include other steps according to the film or layer structure on the array substrate.
  • the film or layer structure related to the present invention is fabricated.
  • other film or layer structures are specifically fabricated according to the specific conditions of the array substrate.
  • the gate insulating layer is located below the pixel electrode and above the data line.
  • the gate insulating film is etched.
  • the manufacturing method includes:
  • Step S701 forming a pixel electrode layer on the substrate of the village.
  • the formation of the pixel electrode layer on the substrate of the substrate may be as in other embodiments of the present invention, and is not described herein.
  • Step S702 forming a gate insulating film on the substrate of the village.
  • the formation of the gate insulating film on the substrate of the substrate may be as in other embodiments of the present invention, and will not be described herein.
  • Step S703 etching the gate insulating film.
  • the etching of the gate insulating film can be performed by dry etching. Of course, it can also use other etching methods.
  • the thickness of the region of the gate insulating layer between the pixel electrode and the data line is 1/5 of a thickness of a region of the gate insulating layer corresponding to the pixel electrode and/or a thickness of a region corresponding to the gate insulating layer and the data line. 4/5.
  • the thickness of the region of the gate insulating layer between the pixel electrode and the data line is 1/2 of the thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • Step S704 forming a data line metal layer on the substrate of the village.
  • the formation of the data line metal layer on the substrate of the substrate may be as in other embodiments of the present invention and will not be described herein.
  • the fabrication of the array substrate is not limited to the above steps, and may further include other steps according to the film or layer structure on the array substrate, which is only relevant to the present invention in the embodiment of the present invention.
  • the fabrication of the film or layer structure is described as an example, and other film or layer structures are specifically produced according to the specific conditions of the array substrate.
  • the gate insulating film is etched before the pixel electrode layer is formed on the substrate.
  • the manufacturing method includes:
  • Step S801 forming a data line metal layer on the substrate of the village.
  • the formation of the data line metal layer on the substrate of the substrate may refer to other embodiments of the present invention, and details are not described herein.
  • Step S802 forming a gate insulating film on the substrate of the village.
  • the formation of the gate insulating film on the substrate of the substrate may be as in other embodiments of the present invention, and will not be described herein.
  • Step S803 etching the gate insulating film.
  • the etching of the gate insulating film can be performed by dry etching. Of course, it can also use other etching methods.
  • the thickness of the region of the gate insulating layer between the pixel electrode and the data line is 1/5 of a thickness of a region of the gate insulating layer corresponding to the pixel electrode and/or a thickness of a region corresponding to the gate insulating layer and the data line. 4/5.
  • the thickness of the region of the gate insulating layer between the pixel electrode and the data line is 1/2 of the thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • Step S804 forming a pixel electrode layer on the substrate of the village.
  • the formation of the pixel electrode layer on the substrate of the substrate may be as in other embodiments of the present invention, and is not described herein.
  • the fabrication of the array substrate is not limited to the above steps, and may further include other steps according to the film or layer structure on the array substrate.
  • the film or layer structure related to the present invention is fabricated.
  • other film or layer structures are specifically fabricated according to the specific conditions of the array substrate.
  • An embodiment of the present invention provides an array substrate, a method for fabricating the same, and a display device.
  • the pixel electrode and the data line of the array substrate are located between the gate insulating layer and the passivation layer, and the pixel electrode and the data line are separated by a certain distance to form a memory.
  • a capacitor a gate insulating layer is located under the pixel electrode and the data line, and a thickness of a region of the gate insulating layer corresponding to the pixel electrode is at least greater than a thickness of a region between the corresponding pixel electrode and the data line of the gate insulating layer, at the pixel electrode and the data line
  • the storage capacitor formed between them is almost blunt
  • the layer generated by the layer has a small interlayer capacitance, which can reduce the interference to the pixel electrode and improve the display effect.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

一种阵列基板及其制作方法、显示装置，该阵列基板包括设置在衬底基板（1）上的栅绝缘层（7）、像素电极层、数据线金属层，其中，数据线金属层包括数据线（4），像素电极层包括像素电极（5）；栅绝缘层（7）对应像素电极（5）和数据线（4）之间的区域的厚度小于栅绝缘层（7）与像素电极（5）对应的区域的厚度和/或栅绝缘层（7）与数据线（4）对应的区域的厚度。

Description

阵列基板及其制作方法、 显示装置
技术领域
本发明的实施例涉及一种阵列基板及其制作方法、 显示装置。 背景技术
现有的液晶显示面板， 包括阵列基板、 彩膜基板以及设置在阵列基板和 彩膜基板之间的液晶。 如图 1、 图 2所示， 液晶显示器中的阵列基板包括： 透明基板 1以及依次设置在透明基板 1上的栅金属层、栅绝缘层 7、钝化层 8、 源漏金属层以及透明导电层， 其中， 栅金属层包括： 栅线 2和栅极 31 , 源漏 金属层包括： 数据线 4、公共电极线 6、 源极 32和漏极 33,透明导电层包括： 像素电极 5。 如图 2所示， 现有的阵列基板上数据线 4与像素电极 5绝缘， 形成存储电容， 但由于栅绝缘层 7的层间电容大于钝化层 8的层间电容， 即 像素电极 5与数据线 4之间的电容 a=b < c。这样数据线对像素电极的干扰比 较严重， 会出现响度电极信号异常， 进而影响显示效果。 发明内容
本发明的实施例提供一种阵列基板及其制作方法、 显示装置， 通过所述 阵列基板可以减小公共电极线和像素电极之间的电容， 减小公共电极线对像 素电极的干扰。
本发明实施例提供了一种阵列基板， 包括： 村底基板， 以及设置在村底 基板上的栅绝缘层、 像素电极层、 数据线金属层， 其中， 数据线金属层包括 数据线， 像素电极层包括像素电极； 栅绝缘层对应像素电极和数据线之间的 区域的厚度小于栅绝缘层与像素电极对应的区域的厚度和 /或栅绝缘层与数 据线对应的区域的厚度。
例如， 所述栅绝缘层位于所述数据线和像素电极的下方。
例如， 所述栅绝缘层位于所述数据线和所述像素电极的上方。
例如， 所述栅绝缘层位于所述像素电极上方， 且位于所述数据线下方。 例如， 所述栅绝缘层位于所述像素电极下方， 且位于所述数据线上方。 例如， 栅绝缘层位于像素电极和数据线之间的区域的厚度是栅绝缘层与 像素电极对应的区域的厚度和 /或栅绝缘层与数据线对应的区域的厚度的
1/5-4/5。
例如， 栅绝缘层位于像素电极和数据线之间的区域的厚度是栅绝缘层与 像素电极对应的区域的厚度和 /或栅绝缘层与数据线对应的区域的厚度的 1/2。
本发明实施例提供了一种显示装置， 包括本发明实施例提供的所述的阵 列基板。
本发明实施例提供了一种阵列基板的制作方法， 包括： 在村底基板上形 成栅绝缘层、像素电极层、数据线金属层， 其中， 数据线金属层包括数据线， 像素电极层包括像素电极； 在村底基板上形成栅绝缘层包括： 在村底基板上 形成栅绝缘薄膜， 以及对栅绝缘薄膜进行刻蚀， 以使得栅绝缘层对应像素电 极和数据线之间的区域的厚度小于栅绝缘层与像素电极对应的区域的厚度和 /或栅绝缘层与数据线对应的区域的厚度。
例如， 所述栅绝缘层位于所述数据线和像素电极的下方。
例如， 依次在村底基板上形成栅绝缘薄膜和像素电极层之后， 在村底基 板上形成数据线金属层之前， 对所述栅绝缘薄膜进行刻蚀。
例如， 依次在村底基板上形成栅绝缘薄膜和数据线金属层之后， 在村底 基板上形成像素电极层之前， 对所述栅绝缘薄膜进行刻蚀。
例如， 依次在村底基板上形成栅绝缘薄膜、 像素电极层以及数据线金属 层之后， 或依次在村底基板上形成栅绝缘薄膜、 数据线金属层以及像素电极 层之后， 对所述栅绝缘薄膜进行刻蚀。
例如， 所述栅绝缘层位于所述数据线和所述像素电极的上方。
例如， 在村底基板上形成数据线金属层和像素电极层之后， 在村底基板 上形成栅绝缘薄膜， 并对村底基板上的栅绝缘薄膜进行刻蚀。
例如， 所述栅绝缘层位于所述像素电极上方， 且位于所述数据线下方。 例如， 依次在村底基板上形成像素电极层、 栅绝缘薄膜和数据线金属层 之后， 对所述栅绝缘薄膜进行刻蚀。
例如， 依次在村底基板上形成像素电极层和栅绝缘薄膜之后， 在村底基 板上形成数据线金属层之前， 对所述栅绝缘薄膜进行刻蚀。
例如， 所述栅绝缘层位于所述像素电极下方， 且位于所述数据线上方。 例如， 依次在村底基板上形成数据线金属层、 栅绝缘薄膜以及像素电极 层之后， 对所述栅绝缘薄膜进行刻蚀。
例如， 依次在村底基板上形成数据线金属层和栅绝缘薄膜之后， 在村底 基板上形成像素电极层之前， 对所述栅绝缘薄膜进行刻蚀。
例如， 栅绝缘层位于像素电极和数据线之间的区域的厚度是栅绝缘层与 像素电极对应的区域的厚度和 /或栅绝缘层与数据线对应的区域的厚度的 1/5-4/5。
例如， 栅绝缘层位于像素电极和数据线之间的区域的厚度是栅绝缘层与 像素电极对应的区域的厚度和 /或栅绝缘层与数据线对应的区域的厚度的 1/2。 附图说明
以下将结合附图对本发明的实施例进行更详细的说明， 以使本领域普通 技术人员更加清楚地理解本发明， 其中：
图 1为现有的阵列基板像素单元俯视结构示意图；
图 2为图 1的局部剖视结构示意图；
图 3 为本发明实施例提供的一种阵列基板像素单元局部剖视结构示意 图；
图 4为本发明实施例提供的另一种阵列基板像素单元局部剖视结构示意 图；
图 5为本发明实施例提供的另一种阵列基板像素单元局部剖视结构示意 图；
图 6为本发明实施例提供的另一种阵列基板像素单元局部剖视结构示意 图；
图 7为本发明实施例提供的另一种阵列基板像素单元局部剖视结构示意 图；
图 8为本发明实施例提供的另一种阵列基板像素单元局部剖视结构示意 图；
图 9为本发明实施例提供的另一种阵列基板像素单元局部剖视结构示意 图；
图 10为本发明实施例提供的一种阵列基板制作方法示意图；
图 11为图 10所示的制作方法中在村底基板上形成栅绝缘薄膜的示意图； 图 12为图 10所示的制作方法中在村底基板上形成像素电极的示意图； 图 13为图 10所示的制作方法中对村底基板上形成的栅绝缘薄膜刻蚀后 的示意图；
图 14为图 10所示的制作方法中在村底基板上形成数据线的示意图； 图 15为本发明实施例提供的另一种阵列基板制作方法示意图； 图 16为图 15所示的制作方法中在村底基板上形成数据线的示意图； 图 17为图 15所示的制作方法中对村底基板上形成的栅绝缘薄膜刻蚀后 的示意图；
图 18为图 15所示的制作方法中在村底基板上形成像素电极的示意图； 图 19为本发明实施例提供的另一种阵列基板制作方法示意图； 图 20为图 19所示的制作方法中在村底基板上形成像素电极和数据线的 示意图；
图 21为图 19所示的制作方法中对村底基板上形成的栅绝缘薄膜刻蚀后 的示意图；
图 22为本发明实施例提供的另一种阵列基板制作方法示意图； 图 23为本发明实施例提供的另一种阵列基板制作方法示意图； 图 24为本发明实施例提供的另一种阵列基板制作方法示意图； 图 25为本发明实施例提供的另一种阵列基板制作方法示意图； 图 26为本发明实施例提供的另一种阵列基板制作方法示意图。
附图标记：
1-村底基板； 2-栅线; 3-薄膜晶体管； 31-栅极； 32-源极； 33-漏极； 4- 数据线； 5-像素电极； 6-公共电极线； 7-栅绝缘层； 70-栅绝缘薄膜； 8-钝化 层。 具体实施方式
为使本发明的实施例的目的、 技术方案和优点更加清楚， 下面将结合本 发明实施例的附图对本发明的实施例的技术方案进行清楚、 完整的描述。 显 然， 所描述的实施例仅是本发明的一部分示例性实施例， 而不是全部的实施 例。 基于所描述的本发明的示例性实施例， 本领域普通技术人员在无需创造 性劳动的前提下所获得的所有其它实施例都属于本发明的保护范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一"、 "第二" 以及类似的词语并不表示任何顺序、 数 量或者重要性， 而只是用来区分不同的组成部分。 同样， "一个"、 "一"或者 "该"等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括 "或者 "包含" 等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后 面列举的元件或者物件及其等同，而不排除其他元件或者物件。 "上"、 "下"、 等仅用于表示相对位置关系， 当被描述对象的绝对位置改变后， 则该相对位 置关系也可能相应地改变。
本发明实施例提供了一种阵列基板， 如图 3-图 9所示， 包括设置在村底 基板上的栅绝缘层 7、 像素电极层、 数据线金属层， 其中， 数据线金属层包 括数据线 4,像素电极层包括像素电极 5;栅绝缘层 7对应像素电极 5和数据 线 4之间的区域的厚度小于栅绝缘层 7与像素电极 5对应的区域的厚度和 / 或栅绝缘层 7与数据线 4对应的区域的厚度。
需要说明的是， 常规技术中， 栅绝缘层在制作过程中一般首先沉积栅绝 缘薄膜， 再对所述栅绝缘薄膜进行刻蚀， 其中， 沉积的栅绝缘薄膜的厚度是 相同的。 而在本发明实施例中， 通过刻蚀栅绝缘薄膜的部分， 使得刻蚀后形 成的栅绝缘层对应像素电极和数据线之间的区域的厚度小于栅绝缘层与像素 电极对应的区域的厚度和 /或栅绝缘层与数据线对应的区域的厚度。
本发明附图中的阵列基板为局部放大视图， 为了清楚而不淹没本发明， 图中仅示出了与本发明的相关的薄膜或层结构， 省略了其它结构， 这并不表 明本发明只包括这些膜层或结构， 本发明的实施例还可以包括其他需要的膜 层或结构特征。
所述栅绝缘层对应像素电极和数据线之间的区域的厚度小于栅绝缘层与 像素电极对应的区域的厚度和 /或栅绝缘层与数据线对应的区域的厚度，可以 是栅绝缘层对应像素电极和数据线之间的区域的厚度小于栅绝缘层与像素电 极对应的区域的厚度； 可以是栅绝缘层对应像素电极和数据线之间的区域的 厚度小于栅绝缘层与数据线对应的区域的厚度。
本发明实施例中， 所述"上"、 "下" 以制作薄膜或层结构的顺序为依据， 例如， 可以是在先制作的薄膜或层结构在 "下"， 在后制作的薄膜或层结构在 "上，，。
在本发明所有实施例中， 需要阐明 "薄膜" 和 "层" 的定义， 以及之间 的关系。其中， "薄膜 "是指利用某一种材料在基板上利用沉积或其他工艺制 作出的一层薄膜。若在整个制作过程当中该 "薄膜"无需构图工艺， 则该 "薄 膜"还可以称为 "层"； 若在整个制作过程当中该 "薄膜"还需构图工艺， 则 在构图工艺前称为 "薄膜"， 构图工艺后称为 "层"。 例如， 上述的栅绝缘层 的形成可以是先在透明基板 1上沉积 SiNx (氮化硅 )薄膜， 再对形成的氮化 硅薄膜进行刻蚀得到此栅绝缘层。 当然， 也可以对形成的氮化硅薄膜进行过 孔刻蚀等其他目的刻蚀。
本发明实施例中， 对所述栅绝缘薄膜进行刻蚀以使得栅绝缘层对应像素 电极和数据线之间的区域的厚度小于栅绝缘层与像素电极对应的区域的厚度 和 /或栅绝缘层与数据线对应的区域的厚度。
本发明实施例提供的一种阵列基板， 所述阵列基板上栅绝缘层对应像素 电极和数据线之间的区域的厚度小于栅绝缘层与像素电极对应的区域的厚度 和 /或栅绝缘层与数据线对应的区域的厚度，， 因此， 在像素电极和数据线之 间形成的存储电容几乎是由绝缘层或钝化层产生， 其层间电容小， 可以保证 电极信号的正常， 提升显示效果。
可选的， 所述栅绝缘层位于所述数据线和像素电极的下方。 需要说明的 是， 阵列基板上包括栅极、 有源层、 源级和漏极， 其中， 栅极、 源极和漏极 是薄膜晶体管的三个电极， 源极和漏极同层设置且绝缘。 有源层与栅极之间 具有的绝缘膜层使其与源极和漏极绝缘。 一般根据有源层和栅极的位置关系 将薄膜晶体管分为两类： 一类是栅极位于有源层（以及源极和漏极）的下面， 这类称之为底栅型薄膜晶体管； 一类是栅极位于有源层（以及源极和漏极） 的上面， 这类称之为顶栅型薄膜晶体管。 上述顶栅型薄膜晶体管和底栅型薄 膜晶体管其源极和漏极同层设置。 另外， 还有一种侧栅型薄膜晶体管， 其源 极和漏极沿垂直基板的方向一个靠近基板， 一个远离基板。
如果所述栅绝缘层位于所述数据线和像素电极的下方， 则所述阵列基板 上的薄膜晶体管为底栅型薄膜晶体管， 其可以是如图 3-图 5所示。 例如， 如 图 3所示， 栅绝缘层 7对应像素电极 5和数据线 4之间的区域的厚度小于栅 绝缘层 7与像素电极 5对应的区域的厚度和栅绝缘层 7与数据线 4对应的区 域的厚度。 如图 4所示， 栅绝缘层 7对应像素电极 5和数据线 4之间的区域 的厚度小于栅绝缘层 7与像素电极 5对应的区域的厚度。 如图 5所示， 栅绝 缘层 7对应像素电极 5和数据线 4之间的区域的厚度小于栅绝缘层 7与数据 线 4对应的区域的厚度。 需要说明的是， 附图中标识箭头的 "a"、 "b"、 "c" 用于说明像素电极和数据线形成的电容和电场的关系， 不代表实际的电容和 电场。
可选的， 所述栅绝缘层位于所述数据线和所述像素电极的上方， 则所述 阵列基板上的薄膜晶体管为顶栅型薄膜晶体管。 例如， 如图 6、 图 7所示， 栅绝缘层 7对应像素电极 5和数据线 4之间的区域的厚度小于栅绝缘层 7与 像素电极 5对应的区域的厚度和栅绝缘层 7与数据线 4对应的区域的厚度。
可选的，所述栅绝缘层位于所述像素电极上方，且位于所述数据线下方。 例如， 如图 8所示， 栅绝缘层 7位于像素电极 5上方， 位于所述数据线 4下 方。 栅绝缘层 7对应像素电极 5和数据线 4之间的区域的厚度小于栅绝缘层 7与像素电极 5对应的区域的厚度和栅绝缘层 7与数据线 4对应的区域的厚 度。 当然， 当所述栅绝缘层位于所述像素电极上方， 且位于所述数据线下方， 所述栅绝缘层对应像素电极和数据线之间的区域的厚度还可以是小于栅绝缘 层与像素电极对应的区域的厚度或栅绝缘层与数据线对应的区域的厚度， 本 发明实施例中仅以图 8为例进行示例说明。
可选的，所述栅绝缘层位于所述像素电极下方，且位于所述数据线上方。 例如， 如图 9所示， 栅绝缘层 7位于像素电极 5下方， 位于所述数据线 4上 方。 栅绝缘层 7对应像素电极 5和数据线 4之间的区域的厚度小于栅绝缘层 7与像素电极 5对应的区域的厚度和栅绝缘层 7与数据线 4对应的区域的厚 度。 当然， 当所述栅绝缘层位于所述像素电极下方， 且位于所述数据线上方， 所述栅绝缘层对应像素电极和数据线之间的区域的厚度还可以是小于栅绝缘 层与像素电极对应的区域的厚度或栅绝缘层与数据线对应的区域的厚度， 本 发明实施例中仅以图 9为例进行示例说明。
可选的， 栅绝缘层位于像素电极和数据线之间的区域的厚度是栅绝缘层 与像素电极对应的区域的厚度和 /或栅绝缘层与数据线对应的区域的厚度的 1/5-4/5。 例如， 栅绝缘层位于像素电极和数据线之间的区域的厚度是栅绝缘 层与像素电极对应的区域的厚度和 /或栅绝缘层与数据线对应的区域的厚度 的 1/2。 这样的设计不仅使层间电容小， 而且使得基板的透过率和电连接性 能好。
本发明实施例还提供一种显示装置， 包括本发明实施例提供的任一所述 的阵列基板。 所述显示装置可以为液晶显示器、 电子纸、 OLED (Organic Light-Emitting Diode,有机发光二极管)显示器等显示器件以及包括这些显示 器件的电视、 数码相机、 手机、 平板电脑等任何具有显示功能的产品或者部 件。
本发明实施例还提供一种阵列基板的制作方法， 包括： 在村底基板上形 成栅绝缘层、像素电极层、数据线金属层， 其中， 数据线金属层包括数据线， 像素电极层包括像素电极； 在村底基板上形成栅绝缘层包括： 在村底基板上 形成栅绝缘薄膜以及对栅绝缘薄膜进行刻蚀， 以使得栅绝缘层对应像素电极 和数据线之间的区域的厚度小于栅绝缘层与像素电极对应的区域的厚度和 / 或栅绝缘层与数据线对应的区域的厚度。
需要说明的是， 阵列基板上各层或薄膜的制作顺序根据阵列基板上的设 置可以不同。 例如阵列基板上的薄膜晶体管为顶栅型薄膜晶体管和阵列基板 上的薄膜晶体管为底栅型薄膜晶体管的制作方法有所不同， 且相同薄膜晶体 管的阵列基板的制作方法也有所不同。 下面将对包括这两种类型的薄膜晶体 管的阵列基板的制作方法进行详细说明。
可选的， 如图 3-图 5所示， 所述栅绝缘层 7形成在所述数据线 4和像素 电极 5的下方。
可选的， 依次在村底基板上形成栅绝缘薄膜和像素电极层之后， 在村底 基板上形成数据线金属层之前， 对所述栅绝缘薄膜进行刻蚀。 例如， 如图 10 所示， 本发明实施例提供了一种阵列基板的制作方法， 包括：
步骤 S101、 在村底基板上形成栅绝缘薄膜。
例如， 如图 11所示， 在村底基板 1上形成栅绝缘薄膜 70。 需要说明的 是,所示村底基板可以是透明基板也可以是形成有其他薄膜或层结构的基板。 例如， 所示村底基板可以是形成有栅金属层的基板， 例如玻璃， 塑料， 石英 基板。
需要说明的是， 形成薄膜或层结构的方法可以是本领域常规的形成薄膜 或层结构的方式， 例如沉积、 溅射等。
步骤 S102、 在村底基板上形成像素电极层。
例如， 所示像素电极层包括像素电极， 如图 12所示， 在形成有栅绝缘薄 膜 70的村底基板 1上形成像素电极 5。
Figure imgf000009_0001
例如， 对所述栅绝缘薄膜进行刻蚀， 刻蚀后形成的栅绝缘层 7如图 13 所示。 例如， 对栅绝缘薄膜的刻蚀可以采用干法刻蚀。 当然， 其也可以采用 其他刻蚀方法。 可选的， 栅绝缘层位于像素电极和数据线之间的区域的厚度 是栅绝缘层与像素电极对应的区域的厚度和 /或栅绝缘层与数据线对应的区 域的厚度的 1/5-4/5。 例如， 栅绝缘层位于像素电极和数据线之间的区域的厚 度是栅绝缘层与像素电极对应的区域的厚度和 /或栅绝缘层与数据线对应的 区域的厚度的 1/2。 这样的设计不仅可以使得层间电容小， 而且使得基板的 透过率和电连接性能好。
步骤 S104、 在村底基板上形成数据线金属层。
例如，在村底基板 1上形成的数据线金属层之后的基板如图 14所示。需 要说明的是，数据线金属层包括：数据线 4以及源极和漏极（未示出），例如， 可以在形成数据线金属层， 形成数据线的同时， 形成薄膜晶体管的源极和漏 极。
需要说明的是， 阵列基板的制作不局限于上述步骤， 根据阵列基板上的 薄膜或层结构， 其还可以包括其他步骤， 本发明实施例中仅以与本发明的相 关的薄膜或层结构的制作为例进行说明， 以使描述更加清楚， 而对于其他薄 膜或层结构可以根据阵列基板的具体情况， 具体制作。 例如， 阵列基板上还 可以设置钝化层 8 , 则在上述步骤之后形成钝化层 8。
可选的， 依次在村底基板上形成栅绝缘薄膜和数据线金属层之后， 在村 底基板上形成像素电极层之前， 对所述栅绝缘薄膜进行刻蚀。 例如， 如图 15 所示， 所示制作方法包括：
步骤 S201、 在村底基板上形成栅绝缘薄膜。
例如， 在村底基板上形成栅绝缘薄膜可以参照上述步骤 S101进行。 步骤 S202、 在村底基板上形成数据线金属层。
例如， 所示数据线金属层包括数据线、 源极和漏极， 如图 16所示， 在村 底基板 1上形成数据线 4。 需要说明的是， 数据线金属层包括： 数据线 4以 及源极和漏极（未示出）， 例如， 可以在形成数据线金属层， 形成数据线的同 时， 形成薄膜晶体管的源极和漏极。
步骤 S203、 对所述栅绝缘薄膜进行刻蚀。
例如， 刻蚀栅绝缘薄膜形成的栅绝缘层 7如图 17所示。 例如， 对栅绝缘 薄膜的刻蚀可以采用干法刻蚀。 当然， 也可以采用其他刻蚀方法。 可选的， 栅绝缘层位于像素电极和数据线之间的区域的厚度是栅绝缘层与像素电极对 应的区域的厚度和 /或栅绝缘层与数据线对应的区域的厚度的 1/5-4/5。 例如， 栅绝缘层位于像素电极和数据线之间的区域的厚度是栅绝缘层与像素电极对 应的区域的厚度和 /或栅绝缘层与数据线对应的区域的厚度的 1/2。 这样的设 计不仅使层间电容小， 而且使基板的透过率和电连接性能好。
步骤 S204、 在村底基板上形成像素电极层。
例如， 在村底基板 1上形成像素电极 5后的阵列基板如图 18所示。 需要说明的是， 阵列基板的制作不局限于上述步骤， 根据阵列基板上的 薄膜或层结构， 其还可以包括其他步骤， 本发明实施例中仅以与本发明相关 的薄膜或层结构的制作为例进行说明， 以使描述更加清楚， 而对于其他薄膜 或层结构根据阵列基板的具体情况， 具体制作。 例如， 阵列基板上还可以设 置钝化层 8, 则在上述步骤之后形成的阵列基板如图 5所示。
可选的， 依次在村底基板上形成栅绝缘薄膜、 像素电极层以及数据线金 属层之后或依次在村底基板上形成栅绝缘薄膜、 数据线金属层以及像素电极 层之后， 对所述栅绝缘薄膜进行刻蚀。 需要说明的是， 所述像素电极层和数 据线金属层的制作顺序可以相互调换， 例如，如图 19所示， 所述制作方法包 括：
步骤 S301、 在村底基板上形成栅绝缘薄膜。
例如， 在村底基板上形成栅绝缘薄膜可以参照上述步骤 S101。
步骤 S302、 在村底基板上形成像素电极层和数据线金属层。
例如， 所述在村底基板上形成像素电极层和数据线金属层， 可以是先在 阵列基板上形成像素电极层之后再形成数据线金属层或者是先在阵列基板上 形成数据线金属层之后再形成像素电极， 在村底基板上形成像素电极层或数 据线金属层如图 20所示。
步骤 S303、 对所述栅绝缘薄膜进行刻蚀。
例如， 对栅绝缘薄膜的刻蚀形成的栅绝缘层 7如图 21所示。 可选的，栅 绝缘层位于像素电极和数据线之间的区域的厚度是栅绝缘层与像素电极对应 的区域的厚度和 /或栅绝缘层与数据线对应的区域的厚度的 1/5-4/5。例如，栅 绝缘层位于像素电极和数据线之间的区域的厚度是栅绝缘层与像素电极对应 的区域的厚度和 /或栅绝缘层与数据线对应的区域的厚度的 1/2。 这样设计不 仅使层间电容小， 而且使基板的透过率和电连接性能好。
需要说明的是， 阵列基板的制作不局限于上述步骤， 根据阵列基板上的 薄膜或层结构， 其还可以包括其他步骤， 本发明实施例中仅以与本发明相关 的薄膜或层结构的制作为例进行说明， 其他薄膜或层结构根据阵列基板的具 体情况， 具体制作。 例如， 阵列基板上还可以设置有钝化层 8, 则在上述步 骤之后形成的阵列基板如图 3所示。
可选的， 如图 6、 图 7所示， 所述栅绝缘层 7位于所述数据线 4和所述 像素电极 5的上方。
可选的， 在村底基板上形成数据线金属层和像素电极层之后， 在村底基 板上形成栅绝缘薄膜， 并对村底基板上的栅绝缘薄膜进行刻蚀。 例如， 如图 22所示， 所述制作方法包括：
步骤 S401、 在村底基板上形成数据线金属层以及像素电极层。
其中， 在村底基板上形成像素电极层或数据线金属层， 可以是先在阵列 基板上形成像素电极层之后再形成数据线金属层或者是先在阵列基板上形成 数据线金属层之后再形成像素电极。
步骤 S402、 在村底基板上形成栅绝缘薄膜。
步骤 S403、 对村底基板上的栅绝缘薄膜进行刻蚀。
需要说明的是， 阵列基板的制作不局限于上述步骤， 根据阵列基板上的 薄膜或层结构， 其还可以包括其他步骤， 本发明实施例中仅以与本发明相关 的薄膜或层结构的制作为例进行说明， 其他薄膜或层结构根据阵列基板的具 体情况， 具体制作。 例如， 阵列基板上还可以设置有钝化层 8, 则在上述步 骤之后形成的阵列基板如图 6、 图 7所示。
可选的， 如图 8所示， 所述栅绝缘层 7位于所述像素电极 5上方， 且位 于所述数据线 4下方。
可选的， 依次在村底基板上形成像素电极层、 栅绝缘薄膜和数据线金属 层之后， 对所述栅绝缘薄膜进行刻蚀。 例如， 如图 23所示， 所述制作方法包 括：
步骤 S501、 在村底基板上形成像素电极层。
例如， 在村底基板上形成像素电极层可以如本发明的其他实施例， 这里 不作赘述。
步骤 S502、 在村底基板上形成栅绝缘薄膜。
例如， 在村底基板上形成栅绝缘薄膜可以如本发明的其他实施例， 这里 不作赘述。 步骤 S503、 在村底基板上形成数据线金属层。
例如， 在村底基板上形成数据线金属层可以如本发明的其他实施例， 这 里不作赘述。
步骤 S504、 对所述栅绝缘薄膜进行刻蚀。
例如， 对栅绝缘薄膜的刻蚀可以采用干法刻蚀。 当然， 其也可以采用其 他刻蚀方法。 可选的， 栅绝缘层位于像素电极和数据线之间的区域的厚度是 栅绝缘层与像素电极对应的区域的厚度和 /或栅绝缘层与数据线对应的区域 的厚度的 1/5-4/5。 例如， 栅绝缘层位于像素电极和数据线之间的区域的厚度 是栅绝缘层与像素电极对应的区域的厚度和 /或栅绝缘层与数据线对应的区 域的厚度的 1/2。 这样的设计不仅使层间电容小， 而且使基板的透过率和电 连接性能好。
需要说明的是， 阵列基板的制作不局限于上述步骤， 根据阵列基板上的 薄膜或层结构， 其还可以包括其他步骤， 本发明实施例中仅以与本发明相关 的薄膜或层结构的制作为例进行说明， 其他薄膜或层结构根据阵列基板的具 体情况， 具体制作。
可选的， 依次在村底基板上形成像素电极层和栅绝缘薄膜之后， 在村底 基板上形成数据线金属层之前， 对所述栅绝缘薄膜进行刻蚀。 例如， 如图 24 所示， 所述制作方法包括：
步骤 S601、 在村底基板上形成像素电极层。
例如， 在村底基板上形成像素电极层可以如本发明的其他实施例， 这里 不作赘述。
步骤 S602、 在村底基板上形成栅绝缘薄膜。
例如， 在村底基板上形成栅绝缘薄膜可以如本发明的其他实施例， 这里 不作赘述。
步骤 S603、 对所述栅绝缘薄膜进行刻蚀。
例如， 对栅绝缘薄膜的刻蚀可以采用干法刻蚀。 当然， 其也可以采用其 他刻蚀方法， 本发明实施例不作具体限定。 可选的， 栅绝缘层位于像素电极 和数据线之间的区域的厚度是栅绝缘层与像素电极对应的区域的厚度和 /或 栅绝缘层与数据线对应的区域的厚度的 1/5-4/5。 例如， 栅绝缘层位于像素电 极和数据线之间的区域的厚度是栅绝缘层与像素电极对应的区域的厚度和 / 或栅绝缘层与数据线对应的区域的厚度的 1/2。 这样的设计不仅使层间电容 小， 而且使基板的透过率和电连接性能好。
步骤 S604、 在村底基板上形成数据线金属层。
例如， 在村底基板上形成数据线金属层可以如本发明的其他实施例， 这 里不作赘述。
需要说明的是， 阵列基板的制作不局限于上述步骤， 根据阵列基板上的 薄膜或层结构， 其还可以包括其他步骤， 本发明实施例中仅以与本发明相关 的薄膜或层结构的制作为例进行说明， 其他薄膜或层结构根据阵列基板的具 体情况， 具体制作。
可选的，所述栅绝缘层位于所述像素电极下方，且位于所述数据线上方。 可选的， 依次在村底基板上形成数据线金属层、 栅绝缘薄膜以及像素电 极层之后， 对所述栅绝缘薄膜进行刻蚀。 例如， 如图 25所示， 所述制作方法 包括：
步骤 S701、 在村底基板上形成像素电极层。
例如， 在村底基板上形成像素电极层可以如本发明的其他实施例， 这里 不作赘述。
步骤 S702、 在村底基板上形成栅绝缘薄膜。
例如， 在村底基板上形成栅绝缘薄膜可以如本发明的其他实施例， 这里 不作赘述。
步骤 S703、 对所述栅绝缘薄膜进行刻蚀。
例如， 对栅绝缘薄膜的刻蚀可以采用干法刻蚀。 当然， 其也可以采用其 他刻蚀方法。 可选的， 栅绝缘层位于像素电极和数据线之间的区域的厚度是 栅绝缘层与像素电极对应的区域的厚度和 /或栅绝缘层与数据线对应的区域 的厚度的 1/5-4/5。 例如， 栅绝缘层位于像素电极和数据线之间的区域的厚度 是栅绝缘层与像素电极对应的区域的厚度和 /或栅绝缘层与数据线对应的区 域的厚度的 1/2。 这样的设计不仅使层间电容小， 而且使基板的透过率和电 连接性能好。
步骤 S704、 在村底基板上形成数据线金属层。
例如， 在村底基板上形成数据线金属层可以如本发明的其他实施例， 这 里不作赘述。
需要说明的是， 阵列基板的制作不局限于上述步骤， 根据阵列基板上的 薄膜或层结构， 其还可以包括其他步骤， 本发明实施例中仅以与本发明相关 的薄膜或层结构的制作为例进行说明， 其他薄膜或层结构根据阵列基板的具 体情况， 具体制作。
可选的， 依次在村底基板上形成数据线金属层和栅绝缘薄膜之后， 在村 底基板上形成像素电极层之前， 对所述栅绝缘薄膜进行刻蚀。 例如， 如图 26 所示， 所述制作方法包括：
步骤 S801、 在村底基板上形成数据线金属层。
例如， 在村底基板上形成数据线金属层可以参照本发明的其他实施例， 这里不作赘述。
步骤 S802、 在村底基板上形成栅绝缘薄膜。
例如， 在村底基板上形成栅绝缘薄膜可以如本发明的其他实施例， 这里 不作赘述。
步骤 S803、 对所述栅绝缘薄膜进行刻蚀。
例如， 对栅绝缘薄膜的刻蚀可以采用干法刻蚀。 当然， 其也可以采用其 他刻蚀方法。 可选的， 栅绝缘层位于像素电极和数据线之间的区域的厚度是 栅绝缘层与像素电极对应的区域的厚度和 /或栅绝缘层与数据线对应的区域 的厚度的 1/5-4/5。 例如， 栅绝缘层位于像素电极和数据线之间的区域的厚度 是栅绝缘层与像素电极对应的区域的厚度和 /或栅绝缘层与数据线对应的区 域的厚度的 1/2。 这样的设计不仅使层间电容小， 而且使基板的透过率和电 连接性能好。
步骤 S804、 在村底基板上形成像素电极层。
例如， 在村底基板上形成像素电极层可以如本发明的其他实施例， 这里 不作赘述。
需要说明的是， 阵列基板的制作不局限于上述步骤， 根据阵列基板上的 薄膜或层结构， 其还可以包括其他步骤， 本发明实施例中仅以与本发明相关 的薄膜或层结构的制作为例进行说明， 其他薄膜或层结构根据阵列基板的具 体情况， 具体制作。
本发明实施例提供的一种阵列基板及其制作方法、 显示装置， 所述阵列 基板的像素电极和数据线位于栅绝缘层和钝化层之间， 且像素电极和数据线 间隔一定距离形成存储电容， 栅绝缘层位于像素电极和数据线的下面， 且栅 绝缘层与像素电极对应的区域的厚度至少大于栅绝缘层对应像素电极和数据 线之间的区域的厚度， 在像素电极和数据线之间形成的存储电容几乎是由钝 化层产生的， 其层间电容小， 可以减小对像素电极的干扰， 提升显示效果。 可以理解的是， 上面所述仅仅是为了说明本发明原理的示例性实施例和 实施方式， 然而本发明并不局限于此。 对于本领域的普通技术人员而言， 在 不脱离本发明的精神和实质的情况下， 可以做出各种变型和改进， 这些变型 和改进也应属于本发明的保护范围。

Claims

权利要求书
1、 一种阵列基板， 包括：
村底基板； 以及
设置在村底基板上的栅绝缘层、 像素电极层和数据线金属层，
其中， 数据线金属层包括数据线， 像素电极层包括像素电极； 栅绝缘层 对应像素电极和数据线之间的区域的厚度小于栅绝缘层与像素电极对应的区 域的厚度和 /或栅绝缘层与数据线对应的区域的厚度。
2、根据权利要求 1所述的阵列基板，其中所述栅绝缘层位于所述数据线 和像素电极的下方。
3、根据权利要求 1所述的阵列基板，其中所述栅绝缘层位于所述数据线 和所述像素电极的上方。
4、根据权利要求 1所述的阵列基板，其中所述栅绝缘层位于所述像素电 极的上方， 且位于所述数据线的下方。
5、根据权利要求 1所述的阵列基板，其中所述栅绝缘层位于所述像素电 极的下方， 且位于所述数据线的上方。
6、根据权利要求 1-5任一项所述的阵列基板， 其中栅绝缘层位于像素电 极和数据线之间的区域的厚度是栅绝缘层与像素电极对应的区域的厚度和 / 或栅绝缘层与数据线对应的区域的厚度的 1/5-4/5。
7、根据权利要求 1-6任一项所述的阵列基板， 其中栅绝缘层位于像素电 极和数据线之间的区域的厚度是栅绝缘层与像素电极对应的区域的厚度和 / 或栅绝缘层与数据线对应的区域的厚度的 1/2。
8、 一种显示装置， 包括权利要求 1-7任一项所述的阵列基板。
9、 一种阵列基板的制作方法， 包括：
在村底基板上形成栅绝缘层、 像素电极层、 数据线金属层， 其中， 数据 线金属层包括数据线， 像素电极层包括像素电极； 其中在村底基板上形成栅 绝缘层包括： 在村底基板上形成栅绝缘薄膜， 以及对栅绝缘薄膜进行刻蚀， 以使得栅绝缘层对应像素电极和数据线之间的区域的厚度小于栅绝缘层与像 素电极对应的区域的厚度和 /或栅绝缘层与数据线对应的区域的厚度。
10、 根据权利要求 9所述的制作方法， 其中所述栅绝缘层形成在所述数 据线和像素电极的下方。
11、根据权利要求 9或 10所述的制作方法，其中依次在村底基板上形成 栅绝缘薄膜和像素电极层之后， 在村底基板上形成数据线金属层之前， 对所 述栅绝缘薄膜进行刻蚀。
12、 根据权利要求 9或 10所述的制作方法， 其中依次在村底基板上形 成栅绝缘薄膜和数据线金属层之后， 在村底基板上形成像素电极层之前， 对 所述栅绝缘薄膜进行刻蚀。
13、根据权利要求 9或 10所述的制作方法，其中依次在村底基板上形成 栅绝缘薄膜、 像素电极层以及数据线金属层之后或依次在村底基板上形成栅 绝缘薄膜、数据线金属层以及像素电极层之后，对所述栅绝缘薄膜进行刻蚀。
14、 根据权利要求 9所述的制作方法， 其中所述栅绝缘层位于所述数据 线和所述像素电极的上方。
15、根据权利要求 14所述的制作方法，其中在村底基板上形成数据线金 属层和像素电极层之后， 在村底基板上形成栅绝缘薄膜， 并对村底基板上的 栅绝缘薄膜进行刻蚀。
16、 根据权利要求 9所述的制作方法， 其中所述栅绝缘层位于所述像素 电极上方， 且位于所述数据线下方。
17、根据权利要求 16所述的制作方法，其中依次在村底基板上形成像素 电极层、 栅绝缘薄膜和数据线金属层之后， 对所述栅绝缘薄膜进行刻蚀。
18、根据权利要求 16所述的制作方法，其中依次在村底基板上形成像素 电极层和栅绝缘薄膜之后， 在村底基板上形成数据线金属层之前， 对所述栅 绝缘薄膜进行刻蚀。
19、 根据权利要求 9所述的制作方法， 其中所述栅绝缘层位于所述像素 电极下方， 且位于所述数据线上方。
20、根据权利要求 19所述的制作方法，其中依次在村底基板上形成数据 线金属层、 栅绝缘薄膜以及像素电极层之后， 对所述栅绝缘薄膜进行刻蚀。
21、根据权利要求 19所述的制作方法，其中依次在村底基板上形成数据 线金属层和栅绝缘薄膜之后， 在村底基板上形成像素电极层之前， 对所述栅 绝缘薄膜进行刻蚀。
22、根据权利要求 9-21任一项所述的制作方法， 其中栅绝缘层位于像素 电极和数据线之间的区域的厚度是栅绝缘层与像素电极对应的区域的厚度和
/或栅绝缘层与数据线对应的区域的厚度的 1/5-4/5。
23、根据权利要求 9-22任一项所述的制作方法， 其中栅绝缘层位于像素 电极和数据线之间的区域的厚度是栅绝缘层与像素电极对应的区域的厚度和 /或栅绝缘层与数据线对应的区域的厚度的 1/2。
PCT/CN2013/088109 2013-07-31 2013-11-29 阵列基板及其制作方法、显示装置 Ceased WO2015014053A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310329486.9A CN103413813B (zh) 2013-07-31 2013-07-31 一种阵列基板及其制作方法、显示装置
CN201310329486.9 2013-07-31

Publications (1)

Publication Number Publication Date
WO2015014053A1 true WO2015014053A1 (zh) 2015-02-05

Family

ID=49606811

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/088109 Ceased WO2015014053A1 (zh) 2013-07-31 2013-11-29 阵列基板及其制作方法、显示装置

Country Status (2)

Country Link
CN (1) CN103413813B (zh)
WO (1) WO2015014053A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103413813B (zh) * 2013-07-31 2016-05-25 北京京东方光电科技有限公司 一种阵列基板及其制作方法、显示装置
CN103794556A (zh) * 2014-01-22 2014-05-14 北京京东方光电科技有限公司 阵列基板及其制作方法和液晶显示装置
CN104112710B (zh) * 2014-07-08 2017-01-18 深圳市华星光电技术有限公司 阵列基板的制作方法、阵列基板及液晶显示装置
CN114740665B (zh) 2022-04-29 2023-08-01 广州华星光电半导体显示技术有限公司 一种显示面板及显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101614917A (zh) * 2008-06-25 2009-12-30 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
CN201974616U (zh) * 2010-12-30 2011-09-14 北京京东方光电科技有限公司 阵列基板和液晶显示面板
CN102929022A (zh) * 2012-10-23 2013-02-13 友达光电股份有限公司 一种液晶显示设备及其制造方法
CN103413813A (zh) * 2013-07-31 2013-11-27 北京京东方光电科技有限公司 一种阵列基板及其制作方法、显示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7858451B2 (en) * 2005-02-03 2010-12-28 Semiconductor Energy Laboratory Co., Ltd. Electronic device, semiconductor device and manufacturing method thereof
CN101526683A (zh) * 2008-03-07 2009-09-09 北京京东方光电科技有限公司 Lcd基板的制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101614917A (zh) * 2008-06-25 2009-12-30 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
CN201974616U (zh) * 2010-12-30 2011-09-14 北京京东方光电科技有限公司 阵列基板和液晶显示面板
CN102929022A (zh) * 2012-10-23 2013-02-13 友达光电股份有限公司 一种液晶显示设备及其制造方法
CN103413813A (zh) * 2013-07-31 2013-11-27 北京京东方光电科技有限公司 一种阵列基板及其制作方法、显示装置

Also Published As

Publication number Publication date
CN103413813A (zh) 2013-11-27
CN103413813B (zh) 2016-05-25

Similar Documents

Publication Publication Date Title
CN104865726B (zh) 一种阵列基板、显示面板、显示装置以及制备方法
CN105116642B (zh) 阵列基板及其制作方法、显示装置
CN107170764B (zh) 阵列基板、阵列基板的制造方法、显示面板和显示装置
CN103296033A (zh) 一种阵列基板及其制作方法
CN103943628B (zh) Tft阵列基板、制造方法及其显示面板
CN103745955B (zh) 显示装置、阵列基板及其制造方法
CN104409462B (zh) 阵列基板及其制造方法、显示装置
WO2018223696A1 (zh) 阵列基板及制作方法、柔性显示面板和显示装置
WO2016095513A1 (zh) 阵列基板及其制作方法、显示装置
CN103454817B (zh) 阵列基板及其制作方法、显示装置
CN104795428A (zh) 一种阵列基板及其制作方法以及显示装置
WO2015100898A1 (zh) 薄膜晶体管、tft阵列基板及其制造方法和显示装置
WO2016029564A1 (zh) 阵列基板及其制备方法、显示面板和显示装置
WO2014206035A1 (zh) 阵列基板及其制作方法、显示面板和显示装置
CN104064601B (zh) Tft、tft阵列基板及其制造方法、显示面板、显示装置
WO2016045241A1 (zh) 阵列基板及其制作方法、显示装置
CN104793420A (zh) 阵列基板及制作方法、显示装置
EP3089214B1 (en) Array substrate and manufacturing method thereof, and display device
WO2015010397A1 (zh) 阵列基板及其制造方法、显示装置
CN105470196A (zh) 薄膜晶体管、阵列基板及其制造方法、和显示装置
WO2016206206A1 (zh) 薄膜晶体管及其制备方法、阵列基板、显示装置
CN104867878A (zh) 一种ltps阵列基板及其制作方法
WO2015085719A1 (zh) 像素单元、阵列基板及其制造方法和显示装置
CN105655348A (zh) 一种阵列基板及其制作方法、显示面板和显示装置
CN102629611B (zh) 一种显示装置、阵列基板及其制作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13890543

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13890543

Country of ref document: EP

Kind code of ref document: A1