WO2015014053A1 - Substrat de réseau, procédé de fabrication associé et appareil d'affichage - Google Patents

Substrat de réseau, procédé de fabrication associé et appareil d'affichage Download PDF

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Publication number
WO2015014053A1
WO2015014053A1 PCT/CN2013/088109 CN2013088109W WO2015014053A1 WO 2015014053 A1 WO2015014053 A1 WO 2015014053A1 CN 2013088109 W CN2013088109 W CN 2013088109W WO 2015014053 A1 WO2015014053 A1 WO 2015014053A1
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Prior art keywords
gate insulating
pixel electrode
data line
layer
substrate
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PCT/CN2013/088109
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English (en)
Chinese (zh)
Inventor
郭建
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北京京东方光电科技有限公司
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Publication of WO2015014053A1 publication Critical patent/WO2015014053A1/fr

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/42—Materials having a particular dielectric constant

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • a conventional liquid crystal display panel includes an array substrate, a color filter substrate, and a liquid crystal disposed between the array substrate and the color filter substrate.
  • the array substrate in the liquid crystal display comprises: a transparent substrate 1 and a gate metal layer, a gate insulating layer 7, a passivation layer 8, a source/drain metal layer, and a transparent conductive layer sequentially disposed on the transparent substrate 1.
  • the gate metal layer includes: a gate line 2 and a gate 31.
  • the source/drain metal layer includes: a data line 4, a common electrode line 6, a source 32 and a drain 33, and the transparent conductive layer comprises: a pixel electrode 5. As shown in FIG.
  • Embodiments of the present invention provide an array substrate, a method of fabricating the same, and a display device.
  • the array substrate can reduce the capacitance between the common electrode line and the pixel electrode, and reduce the interference of the common electrode line to the pixel electrode.
  • An embodiment of the present invention provides an array substrate, including: a substrate substrate, and a gate insulating layer, a pixel electrode layer, and a data line metal layer disposed on the substrate of the substrate, wherein the data line metal layer includes a data line, and the pixel electrode
  • the layer includes a pixel electrode; a thickness of a region of the gate insulating layer corresponding to the pixel electrode and the data line is smaller than a thickness of a region of the gate insulating layer corresponding to the pixel electrode and/or a thickness of a region of the gate insulating layer corresponding to the data line.
  • the gate insulating layer is located below the data line and the pixel electrode.
  • the gate insulating layer is located above the data line and the pixel electrode.
  • the gate insulating layer is located above the pixel electrode and under the data line.
  • the gate insulating layer is located below the pixel electrode and above the data line.
  • the thickness of the gate insulating layer between the pixel electrode and the data line is the gate insulating layer and The thickness of the region corresponding to the pixel electrode and/or the thickness of the region corresponding to the gate insulating layer and the data line
  • the thickness of the region where the gate insulating layer is located between the pixel electrode and the data line is 1/2 of the thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • the embodiment of the invention provides a display device, which comprises the array substrate provided by the embodiment of the invention.
  • the embodiment of the present invention provides a method for fabricating an array substrate, including: forming a gate insulating layer, a pixel electrode layer, and a data line metal layer on a substrate substrate, wherein the data line metal layer includes a data line, and the pixel electrode layer includes a pixel
  • Forming a gate insulating layer on the substrate of the substrate comprises: forming a gate insulating film on the substrate of the substrate, and etching the gate insulating film such that a thickness of a region between the pixel insulating layer corresponding to the pixel electrode and the data line is smaller than The thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • the gate insulating layer is located below the data line and the pixel electrode.
  • the gate insulating film and the pixel electrode layer are formed on the substrate substrate in this order, the gate insulating film is etched before the data line metal layer is formed on the substrate substrate.
  • the gate insulating film and the data line metal layer are sequentially formed on the substrate of the substrate, the gate insulating film is etched before the pixel electrode layer is formed on the substrate.
  • the gate is insulated.
  • the film is etched.
  • the gate insulating layer is located above the data line and the pixel electrode.
  • a gate insulating film is formed on the substrate, and the gate insulating film on the substrate is etched.
  • the gate insulating layer is located above the pixel electrode and under the data line.
  • the gate insulating film, and the data line metal layer are sequentially formed on the substrate of the substrate, the gate insulating film is etched.
  • the gate insulating film is etched before the data line metal layer is formed on the substrate substrate.
  • the gate insulating layer is located below the pixel electrode and above the data line.
  • a data line metal layer, a gate insulating film, and a pixel electrode are sequentially formed on the substrate of the substrate. After the layer, the gate insulating film is etched.
  • the gate insulating film is etched before the pixel electrode layer is formed on the substrate.
  • the thickness of the region where the gate insulating layer is located between the pixel electrode and the data line is 1/5-4 of the thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line. 5.
  • the thickness of the region where the gate insulating layer is located between the pixel electrode and the data line is 1/2 of the thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • FIG. 1 is a schematic top plan view of a conventional array substrate pixel unit
  • Figure 2 is a partial cross-sectional structural view of Figure 1;
  • FIG. 3 is a schematic partial cross-sectional structural view of a pixel unit of an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic partial cross-sectional structural view of another array substrate pixel unit according to an embodiment of the present invention.
  • FIG. 5 is a schematic partial cross-sectional structural view of another array substrate pixel unit according to an embodiment of the present invention.
  • FIG. 6 is a schematic partial cross-sectional structural view of another array substrate pixel unit according to an embodiment of the present invention.
  • FIG. 7 is a schematic partial cross-sectional structural view of another array substrate pixel unit according to an embodiment of the present invention.
  • FIG. 8 is a schematic partial cross-sectional structural view of another array substrate pixel unit according to an embodiment of the present invention.
  • FIG. 9 is a schematic partial cross-sectional structural view of another array substrate pixel unit according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 13 is a schematic view showing the etching of the gate insulating film formed on the substrate of the substrate in the manufacturing method shown in FIG.
  • FIG. 14 is a schematic diagram of forming a data line on a substrate of the substrate in the manufacturing method shown in FIG. 10;
  • FIG. 15 is a schematic diagram of another method for fabricating an array substrate according to an embodiment of the present invention;
  • FIG. 17 is a schematic view showing the etching of the gate insulating film formed on the substrate of the substrate in the manufacturing method shown in FIG. 15;
  • FIG. 14 is a schematic diagram of forming a data line on a substrate of the substrate in the manufacturing method shown in FIG. 10;
  • FIG. 15 is a schematic diagram of another method for fabricating an array substrate according to an embodiment of the present invention;
  • FIG. 17 is a schematic view showing the etching of the gate insulating film formed on the substrate of the substrate in the manufacturing method shown in FIG. 15;
  • FIG. 18 is a schematic diagram of forming a pixel electrode on a substrate of the substrate in the manufacturing method shown in FIG. 15;
  • FIG. 19 is a schematic diagram of another method for fabricating an array substrate according to an embodiment of the present invention;
  • FIG. A schematic diagram of forming a pixel electrode and a data line on a substrate of a village;
  • FIG. 21 is a schematic view showing the etching of the gate insulating film formed on the substrate of the substrate in the manufacturing method shown in FIG. 19;
  • FIG. 22 is a schematic diagram of another method for fabricating an array substrate according to an embodiment of the present invention
  • FIG. 23 is a schematic diagram of another method for fabricating an array substrate according to an embodiment of the present invention
  • FIG. 25 is a schematic diagram of another method for fabricating an array substrate according to an embodiment of the present invention
  • FIG. 26 is a schematic diagram of another method for fabricating an array substrate according to an embodiment of the present invention.
  • 1-village substrate 2-gate line; 3-thin film transistor; 31-gate; 32-source; 33-drain; 4-data line; 5-pixel electrode; 6- common electrode line; Insulation layer; 70-gate insulating film; 8-passivation layer.
  • An embodiment of the present invention provides an array substrate, as shown in FIG. 3 to FIG. 9, including a gate insulating layer 7, a pixel electrode layer, and a data line metal layer disposed on a substrate of the substrate, wherein the data line metal layer includes data.
  • the pixel electrode layer includes the pixel electrode 5; the thickness of the region of the gate insulating layer 7 corresponding to the pixel electrode 5 and the data line 4 is smaller than the thickness of the region of the gate insulating layer 7 corresponding to the pixel electrode 5 and/or the gate insulating layer 7 The thickness of the area corresponding to the data line 4.
  • the gate insulating layer is generally first deposited with a gate insulating film during the fabrication process, and then the gate insulating film is etched, wherein the thickness of the deposited gate insulating film is the same.
  • the thickness of the region between the pixel electrode and the data line formed by the gate insulating layer formed after the etching is smaller than the thickness of the region corresponding to the gate insulating layer and the pixel electrode. And/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • the array substrate in the drawings of the present invention is a partially enlarged view, and the present invention is not submerged for the sake of clarity. Only the film or layer structure related to the present invention is shown in the drawings, and other structures are omitted, which does not indicate that the present invention only Including these layers or structures, embodiments of the invention may also include other desired film layers or structural features.
  • the thickness of the region between the pixel insulating layer corresponding to the pixel electrode and the data line is smaller than the thickness of the region corresponding to the pixel insulating layer and the pixel electrode and/or the thickness of the region corresponding to the gate insulating layer and the data line, and may be corresponding to the gate insulating layer.
  • a thickness of a region between the pixel electrode and the data line is smaller than a thickness of a region of the gate insulating layer corresponding to the pixel electrode; and a thickness of a region between the pixel electrode and the data line corresponding to the gate insulating layer may be smaller than a gate insulating layer corresponding to the data line.
  • the "upper” and “lower” are based on the order of fabricating the film or the layer structure, for example, the film or layer structure which is previously produced may be “below”, and the film or layer which is fabricated later.
  • the structure is "on,,.
  • film refers to a film formed by deposition or other processes on a substrate using a certain material. If the “film” does not require a patterning process throughout the manufacturing process, the “film” may also be referred to as a “layer”; if the “film” requires a patterning process throughout the manufacturing process, it is referred to as "before the patterning process”.
  • the gate insulating layer may be formed by depositing a SiNx (silicon nitride) film on the transparent substrate 1 and etching the formed silicon nitride film to obtain the gate insulating layer. Of course, the formed silicon nitride film may be etched by other purposes such as via etching.
  • the gate insulating film is etched such that a thickness of a region between the pixel insulating layer corresponding to the pixel electrode and the data line is smaller than a thickness of the region corresponding to the gate insulating layer and the pixel electrode and/or a gate insulating layer The thickness of the area corresponding to the data line.
  • An embodiment of the present invention provides an array substrate, wherein a thickness of a region between a pixel electrode and a data line of the gate insulating layer on the array substrate is smaller than a thickness of a region corresponding to the gate insulating layer and the pixel electrode, and/or a gate insulating layer
  • the thickness of the region corresponding to the data line therefore, the storage capacitor formed between the pixel electrode and the data line is almost generated by the insulating layer or the passivation layer, and the interlayer capacitance is small, which can ensure the normality of the electrode signal and improve the display effect.
  • the gate insulating layer is located below the data line and the pixel electrode.
  • the array substrate includes a gate, an active layer, a source layer and a drain, wherein the gate, the source and the drain are three electrodes of the thin film transistor, and the source and the drain are disposed and insulated in the same layer. .
  • An insulating film layer between the active layer and the gate is insulated from the source and the drain.
  • thin film transistors are classified into two types according to the positional relationship between the active layer and the gate: one type is that the gate is under the active layer (and the source and the drain), and this type is called a bottom gate type thin film transistor; One type is that the gate is on the active layer (and the source and drain), and this type is called a top-gate thin film transistor.
  • the above-described top gate type thin film transistor and bottom gate type thin film transistor have their source and drain electrodes disposed in the same layer.
  • there is a side gate type thin film transistor having a source and a drain which are adjacent to the substrate in the direction of the vertical substrate and one away from the substrate.
  • the thin film transistor on the array substrate is a bottom gate type thin film transistor, which may be as shown in FIGS.
  • the thickness of the region of the gate insulating layer 7 corresponding to the pixel electrode 5 and the data line 4 is smaller than the thickness of the region of the gate insulating layer 7 corresponding to the pixel electrode 5 and the gate insulating layer 7 corresponds to the data line 4.
  • the thickness of the area As shown in FIG. 4, the thickness of the region of the gate insulating layer 7 corresponding to the pixel electrode 5 and the data line 4 is smaller than the thickness of the region of the gate insulating layer 7 corresponding to the pixel electrode 5. As shown in FIG.
  • the thickness of the region between the pixel electrode 5 and the data line 4 of the gate insulating layer 7 is smaller than that of the gate insulating layer 7 and the data.
  • the gate insulating layer is located above the data line and the pixel electrode, and the thin film transistor on the array substrate is a top gate type thin film transistor.
  • the thickness of the region between the pixel electrode 5 and the data line 4 of the gate insulating layer 7 is smaller than the thickness of the region corresponding to the gate insulating layer 7 and the pixel electrode 5, and the gate insulating layer 7 and the data.
  • the gate insulating layer is located above the pixel electrode and below the data line.
  • the gate insulating layer 7 is located above the pixel electrode 5 and below the data line 4.
  • the thickness of the region between the pixel insulating layer 7 and the data line 4 of the gate insulating layer 7 is smaller than the thickness of the region of the gate insulating layer 7 corresponding to the pixel electrode 5 and the thickness of the region of the gate insulating layer 7 corresponding to the data line 4.
  • the thickness of the region between the pixel insulating layer corresponding to the pixel electrode and the data line may be smaller than the gate insulating layer and the pixel electrode.
  • the thickness of the corresponding region or the thickness of the region corresponding to the data line of the gate insulating layer is exemplified by way of example only in FIG. 8 in the embodiment of the present invention.
  • the gate insulating layer is located below the pixel electrode and above the data line.
  • the gate insulating layer 7 is located below the pixel electrode 5 and above the data line 4.
  • the thickness of the region between the pixel insulating layer 7 and the data line 4 of the gate insulating layer 7 is smaller than the thickness of the region of the gate insulating layer 7 corresponding to the pixel electrode 5 and the thickness of the region of the gate insulating layer 7 corresponding to the data line 4.
  • the thickness of the region between the pixel insulating layer corresponding to the pixel electrode and the data line may be smaller than the gate insulating layer and the pixel electrode.
  • the thickness of the corresponding region or the thickness of the region corresponding to the data line of the gate insulating layer is exemplified in the embodiment of the present invention by way of example only in FIG.
  • the thickness of the region of the gate insulating layer between the pixel electrode and the data line is 1/5 of a thickness of a region of the gate insulating layer corresponding to the pixel electrode and/or a thickness of a region corresponding to the gate insulating layer and the data line. 4/5.
  • the thickness of the region where the gate insulating layer is located between the pixel electrode and the data line is 1/2 of the thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • the embodiment of the present invention further provides a display device, including the array substrate according to any one of the embodiments of the present invention.
  • the display device may be a liquid crystal display, an electronic paper, or an OLED (Organic) Display devices such as Light-Emitting Diode (OLED) displays, and any products or components having display functions such as televisions, digital cameras, mobile phones, and tablets including these display devices.
  • OLED Organic LED
  • the embodiment of the invention further provides a method for fabricating an array substrate, comprising: forming a gate insulating layer, a pixel electrode layer, and a data line metal layer on a substrate substrate, wherein the data line metal layer comprises a data line, and the pixel electrode layer comprises a pixel
  • Forming a gate insulating layer on the substrate of the substrate comprises: forming a gate insulating film on the substrate of the substrate and etching the gate insulating film such that a thickness of a region between the pixel insulating layer corresponding to the pixel electrode and the data line is smaller than a gate The thickness of the region of the insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • the order of making each layer or film on the array substrate may be different according to the arrangement on the array substrate.
  • the thin film transistor on the array substrate is a top gate thin film transistor and the thin film transistor on the array substrate is different in the fabrication method of the bottom gate thin film transistor, and the fabrication method of the same thin film transistor array substrate is also different. A method of fabricating an array substrate including these two types of thin film transistors will be described in detail below.
  • the gate insulating layer 7 is formed under the data line 4 and the pixel electrode 5.
  • an embodiment of the present invention provides a method for fabricating an array substrate, including:
  • Step S101 forming a gate insulating film on the substrate of the village.
  • a gate insulating film 70 is formed on the substrate 1 on the substrate.
  • the substrate substrate shown may be a transparent substrate or a substrate formed with another film or layer structure.
  • the substrate substrate shown may be a substrate on which a gate metal layer is formed, such as a glass, plastic, or quartz substrate.
  • the method of forming the film or layer structure may be a conventional manner of forming a film or layer structure in the art, such as deposition, sputtering, or the like.
  • Step S102 forming a pixel electrode layer on the substrate of the village.
  • the pixel electrode layer shown includes a pixel electrode, and as shown in Fig. 12, a pixel electrode 5 is formed on the substrate 1 on which the gate insulating film 70 is formed.
  • the gate insulating film is etched, and the gate insulating layer 7 formed after etching is as shown in FIG. Shown.
  • the etching of the gate insulating film can be performed by dry etching. Of course, other etching methods can also be used.
  • the thickness of the region of the gate insulating layer between the pixel electrode and the data line is 1/5 of a thickness of a region of the gate insulating layer corresponding to the pixel electrode and/or a thickness of a region corresponding to the gate insulating layer and the data line. 4/5.
  • the thickness of the region where the gate insulating layer is located between the pixel electrode and the data line is 1/2 of the thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • Step S104 forming a data line metal layer on the substrate of the village.
  • the substrate after the data line metal layer formed on the substrate 1 is as shown in Fig. 14.
  • the data line metal layer includes: a data line 4 and a source and a drain (not shown).
  • a source and a drain of the thin film transistor may be formed while forming a data line metal layer to form a data line. pole.
  • the fabrication of the array substrate is not limited to the above steps, and may further include other steps according to the film or layer structure on the array substrate, and only the film or layer structure related to the present invention is used in the embodiment of the present invention.
  • the fabrication is described as an example to make the description clearer, and other film or layer structures can be specifically fabricated according to the specific conditions of the array substrate.
  • a passivation layer 8 may be disposed on the array substrate, and a passivation layer 8 is formed after the above steps.
  • the gate insulating film and the data line metal layer are sequentially formed on the substrate of the substrate, the gate insulating film is etched before the pixel electrode layer is formed on the substrate.
  • the production methods shown include:
  • Step S201 forming a gate insulating film on the substrate of the village.
  • the formation of the gate insulating film on the substrate of the substrate can be carried out by referring to the above step S101.
  • the data line metal layer shown includes a data line, a source and a drain, and as shown in Fig. 16, a data line 4 is formed on the substrate substrate 1.
  • the data line metal layer includes: a data line 4 and a source and a drain (not shown).
  • a source and a drain of the thin film transistor may be formed while forming a data line metal layer to form a data line. pole.
  • Step S203 etching the gate insulating film.
  • the gate insulating layer 7 formed by etching the gate insulating film is as shown in FIG.
  • the etching of the gate insulating film can be performed by dry etching.
  • other etching methods can also be used.
  • the thickness of the region of the gate insulating layer between the pixel electrode and the data line is a gate insulating layer and a pixel electrode pair.
  • the thickness of the area to be applied and/or the thickness of the area corresponding to the gate insulating layer and the data line is 1/5 to 4/5.
  • the thickness of the region where the gate insulating layer is located between the pixel electrode and the data line is 1/2 of the thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • Step S204 forming a pixel electrode layer on the substrate of the village.
  • the array substrate after the pixel electrode 5 is formed on the substrate 1 is as shown in Fig. 18. It should be noted that the fabrication of the array substrate is not limited to the above steps, and may further include other steps according to the film or layer structure on the array substrate. In the embodiment of the present invention, only the film or layer structure related to the present invention is fabricated. For example, the description will be made to make the description clearer, and other film or layer structures are specifically fabricated according to the specific conditions of the array substrate. For example, a passivation layer 8 may be disposed on the array substrate, and the array substrate formed after the above steps is as shown in FIG.
  • the gate is The insulating film is etched. It should be noted that the order in which the pixel electrode layer and the data line metal layer are formed may be interchanged. For example, as shown in FIG. 19, the manufacturing method includes:
  • Step S301 forming a gate insulating film on the substrate of the village.
  • the step S101 can be referred to by forming a gate insulating film on the substrate of the substrate.
  • Step S302 forming a pixel electrode layer and a data line metal layer on the substrate of the village.
  • the pixel electrode layer and the data line metal layer are formed on the substrate of the substrate, and the data electrode metal layer may be formed after the pixel electrode layer is formed on the array substrate or after the data line metal layer is formed on the array substrate.
  • a pixel electrode is formed again, and a pixel electrode layer or a data line metal layer is formed on the substrate of the substrate as shown in FIG.
  • Step S303 etching the gate insulating film.
  • the gate insulating layer 7 formed by etching the gate insulating film is as shown in Fig.21.
  • the thickness of the region of the gate insulating layer between the pixel electrode and the data line is 1/5 of the thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region corresponding to the gate insulating layer and the data line. 4/5.
  • the thickness of the region where the gate insulating layer is located between the pixel electrode and the data line is 1/2 of the thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • the fabrication of the array substrate is not limited to the above steps, according to the array substrate.
  • the film or layer structure may further include other steps.
  • only the film or layer structure related to the present invention is described as an example.
  • Other film or layer structures are specifically fabricated according to the specific conditions of the array substrate.
  • a passivation layer 8 may be disposed on the array substrate, and the array substrate formed after the above steps is as shown in FIG. 3.
  • the gate insulating layer 7 is located above the data line 4 and the pixel electrode 5.
  • the manufacturing method includes:
  • Step S401 forming a data line metal layer and a pixel electrode layer on the substrate of the village.
  • the pixel electrode layer or the data line metal layer is formed on the substrate of the substrate, and the data electrode metal layer is formed after the pixel electrode layer is formed on the array substrate, or the data line metal layer is formed on the array substrate. Pixel electrode.
  • Step S402 forming a gate insulating film on the substrate of the village.
  • Step S403 etching the gate insulating film on the substrate of the village.
  • the fabrication of the array substrate is not limited to the above steps, and may further include other steps according to the film or layer structure on the array substrate.
  • the film or layer structure related to the present invention is fabricated.
  • other film or layer structures are specifically fabricated according to the specific conditions of the array substrate.
  • a passivation layer 8 may be disposed on the array substrate, and the array substrate formed after the above steps is as shown in FIGS. 6 and 7.
  • the gate insulating layer 7 is located above the pixel electrode 5 and below the data line 4.
  • the manufacturing method includes:
  • Step S501 forming a pixel electrode layer on the substrate of the village.
  • the formation of the pixel electrode layer on the substrate of the substrate may be as in other embodiments of the present invention, and is not described herein.
  • Step S502 forming a gate insulating film on the substrate of the village.
  • Step S503 forming a data line metal layer on the substrate of the village.
  • the formation of the data line metal layer on the substrate of the substrate may be as in other embodiments of the present invention and will not be described herein.
  • Step S504 etching the gate insulating film.
  • the etching of the gate insulating film can be performed by dry etching. Of course, it can also use other etching methods.
  • the thickness of the region of the gate insulating layer between the pixel electrode and the data line is 1/5 of a thickness of a region of the gate insulating layer corresponding to the pixel electrode and/or a thickness of a region corresponding to the gate insulating layer and the data line. 4/5.
  • the thickness of the region of the gate insulating layer between the pixel electrode and the data line is 1/2 of the thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • the fabrication of the array substrate is not limited to the above steps, and may further include other steps according to the film or layer structure on the array substrate.
  • the film or layer structure related to the present invention is fabricated.
  • other film or layer structures are specifically fabricated according to the specific conditions of the array substrate.
  • the manufacturing method includes:
  • Step S601 forming a pixel electrode layer on the substrate of the village.
  • the formation of the pixel electrode layer on the substrate of the substrate may be as in other embodiments of the present invention, and is not described herein.
  • Step S602 forming a gate insulating film on the substrate of the village.
  • the formation of the gate insulating film on the substrate of the substrate may be as in other embodiments of the present invention, and will not be described herein.
  • Step S603 etching the gate insulating film.
  • the etching of the gate insulating film can be performed by dry etching.
  • the thickness of the region of the gate insulating layer between the pixel electrode and the data line is 1/5 of a thickness of a region of the gate insulating layer corresponding to the pixel electrode and/or a thickness of a region corresponding to the gate insulating layer and the data line. 4/5.
  • the thickness of the region where the gate insulating layer is located between the pixel electrode and the data line is 1/2 of the thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • Step S604 forming a data line metal layer on the substrate of the village.
  • the formation of the data line metal layer on the substrate of the substrate may be as in other embodiments of the present invention and will not be described herein.
  • the fabrication of the array substrate is not limited to the above steps, and may further include other steps according to the film or layer structure on the array substrate.
  • the film or layer structure related to the present invention is fabricated.
  • other film or layer structures are specifically fabricated according to the specific conditions of the array substrate.
  • the gate insulating layer is located below the pixel electrode and above the data line.
  • the gate insulating film is etched.
  • the manufacturing method includes:
  • Step S701 forming a pixel electrode layer on the substrate of the village.
  • the formation of the pixel electrode layer on the substrate of the substrate may be as in other embodiments of the present invention, and is not described herein.
  • Step S702 forming a gate insulating film on the substrate of the village.
  • the formation of the gate insulating film on the substrate of the substrate may be as in other embodiments of the present invention, and will not be described herein.
  • Step S703 etching the gate insulating film.
  • the etching of the gate insulating film can be performed by dry etching. Of course, it can also use other etching methods.
  • the thickness of the region of the gate insulating layer between the pixel electrode and the data line is 1/5 of a thickness of a region of the gate insulating layer corresponding to the pixel electrode and/or a thickness of a region corresponding to the gate insulating layer and the data line. 4/5.
  • the thickness of the region of the gate insulating layer between the pixel electrode and the data line is 1/2 of the thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • Step S704 forming a data line metal layer on the substrate of the village.
  • the formation of the data line metal layer on the substrate of the substrate may be as in other embodiments of the present invention and will not be described herein.
  • the fabrication of the array substrate is not limited to the above steps, and may further include other steps according to the film or layer structure on the array substrate, which is only relevant to the present invention in the embodiment of the present invention.
  • the fabrication of the film or layer structure is described as an example, and other film or layer structures are specifically produced according to the specific conditions of the array substrate.
  • the gate insulating film is etched before the pixel electrode layer is formed on the substrate.
  • the manufacturing method includes:
  • Step S801 forming a data line metal layer on the substrate of the village.
  • the formation of the data line metal layer on the substrate of the substrate may refer to other embodiments of the present invention, and details are not described herein.
  • Step S802 forming a gate insulating film on the substrate of the village.
  • the formation of the gate insulating film on the substrate of the substrate may be as in other embodiments of the present invention, and will not be described herein.
  • Step S803 etching the gate insulating film.
  • the etching of the gate insulating film can be performed by dry etching. Of course, it can also use other etching methods.
  • the thickness of the region of the gate insulating layer between the pixel electrode and the data line is 1/5 of a thickness of a region of the gate insulating layer corresponding to the pixel electrode and/or a thickness of a region corresponding to the gate insulating layer and the data line. 4/5.
  • the thickness of the region of the gate insulating layer between the pixel electrode and the data line is 1/2 of the thickness of the region of the gate insulating layer corresponding to the pixel electrode and/or the thickness of the region of the gate insulating layer corresponding to the data line.
  • Step S804 forming a pixel electrode layer on the substrate of the village.
  • the formation of the pixel electrode layer on the substrate of the substrate may be as in other embodiments of the present invention, and is not described herein.
  • the fabrication of the array substrate is not limited to the above steps, and may further include other steps according to the film or layer structure on the array substrate.
  • the film or layer structure related to the present invention is fabricated.
  • other film or layer structures are specifically fabricated according to the specific conditions of the array substrate.
  • An embodiment of the present invention provides an array substrate, a method for fabricating the same, and a display device.
  • the pixel electrode and the data line of the array substrate are located between the gate insulating layer and the passivation layer, and the pixel electrode and the data line are separated by a certain distance to form a memory.
  • a capacitor a gate insulating layer is located under the pixel electrode and the data line, and a thickness of a region of the gate insulating layer corresponding to the pixel electrode is at least greater than a thickness of a region between the corresponding pixel electrode and the data line of the gate insulating layer, at the pixel electrode and the data line
  • the storage capacitor formed between them is almost blunt
  • the layer generated by the layer has a small interlayer capacitance, which can reduce the interference to the pixel electrode and improve the display effect.

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Abstract

La présente invention concerne un substrat de réseau, un procédé de fabrication associé et un appareil d'affichage. Le substrat de réseau comprend une couche d'isolation de grille (7), une couche d'électrode de pixel et une couche métallique de ligne de données, toutes étant disposées sur un substrat de base (1). La couche métallique de ligne de données comprend une ligne de données (4). La couche d'électrode de pixel comprend une électrode de pixel (5). L'épaisseur d'une zone, correspondant à une zone entre l'électrode de pixel (5) et la ligne de données (4), de la couche d'isolation de grille (7) est inférieure à l'épaisseur d'une zone, correspondant à l'électrode de pixel (5), de la couche d'isolation de grille (7) et/ou l'épaisseur d'une zone, correspondant à la ligne de données (4), de la couche d'isolation de grille (7).
PCT/CN2013/088109 2013-07-31 2013-11-29 Substrat de réseau, procédé de fabrication associé et appareil d'affichage WO2015014053A1 (fr)

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CN103413813B (zh) * 2013-07-31 2016-05-25 北京京东方光电科技有限公司 一种阵列基板及其制作方法、显示装置
CN103794556A (zh) * 2014-01-22 2014-05-14 北京京东方光电科技有限公司 阵列基板及其制作方法和液晶显示装置
CN104112710B (zh) * 2014-07-08 2017-01-18 深圳市华星光电技术有限公司 阵列基板的制作方法、阵列基板及液晶显示装置
CN114740665B (zh) * 2022-04-29 2023-08-01 广州华星光电半导体显示技术有限公司 一种显示面板及显示装置

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