WO2015013415A1 - A soc design with critical technology pitch alignment - Google Patents

A soc design with critical technology pitch alignment Download PDF

Info

Publication number
WO2015013415A1
WO2015013415A1 PCT/US2014/047834 US2014047834W WO2015013415A1 WO 2015013415 A1 WO2015013415 A1 WO 2015013415A1 US 2014047834 W US2014047834 W US 2014047834W WO 2015013415 A1 WO2015013415 A1 WO 2015013415A1
Authority
WO
WIPO (PCT)
Prior art keywords
interconnects
pitch
metal
interconnect
interconnect level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2014/047834
Other languages
English (en)
French (fr)
Inventor
Xiangdong Chen
Ohsang Kwon
Esin Terzioglu
Hadi BUNNALIM
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Priority to CA2917642A priority Critical patent/CA2917642A1/en
Priority to JP2016529862A priority patent/JP6208350B2/ja
Priority to EP14758188.8A priority patent/EP3025370B1/en
Priority to CN201480041649.6A priority patent/CN105453263B/zh
Priority to KR1020167003858A priority patent/KR101820813B1/ko
Publication of WO2015013415A1 publication Critical patent/WO2015013415A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present disclosure relates generally to a circuit layout, and more particularly, to a system on a chip (SOC) design with critical technology pitch alignment.
  • SOC system on a chip
  • a pitch is the distance between the same type of adjacent elements.
  • an area scaling of approximately x 2 % should be obtained.
  • approximately a 50% area scaling should be obtained.
  • an x% pitch scaling may not provide the best cost, power, and performance benefits. As such, methods and apparatuses are needed for determining a pitch or pitch scaling given a desired area scaling.
  • An SOC apparatus includes a plurality of gate interconnects with a minimum pitch g, a plurality of metal interconnects with a minimum pitch m, and a plurality of vias interconnecting the gate interconnects and the metal interconnects.
  • the vias have a minimum pitch v.
  • the values m, g, and v are such that g 2 + m 2 ⁇ v 2 and an LCM of g and m is less than 20g.
  • FIG. 1 is a diagram illustrating pitch scalings.
  • FIG. 2 is a diagram illustrating gate interconnect, metal interconnect, and via pitches.
  • FIG. 3 is a diagram illustrating a first set of exemplary gate interconnect, metal interconnect, and via pitches.
  • FIG. 4 is a diagram illustrating a second set of exemplary gate interconnect, metal interconnect, and via pitches.
  • FIG. 5 is a flow chart of a method of operating an SOC apparatus.
  • FIG. 1 is a diagram 100 illustrating pitch scalings. As shown in FIG. 1, in a
  • the gate interconnect may also be referred to as "POLY" interconnect
  • POLY interconnect may have a minimum pitch of gi (the distance between any two gate interconnects is at the minimum gi).
  • the gate interconnect may have a minimum pitch of g 2 (the distance between any two gate interconnects is at the minimum g 2 ).
  • gi may be 130nm. A 70% scaling of the gate interconnect pitch would result in a g 2 of 90nm.
  • the first metal layer Ml may have a minimum pitch of ml i (the distance between any two first metal layer Ml interconnects is at the minimum ml i).
  • the first metal layer Ml may have a minimum pitch of ml 2 (the distance between any two first metal layer Ml interconnects is at the minimum ml 2 ).
  • ml i may be 90nm. A 70% scaling of the first metal layer Ml interconnect pitch would result in an ml 2 of 64nm.
  • other metal layers Ma may have a minimum pitch of mai (the distance between any two metal layer Ma interconnects is at the minimum mai).
  • the metal layer Ma may have a minimum pitch of ma 2 (the distance between any two metal layer Ma interconnects is at the minimum ma 2 ).
  • mai may be 90nm.
  • a 70% scaling of the metal layer Ma interconnect pitch would result in an ma 2 of 64nm.
  • the Mb metal layer may have a pitch of mb.
  • the Mb metal layer is higher than the Ma metal layer and may be wider than the Ma metal layer.
  • the Ma metal layer may include an M2 metal layer and an M3 metal layer, and the Mb metal layer may include an M4 metal layer.
  • the Ma metal layer may include an M2 metal layer, an M3 metal layer, and an M4 metal layer, and the Mb metal layer may include an M5 metal layer.
  • mb is 80nm. In a 28nm manufacturing process technology, vias may have a minimum pitch of vi (the distance between any two vias is at the minimum vi).
  • the vias may have a minimum pitch of v 2 (the distance between any two vias is at the minimum v 2 ).
  • vi may be 130nm. Maintaining a process limit due to a single patterning process (using only one mask rather than multiple masks in a double patterning process) limits the minimum pitch of any two vias. Assuming a 115nm minimum pitch (i.e., assuming v 2 is 115nm) results in an 88% scaling of the vias.
  • the via pitch is not necessarily scaled similar to other elements, such as the gate and metal interconnects.
  • FIG. 2 is a diagram 200 illustrating gate interconnect, metal interconnect, and via pitches.
  • the two shown metal layer Ml interconnects extend in the same direction as the gate interconnects, are connected to the gate interconnects, and have the same pitch as the gate interconnects.
  • Other metal layer Ml interconnects may have a smaller pitch, such as 64nm. Accordingly, as shown in FIG. 2, when the gate interconnect pitch g 2 is a minimum 90nm and the metal layer M2 pitch ma 2 is a minimum 64nm, the via pitch v 2 is 1 lOnm. If the process limit for single patterning is 115nm for the via pitch, a via pitch of 1 lOnm would not satisfy the minimum via pitch requirements for single patterning.
  • the gate interconnect, vias, and metal interconnect pitches would not align, which can cause pin access difficulty, degrade place and route efficiency, and cause a low place and route utilization (the area utilized may not be reduced to 50%).
  • the scaling of the gate interconnect pitch g 2 and/or the metal layer M2 interconnect pitch ma 2 may be increased in order to satisfy the requisite scaling of the via pitch v 2 , and allow for improved pin access, place and route efficiency, and place and route utilization.
  • FIG. 3 is a diagram 300 illustrating a first set of exemplary gate interconnect, metal interconnect, and via pitches.
  • the scaling of the gate interconnect pitch g 2 and/or the metal layer M2 interconnect pitch ma 2 may be increased in order to satisfy the requisite scaling of the via pitch v 2 .
  • the scaling of the gate interconnect pitch g 2 is increased to 73.85%).
  • the via pitch v 2 is 115nm, which satisfies the aforementioned 115nm via pitch limit. As shown in FIG.
  • the metal layer M3 pitch may also be a minimum of 64nm.
  • the least common multiple (LCM) also referred to as lowest common multiple
  • the LCM of the minimum gate and metal interconnect pitches may be constrained to be less than 20 times the minimum gate interconnect pitch.
  • the LCM of the minimum gate and metal interconnect pitches may be constrained to be less than 1920nm (20*96nm). In this case, the minimum gate and metal interconnect pitches of 96nm and 64nm, respectively, satisfy such a requirement.
  • FIG. 4 is a diagram 400 illustrating a second set of exemplary gate interconnect, metal interconnect, and via pitches.
  • the minimum gate interconnect pitch may be 96nm
  • the minimum metal layers M2 may be 64nm
  • the minimum metal layer M3 pitch may be 72nm
  • the minimum metal layer M5 pitch may be 80nm.
  • the LCM of 96nm, 72nm, and 80nm is 1440nm.
  • an SOC apparatus may have a plurality of gate interconnects with a minimum pitch g, a plurality of metal interconnects with a minimum pitch m, and a plurality of vias interconnecting the gate interconnects and the metal interconnects.
  • the vias have a minimum pitch v.
  • the pitches g, m, and v are such that g 2 + m 2 ⁇ v 2 and an LCM of g and m is less than 20g.
  • g is equal to or is approximately equal to 96nm
  • m is equal to or is approximately equal to 64nm
  • v is equal to or is approximately equal to 115nm.
  • the LCM is 192nm, which is less than 1920nm.
  • the pitches g, m, and v are constrained by the equations g 2 + m 2 > v 2 and LCM(g,m) ⁇ 20g.
  • a via pitch v is assumed, and the gate interconnect pitch g and metal interconnect pitch m are adjusted to satisfy the equations.
  • the plurality of metal interconnects are on at least one of a first interconnect level or a second interconnect level, and the vias interconnect the metal interconnects between the first interconnect level and the second interconnect level.
  • the first interconnect level may be a first metal layer Ml and the second interconnect level may be a second metal layer M2.
  • the SOC apparatus may further include a second plurality of metal interconnects with a minimum pitch of m 2 , where m 2 > m and the LCM of g, m, and m 2 is less than 20g.
  • g is equal to or is approximately equal to 96nm
  • m is equal to or is approximately equal to 72nm
  • v is equal to or is approximately equal to 115nm
  • m 2 is equal to or is approximately equal to 80nm.
  • the LCM is 1440nm.
  • the pitches g, m, m 2 , and v are constrained by the equations g 2 + m 2 > v 2 and LCM(g,m,m 2 ) ⁇ 20g.
  • a via pitch v is assumed, and the gate interconnect pitch g, metal interconnect pitch m, and metal interconnect pitch m 2 are adjusted to satisfy the equations.
  • the plurality of metal interconnects may be on a third interconnect level (e.g., metal layer M3) and the second plurality of metal interconnects may be on a fifth interconnect level (e.g., metal layer M5) higher than the third interconnect level.
  • the vias interconnect metal interconnects between the plurality of metal interconnects and the second plurality of metal interconnects.
  • the third interconnect level may be a third metal layer M3 and the fifth interconnect level may be a fifth metal layer M5.
  • FIG. 5 is a flow chart 500 of a method of operating an SOC apparatus. At step
  • a current is flowed through a plurality of gate interconnects with a minimum pitch g.
  • a current is flowed through a plurality of metal interconnects with a minimum pitch m.
  • a current is flowed through a plurality of vias interconnecting the gate interconnects and the metal interconnects.
  • the vias have a minimum pitch v.
  • the pitches of the gate interconnects, metal interconnects, and vias satisfy g 2 + m 2 ⁇ v 2 .
  • an LCM of g and m is less than 20g.
  • the plurality of metal interconnects may be on at least one of a first interconnect level or a second interconnect level, and the vias may interconnect the metal interconnects between the first interconnect level and the second interconnect level.
  • the first interconnect level may be a first metal layer and the second interconnect level may be a second metal layer.
  • a current is flowed through a second plurality of metal interconnects with a minimum pitch of m 2 , where m 2 > m and the LCM of g, m, and m 2 is less than 20g.
  • the plurality of metal interconnects may be on a third interconnect level and the second plurality of metal interconnects may be on a fifth interconnect level.
  • the vias may interconnect metal interconnects between the plurality of metal interconnects and the second plurality of metal interconnects.
  • the third interconnect level may be a third metal layer and the fifth interconnect level may be a fifth metal layer.
  • an SOC apparatus includes means for flowing a current through a plurality of gate interconnects with a minimum pitch g, means for flowing a current through a plurality of metal interconnects with a minimum pitch m, and means for flowing a current through a plurality of vias interconnecting the gate interconnects and the metal interconnects.
  • the vias having a minimum pitch v, g 2 + m 2 ⁇ v 2 , and an LCM of g and m is less than 20g.
  • the means for flowing a current through a plurality of gate interconnects is the plurality of gate interconnects
  • the means for flowing a current through a plurality of metal interconnects is the plurality of metal interconnects
  • the means for flowing a current through a plurality of vias is the plurality of vias.
  • the SOC apparatus may further include means for flowing a current through a second plurality of metal interconnects with a minimum pitch of m 2 , where m 2 > m and the LCM of g, m, and m 2 is less than 20g.
  • the means for flowing a current through a second plurality of metal interconnects is the second plurality of metal interconnects.
  • x% pitch scaling may be used for some interconnects.
  • the minimum pitch scaling may be determined based on minimum via pitch limits. Such a scaling may provide improved cost, power, and performance benefits over an x% pitch scaling for all interconnects.
  • Combinations such as "at least one of A, B, or C,” “at least one of A, B, and C,” and “A, B, C, or any combination thereof include any combination of A, B, and/or C, and may include multiples of A, multiples of B, or multiples of C.
  • combinations such as “at least one of A, B, or C,” “at least one of A, B, and C,” and “A, B, C, or any combination thereof may be A only, B only, C only, A and B, A and C, B and C, or A and B and C, where any such combinations may contain one or more member or members of A, B, or C.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • General Engineering & Computer Science (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
PCT/US2014/047834 2013-07-25 2014-07-23 A soc design with critical technology pitch alignment Ceased WO2015013415A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CA2917642A CA2917642A1 (en) 2013-07-25 2014-07-23 A soc design with critical technology pitch alignment
JP2016529862A JP6208350B2 (ja) 2013-07-25 2014-07-23 クリティカル技術ピッチ整合をもつｓｏｃ設計
EP14758188.8A EP3025370B1 (en) 2013-07-25 2014-07-23 A soc design with critical technology pitch alignment
CN201480041649.6A CN105453263B (zh) 2013-07-25 2014-07-23 具有关键技术节距对准的soc设计
KR1020167003858A KR101820813B1 (ko) 2013-07-25 2014-07-23 Soc 장치 및 soc 장치를 동작시키는 방법

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201361858567P 2013-07-25 2013-07-25
US61/858,567 2013-07-25
US14/338,229 US9331016B2 (en) 2013-07-25 2014-07-22 SOC design with critical technology pitch alignment
US14/338,229 2014-07-22

Publications (1)

Publication Number Publication Date
WO2015013415A1 true WO2015013415A1 (en) 2015-01-29

Family

ID=52389817

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2014/047834 Ceased WO2015013415A1 (en) 2013-07-25 2014-07-23 A soc design with critical technology pitch alignment

Country Status (7)

Country Link
US (1) US9331016B2 (enExample)
EP (1) EP3025370B1 (enExample)
JP (1) JP6208350B2 (enExample)
KR (1) KR101820813B1 (enExample)
CN (1) CN105453263B (enExample)
CA (1) CA2917642A1 (enExample)
WO (1) WO2015013415A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9391056B2 (en) * 2013-08-16 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Mask optimization for multi-layer contacts
US9786663B2 (en) * 2013-08-23 2017-10-10 Qualcomm Incorporated Layout construction for addressing electromigration
US9972624B2 (en) 2013-08-23 2018-05-15 Qualcomm Incorporated Layout construction for addressing electromigration
US11205616B2 (en) 2017-06-20 2021-12-21 Intel Corporation Internal node jumper for memory bit cells
US10903239B2 (en) * 2017-07-28 2021-01-26 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit device with improved layout
DE102018118053A1 (de) 2017-07-28 2019-01-31 Taiwan Semiconductor Manufacturing Co., Ltd. Integrierte Schaltungsvorrichtung mit verbessertem Layout
US10916498B2 (en) 2018-03-28 2021-02-09 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure for logic circuit
KR102842752B1 (ko) * 2019-12-04 2025-08-04 삼성전자주식회사 반도체 장치

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5471093A (en) * 1994-10-28 1995-11-28 Advanced Micro Devices, Inc. Pseudo-low dielectric constant technology
US20040068710A1 (en) * 2002-10-04 2004-04-08 Yasuhiro Miyakawa Method of fabricating a semiconductor device having a multilevel interconnections
US20060289861A1 (en) * 2005-06-27 2006-12-28 Correale Anthony Jr Systems and arrangements to interconnect components of a semiconductor device
US20080061441A1 (en) * 2006-09-07 2008-03-13 Chung-Shi Liu Flexible via design to improve reliability
US20100006951A1 (en) * 2006-03-09 2010-01-14 Tela Innovations, Inc. Semiconductor Device Portion Having Sub-193 Nanometers -Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having Equal Number of PMOS and NMOS Transistors
US20130072020A1 (en) * 2011-09-19 2013-03-21 Texas Instruments Incorporated Method For Ensuring DPT Compliance for Auto-Routed Via Layers

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3241106B2 (ja) * 1992-07-17 2001-12-25 株式会社東芝 ダイナミック型半導体記憶装置及びその製造方法
US5508938A (en) 1992-08-13 1996-04-16 Fujitsu Limited Special interconnect layer employing offset trace layout for advanced multi-chip module packages
US6207479B1 (en) * 1999-06-14 2001-03-27 Taiwan Semiconductor Manufacturing Co., Ltd. Place and route method for integrated circuit design
US7398498B2 (en) * 2001-08-23 2008-07-08 Cadence Design Systems, Inc. Method and apparatus for storing routes for groups of related net configurations
US6618846B2 (en) * 2001-08-31 2003-09-09 Synopsys, Inc. Estimating capacitance effects in integrated circuits using congestion estimations
US7084476B2 (en) * 2004-02-26 2006-08-01 International Business Machines Corp. Integrated circuit logic with self compensating block delays
US7414275B2 (en) * 2005-06-24 2008-08-19 International Business Machines Corporation Multi-level interconnections for an integrated circuit chip
JP4791855B2 (ja) * 2006-02-28 2011-10-12 株式会社東芝 半導体記憶装置
US7446352B2 (en) * 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
JP2008171977A (ja) * 2007-01-11 2008-07-24 Matsushita Electric Ind Co Ltd 半導体集積回路のレイアウト構造
US7888705B2 (en) * 2007-08-02 2011-02-15 Tela Innovations, Inc. Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same
US7737554B2 (en) * 2007-06-25 2010-06-15 Taiwan Semiconductor Manufacturing Company, Ltd. Pitch by splitting bottom metallization layer
WO2010019441A1 (en) 2008-08-14 2010-02-18 Nantero, Inc. Nonvolatile nanotube programmable logic devices and field programmable gate array
US8198655B1 (en) * 2009-04-27 2012-06-12 Carnegie Mellon University Regular pattern arrays for memory and logic on a semiconductor substrate
US8174868B2 (en) 2009-09-30 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Embedded SRAM structure and chip
WO2012053125A1 (ja) * 2010-10-21 2012-04-26 パナソニック株式会社 半導体装置
JP6066542B2 (ja) 2010-11-18 2017-01-25 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置
US8860141B2 (en) * 2012-01-06 2014-10-14 International Business Machines Corporation Layout to minimize FET variation in small dimension photolithography
US8863048B1 (en) * 2013-03-15 2014-10-14 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for implementing multiple-patterning-aware correct-by-construction layout processing for an electronic design

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5471093A (en) * 1994-10-28 1995-11-28 Advanced Micro Devices, Inc. Pseudo-low dielectric constant technology
US20040068710A1 (en) * 2002-10-04 2004-04-08 Yasuhiro Miyakawa Method of fabricating a semiconductor device having a multilevel interconnections
US20060289861A1 (en) * 2005-06-27 2006-12-28 Correale Anthony Jr Systems and arrangements to interconnect components of a semiconductor device
US20100006951A1 (en) * 2006-03-09 2010-01-14 Tela Innovations, Inc. Semiconductor Device Portion Having Sub-193 Nanometers -Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having Equal Number of PMOS and NMOS Transistors
US20080061441A1 (en) * 2006-09-07 2008-03-13 Chung-Shi Liu Flexible via design to improve reliability
US20130072020A1 (en) * 2011-09-19 2013-03-21 Texas Instruments Incorporated Method For Ensuring DPT Compliance for Auto-Routed Via Layers

Also Published As

Publication number Publication date
CA2917642A1 (en) 2015-01-29
JP2016527724A (ja) 2016-09-08
KR101820813B1 (ko) 2018-01-22
EP3025370B1 (en) 2017-02-01
CN105453263A (zh) 2016-03-30
US20150028495A1 (en) 2015-01-29
US9331016B2 (en) 2016-05-03
EP3025370A1 (en) 2016-06-01
CN105453263B (zh) 2021-03-12
KR20160034338A (ko) 2016-03-29
JP6208350B2 (ja) 2017-10-04

Similar Documents

Publication Publication Date Title
EP3025370B1 (en) A soc design with critical technology pitch alignment
US10593700B2 (en) Standard cell architecture with M1 layer unidirectional routing
US11437375B2 (en) Layout construction for addressing electromigration
CN110036478B (zh) 采用电耦合到金属分流器的电压轨以减少或避免电压降的增加的标准单元电路
US8255858B2 (en) Method for adjusting capacitance of capacitors without affecting die area
US20070228419A1 (en) Unit cell of semiconductor integrated circuit and wiring method and wiring program using unit cell
KR101488697B1 (ko) 감소된 전력 상태들을 구현하는 시스템 및 방법
EP3493256A3 (en) Pitch-divided interconnects for advanced integrated circuit structure fabrication
US20140159200A1 (en) High-density stacked planar metal-insulator-metal capacitor structure and method for manufacturing same
EP3036767B1 (en) Layout construction for addressing electromigration
US20160351490A1 (en) Cross-couple in multi-height sequential cells for uni-directional m1
WO2017196458A1 (en) Power gate placement techniques in three-dimensional (3d) integrated circuits (ics) (3dics)
EP3311409A1 (en) Circuit and layout for a high density antenna protection diode
US20180308796A1 (en) Metal Patterning For Internal Cell Routing
CN110494978A (zh) 采用电耦合源极区和电源轨来放宽相邻mos标准单元之间的源极-漏极端到端间距的金属氧化物半导体(mos)标准单元
DE112017008330T5 (de) Integrierte schaltungen (ics) mit elektromigrations (em) -resistenten segmenten in einer verbindungsebene
CN107463724B (zh) 用于设计和制造半导体器件的方法以及相应的半导体器件
CN104079480A (zh) 一种三维集成电路片上网络的路由方法及其系统
CN108988401A (zh) 多通道交直流混联断面输电能力及其约束条件的评估方法
US10026735B2 (en) Decoupling capacitor with metal programmable knee frequency
US20130191796A1 (en) Integrated circuit layout modification
Roberts et al. Application of on-chip MIM decoupling capacitor for 90nm SOI microprocessor
US10431541B2 (en) Semiconductor device, layout pattern and method for manufacturing an integrated circuit
JP2009111265A (ja) 半導体装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201480041649.6

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14758188

Country of ref document: EP

Kind code of ref document: A1

DPE1 Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101)
ENP Entry into the national phase

Ref document number: 2917642

Country of ref document: CA

ENP Entry into the national phase

Ref document number: 2016529862

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: IDP00201600674

Country of ref document: ID

REG Reference to national code

Ref country code: BR

Ref legal event code: B01A

Ref document number: 112016001318

Country of ref document: BR

ENP Entry into the national phase

Ref document number: 20167003858

Country of ref document: KR

Kind code of ref document: A

REEP Request for entry into the european phase

Ref document number: 2014758188

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2014758188

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 112016001318

Country of ref document: BR

Kind code of ref document: A2

Effective date: 20160121