CN105453263B - 具有关键技术节距对准的soc设计 - Google Patents

具有关键技术节距对准的soc设计 Download PDF

Info

Publication number
CN105453263B
CN105453263B CN201480041649.6A CN201480041649A CN105453263B CN 105453263 B CN105453263 B CN 105453263B CN 201480041649 A CN201480041649 A CN 201480041649A CN 105453263 B CN105453263 B CN 105453263B
Authority
CN
China
Prior art keywords
interconnects
pitch
metal
interconnect level
interconnect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201480041649.6A
Other languages
English (en)
Chinese (zh)
Other versions
CN105453263A (zh
Inventor
X·陈
O·翁
E·特泽格鲁
H·汶纳林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN105453263A publication Critical patent/CN105453263A/zh
Application granted granted Critical
Publication of CN105453263B publication Critical patent/CN105453263B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • General Engineering & Computer Science (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CN201480041649.6A 2013-07-25 2014-07-23 具有关键技术节距对准的soc设计 Active CN105453263B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361858567P 2013-07-25 2013-07-25
US61/858,567 2013-07-25
US14/338,229 US9331016B2 (en) 2013-07-25 2014-07-22 SOC design with critical technology pitch alignment
US14/338,229 2014-07-22
PCT/US2014/047834 WO2015013415A1 (en) 2013-07-25 2014-07-23 A soc design with critical technology pitch alignment

Publications (2)

Publication Number Publication Date
CN105453263A CN105453263A (zh) 2016-03-30
CN105453263B true CN105453263B (zh) 2021-03-12

Family

ID=52389817

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480041649.6A Active CN105453263B (zh) 2013-07-25 2014-07-23 具有关键技术节距对准的soc设计

Country Status (7)

Country Link
US (1) US9331016B2 (enExample)
EP (1) EP3025370B1 (enExample)
JP (1) JP6208350B2 (enExample)
KR (1) KR101820813B1 (enExample)
CN (1) CN105453263B (enExample)
CA (1) CA2917642A1 (enExample)
WO (1) WO2015013415A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9391056B2 (en) * 2013-08-16 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Mask optimization for multi-layer contacts
US9972624B2 (en) 2013-08-23 2018-05-15 Qualcomm Incorporated Layout construction for addressing electromigration
US9786663B2 (en) 2013-08-23 2017-10-10 Qualcomm Incorporated Layout construction for addressing electromigration
KR20250008983A (ko) * 2017-06-20 2025-01-16 인텔 코포레이션 메모리 비트 셀들을 위한 내부 노드 점퍼
US10903239B2 (en) 2017-07-28 2021-01-26 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit device with improved layout
DE102018118053A1 (de) 2017-07-28 2019-01-31 Taiwan Semiconductor Manufacturing Co., Ltd. Integrierte Schaltungsvorrichtung mit verbessertem Layout
US10916498B2 (en) 2018-03-28 2021-02-09 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure for logic circuit
KR102842752B1 (ko) 2019-12-04 2025-08-04 삼성전자주식회사 반도체 장치

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5471093A (en) * 1994-10-28 1995-11-28 Advanced Micro Devices, Inc. Pseudo-low dielectric constant technology

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3241106B2 (ja) * 1992-07-17 2001-12-25 株式会社東芝 ダイナミック型半導体記憶装置及びその製造方法
US5508938A (en) 1992-08-13 1996-04-16 Fujitsu Limited Special interconnect layer employing offset trace layout for advanced multi-chip module packages
US6207479B1 (en) * 1999-06-14 2001-03-27 Taiwan Semiconductor Manufacturing Co., Ltd. Place and route method for integrated circuit design
US7398498B2 (en) * 2001-08-23 2008-07-08 Cadence Design Systems, Inc. Method and apparatus for storing routes for groups of related net configurations
US6618846B2 (en) * 2001-08-31 2003-09-09 Synopsys, Inc. Estimating capacitance effects in integrated circuits using congestion estimations
US6735753B2 (en) 2002-10-04 2004-05-11 Oki Electric Industry Co., Ltd. Method of fabricating a semiconductor device having a multilevel interconnections
US7084476B2 (en) * 2004-02-26 2006-08-01 International Business Machines Corp. Integrated circuit logic with self compensating block delays
US7414275B2 (en) * 2005-06-24 2008-08-19 International Business Machines Corporation Multi-level interconnections for an integrated circuit chip
US7492013B2 (en) * 2005-06-27 2009-02-17 International Business Machines Corporation Systems and arrangements to interconnect components of a semiconductor device
JP4791855B2 (ja) * 2006-02-28 2011-10-12 株式会社東芝 半導体記憶装置
US7932545B2 (en) 2006-03-09 2011-04-26 Tela Innovations, Inc. Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers
US7446352B2 (en) * 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US7557449B2 (en) 2006-09-07 2009-07-07 Taiwan Semiconductor Manufacturing Company, Ltd. Flexible via design to improve reliability
JP2008171977A (ja) * 2007-01-11 2008-07-24 Matsushita Electric Ind Co Ltd 半導体集積回路のレイアウト構造
US7888705B2 (en) * 2007-08-02 2011-02-15 Tela Innovations, Inc. Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same
US7737554B2 (en) * 2007-06-25 2010-06-15 Taiwan Semiconductor Manufacturing Company, Ltd. Pitch by splitting bottom metallization layer
WO2010019441A1 (en) 2008-08-14 2010-02-18 Nantero, Inc. Nonvolatile nanotube programmable logic devices and field programmable gate array
US8198655B1 (en) * 2009-04-27 2012-06-12 Carnegie Mellon University Regular pattern arrays for memory and logic on a semiconductor substrate
US8174868B2 (en) 2009-09-30 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Embedded SRAM structure and chip
WO2012053125A1 (ja) * 2010-10-21 2012-04-26 パナソニック株式会社 半導体装置
JP6066542B2 (ja) 2010-11-18 2017-01-25 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置
US9112000B2 (en) * 2011-09-19 2015-08-18 Texas Instruments Incorporated Method for ensuring DPT compliance for auto-routed via layers
US8860141B2 (en) * 2012-01-06 2014-10-14 International Business Machines Corporation Layout to minimize FET variation in small dimension photolithography
US8863048B1 (en) * 2013-03-15 2014-10-14 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for implementing multiple-patterning-aware correct-by-construction layout processing for an electronic design

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5471093A (en) * 1994-10-28 1995-11-28 Advanced Micro Devices, Inc. Pseudo-low dielectric constant technology

Also Published As

Publication number Publication date
EP3025370A1 (en) 2016-06-01
US9331016B2 (en) 2016-05-03
EP3025370B1 (en) 2017-02-01
US20150028495A1 (en) 2015-01-29
CN105453263A (zh) 2016-03-30
JP2016527724A (ja) 2016-09-08
WO2015013415A1 (en) 2015-01-29
JP6208350B2 (ja) 2017-10-04
CA2917642A1 (en) 2015-01-29
KR101820813B1 (ko) 2018-01-22
KR20160034338A (ko) 2016-03-29

Similar Documents

Publication Publication Date Title
CN105453263B (zh) 具有关键技术节距对准的soc设计
US10593700B2 (en) Standard cell architecture with M1 layer unidirectional routing
KR101775211B1 (ko) 집적 회로용 레이아웃 설계 시스템 및 방법
US11437375B2 (en) Layout construction for addressing electromigration
JP6352561B1 (ja) 高密度アンテナ保護ダイオードのための回路およびレイアウト
US11508725B2 (en) Layout construction for addressing electromigration
CN107683474B (zh) 用于单向m1的多高度顺序单元中的交叉耦合的时钟信号分发布局
CA2962779A1 (en) Via structure for optimizing signal porosity
US9634026B1 (en) Standard cell architecture for reduced leakage current and improved decoupling capacitance
CN110036477A (zh) 用于高性能标准单元的多过孔结构
CN109791929A (zh) 用于减小面积的最小轨道标准单元电路
Vaidyanathan et al. Design implications of extremely restricted patterning
CN110024122B (zh) 具有金属可编程拐点频率的去耦电容器
CN107078121B (zh) Io功率总线网格结构设计
Tsai et al. Productivity enhancement study: yield, cost, and turn-around-time modeling for EUV and high NA EUV

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant