Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
  • H01L29/66742—Thin film unipolar transistors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
  • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
  • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
  • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

• the present disclosure relates to methods for locally improving the electrical conductivity of metal oxide semiconductor layers.
• the present disclosure further relates to methods for fabricating metal oxide semiconductor based thin film transistors.
• Amorphous metal oxide semiconductor thin film transistors such as for example amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors, have been investigated as a potential replacement for silicon-based TFTs in flat-panel display applications, because of their higher mobility and larger area uniformity.
• a-IGZO amorphous indium-gallium-zinc oxide
• the conventional amorphous silicon TFTs used as switching devices in active-matrix liquid crystal displays, have the advantage of large area uniformity. However, their field-effect mobility ( ⁇ 1 cm 2 /V. s) is too low to drive organic light- emitting diodes (OLED).
• the high parasitic capacitance in such TFT structures is related to the presence of an overlap between source and gate and/or between drain and gate. This overlap is due to the use of a transistor gate length that is larger than the channel length, to avoid or limit the negative consequences of misalignment between the gate and the source and drain.
• Another approach consists of performing an argon plasma treatment, a hydrogen plasma treatment or a NH 3 plasma treatment.
• argon plasma treatment a hydrogen plasma treatment or a NH 3 plasma treatment.
• the thickness of the metal film is preferably 10 nm or less, such that the metal film may be completely oxidized during the heat treatment in the oxygen containing atmosphere. In this way the need for performing an etching step to remove non-oxidized metal may be avoided.
• the present disclosure aims to provide a method for locally increasing the electrical conductivity of metal oxide semiconductor layers, wherein the increased conductivity has a good thermal stability, and wherein the method can be performed at temperatures lower than 200 °C.
• the present disclosure further aims to provide a method for fabricating self- aligned top-gate metal oxide semiconductor thin film transistors with good source and drain contacts, a good field effect mobility (e.g. higher than 10 cm 2 /Vs), a good thermal stability, and a good bias stability, wherein the transistors can be fabricated at temperatures lower than 200 °C.
• a good field effect mobility e.g. higher than 10 cm 2 /Vs
• a good thermal stability e.g. higher than 10 cm 2 /Vs
• a good bias stability e.g. higher than 10 cm 2 /Vs
• the disclosure relates to a method for improving the electrical conductivity of a metal oxide semiconductor layer at predetermined locations.
• the method comprises: providing on a substrate a metal oxide semiconductor layer; and providing by means of Atomic Layer Deposition (ALD) a metal oxide layer on top of the metal oxide semiconductor layer, wherein the metal oxide layer is in physical contact, i.e. is interfacing by means of a direct physical interface, with the metal oxide semiconductor layer at the predetermined locations.
• ALD Atomic Layer Deposition
• the metal oxide layer may for example have a thickness in the range between 10 nm and 100 nm, or between 1 1 nm and 99 nm, the present disclosure not being limited thereto.
• providing, for instance depositing, the metal oxide layer by means of Atomic Layer Deposition may be done at a temperature in the range between 150 °C and 200 °C.
• the method may further comprise, before providing the metal oxide layer on top of the metal oxide semiconductor layer: providing a reducing layer comprising an alkaline metal (e.g. any of or any combination of Li, Na, K, Rb, Cs or Fr) or an alkaline earth metal (e.g. any of or any combination of Be, Mg, Ca, Sr, Ba or a) in physical contact with the metal oxide semiconductor layer at the predetermined locations; inducing a chemical reduction reaction between the reducing layer and the metal oxide semiconductor layer, e.g. by performing an annealing step at a temperature in the range between 20 °C and 200 ' ⁇ ; and removing the reducing layer and reaction by-products from the reduction reaction, e.g. by rinsing in water or alcohol.
• an alkaline metal e.g. any of or any combination of Li, Na, K, Rb, Cs or Fr
• an alkaline earth metal e.g. any of or any combination of Be, Mg, Ca, Sr, Ba or
• the metal oxide semiconductor layer may for example comprise gallium-indium-zinc-oxide (GIZO or IGZO) and the metal oxide layer may for example comprise Al 2 0 3 .
• GZO or IGZO gallium-indium-zinc-oxide
• the present disclosure is not limited thereto.
• Other metal oxide semiconductors may be used, such as for example ZnO, ZnSnO, InO, InZnO, InZnSnO, LalnZnO, GalnO, HflnZnO, MgZnO, LalnZnO, TiO, TilnSnO, SclnZnO, SilnZnO and ZrlnZnO, or ZrZnSnO.
• Other metal oxide layers may be used, such as for example Hf0 2 , Ta 2 0 5 , Zr0 2 , or Ga 2 0 3 .
• the metal oxide layer may be deposited from trimethylaluminium and water (H20) as precursors, or for example from triethylaluminium and water or from triisobutylaluminium and water as precursors.
• H20 trimethylaluminium and water
• different precursors may be mixed or different precursors may be used alternatingly when forming the metal oxide layer.
• the disclosure further relates to a method for fabricating self-aligned (meaning that the source and drain are self-aligned to the gate) top-gate (the gate is provided on top of the metal oxide semiconductor layer) metal oxide semiconductor thin film transistors.
• the method comprises: providing a metal oxide semiconductor layer on a substrate; depositing a gate dielectric layer on top of the metal oxide semiconductor layer; depositing a gate electrode layer on the gate dielectric layer; patterning the gate electrode layer and the gate insulating layer to form a gate electrode and a gate insulator, thereby defining a channel region in the metal oxide semiconductor layer; patterning the metal oxide semiconductor layer, thereby defining a source region and a drain region in the metal oxide semiconductor layer; and depositing a metal oxide layer by means of Atomic Layer Deposition, for instance at least in the source and the drain region, thereby increasing the electrical conductivity of the metal oxide semiconductor layer in the source region and in the drain region where the metal oxide layer is in direct physical contact, i.e.
• the method may further comprise: providing a dielectric layer on top of the metal oxide layer; forming vias through the dielectric layer and the metal oxide layer; and filling the vias with a metal to form a source contact and a drain contact.
• the method may further comprise, before providing the metal oxide layer on top of the metal oxide semiconductor layer: providing a reducing layer comprising an alkaline metal (e.g. any of or any combination of Li, Na, K, Rb, Cs or Fr) or an alkaline earth metal (e.g. any of or any combination of Be, Mg, Ca, Sr, Ba or a) in physical contact with the metal oxide semiconductor layer at the predetermined locations; inducing a chemical reduction reaction between the reducing layer and the metal oxide semiconductor layer, e.g. by performing an annealing step at a temperature in the range between 20 °C and 200 ⁇ ; and removing the reducing layer and reaction by-products from the reduction reaction, e.g. by rinsing in water or alcohol.
• an alkaline metal e.g. any of or any combination of Li, Na, K, Rb, Cs or Fr
• an alkaline earth metal e.g. any of or any combination of Be, Mg, Ca, Sr, Ba or
• metal oxide layer not only results in an improved electrical conductivity of the underlying metal oxide semiconductor layer, but that depositing the metal oxide layer in addition results in passivation and encapsulation (e.g. the metal oxide semiconductor layer is fully covered or encapsulated, i.e. not exposed anymore to the environment) of the underlying metal oxide semiconductor layer.
• Figure 1 (a) to Figure 1 (f) illustrate a method for fabricating a metal oxide semiconductor thin film transistor in accordance with a method of the present disclosure.
• Figure 2 shows transfer characteristics (IDS-VQS) of an a-IGZO thin film transistor fabricated in accordance with a method of the present disclosure.
• Figure 3 shows output characteristics (l D s-V D s) of an a-IGZO thin film transistor fabricated in accordance with a method of the present disclosure.
• Figure 5 shows the V TH shift of a-IGZO TFTs fabricated according to a method of the present disclosure, as a function of the stress time in both positive and negative directions.
• top, bottom, over, under and the like in the description are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the disclosure described herein are capable of operation in other orientations than described or illustrated herein.
• the present disclosure provides a method for improving (increasing) the electrical conductivity of metal oxide semiconductor layers, for example for locally improving the electrical conductivity of such layers at the location of the source and drain contacts of a metal oxide semiconductor thin film transistor.
• the increase of the electrical conductivity may be substantial, for instance by at least 1 order of magnitude, e.g. up to 3 orders of magnitude.
• a method for increasing the electrical conductivity of a metal oxide semiconductor layer at predetermined locations comprises: depositing a metal oxide layer, by means of Atomic Layer Deposition, on top of and in physical contact, thus interfacing, with the metal oxide semiconductor layer at the predetermined locations.
• depositing a metal oxide layer, by means of Atomic Layer Deposition on top of and in physical contact, thus interfacing, with the metal oxide semiconductor layer at the predetermined locations.
• the metal oxide layer can for example comprise Al 2 0 3 , Hf0 2 , Ta 2 0 5 , Zr0 2 , or Ga 2 0 3 , the present disclosure not being limited thereto.
• the metal oxide layer may for example be an Al 2 0 3 layer. It may for example be deposited from trimethylaluminium (TMA, AI(CH 3 ) 3 ) and water (H 2 0) as precursors. However, other precursors may be used, such as for example triethylaluminium and water or triisobutylaluminium and water to form an Al 2 0 3 layer.
• the metal oxide layer may for example be a Ga 2 0 3 layer.
• Precursors that may be used for this layer comprise for example triethylgallium and water, trimethylgallium and water, triisopropylgallium and water or tri-tert-butylgallium and water, the present disclosure not being limited thereto.
• different precursors may be mixed or different precursors may be used alternatingly when forming the metal oxide layer.
• the metal oxide layer may for example have a thickness in the range between 10 nm and 100 nm, and it may for example be deposited at a temperature in the range between 150 ⁇ € and 200 ⁇ €, for example between 150 ⁇ € and 170°C, the present disclosure not being limited thereto.
• the method of the present disclosure can advantageously be used in a fabrication process for thin film transistors having a metal oxide semiconductor active layer, for locally increasing the electrical conductivity at predetermined locations corresponding to source regions and drain regions, thereby improving charge injection from the source and drain contacts.
• the method can advantageously be used in a fabrication process for self-aligned top-gate thin film transistors.
• the method may also be used in a fabrication process for other metal oxide semiconductor based devices, e.g. diodes or transistor-diodes, for improving charge injection from contacts.
• the metal oxide semiconductor layer can for example comprise gallium-indium- zinc-oxide (GIZO, also referred to as IGZO), or other metal oxide based semiconductors, e.g. of following compositions (without indication of the stoichiometry): ZnO, ZnSnO, InO, InZnO, InZnSnO, LalnZnO, GalnO, HflnZnO, MgZnO, LalnZnO, TiO, TilnSnO, SclnZnO, SilnZnO and ZrlnZnO, ZrZnSnO.
• GZO gallium-indium- zinc-oxide
• IGZO gallium-indium- zinc-oxide
• the present disclosure is not limited thereto and the method can be used with other suitable metal oxide semiconductors known to a person skilled in the art.
• These semiconductor layers of typical thickness between 5 nm and 50 nm, or between 6 nm and 49 nm, can be provided by a multitude of methods such as for example sputtering, thermal evaporation, pulsed laser deposition, and spin-casting, ink-jet printing or drop casting of precursor solutions.
• a method for fabricating self-aligned top-gate metal oxide semiconductor thin film transistors is further described, wherein a method of the present disclosure is used for locally improving the electrical conductivity of the metal oxide semiconductor layer in the source and drain regions.
• the ALD metal oxide layer changes the conductivity of the underlying source and drain regions, and it also has the function of a passivation and encapsulation layer.
• FIG. 1 An exemplary process flow for fabricating a metal oxide semiconductor thin film transistor in accordance with the present disclosure is schematically illustrated in Figure 1 (a) to Figure 1 (f).
• a metal oxide semiconductor layer 12, such as a GIZO layer is provided on a substrate 10, e.g. by sputtering, laser ablation or spin-coating from a precursor solution.
• the substrate 10 comprises a silicon substrate 101 and a dielectric layer 102, e.g. a silicon oxide layer.
• the thickness of the GIZO layer 12 can for example be in the order of about 10 nm or about 15 nm to 20 nm, for instance in between 10 nm and 20 nm, or between 1 1 and 19 nm, but other suitable thicknesses can be used.
• a gate dielectric layer 13 such as for example a silicon dioxide layer, is deposited on top of the metal oxide semiconductor layer 12, for example by means of plasma enhanced Chemical Vapour Deposition.
• a gate electrode layer 14 such as for example a Mo layer, on top of the gate dielectric layer 13 ( Figure 1 (b)).
• the gate electrode layer 14 and the gate insulating layer 13 are then patterned, e.g. by dry etching, to form a gate electrode 141 and a gate insulator 131 , as illustrated in Figure 1 (c).
• the metal oxide semiconductor layer 12 is patterned, thereby defining the active layer 1 1 of the thin film transistor ( Figure 1 (d)).
• the metal oxide semiconductor layer can for example be patterned by wet etching, for example using buffered HF or oxalic acid. It is an advantage of using oxalic acid for the active layer patterning that it has a good selectivity towards the underlying layers.
• the patterned gate electrode 141 defines in the active layer 1 1 a channel region 1 10, a source region 1 1 1 and a drain region 1 12, as schematically illustrated in Figure 1 (d). The source and drain regions are directly adjacent to the channel region, and are self-aligned.
• the metal oxide semiconductor layer is patterned after patterning of the gate electrode layer and the gate dielectric layer.
• the present disclosure is not limited thereto.
• the metal oxide semiconductor layer can also be patterned before the gate fabrication process, or in a later stage after the gate fabrication process.
• TMA trimethylaluminium
• AI(CH 3 ) 3 trimethylaluminium
• H 2 0 water
• the deposition of such a layer results in an increased conductivity of the metal oxide semiconductor layer at locations where the Al 2 0 3 layer 15 is in direct physical contact with the metal oxide semiconductor layer 1 1 . Therefore, in the source region 1 1 1 and the drain region 1 12 of the metal oxide semiconductor layer 1 1 an enhanced conductivity is obtained, at least in an upper portion of the metal oxide semiconductor layer.
• TMA and H 2 0 used as ALD precursors for Al 2 0 3 may react with the IGZO surface.
• the doping effect occurs.
• the upper portion preferably has a depth/thickness of a few nm up to 10 or about 10 nm. If the ALD metal oxide deposition is combined with an additional doping (e.g. using Ca, see above), the enhanced conductivity is expected to extend deeper into the metal oxide semiconductor layer, for example up to a few tens of nm, as for instance up to 20 nm or up to 30 nm.
• a dielectric layer 16 such as for example a silicon nitride layer is provided on top of the metal oxide layer 15, followed by the formation of vias through this dielectric layer 16 and the underlying metal oxide layer 15 at the location where source and drain contacts are to be formed.
• the vias are then filled with a suitable metal, such as for example Mo, to form a source electrode 21 and a drain electrode 22.
• a suitable metal such as for example Mo
• Figure 2 shows transfer characteristics (l D s-V G s) of an a-IGZO thin film transistor fabricated in accordance with a method of the present disclosure as described above, with an ALD Al 2 0 3 metal oxide layer 15.
• Figure 3 shows output characteristics (l D s-V D s) of this transistor.
• the a-IGZO TFT exhibits high thermal stability and good electrical performance.
• a field-effect mobility of 14.82 cm 2 /V.s, a threshold voltage of 3.6 V, a sub-threshold swing of 0.42 V/dec, and an on/off current ratio of about 10 8 are observed.

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Ceramic Engineering (AREA)
• Manufacturing & Machinery (AREA)
• Thin Film Transistor (AREA)
• Chemical & Material Sciences (AREA)
• Chemical Kinetics & Catalysis (AREA)
• Crystallography & Structural Chemistry (AREA)
• General Chemical & Material Sciences (AREA)

Priority Applications (3)

Applications Claiming Priority (2)

Publications (1)

Family

ID=48856533

Family Applications (1)

Country Status (5)

Cited By (2)

Families Citing this family (4)

Citations (4)

Family Cites Families (5)

• 2014
  • 2014-06-11 WO PCT/EP2014/062120 patent/WO2015010825A1/en active Application Filing
  • 2014-06-11 JP JP2016528381A patent/JP6426177B2/ja not_active Expired - Fee Related
  • 2014-06-11 KR KR1020157037203A patent/KR20160034262A/ko active IP Right Grant
  • 2014-06-11 CN CN201480041709.4A patent/CN105409003B/zh not_active Expired - Fee Related
  • 2014-06-13 TW TW103120479A patent/TWI660432B/zh not_active IP Right Cessation

Patent Citations (4)

Also Published As

Similar Documents

Legal Events