WO2015004715A1 - Dispositif de mémoire à semi-conducteurs et son procédé de commande - Google Patents

Dispositif de mémoire à semi-conducteurs et son procédé de commande Download PDF

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Publication number
WO2015004715A1
WO2015004715A1 PCT/JP2013/068665 JP2013068665W WO2015004715A1 WO 2015004715 A1 WO2015004715 A1 WO 2015004715A1 JP 2013068665 W JP2013068665 W JP 2013068665W WO 2015004715 A1 WO2015004715 A1 WO 2015004715A1
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WIPO (PCT)
Prior art keywords
current
cache
memory device
semiconductor memory
bit line
Prior art date
Application number
PCT/JP2013/068665
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English (en)
Japanese (ja)
Inventor
阿部　克巳
吉原　正浩
尚文 安彦
Original Assignee
株式会社 東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Priority to PCT/JP2013/068665 priority Critical patent/WO2015004715A1/fr
Publication of WO2015004715A1 publication Critical patent/WO2015004715A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells

Definitions

  • Embodiments relate to a semiconductor memory device and a control method thereof.
  • NAND flash memory Semiconductor memory devices such as NAND flash memory are widely known.
  • a semiconductor memory device capable of improving the efficiency of core operation and a control method thereof.
  • a semiconductor memory device is electrically connected to a plurality of memory cells, a plurality of word lines electrically connected to control gates of the plurality of memory cells, and the plurality of memory cells.
  • the device further includes a data cache electrically connected to the bit line, and a controller that controls a write operation to the memory cell. Furthermore, when the cache operation of the data cache is used in the write operation, the device repeats the program operation and the verify operation at a first time period, and does not use the cache operation of the data cache in the write operation. In this case, the program operation and the verify operation are repeated at a period of a second time shorter than the first time.
  • FIG. 1 is a circuit diagram showing a structure of a semiconductor memory device according to a first embodiment.
  • FIG. 6 is a diagram for explaining a core operation and a serial operation of the semiconductor memory device according to the first embodiment. It is a wave form diagram for demonstrating operation
  • FIG. 6 is a waveform diagram for explaining the operation of the semiconductor memory device according to the first embodiment.
  • FIG. 6 is a waveform diagram for explaining in detail the operation of the semiconductor memory device of the first embodiment. It is a circuit diagram which shows the structure of the semiconductor memory device of 2nd Embodiment.
  • FIG. 1 is a circuit diagram showing the structure of the semiconductor memory device of the first embodiment.
  • the semiconductor memory device of FIG. 1 is a NAND flash memory.
  • a storage circuit 9 and a current supply unit 10 are provided.
  • the current supply unit 10 includes a first constant current source 11, a second constant current source 12, a first MOS transistor 13 as an example of a first switch unit, and an example of a second switch unit.
  • the second MOS transistor 14 and the comparator 15 are provided.
  • the memory cell array 1 includes a plurality of NAND cell units 1a arranged in a matrix.
  • Each NAND cell unit 1a includes a plurality of memory cells MC (MC0 to MC31) connected in series to each other, and selection transistors S1 and S2 connected to both ends of these memory cells MC.
  • the control gates of these memory cells MC are electrically connected to different word lines WL (WL0 to WL31), respectively, and the gate electrodes of the selection transistors S1, S2 are selection gate lines SG1, parallel to the word line WL, Each is electrically connected to SG2.
  • a set of a plurality of memory cells MC sharing one word line WL constitutes one page or a plurality of pages.
  • a set of a plurality of NAND cell units 1a sharing the same word line WL and select gate lines SG1 and SG2 constitutes a block BLK serving as a data erasing unit.
  • each NAND cell unit 1a the source of the selection transistor S1 is electrically connected to the common source line CELSRC, and the drain of the selection transistor S2 is electrically connected to the corresponding bit line BL (BL0 to BLj). Has been.
  • the memory cell array 1 includes a plurality of blocks BLK (BLK0 to BLKn) in the extending direction of the bit lines BL.
  • the memory cell array 1 including these blocks BLK is formed in one cell well (CPWELL) of the semiconductor substrate.
  • Each block BLK has a plurality of NAND cell units 1a.
  • the sense amplifier 2 is electrically connected to a plurality of sense amplifiers 2a electrically connected to the corresponding bit line BL, a plurality of sense latches 2b electrically connected to the corresponding sense amplifier 2a, and each sense amplifier 2a. And a switch transistor 2c that operates in response to a BLPRE signal from the controller 6.
  • the sense amplifier 2 forms a page buffer for sensing read data and holding write data.
  • the data cache 3 includes a plurality of data caches 3a electrically connected to the corresponding sense latch 2b. These data caches 3 a are connected to data input / output terminals via the input / output buffer 5. The data cache 3 can temporarily store read data and write data.
  • the row decoder 4 is electrically connected to the word line WL and the select gate lines SG1 and SG2. The row decoder 4 selects and drives the word line WL and the selection gate lines SG1 and SG2 of any block BLK.
  • the input / output buffer 5 exchanges data between the data cache 3 and the data input / output terminal, and receives command data and address data.
  • the controller 6 constitutes a control unit that controls a sequence (for example, write operation, read operation, erase operation, etc.) for the memory cell array 1.
  • the controller 6 receives external control signals such as a write enable signal WEn, a read enable signal REn, an address latch enable signal ALE, a command latch enable signal CLE, and performs overall control of the memory operation.
  • the controller 6 has a command interface (not shown) and an address holding / transfer circuit, and determines whether the supplied data is write data or address data. In accordance with the determination result, write data is transferred to the sense amplifier 2, and address data is transferred to the row decoder 4 and the sense amplifier 2.
  • the controller 6 performs read, write, and erase sequence control and control of applied voltages such as a read voltage, a write voltage, and an erase voltage based on an external control signal.
  • the controller 6 controls the sequence by controlling the sense amplifier 2, the data cache 3, the row decoder 4, the input / output buffer 5, and the voltage control circuit 7.
  • the voltage generation circuit 7 includes a plurality (eight in this example) of boosting circuits 7a and a pulse generation circuit 7b.
  • the booster circuit 7a can be configured by a charge pump circuit.
  • the voltage generation circuit 7 switches the number of boosting circuits 7 a to be driven according to a control signal from the controller 6.
  • the booster circuit 7a controls the pulse generation circuit 7b to adjust the pulse width and pulse height of the pulse voltage for the write operation and the erase operation.
  • the ROM fuse 8 is provided in the ROM fuse area of the memory cell array 1.
  • the data held in the ROM fuse area is written at the time of shipment of the NAND flash memory, for example, and is not erased after shipment. Examples of such data include the pulse width and pulse height (voltage setting data) of the pulse voltage for the write operation and the erase operation, information on the bad block and bad column, and the like.
  • the controller 6 controls the number of boosting circuits 7a to be driven according to the voltage setting data and the like.
  • the ROM fuse 8 is provided in the ROM fuse area of the memory cell array 1.
  • the present invention is not limited to such a configuration.
  • a register may be provided outside the memory cell array 1.
  • the data storage circuit 9 is a rewritable nonvolatile storage circuit for storing various data for memory control.
  • the first and second constant current sources 11 and 12 generate first and second currents I 1 and I 2 , respectively.
  • the first and second MOS transistors 13 and 14 switch whether the first and second currents I 1 and I 2 are allowed to pass or be cut off in accordance with the CACHE signal and the NOCACHE signal from the controller 6, respectively.
  • the CACHE signal and the NOCACHE signal are examples of the first and second control signals, respectively.
  • the comparator 15 compares the voltage VHSA of the wiring for supplying the first and second currents I 1 and I 2 to the sense amplifier 2 and the power supply voltage VDDSA, and the comparison result between the voltage VHSA and the power supply voltage VDDSA. (VHSA detection signal) is output to the controller 6.
  • first and second constant current sources 11 and 12 the first and second MOS transistors 13 and 14, and the comparator 15 will be described later.
  • FIG. 2 is a diagram for explaining a core operation and a serial operation of the semiconductor memory device of the first embodiment.
  • the semiconductor memory device of this embodiment includes a data cache 3 and can perform data transfer between the data cache 3 and the data input / output terminal behind the core operation for the memory cell array 1. Since this data transfer is performed using a serial bus between them, it is called a serial operation. Further, the semiconductor memory device of this embodiment can select whether or not to use the cache operation of the data cache 3 in accordance with a command from the controller 6 or the like.
  • serial operation there is a process of transferring data from the data input / output terminal to the data cache 3 when writing data to the memory cell MC of the memory cell array 1.
  • core operation there is a process of charging the bit line BL for the non-write target memory cell MC when writing data to the memory cell MC of the memory cell array 1.
  • FIG. 2A shows the operation of the semiconductor memory device when the cache operation is used.
  • FIG. 2B shows the operation of the semiconductor memory device when the cache operation is not used.
  • FIG. 3 is a waveform diagram for explaining the operation of the semiconductor memory device of the comparative example.
  • Fig. 3 (a) shows the core operation when the cache operation is used.
  • FIG. 3A shows a CACHE signal that is set to high when instructing to use a cache operation, and a NOCACHE signal that is set to high when instructing not to use a cache operation. .
  • the CACHE signal is set to high and the NOCACHE signal is set to low.
  • FIG. 3A further shows a voltage V B applied to the bit line BL for the non-write target memory cell MC and a voltage applied to the word line WL (selected word line) for the memory cell MC.
  • V W and current I flowing into the sense amplifier 2a for the memory cell MC are shown.
  • the ground voltage VSS is applied to the bit line BL connected to the write target memory cell MC during the verify operation.
  • a desired first voltage V B1 is applied to the bit line BL connected to the non-write target memory cell MC as shown in FIG.
  • the desired second voltage V B2 is applied.
  • the first voltage V B1 and the second voltage V B2 are different voltages.
  • bit line BL connected to the non-write target memory cell MC is charged to increase the voltage V B of the bit line BL to the power supply voltage VDDSA, and then the voltage of the bit line BL. V B is maintained at the power supply voltage VDDSA.
  • a symbol T 1 indicates an execution period of the program operation when the cache operation is used.
  • One cycle period corresponds to a period of one loop of the program operation and the verify operation.
  • a limit value I peak of a peak current during operation is defined.
  • the core operating current I C when charging the bit line BL is one of the factors that cause a large peak current. Therefore, if the core operating current I C is increased for fast charging of the bit line BL, it becomes difficult to limit the current I to the limit value I peak or less. Therefore, in FIG. 3 (a), the core operation current I C at the time of charging the bit line BL (specifically, I peak -I S) relatively small value is limited to.
  • Fig. 3 (b) shows the core operation when the cache operation is not used.
  • a symbol T 2 indicates an execution period of the program operation when the cache operation is not used.
  • the core operating current I C is set to the same value whether or not the cache operation is used, but generally, the period required for charging the bit line BL is equal to the core operating current I C. Proportional to size.
  • the time required for the verify operation does not change whether the cache operation is used or not. Therefore, in this comparative example, the one cycle period t 1 when the cache operation is used and the cache operation are not used.
  • FIG. 4 is a waveform diagram for explaining the operation of the semiconductor memory device of the first embodiment.
  • FIG. 4 (a) shows the core operation when the cache operation is used.
  • FIG. 4B shows the core operation when the cache operation is not used.
  • the core operating current (bit line charging current) I C ′ when the cache operation is not used is set to a value larger than the core operating current I C when the cache operation is used (I C '> I C ).
  • the value of I C ′ is set to I C + I S.
  • the currents I C and I C ′ are examples of first and second currents, respectively.
  • the bit line BL when the cache operation is not used, the bit line BL can be charged in a short period by charging the bit line BL with a large core operating current I C ′. Therefore, in this embodiment, the execution period T 2 of the program operation when the cache operation is not used is shorter than the execution period T 1 of the program operation when the cache operation is used (T 2 ⁇ T 1 ). .
  • the cache operation is used for one cycle period t 2 when the cache operation is not used. This is shorter than the one cycle period t 1 in the case (t 2 ⁇ t 1 ).
  • the one cycle period t 1 when the cache operation is used is an example of the first time
  • the one cycle period t 2 when the cache operation is not used is the example of the second time that is shorter than the first time. is there.
  • the core operation when using the cache operation, not only can the core operation be made efficient by parallelization, but also when the cache operation is not used, the core operation is made efficient by increasing the core operation current. Can be realized.
  • the CACHE signal When using a cache operation, the CACHE signal is set high and the NOCACHE signal is set low. As a result, the first current I 1 from the first constant current source 11 passes through the first MOS transistor 13, and the second current I 2 from the second constant current source 12 is It is cut off by the MOS transistor 14. As a result, the first current I 1 is supplied to the bit line BL for the non-write target memory cell MC via the sense amplifier 2a. This first current I 1 corresponds to the core operating current I C.
  • the CACHE signal is set to low and the NOCACHE signal is set to high.
  • the first current I 1 from the first constant current source 11 is cut off by the first MOS transistor 13, and the second current I 2 from the second constant current source 12 is Passes through the MOS transistor 14.
  • a second current I 2 that is larger than the first current I 1 is supplied to the bit line BL for the memory cell MC that is not to be written via the sense amplifier 2a.
  • This second current I 2 corresponds to the core operating current I C ′.
  • the current I needs to be limited to the limit value I peak or less as described above. Therefore, in this embodiment, by using constant current sources (first and second constant current sources 13 and 14) as current sources of the first and second currents I 1 and I 2 , the magnitude of the current I is increased. Is limited.
  • the voltage VHSA of the wiring for supplying these currents I 1 and I 2 also rises with the charging of the bit line BL.
  • the comparator 15 compares the voltage VHSA with the power supply voltage VDDSA and outputs the comparison result (VHSA detection signal) to the controller 6. That is, the comparator 15 detects that the voltage VHSA has reached the power supply voltage VDDSA and outputs a detection signal to the controller 6. When receiving this detection signal, the controller 6 performs control to make a transition to the next operation.
  • the current supply unit 10 dynamically selects the core operating currents I C and I C ′ according to whether or not to use the cache operation, and completes charging. Accordingly, the writing process can be shifted to the next sequence.
  • FIG. 5 is a waveform diagram for explaining in detail the operation of the semiconductor memory device of the first embodiment.
  • FIG. 5 (a) shows a serial operation and a core operation at the time of write processing when using a cache operation.
  • command data CMD In the serial operation when the cache operation is used, command data CMD, address data ADD, write data DATA, and command data 10h indicating that the cache operation is used are transferred from the data input / output terminal to the data cache 3a.
  • the program operation of applying a write voltage V PGM to the selected word line WL, and the verify operation of applying a verify voltage V R to the selected word line WL are alternately performed.
  • the ground voltage VSS is applied to the bit line BL connected to the memory cell MC to be written during the verify operation, and the bit line BL is held at a desired voltage during the verify operation.
  • a desired first voltage V B1 is applied to the bit line BL connected to the non-write target memory cell MC during the program operation, and during the verify operation.
  • a desired second voltage V B2 is applied.
  • the application process of the first voltage V B1 is executed during the period T 1 , and at this time, the core operating current I C is used for charging the bit line BL.
  • FIG. 5B shows a serial operation and a core operation at the time of write processing when the cache operation is not used.
  • command data CMD In the serial operation when the cache operation is not used, command data CMD, address data ADD, write data DATA, and command data 15h indicating that the cache operation is not used are transferred from the data input / output terminal to the sense latch 2b.
  • the program operation of applying a write voltage V PGM to the selected word line WL, and the verify operation of applying a verify voltage V R to the selected word line WL are alternately performed.
  • the ground voltage VSS is applied to the bit line BL connected to the memory cell MC to be written during the verify operation, and the bit line BL is held at a desired voltage during the verify operation.
  • a desired first voltage V B1 is applied to the bit line BL connected to the non-write target memory cell MC during the program operation, and during the verify operation.
  • a desired second voltage V B2 is applied.
  • the application process of the first voltage V B1 is executed during the period T 2 , and at this time, the core operating current I C ′ is used for charging the bit line BL.
  • the efficiency of the core operation in the semiconductor memory device including the data cache 3a can be improved.
  • the switching of the core operating currents I C and I C ′ in this embodiment can be applied to core operations other than the bit line charging in the writing process, for example, various core operations in the reading process and the erasing process. Applicable.
  • serial operation example of the present embodiment includes a process of transferring data from the data cache 3 to the data input / output terminal in addition to a process of transferring data from the data input / output terminal to the data cache 3.
  • FIG. 6 is a circuit diagram showing the structure of the semiconductor memory device of the second embodiment.
  • MOS transistor 21 is provided.
  • the first and third MOS transistors 13 and 21 are examples of a first switch unit, and the second MOS transistor 14 is an example of a second switch unit.
  • the first constant current source 11 generates the first current I 1 as in the first embodiment.
  • the first and third MOS transistors 13 and 21 are connected in parallel to the first constant current source 11.
  • the first MOS transistor 13 switches whether to pass or block the first current I 1 according to the CACHE signal from the controller 6.
  • the third MOS transistor 21 switches whether the first current I 1 is allowed to pass or cut off in accordance with the NOCACHE signal from the controller 6.
  • the second MOS transistor 14 is connected to the second constant current source 12. The second MOS transistor 14 switches whether to pass or block the third current I 3 according to the NOCACHE signal from the controller 6.
  • the CACHE signal When using a cache operation, the CACHE signal is set high and the NOCACHE signal is set low. As a result, the first current I 1 from the first constant current source 12 is cut off by the third MOS transistor 13, but passes through the first MOS transistor 13. Further, the third current I 3 from the second constant current source 12 is interrupted by the second MOS transistor 14. As a result, the first current I 1 is supplied to the bit line BL for the non-write target memory cell MC via the sense amplifier 2a. This first current I 1 corresponds to the core operating current I C.
  • the CACHE signal is set to low and the NOCACHE signal is set to high.
  • the first current I 1 from the first constant current source 11 is blocked by the first MOS transistor 13, but passes through the third MOS transistor 21.
  • the second current I 2 from the second constant current source 12 passes through the second MOS transistor 14.
  • the sum of the first current I 1 and the third current I 3 that is, the second current I 2 is applied to the bit line BL for the non-write target memory cell MC via the sense amplifier 2a. Supplied.
  • This second current I 2 corresponds to the core operating current I C ′.
  • the efficiency of the core operation in the semiconductor memory device including the data cache 3a can be improved.
  • a page unit is a range of a plurality of memory cells MC along one word line WL
  • a block BLK unit is a plurality of NAND cell units 1a arranged in the word line WL direction.
  • the present invention is not limited to this case.
  • each sub-block is composed of a plurality of so-called strings.
  • a plurality of memory cells commonly connected to one word line a plurality of memory cells included in a certain sub-block may be used as a page, and a sub-block may be used as an erase unit.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Le problème décrit par la présente invention est d'obtenir un dispositif de mémoire à semi-conducteurs et un procédé de commande de ce dispositif de mémoire à semi-conducteurs, pouvant rendre plus efficaces les opérations du cœur de ce dispositif. La solution selon l'invention porte sur un dispositif de mémoire à semi-conducteurs qui comprend, dans un mode de réalisation : une pluralité de cellules de mémoire; une pluralité de lignes de mots connectées électriquement aux portes de commande de la pluralité de cellules de mémoire; et une pluralité de lignes binaires connectées électriquement à la pluralité de cellules de mémoire. Ledit dispositif de mémoire à semi-conducteurs comporte en outre un cache de données connecté électriquement aux lignes binaires, et un contrôleur servant à commander l'opération d'écriture dans les cellules de mémoire. Le dispositif de mémoire à semi-conducteurs répète la programmation et la vérification lors d'un premier cycle quand il met des données en cache pendant l'opération d'écriture, et il répète la programmation et la vérification lors d'un second cycle plus court que le premier quand il ne met pas de données en cache pendant l'opération d'écriture.
PCT/JP2013/068665 2013-07-08 2013-07-08 Dispositif de mémoire à semi-conducteurs et son procédé de commande WO2015004715A1 (fr)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001325796A (ja) * 2000-03-08 2001-11-22 Toshiba Corp 不揮発性半導体記憶装置
JP2005267821A (ja) * 2004-03-22 2005-09-29 Toshiba Corp 不揮発性半導体メモリ

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001325796A (ja) * 2000-03-08 2001-11-22 Toshiba Corp 不揮発性半導体記憶装置
JP2005267821A (ja) * 2004-03-22 2005-09-29 Toshiba Corp 不揮発性半導体メモリ

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