WO2015004715A1 - Semiconductor storage device and method for controlling same - Google Patents

Semiconductor storage device and method for controlling same Download PDF

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Publication number
WO2015004715A1
WO2015004715A1 PCT/JP2013/068665 JP2013068665W WO2015004715A1 WO 2015004715 A1 WO2015004715 A1 WO 2015004715A1 JP 2013068665 W JP2013068665 W JP 2013068665W WO 2015004715 A1 WO2015004715 A1 WO 2015004715A1
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Prior art keywords
current
operation
cache
memory device
semiconductor memory
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PCT/JP2013/068665
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French (fr)
Japanese (ja)
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阿部 克巳
吉原 正浩
尚文 安彦
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株式会社 東芝
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Priority to PCT/JP2013/068665 priority Critical patent/WO2015004715A1/en
Publication of WO2015004715A1 publication Critical patent/WO2015004715A1/en

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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642Sensing or reading circuits; Data output circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • G11C16/3454Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

[Problem] To provide a semiconductor storage device and a method for controlling the semiconductor storage device capable of improving efficiency of core operations. [Solution] The semiconductor storage device according to an embodiment comprises: a plurality of memory cells; a plurality of word lines electrically connected to the control gates of the plurality of memory cells; and a plurality of bit lines electrically connected to the plurality of memory cells. The semiconductor storage device further includes a data cache electrically connected to the bit lines and a controller for controlling writing operation into the memory cells. The semiconductor storage device repeats programming and verification at a first cycle when caching data during the writing operation, while the semiconductor storage device repeats programming and verification at a second cycle shorter than the first cycle when not caching data during the writing operation.

Description

Semiconductor memory device and control method thereof

Embodiments relate to a semiconductor memory device and a control method thereof.

Semiconductor memory devices such as NAND flash memory are widely known.

JP 2001-325796 A

Provided is a semiconductor memory device capable of improving the efficiency of core operation and a control method thereof.

According to one embodiment, a semiconductor memory device is electrically connected to a plurality of memory cells, a plurality of word lines electrically connected to control gates of the plurality of memory cells, and the plurality of memory cells. A plurality of bit lines. The device further includes a data cache electrically connected to the bit line, and a controller that controls a write operation to the memory cell. Furthermore, when the cache operation of the data cache is used in the write operation, the device repeats the program operation and the verify operation at a first time period, and does not use the cache operation of the data cache in the write operation. In this case, the program operation and the verify operation are repeated at a period of a second time shorter than the first time.

1 is a circuit diagram showing a structure of a semiconductor memory device according to a first embodiment. FIG. 6 is a diagram for explaining a core operation and a serial operation of the semiconductor memory device according to the first embodiment. It is a wave form diagram for demonstrating operation | movement of the semiconductor memory device of a comparative example. FIG. 6 is a waveform diagram for explaining the operation of the semiconductor memory device according to the first embodiment. FIG. 6 is a waveform diagram for explaining in detail the operation of the semiconductor memory device of the first embodiment. It is a circuit diagram which shows the structure of the semiconductor memory device of 2nd Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

In this description, common parts are denoted by common reference symbols throughout the drawings. However, the drawings are schematic, and it should be noted that the relationship between the thickness of each layer and the planar dimensions, the ratio between the thickness of one layer and the thickness of another layer, etc. are different from the actual ones. is there. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios from the actual drawings are included in different drawings.

(First embodiment)
FIG. 1 is a circuit diagram showing the structure of the semiconductor memory device of the first embodiment. The semiconductor memory device of FIG. 1 is a NAND flash memory.

1 includes a memory cell array 1, a sense amplifier 2, a data cache 3, a row decoder 4, an input / output buffer 5, a controller 6, a voltage generation circuit 7, a ROM fuse 8, and data. A storage circuit 9 and a current supply unit 10 are provided.

The current supply unit 10 includes a first constant current source 11, a second constant current source 12, a first MOS transistor 13 as an example of a first switch unit, and an example of a second switch unit. The second MOS transistor 14 and the comparator 15 are provided.

The memory cell array 1 includes a plurality of NAND cell units 1a arranged in a matrix. Each NAND cell unit 1a includes a plurality of memory cells MC (MC0 to MC31) connected in series to each other, and selection transistors S1 and S2 connected to both ends of these memory cells MC.

The control gates of these memory cells MC are electrically connected to different word lines WL (WL0 to WL31), respectively, and the gate electrodes of the selection transistors S1, S2 are selection gate lines SG1, parallel to the word line WL, Each is electrically connected to SG2. A set of a plurality of memory cells MC sharing one word line WL constitutes one page or a plurality of pages. A set of a plurality of NAND cell units 1a sharing the same word line WL and select gate lines SG1 and SG2 constitutes a block BLK serving as a data erasing unit.

In each NAND cell unit 1a, the source of the selection transistor S1 is electrically connected to the common source line CELSRC, and the drain of the selection transistor S2 is electrically connected to the corresponding bit line BL (BL0 to BLj). Has been.

The memory cell array 1 includes a plurality of blocks BLK (BLK0 to BLKn) in the extending direction of the bit lines BL. The memory cell array 1 including these blocks BLK is formed in one cell well (CPWELL) of the semiconductor substrate. Each block BLK has a plurality of NAND cell units 1a.

The sense amplifier 2 is electrically connected to a plurality of sense amplifiers 2a electrically connected to the corresponding bit line BL, a plurality of sense latches 2b electrically connected to the corresponding sense amplifier 2a, and each sense amplifier 2a. And a switch transistor 2c that operates in response to a BLPRE signal from the controller 6. The sense amplifier 2 forms a page buffer for sensing read data and holding write data.

The data cache 3 includes a plurality of data caches 3a electrically connected to the corresponding sense latch 2b. These data caches 3 a are connected to data input / output terminals via the input / output buffer 5. The data cache 3 can temporarily store read data and write data.

The row decoder 4 is electrically connected to the word line WL and the select gate lines SG1 and SG2. The row decoder 4 selects and drives the word line WL and the selection gate lines SG1 and SG2 of any block BLK.

The input / output buffer 5 exchanges data between the data cache 3 and the data input / output terminal, and receives command data and address data.

The controller 6 constitutes a control unit that controls a sequence (for example, write operation, read operation, erase operation, etc.) for the memory cell array 1. For example, the controller 6 receives external control signals such as a write enable signal WEn, a read enable signal REn, an address latch enable signal ALE, a command latch enable signal CLE, and performs overall control of the memory operation.

Specifically, the controller 6 has a command interface (not shown) and an address holding / transfer circuit, and determines whether the supplied data is write data or address data. In accordance with the determination result, write data is transferred to the sense amplifier 2, and address data is transferred to the row decoder 4 and the sense amplifier 2. The controller 6 performs read, write, and erase sequence control and control of applied voltages such as a read voltage, a write voltage, and an erase voltage based on an external control signal. The controller 6 controls the sequence by controlling the sense amplifier 2, the data cache 3, the row decoder 4, the input / output buffer 5, and the voltage control circuit 7.

The voltage generation circuit 7 includes a plurality (eight in this example) of boosting circuits 7a and a pulse generation circuit 7b. The booster circuit 7a can be configured by a charge pump circuit. The voltage generation circuit 7 switches the number of boosting circuits 7 a to be driven according to a control signal from the controller 6. The booster circuit 7a controls the pulse generation circuit 7b to adjust the pulse width and pulse height of the pulse voltage for the write operation and the erase operation.

The ROM fuse 8 is provided in the ROM fuse area of the memory cell array 1. The data held in the ROM fuse area is written at the time of shipment of the NAND flash memory, for example, and is not erased after shipment. Examples of such data include the pulse width and pulse height (voltage setting data) of the pulse voltage for the write operation and the erase operation, information on the bad block and bad column, and the like. After the power is turned on, the controller 6 controls the number of boosting circuits 7a to be driven according to the voltage setting data and the like. In the present embodiment, the ROM fuse 8 is provided in the ROM fuse area of the memory cell array 1. However, the present invention is not limited to such a configuration. For example, a register may be provided outside the memory cell array 1.

The data storage circuit 9 is a rewritable nonvolatile storage circuit for storing various data for memory control.

The first and second constant current sources 11 and 12 generate first and second currents I 1 and I 2 , respectively. The first and second MOS transistors 13 and 14 switch whether the first and second currents I 1 and I 2 are allowed to pass or be cut off in accordance with the CACHE signal and the NOCACHE signal from the controller 6, respectively. . The CACHE signal and the NOCACHE signal are examples of the first and second control signals, respectively. The comparator 15 compares the voltage VHSA of the wiring for supplying the first and second currents I 1 and I 2 to the sense amplifier 2 and the power supply voltage VDDSA, and the comparison result between the voltage VHSA and the power supply voltage VDDSA. (VHSA detection signal) is output to the controller 6.

Details of the first and second constant current sources 11 and 12, the first and second MOS transistors 13 and 14, and the comparator 15 will be described later.

(1) Operation of Semiconductor Memory Device of First Embodiment FIG. 2 is a diagram for explaining a core operation and a serial operation of the semiconductor memory device of the first embodiment.

The semiconductor memory device of this embodiment includes a data cache 3 and can perform data transfer between the data cache 3 and the data input / output terminal behind the core operation for the memory cell array 1. Since this data transfer is performed using a serial bus between them, it is called a serial operation. Further, the semiconductor memory device of this embodiment can select whether or not to use the cache operation of the data cache 3 in accordance with a command from the controller 6 or the like.

As an example of the serial operation, there is a process of transferring data from the data input / output terminal to the data cache 3 when writing data to the memory cell MC of the memory cell array 1. Further, as an example of the core operation, there is a process of charging the bit line BL for the non-write target memory cell MC when writing data to the memory cell MC of the memory cell array 1. Hereinafter, the serial operation and the core operation of the present embodiment will be described using these examples as subjects.

FIG. 2A shows the operation of the semiconductor memory device when the cache operation is used.

In FIG. 2A, when the serial operation 1 for transferring data from the data input / output terminal to the data cache 3a is completed and data is transferred from the data cache 3a to the sense latch 2b, the data cache 3a and the sense latch 2b are transferred. And are separated. As a result, the data cache 3a becomes free and the data cache 3a can be used freely. Therefore, the next serial operation 2 can be performed behind the core operation 1 between the sense latch 2 b and the memory cell array 1. As described above, when the cache operation is used, the serial operation and the core operation are executed in parallel.

FIG. 2B shows the operation of the semiconductor memory device when the cache operation is not used.

In FIG. 2B, when the serial operation 1 is completed, the core operation 1 is started. Further, when the core operation 1 is finished, the next serial operation 2 is started. As described above, when the cache operation is not used, the serial operation and the core operation are alternately performed.

It should be noted that the execution period of each core operation in FIG. 2B is set shorter than the execution period of each core operation in FIG. The reason for this will be described later.

(2) Comparison between the First Embodiment and the Comparative Example Next, referring to FIGS. 3 and 4, the operation of the semiconductor memory device of the first embodiment and the operation of the semiconductor memory device of the comparative example are compared. For convenience of explanation, the reference numerals in FIG. 1 are used in the explanation of the comparative example as in the explanation of the first embodiment.

FIG. 3 is a waveform diagram for explaining the operation of the semiconductor memory device of the comparative example.

Fig. 3 (a) shows the core operation when the cache operation is used.

FIG. 3A shows a CACHE signal that is set to high when instructing to use a cache operation, and a NOCACHE signal that is set to high when instructing not to use a cache operation. . In FIG. 3A, the CACHE signal is set to high and the NOCACHE signal is set to low.

FIG. 3A further shows a voltage V B applied to the bit line BL for the non-write target memory cell MC and a voltage applied to the word line WL (selected word line) for the memory cell MC. V W and current I flowing into the sense amplifier 2a for the memory cell MC are shown.

As shown in FIG. 3 (a), applied when the program operation of applying a write voltage V PGM to the selected word line WL, a check voltage V R to the selected word line WL for writing data into the memory cell MC The verify operation is repeated until the threshold voltage of the memory cell MC reaches a desired voltage.

Further, for example, the ground voltage VSS is applied to the bit line BL connected to the write target memory cell MC during the verify operation.

On the other hand, for example, a desired first voltage V B1 is applied to the bit line BL connected to the non-write target memory cell MC as shown in FIG. Sometimes, for example, the desired second voltage V B2 is applied. As shown in FIG. 3A, the first voltage V B1 and the second voltage V B2 are different voltages.

In the program operation, the bit line BL connected to the non-write target memory cell MC is charged to increase the voltage V B of the bit line BL to the power supply voltage VDDSA, and then the voltage of the bit line BL. V B is maintained at the power supply voltage VDDSA. A symbol T 1 indicates an execution period of the program operation when the cache operation is used.

Note that the period from one rise of the write voltage V PRG to the next rise coincides with one cycle period of the write operation. One cycle period corresponds to a period of one loop of the program operation and the verify operation.

In FIG. 3A, since the cache operation is used, the serial operation and the core operation are executed in parallel. Therefore, the sense amplifier 2a in the core operation, serial operation current I S flows caused by the cache operation. Further, when the bit line BL is charged, a large bit line charging current is generated as the core operating current I C. Therefore, a large current I S + I C flows into the sense amplifier 2a during the core operation while the bit line BL is being charged.

In general, in a semiconductor memory device such as a NAND flash memory, a limit value I peak of a peak current during operation is defined. On the other hand, the core operating current I C when charging the bit line BL is one of the factors that cause a large peak current. Therefore, if the core operating current I C is increased for fast charging of the bit line BL, it becomes difficult to limit the current I to the limit value I peak or less. Therefore, in FIG. 3 (a), the core operation current I C at the time of charging the bit line BL (specifically, I peak -I S) relatively small value is limited to.

Fig. 3 (b) shows the core operation when the cache operation is not used.

In FIG. 3B, since the cache operation is not used, the serial operation is not executed during the core operation. Therefore, only the core operating current I C flows into the sense amplifier 2a during the core operation. Therefore, there is a large difference between the current I and the limit value Ipeak, and the core operation is performed in a state where there is a margin with respect to the limit value Ipeak .

A symbol T 2 indicates an execution period of the program operation when the cache operation is not used. In this comparative example, the core operating current I C is set to the same value whether or not the cache operation is used, but generally, the period required for charging the bit line BL is equal to the core operating current I C. Proportional to size.

Therefore, in this comparative example, the execution period T 1 of the program operation when the cache operation is used and the execution period T 2 of the program operation when the cache operation is not used are substantially equal (that is, about the same). (T 1 = T 2 ).

Further, the time required for the verify operation does not change whether the cache operation is used or not. Therefore, in this comparative example, the one cycle period t 1 when the cache operation is used and the cache operation are not used. The one cycle period t 2 in the case is substantially equal (ie, comparable) (t 1 = t 2 ).

FIG. 4 is a waveform diagram for explaining the operation of the semiconductor memory device of the first embodiment.

FIG. 4 (a) shows the core operation when the cache operation is used.

In FIG. 4A, since the cache operation is used, the serial operation and the core operation are executed in parallel. Therefore, the sense amplifier 2a in the core operation, serial operation current I S flows caused by the cache operation. Further, when the bit line BL is charged, a large bit line charging current is generated as the core operating current I C. Therefore, a large current I S + I C flows into the sense amplifier 2a during the core operation while the bit line BL is being charged.

FIG. 4B shows the core operation when the cache operation is not used.

In FIG. 4B, since the cache operation is not used, the serial operation is not executed during the core operation. Therefore, only the core operating current flows into the sense amplifier 2a during the core operation.

However, in this embodiment, the core operating current (bit line charging current) I C ′ when the cache operation is not used is set to a value larger than the core operating current I C when the cache operation is used (I C '> I C ). Specifically, the value of I C ′ is set to I C + I S. The currents I C and I C ′ are examples of first and second currents, respectively.

Therefore, according to the present embodiment, when the cache operation is not used, the bit line BL can be charged in a short period by charging the bit line BL with a large core operating current I C ′. Therefore, in this embodiment, the execution period T 2 of the program operation when the cache operation is not used is shorter than the execution period T 1 of the program operation when the cache operation is used (T 2 <T 1 ). .

In addition, since the time required for the verify operation does not change whether the cache operation is used or not, in this embodiment, the cache operation is used for one cycle period t 2 when the cache operation is not used. This is shorter than the one cycle period t 1 in the case (t 2 <t 1 ). The one cycle period t 1 when the cache operation is used is an example of the first time, and the one cycle period t 2 when the cache operation is not used is the example of the second time that is shorter than the first time. is there.

As described above, according to the present embodiment, when using the cache operation, not only can the core operation be made efficient by parallelization, but also when the cache operation is not used, the core operation is made efficient by increasing the core operation current. Can be realized.

(3) Structure of Current Supply Unit 10 Next, referring to FIG. 1 again, the structure of a semiconductor memory device capable of performing the core operation of FIGS. 4A and 4B will be described. Specifically, the structure of the current supply unit 10 will be described.

When using a cache operation, the CACHE signal is set high and the NOCACHE signal is set low. As a result, the first current I 1 from the first constant current source 11 passes through the first MOS transistor 13, and the second current I 2 from the second constant current source 12 is It is cut off by the MOS transistor 14. As a result, the first current I 1 is supplied to the bit line BL for the non-write target memory cell MC via the sense amplifier 2a. This first current I 1 corresponds to the core operating current I C.

On the other hand, when the cache operation is not used, the CACHE signal is set to low and the NOCACHE signal is set to high. As a result, the first current I 1 from the first constant current source 11 is cut off by the first MOS transistor 13, and the second current I 2 from the second constant current source 12 is Passes through the MOS transistor 14. As a result, a second current I 2 that is larger than the first current I 1 is supplied to the bit line BL for the memory cell MC that is not to be written via the sense amplifier 2a. This second current I 2 corresponds to the core operating current I C ′.

Note that the current I needs to be limited to the limit value I peak or less as described above. Therefore, in this embodiment, by using constant current sources (first and second constant current sources 13 and 14) as current sources of the first and second currents I 1 and I 2 , the magnitude of the current I is increased. Is limited.

When the first or second current I 1 or I 2 starts to be supplied to the bit line BL, the voltage VHSA of the wiring for supplying these currents I 1 and I 2 also rises with the charging of the bit line BL. To go. The comparator 15 compares the voltage VHSA with the power supply voltage VDDSA and outputs the comparison result (VHSA detection signal) to the controller 6. That is, the comparator 15 detects that the voltage VHSA has reached the power supply voltage VDDSA and outputs a detection signal to the controller 6. When receiving this detection signal, the controller 6 performs control to make a transition to the next operation.

In the semiconductor memory device of this embodiment, the current supply unit 10 dynamically selects the core operating currents I C and I C ′ according to whether or not to use the cache operation, and completes charging. Accordingly, the writing process can be shifted to the next sequence.

(4) Details of Operation of Semiconductor Memory Device of First Embodiment FIG. 5 is a waveform diagram for explaining in detail the operation of the semiconductor memory device of the first embodiment.

FIG. 5 (a) shows a serial operation and a core operation at the time of write processing when using a cache operation.

In the serial operation when the cache operation is used, command data CMD, address data ADD, write data DATA, and command data 10h indicating that the cache operation is used are transferred from the data input / output terminal to the data cache 3a.

Next, when the BUSY signal is changed from high to low, after the data in the data cache 3a is transferred to the data latch 2b, the core operation relating to this data is started.

Specifically, the program operation of applying a write voltage V PGM to the selected word line WL, and the verify operation of applying a verify voltage V R to the selected word line WL are alternately performed.

At this time, for example, the ground voltage VSS is applied to the bit line BL connected to the memory cell MC to be written during the verify operation, and the bit line BL is held at a desired voltage during the verify operation.

Further, as shown in FIG. 5A, for example, a desired first voltage V B1 is applied to the bit line BL connected to the non-write target memory cell MC during the program operation, and during the verify operation. For example, a desired second voltage V B2 is applied.

The application process of the first voltage V B1 is executed during the period T 1 , and at this time, the core operating current I C is used for charging the bit line BL.

FIG. 5B shows a serial operation and a core operation at the time of write processing when the cache operation is not used.

In the serial operation when the cache operation is not used, command data CMD, address data ADD, write data DATA, and command data 15h indicating that the cache operation is not used are transferred from the data input / output terminal to the sense latch 2b.

Next, when the BUSY signal is changed from high to low, the core operation relating to the data in the data latch 2b is started.

Specifically, the program operation of applying a write voltage V PGM to the selected word line WL, and the verify operation of applying a verify voltage V R to the selected word line WL are alternately performed.

At this time, for example, the ground voltage VSS is applied to the bit line BL connected to the memory cell MC to be written during the verify operation, and the bit line BL is held at a desired voltage during the verify operation.

Further, as shown in FIG. 5B, for example, a desired first voltage V B1 is applied to the bit line BL connected to the non-write target memory cell MC during the program operation, and during the verify operation. For example, a desired second voltage V B2 is applied.

The application process of the first voltage V B1 is executed during the period T 2 , and at this time, the core operating current I C ′ is used for charging the bit line BL.

According to this embodiment, in the case of not using the cache operation, shorten the core operation current by increasing the I C 'from I C, the execution time of a program operation from T 1 to T 2, further, writing One cycle period (repetition period) of the operation can be shortened from t 1 to t 2 , thereby shortening the execution period of the core operation.

As described above, according to the present embodiment, the efficiency of the core operation in the semiconductor memory device including the data cache 3a can be improved.

Note that the switching of the core operating currents I C and I C ′ in this embodiment can be applied to core operations other than the bit line charging in the writing process, for example, various core operations in the reading process and the erasing process. Applicable.

In addition, the serial operation example of the present embodiment includes a process of transferring data from the data cache 3 to the data input / output terminal in addition to a process of transferring data from the data input / output terminal to the data cache 3.

(Second Embodiment)
FIG. 6 is a circuit diagram showing the structure of the semiconductor memory device of the second embodiment.

6 includes a first constant current source 11, a second constant current source 12, a first MOS transistor 13, a second MOS transistor 14, a comparator 15, and a third constant current source 11. MOS transistor 21 is provided. The first and third MOS transistors 13 and 21 are examples of a first switch unit, and the second MOS transistor 14 is an example of a second switch unit.

The first constant current source 11 generates the first current I 1 as in the first embodiment. On the other hand, unlike the first embodiment, the second constant current source 12 has a third current I 3 (= I 2 −I) corresponding to the difference between the first current I 1 and the second current I 2. 1 ) Generate.

The first and third MOS transistors 13 and 21 are connected in parallel to the first constant current source 11. The first MOS transistor 13 switches whether to pass or block the first current I 1 according to the CACHE signal from the controller 6. The third MOS transistor 21 switches whether the first current I 1 is allowed to pass or cut off in accordance with the NOCACHE signal from the controller 6.

The second MOS transistor 14 is connected to the second constant current source 12. The second MOS transistor 14 switches whether to pass or block the third current I 3 according to the NOCACHE signal from the controller 6.

When using a cache operation, the CACHE signal is set high and the NOCACHE signal is set low. As a result, the first current I 1 from the first constant current source 12 is cut off by the third MOS transistor 13, but passes through the first MOS transistor 13. Further, the third current I 3 from the second constant current source 12 is interrupted by the second MOS transistor 14. As a result, the first current I 1 is supplied to the bit line BL for the non-write target memory cell MC via the sense amplifier 2a. This first current I 1 corresponds to the core operating current I C.

On the other hand, when the cache operation is not used, the CACHE signal is set to low and the NOCACHE signal is set to high. As a result, the first current I 1 from the first constant current source 11 is blocked by the first MOS transistor 13, but passes through the third MOS transistor 21. The second current I 2 from the second constant current source 12 passes through the second MOS transistor 14. As a result, the sum of the first current I 1 and the third current I 3 , that is, the second current I 2 is applied to the bit line BL for the non-write target memory cell MC via the sense amplifier 2a. Supplied. This second current I 2 corresponds to the core operating current I C ′.

Therefore, according to the present embodiment, as in the first embodiment, the efficiency of the core operation in the semiconductor memory device including the data cache 3a can be improved.

The configuration of the memory cell array is described in, for example, US patent application Ser. No. 12 / 407,403 filed on Mar. 19, 2009, called “three-dimensional stacked nonvolatile semiconductor memory”. Also, US patent application Ser. No. 12 / 406,524 filed Mar. 18, 2009 entitled “Three-dimensional stacked nonvolatile semiconductor memory”, Mar. 25, 2010 entitled “Nonvolatile semiconductor memory device and manufacturing method thereof” No. 12 / 679,991, filed Mar. 23, 2009, entitled “Semiconductor Memory and Manufacturing Method thereof”. These patent applications are hereby incorporated by reference in their entirety.

In the first and second embodiments, a page unit is a range of a plurality of memory cells MC along one word line WL, and a block BLK unit is a plurality of NAND cell units 1a arranged in the word line WL direction. However, the present invention is not limited to this case. For example, in the above four documents, there are a plurality of sub-blocks in one block, and each sub-block is composed of a plurality of so-called strings. Of a plurality of memory cells commonly connected to one word line, a plurality of memory cells included in a certain sub-block may be used as a page, and a sub-block may be used as an erase unit.

Although several embodiments have been described above, these embodiments are presented only as examples, and are not intended to limit the scope of the invention. The novel apparatus and methods described herein can be implemented in a variety of other forms. In addition, various omissions, substitutions, and changes can be made to the forms of the apparatus and method described in the present specification without departing from the spirit of the invention. The appended claims and their equivalents are intended to include such forms and modifications as fall within the scope and spirit of the invention.

1: memory cell array, 1a: NAND cell unit, 2: sense amplifier,
2a: sense amplifier, 2b: sense latch, 2c: switch transistor,
3: data cache, 3a: data cache,
4: row decoder, 5: input / output buffer, 6: controller,
7: voltage generation circuit, 7a: boosting circuit, 7b: pulse generation circuit,
8: ROM fuse, 9: Data storage circuit, 10: Current supply unit,
11: first constant current source, 12: second constant current source,
13: first MOS transistor, 14: second MOS transistor,
15: Comparator, 21: Third MOS transistor

Claims (20)

  1. A plurality of memory cells;
    A plurality of word lines electrically connected to control gates of the plurality of memory cells;
    A plurality of bit lines electrically connected to the plurality of memory cells;
    A data cache electrically connected to the bit line;
    A controller for controlling a write operation to the memory cell,
    When the cache operation of the data cache is used in the write operation, the program operation and the verify operation are repeated in a first time period,
    When the cache operation of the data cache is not used in the write operation, the program operation and the verify operation are repeated at a period of a second time shorter than the first time.
    Semiconductor memory device.
  2. 2. The semiconductor memory device according to claim 1, wherein the controller controls the write operation so as to charge a bit line electrically connected to a non-write target memory cell.
  3. 3. The semiconductor memory device according to claim 2, wherein the controller controls the write operation so that charging of the bit line and the cache operation are executed in parallel.
  4. A current supply unit for supplying current to the bit line to charge the bit line;
    The current supply unit is
    When using the cache operation, the bit line is charged with a first current;
    Charging the bit line with a second current greater than the first current when not using the cache operation;
    The semiconductor memory device according to claim 2.
  5. The current supply unit is
    A first constant current source for generating the first current;
    A second constant current source for generating the second current;
    A semiconductor memory device according to claim 4.
  6. The current supply unit is
    A first switch unit that operates to pass the first current when receiving a first control signal instructing to use the cache operation;
    A second switch unit that operates to pass the second current when receiving a second control signal instructing not to use the cache operation;
    A semiconductor memory device according to claim 5.
  7. The current supply unit is
    A first constant current source for generating the first current;
    A second constant current source for generating a third current corresponding to the difference between the first and second currents;
    A semiconductor memory device according to claim 4.
  8. The current supply unit is
    The first control signal is received both when the first control signal instructing to use the cache operation is received and when the second control signal instructing not to use the cache operation is received. A first switch that operates to pass current;
    A second switch unit that operates to pass the second current when the second control signal instructing not to use the cache operation is received;
    A semiconductor memory device according to claim 7.
  9. The current supply unit includes a comparator that compares a voltage of a wiring for supplying the current to the bit line and a power supply voltage, and outputs a comparison result of the voltage of the wiring and the power supply voltage to the controller. The semiconductor memory device according to claim 4.
  10. 5. The semiconductor memory device according to claim 4, wherein the current supply unit sets the second current to a total value of the first current and a current generated by the cache operation.
  11. A plurality of memory cells;
    A plurality of word lines electrically connected to control gates of the plurality of memory cells;
    A plurality of bit lines electrically connected to the plurality of memory cells;
    A data cache electrically connected to the bit line;
    A controller for controlling a write operation to the memory cell;
    A method for controlling a semiconductor memory device comprising:
    When the cache operation of the data cache is used in the write operation, the program operation and the verify operation are repeated in a first time period,
    When the cache operation of the data cache is not used in the write operation, the program operation and the verify operation are repeated at a period of a second time shorter than the first time.
    A method for controlling a semiconductor memory device.
  12. 12. The method of controlling a semiconductor memory device according to claim 11, further comprising controlling the write operation so that the controller charges a bit line electrically connected to a non-write target memory cell.
  13. 13. The method of controlling a semiconductor memory device according to claim 12, wherein the controller controls the write operation so that the charging to the bit line and the cache operation are executed in parallel.
  14. When using the cache operation, the bit line is charged with a first current;
    Charging the bit line with a second current greater than the first current when not using the cache operation;
    The method for controlling a semiconductor memory device according to claim 12, comprising:
  15. Generating the first current by a first constant current source;
    Generating the second current by a second constant current source;
    15. The method for controlling a semiconductor memory device according to claim 14, further comprising:
  16. When the first switch unit receives the first control signal instructing to use the cache operation, the first switch passes the first current;
    When the second switch unit receives the second control signal instructing not to use the cache operation, the second current is passed;
    16. A method for controlling a semiconductor memory device according to claim 15, further comprising:
  17. Generating the first current by a first constant current source;
    A third current corresponding to a difference between the first and second currents is generated by a second constant current source;
    15. The method for controlling a semiconductor memory device according to claim 14, further comprising:
  18. Both when the first switch unit receives the first control signal instructing to use the cache operation and when receiving the second control signal instructing not to use the cache operation If the first current is passed through,
    When the second switch unit receives the second control signal instructing not to use the cache operation, the second current is passed;
    18. A method for controlling a semiconductor memory device according to claim 17, further comprising:
  19. The method according to claim 14, comprising comparing a voltage of a wiring for supplying the current to the bit line and a power supply voltage, and outputting a comparison result between the voltage of the wiring and the power supply voltage to the controller. A method for controlling a semiconductor memory device.
  20. 15. The method of controlling a semiconductor memory device according to claim 14, wherein the second current is set to a total value of the first current and a current generated by the cache operation.
PCT/JP2013/068665 2013-07-08 2013-07-08 Semiconductor storage device and method for controlling same WO2015004715A1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001325796A (en) * 2000-03-08 2001-11-22 Toshiba Corp Non-volatile semiconductor memory
JP2005267821A (en) * 2004-03-22 2005-09-29 Toshiba Corp Nonvolatile semiconductor memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001325796A (en) * 2000-03-08 2001-11-22 Toshiba Corp Non-volatile semiconductor memory
JP2005267821A (en) * 2004-03-22 2005-09-29 Toshiba Corp Nonvolatile semiconductor memory

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