WO2014206174A1 - 非穿通型反向导通绝缘栅双极型晶体管的制造方法 - Google Patents

非穿通型反向导通绝缘栅双极型晶体管的制造方法 Download PDF

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WO2014206174A1
WO2014206174A1 PCT/CN2014/078790 CN2014078790W WO2014206174A1 WO 2014206174 A1 WO2014206174 A1 WO 2014206174A1 CN 2014078790 W CN2014078790 W CN 2014078790W WO 2014206174 A1 WO2014206174 A1 WO 2014206174A1
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type
bipolar transistor
type substrate
insulated gate
gate bipolar
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PCT/CN2014/078790
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English (en)
French (fr)
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黄璇
邓小社
王根毅
王万礼
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无锡华润上华半导体有限公司
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Publication of WO2014206174A1 publication Critical patent/WO2014206174A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions

Definitions

  • the present invention relates to an insulated gate bipolar transistor technology, and more particularly to a method of fabricating a non-punch-through reverse conducting insulated gate bipolar transistor.
  • Figure 1 is a non-punch-through reverse conducting insulated gate bipolar transistor (Non Punch Through Reverse) Conducting Insulated Gate Bipolar Transistor, NPT RC IGBT) internal structure section schematic.
  • the front structure of the IGBT is the same as VDMOS except that a P-type layer is added between the drain and drain regions.
  • a process similar to that of manufacturing a field effect transistor is performed on the front side, and then the silicon wafer is thinned, and then a P+ emitter region is formed on the back surface thereof (that is, the extra P-type layer is formed).
  • the difficulty of this method mainly has two aspects: First, the need to reduce the silicon wafer flow capacity, especially for the common IGBT below 1200 volts, the thickness of which is below 200 microns, the film circulation process is very demanding; A special double exposure machine is required to expose the wafer.
  • a method for fabricating a non-punch-through reverse conducting insulated gate bipolar transistor includes the steps of: providing an N-type substrate; forming a P+ emitter region by ion implantation on the N-type substrate; Forming an N-type drift region on one side of the type substrate having a P+ emitter region; preparing a front surface structure of the insulated gate bipolar transistor on the N-type drift region; thinning the N-type substrate to the back surface The P+ emitter region; forming a metal electrode on the back surface of the N-type substrate.
  • the N-type substrate has a thickness of 100 to 650 microns
  • the N-type drift region has a thickness of 10 to 650 microns
  • the thickness of the N-type substrate and the N-type drift region is It is equivalent to the thickness of a normal circulating silicon wafer.
  • the normally flowing silicon wafer is a 6 inch silicon wafer having a thickness of 625 microns or 675 microns, or an 8 inch silicon wafer having a thickness of 725 microns.
  • the normally flowing silicon wafer is a 6 inch silicon wafer
  • the N-type drift region is 300 microns thick
  • the N-type substrate is 325 microns or 375 microns thick.
  • the normally flowing silicon wafer is an 8-inch silicon wafer
  • the N-type drift region is 400 microns thick
  • the N-type substrate is 325 microns thick.
  • the step of forming a P+ emitter region by ion implantation on an N-type substrate comprises: photolithographically forming an implant pattern on the N-type substrate; performing ions on the implant pattern Injection forms a P+ emitter region.
  • the implanted ions are boron and the implant dose is 1E13 ⁇ 1E20. Cm-2, the implantation energy is 30 ⁇ 200 keV.
  • the N-type substrate has a resistivity of 0.001 to 10 ohm.cm
  • the N-type drift region has a resistivity of 5 to 500 ohm.cm.
  • the metal electrode in the step of forming a metal electrode on the back surface of the N-type substrate, may be formed by sputtering or evaporation.
  • the step of preparing a front side structure of the insulated gate bipolar transistor on the N-type drift region includes: forming a P-type body region on the N-type drift region; and forming the P-type body region; Forming an N-type emitter region on the region; forming a gate layer on the N-type channel between the P-type body regions; extracting an emitter electrode on the N-type emitter region, and extracting a gate electrode on the gate layer electrode.
  • the N-type substrate is thinned using mechanical grinding.
  • the metal electrode is formed by sputtering or evaporation.
  • the above method uses an injection and epitaxy method to prepare an NPT RC IGBT.
  • the P/N spacer structure on the N-type substrate can be operated by a conventional lithography machine and an ion implantation apparatus, and the thickness of the wafer after extension is the same as that of the normal circulation wafer, and thus is compatible with the existing conventional processes.
  • Figure 1 is a schematic cross-sectional view of the internal structure of the NPT RC IGBT
  • FIG. 2 is a flow chart showing a method of manufacturing an NPT IGBT according to an embodiment
  • FIG. 5 is an NPT RC IGBT structure corresponding to step S103 of FIG. 2;
  • NPT RC IGBT structure corresponding to step S104 of FIG. 2;
  • FIG. 7 is an NPT RC IGBT structure corresponding to step S105 of FIG. 2;
  • FIG. 8 is an NPT RC IGBT structure corresponding to step S106 of FIG. 2.
  • FIG. 2 is a flow chart showing a method of manufacturing a non-punch-through reverse conducting insulated gate bipolar transistor according to an embodiment. The method includes the following steps S101 to S106.
  • Step S101 providing an N-type substrate.
  • the N-type substrate refers to a substrate formed by doping N-type ions into a semiconductor material, and is formed into a wafer shape of a standard size (6 inches or 8 inches, etc.), on which various semiconductor processes can be performed, such as Figure 3 shows.
  • the N-type substrate has a thickness of 100 to 650 ⁇ m and a resistivity of 0.001 to 10 ohm•cm ( ⁇ •cm).
  • the N-type substrate 100 serves as a support for the subsequent epitaxial layer and is also used to form the final P-type layer.
  • Step S102 forming a P+ emitter region by ion implantation on the N-type substrate.
  • a plurality of P-type regions 102 are formed on the N-type substrate 100 at intervals.
  • the P-type region 102 is formed by ion implantation.
  • the ion implantation specifically includes the following steps:
  • Step S121 photolithographically forming an implant pattern on the N-type substrate.
  • This step is a conventional step of photolithography, including steps of coating photoresist, baking, photolithography, cleaning, and the like.
  • an implantation pattern is formed on the N-type substrate 100, that is, a part of the surface of the N-type substrate 100 is covered with the photoresist 200, and the other portion is exposed. The exposed portion is the area used to form the P-type region.
  • Step S122 performing ion implantation on the implantation pattern to form a P+ emitter region.
  • Ion implantation is performed by bombarding the surface of the entire N-type substrate 100 with ions.
  • the implanted ions are boron, and the implantation dose is 1E13 ⁇ 1E20. Cm-2, the implantation energy is 30 ⁇ 200 keV.
  • a plurality of spaced P-type regions 102 as shown in FIG. 4, that is, P+ emitter regions of the finally formed IGBT, can be formed on the N-type substrate 100.
  • Step S123 Clearing the photoresist.
  • the photoresist 200 is removed from the surface of the N-type substrate 100.
  • an N-type substrate 100 having a P-type region 102 is formed.
  • Step S103 epitaxially preparing an N-type drift region on one side of the N-type substrate having a P+ emitter region.
  • epitaxial fabrication refers to forming a substrate, referred to as an epitaxial layer, over the N-type substrate 100. That is, the N-type drift region 300 shown in FIG.
  • the technique for preparing the epitaxial layer is relatively conventional and will not be described here.
  • the thickness of the formed N-type drift region 300 is 10 to 650 ⁇ m, and the sum of the thicknesses of the N-type substrate 100 is equivalent to the thickness of the normal-flow silicon wafer.
  • the N-type drift region 300 is used to form other layers of the IGBT other than the P+ emitter region, and is referred to as a front surface structure of the IGBT in this embodiment. That is, the thickness of the N-type drift region 300 can be used to form a complete IGBT front surface structure, and the thickness together with the N-type substrate 100 is equivalent to the thickness of a normal flow silicon wafer.
  • a normal flow silicon wafer is typically a 6 inch silicon wafer having a thickness of 625 microns or 675 microns, or an 8 inch silicon wafer having a thickness of 725 microns.
  • examples of possible thicknesses are: when used in a 6 inch silicon wafer process, the N-type drift region 300 is 300 microns thick, the N-type substrate 100 is 325 microns or 375 microns thick; when used in an 8-inch silicon wafer process The N-type drift region 300 is 400 microns thick, and the N-type substrate 100 is 325 microns thick.
  • other thicknesses satisfying the above two conditions can also be selected.
  • the resistivity of the N-type drift region 300 is 5 to 500 ohm•cm ( ⁇ •cm).
  • Step S104 preparing a front structure of the insulated gate bipolar transistor on the N-type drift region.
  • the front structure is shown in FIG. 6.
  • This step includes forming a P-type body region 302 on the N-type drift region 300 and forming an N-type emitter region 304 on the P-type body region 302. Between the two P-type body regions 302 is an N-type channel, and a gate layer 306 is formed on the N-type channel. They are then taken up through the electrodes as emitters and gates.
  • Step S105 thinning the N-type substrate to the N-type channel.
  • the N-type substrate 100 is thinned from a direction facing away from the P-type region 102 toward the P-type region 102 until the P-type region 102 is also exposed on the back surface of the N-type substrate 100.
  • the thinned N-type substrate 100 is as shown in FIG.
  • the manner in which the N-type substrate 100 is thinned may be mechanically ground. It can be understood that in order to reduce the processing time at the time of thinning and to avoid the waste generated by the N-type substrate 100, the thickness of the N-type substrate 100 should be as small as possible while ensuring the safety of circulation.
  • Step S106 forming a metal electrode on the back surface of the N-type substrate. That is, a metal layer is formed on the P+ emitter region and thus the electrode acts as a collector of the entire IGBT, and finally forms an NPT Refer to Figure 7 for the complete structure of the IGBT.
  • the metal electrode may be formed by sputtering or evaporation.
  • an NPT RC IGBT is prepared by injection and epitaxy.
  • the P/N spacer structure on the N-type substrate 100 can be operated by a conventional lithography machine and an ion implantation apparatus, and the thickness of the wafer after extension is the same as that of the normal circulation wafer, and thus is compatible with the existing conventional processes. .

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Abstract

一种非穿通型反向导通绝缘栅双极型晶体管的制造方法，包括如下步骤：制备N型衬底（100）；在所述N型衬底（100）上采用离子注入的方式形成P+发射区（102）；在所述N型衬底（100）上具有P+发射区（102）的一面外延制备N型漂移区（300）；在所述N型漂移区（300）上制备所述绝缘栅双极型晶体管的正面结构；将所述N型衬底（100）减薄至背面露出所述P+发射区（102）；在所述N型衬底（100）背面形成金属电极。上述方法采用注入与外延方式结合制备NPT RC IGBT，与常规的硅片工艺兼容，不需要较高的薄片流通工艺要求，也不需要专用的双面曝光机。

Description

非穿通型反向导通绝缘栅双极型晶体管的制造方法
【技术领域】
本发明涉及绝缘栅双极型晶体管技术，特别是涉及一种非穿通型反向导通绝缘栅双极型晶体管的制造方法。
【背景技术】
图1是一种非穿通型反向导通绝缘栅双极晶体管（Non Punch Through Reverse Conducting Insulated Gate Bipolar Transistor，NPT RC IGBT）内部结构断面示意图。IGBT的正面结构与VDMOS相同，只是在漏极和漏区之间增加了一个P型层。传统的制造方法中，在其正面进行与制造场效应晶体管类似的工艺，然后将硅片减薄，接着在其背面形成P+发射区（也即制造该多出的P型层）。这种方法的难点主要有两个方面：一、需要有减薄硅片流通能力，特别是对于常见的1200伏以下的IGBT，其厚度在200微米以下，对薄片流通工艺要求很高；二、需要专门的双面曝光机对硅片曝光。
【发明内容】
基于此，有必要针对提供一种不需要双面曝光机且不需要较高的薄片流通工艺要求的非穿通型反向导通绝缘栅双极型晶体管的制造方法。
一种非穿通型反向导通绝缘栅双极型晶体管的制造方法，包括如下步骤：提供N型衬底；在所述N型衬底上采用离子注入的方式形成P+发射区；在所述N型衬底上具有P+发射区的一面外延制备N型漂移区；在所述N型漂移区上制备所述绝缘栅双极型晶体管的正面结构；将所述N型衬底减薄至背面露出所述P+发射区；在所述N型衬底背面形成金属电极。
在其中一个实施例中，所述N型衬底的厚度为100~650微米，所述N型漂移区的厚度为10~650微米，且所述N型衬底和N型漂移区的厚度之和与正常流通硅片的厚度相当。
在其中一个实施例中，所述正常流通硅片是厚度为625微米或675微米的6英寸硅片，或者是厚度为725微米的8英寸硅片。
在其中一个实施例中，所述正常流通硅片采用6英寸硅片，所述N型漂移区为300微米厚，所述N型衬底为325微米或375微米厚。
在其中一个实施例中，所述正常流通硅片采用8英寸硅片，所述N型漂移区为400微米厚，所述N型衬底为325微米厚。在其中一个实施例中，所述在N型衬底上采用离子注入的方式形成P+发射区的步骤包括：在所述N型衬底上光刻形成注入图形；在所述注入图形上进行离子注入形成P+发射区。
在其中一个实施例中，注入离子为硼，注入剂量为1E13~1E20 cm-2，注入能量为30~200千电子伏特。
在其中一个实施例中，所述N型衬底的电阻率为0.001~10欧姆•厘米，所述N型漂移区的电阻率为5~500欧姆•厘米。
在其中一个实施例中，所述在N型衬底背面形成金属电极的步骤中，可以采用溅射或蒸发方式形成所述金属电极。
在其中一个实施例中，所述在N型漂移区上制备绝缘栅双极型晶体管的正面结构的步骤包括：在所述N型漂移区上间隔形成P型体区；在所述P型体区上形成N型发射区；在所述P型体区之间的N型沟道上形成栅极层；在所述N型发射区上引出发射极电极，在所述栅极层上引出栅极电极。
在其中一个实施例中，采用机械研磨减薄所述N型衬底。
在其中一个实施例中，采用溅射或蒸发方式形成所述金属电极。
上述方法采用注入与外延方式结合制备 NPT RC IGBT。 其中，N型衬底上的P/N交隔结构可以采用常规光刻机和离子注入设备作业，在其上外延后圆片厚度与正常流通圆片相同，因此与现有的常规工艺兼容。此外，也无需专用的双面曝光设备，大大降低工艺成本。
【附图说明】
图1为NPT RC IGBT内部结构断面示意图；
图2为一实施例的NPT IGBT的制造方法流程图；
图3为与图2的步骤S101对应的NPT RC IGBT结构；
图4为与图2的步骤S102对应的NPT RC IGBT结构；
图5为与图2的步骤S103对应的NPT RC IGBT结构；
图6为与图2的步骤S104对应的NPT RC IGBT结构；
图7为与图2的步骤S105对应的NPT RC IGBT结构；
图8为与图2的步骤S106对应的NPT RC IGBT结构。
【具体实施方式】
以下结合附图和实施例对本发明进行进一步说明。
如图2所示，为一实施例的非穿通型反向导通绝缘栅双极型晶体管的制造方法流程图。该方法包括如下步骤S101~S106。
步骤S101：提供N型衬底。N型衬底是指在半导体材料中掺入N型离子后所形成的衬底，做成标准尺寸（6英寸或8英寸等）的圆片形状，能够在其上进行各种半导体工艺，如图3所示。所述N型衬底的厚度为100~650微米，电阻率为0.001~10欧姆•厘米（Ω•cm）。N型衬底100作为后续的外延层的支撑，同时也用于形成最后的P型层。
步骤S102：在所述N型衬底上采用离子注入的方式形成P+发射区。参考图4，N型衬底100上间隔形成了多个P型区102。该P型区102是采用离子注入方式形成的。离子注入具体包括以下步骤：
步骤S121：在N型衬底上光刻形成注入图形。该步骤是光刻的常规步骤，包括涂覆光刻胶、烘焙、光刻蚀、清洗等步骤。经过光刻后，在N型衬底100上形成了注入图形，也即N型衬底100的表面一部分被光刻胶200覆盖，另一部分露出。露出的部分是用来形成P型区的区域。
步骤S122：在所述注入图形上进行离子注入形成P+发射区。对整个N型衬底100表面用离子进行轰击，实现离子注入。本实施例中，注入离子为硼，注入剂量为1E13~1E20 cm-2，注入能量为30~200千电子伏特。经过本步骤之后，就可以在N型衬底100上形成如图4所示的多个间隔的P型区102，也即最后形成的IGBT的P+发射区。
步骤S123：清除光刻胶。将光刻胶200从N型衬底100的表面移除。
上述步骤之后，就形成了具有P型区102的N型衬底100。
步骤S103：在所述N型衬底上具有P+发射区的一面外延制备N型漂移区。参考图5，外延制备是指在N型衬底100之上再形成一个衬底，称为外延层。也即图5所示的N型漂移区300。制备外延层的技术较为常规，在此不赘述。所形成的N型漂移区300的厚度为10~650微米，并且与N型衬底100的厚度之和与正常流通硅片的厚度相当。N型漂移区300用于形成IGBT中除P+发射区之外的其他层，本实施例中，称为IGBT的正面结构。也即是说，N型漂移区300的厚度既要能够用于形成完整的IGBT正面结构，又要与N型衬底100一起的厚度与正常流通硅片的厚度相当。正常流通硅片一般是厚度为625微米或675微米的6英寸硅片，或者是厚度为725微米的8英寸硅片。因此，可行的厚度示例为：当用于6英寸硅片工艺时，N型漂移区300为300微米厚，N型衬底100为325微米或375微米厚；当用于8英寸硅片工艺时，N型漂移区300为400微米厚，N型衬底100为325微米厚。当然，也可以选择其他满足上述两个条件的厚度。
N型漂移区300的电阻率为5~500欧姆•厘米（Ω•cm）。
步骤S104：在所述N型漂移区上制备绝缘栅双极型晶体管的正面结构。该正面结构如图6所示。本步骤包括在N型漂移区300上形成P型体区302和在P型体区302上形成N型发射区304。两个P型体区302之间是N型沟道，N型沟道上形成栅极层306。然后分别经过电极引出作为发射极和栅极。
步骤S105：将所述N型衬底减薄至N型通道处。将N型衬底100自背向P型区102的一面向P型区102的方向减薄，直至P型区102在N型衬底100的背面也露出。减薄后的N型衬底100如图7所示。减薄N型衬底100的方式可以采用机械研磨。可以理解，为减少减薄时的处理时间和避免减薄N型衬底100产生的浪费，N型衬底100的厚度在保证流通安全的前提下应当尽可能少。
步骤S106：在所述N型衬底背面形成金属电极。即在P+发射区上形成金属层并因此电极作为整个IGBT的集电极，并最终形成NPT IGBT的完整结构，参考图7。本步骤中，可以采用溅射或蒸发方式形成所述金属电极。
上述方法中，采用注入与外延方式结合制备 NPT RC IGBT。 其中，N型衬底100上的P/N交隔结构可以采用常规光刻机和离子注入设备作业，在其上外延后圆片厚度与正常流通圆片相同，因此与现有的常规工艺兼容。此外，也无需专用的双面曝光设备，大大降低工艺成本。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (12)

  1. 一种非穿通型反向导通绝缘栅双极型晶体管的制造方法，包括如下步骤：
    提供N型衬底；
    在所述N型衬底上采用离子注入的方式形成P+发射区；
    在所述N型衬底上具有P+发射区的一面外延制备N型漂移区；
    在所述N型漂移区上制备所述绝缘栅双极型晶体管的正面结构；
    将所述N型衬底减薄至背面露出所述P+发射区；及
    在所述N型衬底背面形成金属电极。
  2. 根据权利要求1所述的非穿通型反向导通绝缘栅双极型晶体管的制造方法，其特征在于，所述N型衬底的厚度为100~650微米，所述N型漂移区的厚度为10~650微米，且所述N型衬底和N型漂移区的厚度之和与正常流通硅片的厚度相当。
  3. 根据权利要求2所述的非穿通型反向导通绝缘栅双极型晶体管的制造方法，其特征在于，所述正常流通硅片是厚度为625微米或675微米的6英寸硅片，或者是厚度为725微米的8英寸硅片。
  4. 根据权利要求3所述的非穿通型反向导通绝缘栅双极型晶体管的制造方法，其特征在于，所述正常流通硅片采用6英寸硅片，所述N型漂移区为300微米厚，所述N型衬底为325微米或375微米厚。
  5. 根据权利要求3所述的非穿通型反向导通绝缘栅双极型晶体管的制造方法，其特征在于，所述正常流通硅片采用8英寸硅片，所述N型漂移区为400微米厚，所述N型衬底为325微米厚。
  6. 根据权利要求1所述的非穿通型反向导通绝缘栅双极型晶体管的制造方法，其特征在于，所述在N型衬底上采用离子注入的方式形成P+发射区的步骤包括：
    在所述N型衬底上光刻形成注入图形；
    在所述注入图形上进行离子注入形成P+发射区。
  7. 根据权利要求6所述的非穿通型反向导通绝缘栅双极型晶体管的制造方法，其特征在于，注入离子为硼，注入剂量为1E13~1E20 cm-2，注入能量为30~200千电子伏特。
  8. 根据权利要求1所述的非穿通型反向导通绝缘栅双极型晶体管的制造方法，其特征在于，所述N型衬底的电阻率为0.001~10欧姆•厘米，所述N型漂移区的电阻率为5~500欧姆•厘米。
  9. 根据权利要求1所述的非穿通型反向导通绝缘栅双极型晶体管的制造方法，其特征在于，所述在N型衬底背面形成金属电极的步骤中，可以采用溅射或蒸发方式形成所述金属电极。
  10. 根据权利要求1所述的非穿通型反向导通绝缘栅双极型晶体管的制造方法，其特征在于，所述在N型漂移区上制备绝缘栅双极型晶体管的正面结构的步骤包括：
    在所述N型漂移区上间隔形成P型体区；
    在所述P型体区上形成N型发射区；
    在所述P型体区之间的N型沟道上形成栅极层；及
    在所述N型发射区上引出发射极电极，在所述栅极层上引出栅极电极。
  11. 根据权利要求1所述的非穿通型反向导通绝缘栅双极型晶体管的制造方法，其特征在于，采用机械研磨减薄所述N型衬底。
  12. 根据权利要求1所述的非穿通型反向导通绝缘栅双极型晶体管的制造方法，其特征在于，采用溅射或蒸发方式形成所述金属电极。
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