WO2014201796A1 - 阵列基板及液晶显示装置 - Google Patents

阵列基板及液晶显示装置 Download PDF

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Publication number
WO2014201796A1
WO2014201796A1 PCT/CN2013/086921 CN2013086921W WO2014201796A1 WO 2014201796 A1 WO2014201796 A1 WO 2014201796A1 CN 2013086921 W CN2013086921 W CN 2013086921W WO 2014201796 A1 WO2014201796 A1 WO 2014201796A1
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Prior art keywords
electrode
slit
pixel units
pixel
array substrate
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Ceased
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PCT/CN2013/086921
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English (en)
French (fr)
Inventor
彭宽军
田允允
崔贤植
金熙哲
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to US14/342,154 priority Critical patent/US9659971B2/en
Publication of WO2014201796A1 publication Critical patent/WO2014201796A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the invention belongs to the technical field of liquid crystal display, and particularly relates to an array substrate and a liquid crystal display device. Background technique
  • the liquid crystal display device of the FFS (Fringe Field Switching) or the advanced super-dimensional field switching mode (ADS, Advanced Dimension Switch) has many advantages such as high transmittance, wide viewing angle, wide color gamut, etc., so that it becomes a liquid crystal display device. Research hotspots.
  • a plurality of pixel units 9 for performing display are disposed on an array substrate of a FFS mode or an ADS mode liquid crystal display device, and a plate electrode 2 is disposed in each pixel unit 9 .
  • a slit electrode 1 is disposed above the plate electrode 2, and an insulating layer (not shown) is disposed between the plate electrode 2 and the slit electrode 1; and an area between the pixel units 9 (ie, the pixel unit 9)
  • the peripheral region is used to set other structures such as the gate line 31, the data line 32, and the thin film transistor 4.
  • the area between the pixel units 9 corresponds to the black matrix on the color filter substrate, so these areas are not used for display (ie, no sold out).
  • the "pixel unit” refers to an area for display, that is, a light-transmissive area (light-emitting area) during display, and a space between each pixel unit, which is used for setting Other structures such as gate lines, data lines, thin film transistors, etc., these areas are blocked by the black matrix when displayed, so they are not counted as “pixel units”.
  • Slit electrode refers to an electrode structure composed of electrode strips and slits arranged between electrode strips
  • “plate electrode” refers to a sheet electrode structure for generating a driving electric field between the slit electrodes, " Both the slit electrode and the “plate electrode” can be obtained, for example, by photolithography of a transparent conductive material layer (such as indium tin oxide).
  • the lower conductive material layers form an electrical connection structure (such as the electrode strips connecting the slit electrodes or will be different).
  • the electrodes in the pixel unit are electrically connected, and these electrical connection structures are formed simultaneously with the slit electrode or the plate electrode, but are not regarded as a part of the slit electrode or the plate electrode.
  • the plate electrode 2 may be a pixel electrode and the slit electrode 1 may be a common electrode, or vice versa, that is, the plate electrode 2 may be a common electrode and the slit electrode 1 may be a pixel electrode.
  • the plate electrode 2 is generally larger than the pixel unit 9 (ie, the plate electrode 2 extends to the periphery of the pixel unit 9), and the slit electrode 1 is The pixel unit 9 is coincident or slightly smaller than the pixel unit 9 (i.e., the boundary of the slit electrode 1 corresponds to or is slightly smaller than the boundary of the pixel unit 9).
  • the inventors have found that at least the following problems exist in the prior art: In a liquid crystal display device of FFS mode or ADS mode, the slit electrode overlaps with or is slightly smaller than the pixel unit, and apparently, the electric field at the edge of the slit electrode and the electric field in the middle portion The distribution is certainly different, the electric field at the edge is prone to disorder, and the driving force to the liquid crystal molecules is poor, which results in low liquid crystal efficiency in the edge region of the pixel unit (corresponding to the edge of the slit electrode), and thus reduces the entire display.
  • the transmittance of the device In a liquid crystal display device of FFS mode or ADS mode, the slit electrode overlaps with or is slightly smaller than the pixel unit, and apparently, the electric field at the edge of the slit electrode and the electric field in the middle portion The distribution is certainly different, the electric field at the edge is prone to disorder, and the driving force to the liquid crystal molecules is poor, which results in low liquid crystal efficiency in the edge region of the pixel unit (corresponding
  • the technical problem to be solved by the present invention includes providing an array substrate having high transmittance and transmittance for a problem of low transmittance of a liquid crystal display device of the conventional FFS mode or ADS mode.
  • the technical solution adopted to solve the technical problem of the present invention is an array substrate comprising a plurality of pixel units, wherein the pixel unit is provided with a plate electrode and a slit electrode located above the plate electrode, and between the plate electrode and the slit electrode An insulating layer is provided; and the plate electrode extends to the periphery of the pixel unit;
  • the slit electrode extends to the periphery of the pixel unit
  • the slit electrode and the plate electrode are simultaneously disposed in at least a portion of the peripheral region of the pixel unit.
  • the slit electrode and the plate electrode are provided in at least a part of the peripheral region of the pixel unit, so that the electric field generated in the pixel region is adjacent to the edge region of the pixel unit adjacent to the peripheral region
  • the electric field generated by the region is no longer different, so the driving ability of the electric field is enhanced in the edge region, so that the liquid crystal
  • the efficiency is high and the transmittance is high, thereby increasing the overall transmittance of the liquid crystal display device.
  • the array substrate further includes a plurality of gate lines and data lines disposed in a crosswise manner, wherein a direction in which the gate lines are arranged is a row direction, and a direction in which the data lines are arranged in a column direction; each two rows of adjacent pixel units There are N gate lines, and each N pixel units in each row of pixel units are alternately connected to N gate lines, N is an integer greater than or equal to 2; and each N column of pixel units is provided with a data line. Each data line is connected to N columns of pixel units at the same time.
  • the direction in which the gate line is set is the row direction, and the direction in which the data line is set in the column direction
  • the length direction of the gate line is defined as the direction of the "row”
  • the length direction of the data line is defined as "
  • the direction of the column that is, the "row/column direction” is determined by the direction of the gate line and the data line, and has nothing to do with the position and placement of the array substrate.
  • Every N pixel units in each row of pixel cells are alternately connected to N gate lines on both sides of the row of pixel cells means that for every N pixel cells in the same row, in a certain direction
  • Each of the N gate lines on both sides of the pixel unit of the row is alternately connected to each other when viewed, that is, any N adjacent pixel units are respectively connected to the N gate lines in a one-to-one manner; for example If N is equal to 2, the first pixel unit from the left in a row of pixel units is connected to the first gate line on the side of the row of pixel units, and the second pixel unit and the other side of the row of pixel units The second gate line is connected, the third pixel unit is connected to the first gate line, the fourth pixel unit is connected to the second gate line, and so on; and for example, if N is equal to 3.
  • a fifth pixel unit is connected to a second gate line on a second side of the row
  • a sixth pixel unit is connected to a third gate line on a first side of the row, and so on; and the following "each column Each N pixel units in a pixel unit are alternately connected to N data lines on both sides of the column of pixel units. The meaning is similar and will not be described in detail.
  • the slit electrode and the plate electrode extend to the pixel unit In the peripheral area on the side not adjacent to the data line in the row direction.
  • the plate electrode is a pixel electrode
  • the slit electrode is a common electrode
  • the slit electrodes of N adjacent pixel units located in the same row without a data line are connected in a unitary structure.
  • the N is 2; every 2 pixel units in each row of pixel units are alternately connected to two gate lines on both sides of the row of pixel units; each data line is simultaneously on both sides of the data line The 2 columns of pixel units are connected.
  • the array substrate further includes a plurality of gate lines and data lines disposed in a crosswise manner, wherein a direction in which the gate lines are arranged is a row direction, and a direction in which the data lines are arranged in a column direction;
  • a gate line each gate line is connected to N rows of pixel units at the same time, N is an integer greater than or equal to 2;
  • N data lines are arranged between each adjacent column of pixel units, and 2 pixels in each column of pixel units The pixel units are alternately connected to the N data lines.
  • the slit electrode and the plate electrode extend into a peripheral region of the pixel unit which is not adjacent to the gate line in the column direction.
  • the plate electrode is a pixel electrode
  • the slit electrode is a common electrode
  • the slit electrodes of N adjacent pixel units located in the same column without a gate line are connected in a unitary structure.
  • the N is 2; each gate line is simultaneously connected to two rows of pixel units on both sides of the gate line; every two pixel units in each column of pixel units are alternately interdigitated with the column of pixel units The two data lines on the side are connected.
  • a plate-shaped electrode and a slit electrode are provided in a peripheral region of each of the pixel units in each direction.
  • the technical solution adopted to solve the technical problem of the present invention is a liquid crystal display device comprising the above array substrate.
  • liquid crystal display device of the present invention Since the liquid crystal display device of the present invention has the above array substrate, its transmittance is high.
  • the present invention is applicable to a liquid crystal display device of an FFS mode or an ADS mode, particularly for use in a liquid crystal display device employing a "double gate line" design.
  • 1 is a partial plan view showing a conventional FFS mode or an ADS mode array substrate
  • FIG. 2 is a partial top plan view of an array substrate according to Embodiment 1 of the present invention
  • FIG. 3 is a partial top plan view of the array substrate according to Embodiment 2 of the present invention
  • FIG. 4 is a partial view of the array substrate according to Embodiment 3 of the present invention
  • the top view is a schematic view; wherein the reference numerals are: 1. a slit electrode; 2. a plate electrode; 31, a gate line; 32, a data line; 33, a common electrode line; 4. a thin film transistor; detailed description
  • the embodiment provides an array substrate including gate lines 31 and data lines 32 disposed at intersections, and a thin film transistor 4 is disposed at an intersection of the gate lines 31 and the data lines 32, and defines pixels.
  • each pixel unit 9 is used to independently display the desired content.
  • the array substrate is in the FFS mode or the ADS mode, that is, each of the pixel units 9 is provided with a plate electrode 2 and a slit electrode 1 located above the plate electrode 2, and the plate electrode 2 and the slit electrode 1 are disposed between An insulating layer (not shown) is used to achieve insulation.
  • the plate electrode 2 in each pixel unit 9 extends to the periphery of the pixel unit 9, that is, the plate electrode 2 is out of the range of the pixel unit 9; meanwhile, the slit electrode 1 also extends to the pixel unit.
  • the slit electrode 1 and the plate electrode 2 are simultaneously provided.
  • both the slit electrode 1 and the plate electrode 2 partially extend outside the pixel unit 9, and the two overlap at the periphery of the pixel unit 9, so that both can generate driving in the peripheral region of the pixel unit 9.
  • the electric field thus, the edge region of the pixel unit 9 adjacent to the peripheral region no longer corresponds to the edge of the slit electrode 1, and the generated electric field is no longer different from the electric field generated in the central portion of the pixel unit.
  • the driving ability of the electric field to the liquid crystal is enhanced, so that the liquid crystal efficiency is high and the transmittance is high, so that the transmittance of the entire display device is high.
  • the plate electrode 2 and the slit electrode 1 are provided on the periphery of each direction of the pixel unit 9.
  • the plate electrode 2 and the slit electrode 1 are provided in the peripheral region adjacent to any position of the edge of the pixel unit 9, or the overlap of the plate electrode 2 and the slit electrode 1 is provided.
  • the area completely surrounds the pixel unit 9; for example, when the pixel unit 9 is rectangular, the outer sides of the four sides and the four corners are provided with the overlapping plate electrodes 2 and the slit electrodes 1.
  • the transmittance of the edge region adjacent to the pixel unit 9 can be improved;
  • the overlapping plate electrodes 2 and the slit electrodes 1 are provided on the periphery of the pixel unit 9, so that the transmittance of all the edge regions of the entire pixel unit 9 is improved, and the effect of improving the transmittance is best achieved.
  • the region beyond the pixel unit 9 of the slit electrode 1 (and the plate electrode 2) does not overlap with the leads such as the gate line 31 and the data line 32, because if the slit electrode 1 and the like When the leads are overlapped, a large parasitic capacitance is generated, which affects the display quality.
  • the slit electrode 1 is overlapped with the leads such as the gate line 31 and the data line 32, it is also possible to provide an insulating layer therebetween.
  • the slit electrode 1 is a common electrode
  • the plate electrode 2 is a pixel electrode. Therefore, as shown in FIG. 2, each slit electrode 1 is electrically connected to the common electrode line 33 (the common electrode line 33). Also connected to the driving chip), and the common electrode line 33 is insulated from the plate electrode 2 (of course, each slit electrode 1 may be electrically connected by other means such as a connecting line), and each of the plate electrodes 2 is insulated from each other and The thin film transistors 4 are connected.
  • Example 2 As shown in FIG. 3, this embodiment provides an array substrate having a structure similar to that of the array substrate of the above embodiment 1.
  • the array substrate of the embodiment adopts a "double gate line” design, in which the number of gate lines 31 is doubled and the number of data lines 32 is halved.
  • This design can reduce the data driver chip (Data Driver IC). ) Quantity, reduce costs.
  • the direction in which the gate lines 31 are arranged is the row direction
  • the direction in which the data lines 32 are arranged is the column direction
  • two gate lines 31 are disposed between the adjacent pixel units 9 in two rows.
  • Each of the two pixel units 9 in each row of pixel units 9 are alternately connected to the two gate lines 31 on both sides of the row of pixel units 9; every second column of pixel units 9 is provided with a data line 32, each of which The data line 32 is simultaneously connected to the two columns of pixel units 9 on both sides of the data line.
  • the pixel unit 9 is provided with the slit electrode 1 and the plate electrode 2 in a peripheral region on the side not adjacent to the data line 32 in the row direction.
  • the slit electrode 1 and the plate electrode 2 in the peripheral region where the data line 32 and the gate line 31 are not provided between the respective pixel units 9, for the following reasons:
  • the slit electrode 1 Preferably, the plate electrode 2 does not overlap with the leads such as the gate line 31 and the data line 32, and as the resolution increases, the gap between the leads and the pixel unit 9 becomes smaller and smaller, which results in the slit electrode 1
  • the plate electrode 2 does not overlap with the lead wire, and the area where the slit electrode 1 and the plate electrode 2 can be overlapped in the peripheral region of the pixel unit 9 is smaller and smaller; and according to the above scheme, the double gate line design is adopted.
  • the plate electrode 2 is a pixel electrode and the slit electrode 1 is a common electrode, as shown in FIG. 3, the narrowness of two adjacent pixel units 9 located in the same row without the data line 32 therebetween
  • the slit electrodes 1 are connected in a unitary structure.
  • the slit electrode 1 when the slit electrode 1 is a common electrode, the slit electrodes 1 of the pixel units 9 are electrically connected by a common electrode line 33 or the like, but the slits are not in communication, that is, each narrow The slit electrode 1 is still set independently.
  • the pole 1 is formed in an integral structure (i.e., the portion between its two pixel units 9 is also the slit electrode 1), or each slit electrode 1 simultaneously covers two adjacent pixel units 9 having no data line 32 therebetween.
  • the slit electrode 1 of the adjacent pixel units 9 without the data lines 32 can be directly connected into an integrated structure to form a cover of the two pixel units 9. Large slit electrode".
  • the plate electrode 2 is a pixel electrode and the slit electrode 1 is a common electrode; but when the plate electrode 2 is a common electrode and the slit electrode 1 is a pixel electrode, it may be located at the same time.
  • the plate electrodes 2 of the two adjacent pixel units 9 in the row and having no data lines 32 therebetween are connected in a unitary structure and will not be described in detail herein.
  • N gate line the number of gate lines 31 can be increased by N times ( N may be an integer greater than 2 for 3, 4, 5, etc., and the number of data lines 32 is reduced to one of N.
  • N may be an integer greater than 2 for 3, 4, 5, etc.
  • the number of data lines 32 is reduced to one of N.
  • N may be an integer greater than 2 for 3, 4, 5, etc.
  • the narrow electrodes (or the plate electrodes 2) of more pixel units 9 can be integrated.
  • N is greater than or equal to 3
  • partial lead overlap is inevitable, and an additional insulating layer needs to be provided, which will not be described in detail herein.
  • this embodiment provides an array substrate having a structure similar to that of the array substrate of the above embodiment 2.
  • the number of data lines 32 is doubled and the number of gate lines 31 is halved.
  • the gate line 31 is provided
  • the setting direction is the row direction
  • the setting direction of the data line 32 is the column direction; wherein, every two rows of the pixel unit 9 is provided with one gate line 31, and each of the gate lines 31 simultaneously has two rows on both sides of the gate line
  • the pixel unit 9 is connected; two data lines 32 are disposed between each two adjacent pixel units 9 , and each of the two pixel units 9 in each column of pixel units 9 are respectively connected to two data lines 32 on both sides of the row of pixel units. .
  • the pixel unit 9 is provided with the slit electrode 1 and the plate electrode 2 in a peripheral region on the side not adjacent to the gate line 31 in the column direction.
  • the slit electrodes 1 of two adjacent pixel units 9 which are located in the same column and have no gate line 31 therebetween are integrally connected. structure.
  • the slit electrodes 1 of the adjacent pixel units 9 having no gate lines 31 therebetween can be connected in a unitary structure to further reduce design and manufacturing difficulty.
  • the plate electrode 2 is a common electrode and the slit electrode 1 is a pixel electrode
  • the plate electrodes of two adjacent pixel units 9 located in the same column without the gate line 31 therebetween can also be used. 2 connected into a single structure.
  • N data line the number of data lines 32 can be increased by N times (N can be an integer greater than 2 such as 3, 4, 5, etc.), and the number of gate lines 31 Decrease to one-N; at this time, there will be no more gate lines 31 between adjacent pixel units 9 in the column direction, so that more space can be left in the periphery of the pixel unit 9 for setting The slit electrode 1 and the plate electrode 2.
  • This embodiment provides a liquid crystal display device including the above array substrate.
  • the liquid crystal display device of this embodiment should also include other known structures, such as a power supply unit, a driving chip, a color filter substrate, a backlight, and the like.
  • the liquid crystal display device of this embodiment may be a liquid crystal display panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, etc. Any product or part that has a display function.
  • the liquid crystal display device of the present embodiment has the above array substrate, the transmittance thereof is high. It is to be understood that the above embodiments are merely exemplary embodiments employed to explain the principles of the invention, but the invention is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and scope of the invention. These modifications and improvements are also considered to be within the scope of the invention.

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Abstract

一种阵列基板以及液晶显示装置，属于液晶显示领域，其可解决现有的液晶显示装置透过率低的问题。阵列基板包括多个像素单元（9），像素单元（9）中设有板状电极（2）和位于板状电极（2）上方的狭缝电极（1），板状电极（2）与狭缝电极（1）间设有绝缘层，且板状电极（2）延伸到像素单元（9）外围；所述狭缝电极（1）延伸到像素单元（9）外围；狭缝电极（1）和板状电极（2）同时设置在所述像素单元（9）的至少部分外围区域中。可用于液晶显示装置中，进一步可用于采用双栅极线设计的液晶显示装置。

Description

阵列基板及液晶显示装置 技术领域
本发明属于液晶显示技术领域， 具体涉及一种阵列基板以及 液晶显示装置。 背景技术
边缘场开关模式 (FFS, Fringe Field Switching)或高级超维场转 换模式 (ADS, Advanced Dimension Switch)的液晶显示装置具有透 过率高、 视角宽、 色域广等诸多优点， 故成为液晶显示装置的研 究热点。
如图 1所示， FFS模式或 ADS模式的液晶显示装置的阵列基 板上设有多个用于进行显示（即用于出光)的像素单元 9, 每个像素 单元 9中设有板状电极 2, 板状电极 2上方设有狭缝电极 1 , 板状 电极 2和狭缝电极 1间设有绝缘层（图中未示出）； 而各像素单元 9 之间的区域 (即像素单元 9的外围区域)则用于设置栅极线 31、 数 据线 32、 薄膜晶体管 4等其他结构， 各像素单元 9之间的区域与 彩膜基板上的黑矩阵对应， 故这些区域不用于显示（即不出光)。
这里， 所述 "像素单元" 是指用于进行显示的区域， 即在显 示过程中光可透过的区域 （出光区） ， 而各像素单元之间还有间 隔的区域， 这些区域用于设置栅极线、 数据线、 薄膜晶体管等其 他结构，这些区域在显示时会被黑矩阵遮挡不出光， 故不算做"像 素单元" 。 "狭缝电极" 是指由电极条和位于电极条之间的狭缝 交替排列组成的电极结构， "板状电极" 是指用于与狭缝电极间 产生驱动电场的片状电极结构， "狭缝电极" 与 "板状电极" 均 可以例如通过对透明导电材料层 (如氧化铟锡)进行光刻得到，在光 刻过程中， 除形成狭缝电极和板状电极外， 还可能多留下一些导 电材料层形成电连接结构（如连接狭缝电极的各电极条或将不同 像素单元中的电极电连接)， 而这些电连接结构虽与狭缝电极或板 状电极同时形成， 但并不视作狭缝电极或板状电极的一部分。
其中，板状电极 2可以为像素电极而狭缝电极 1为公共电极， 或者也可反之， 即板状电极 2可以为公共电极而狭缝电极 1为像 素电极。 但不论电极的具体类型是怎样的， 如图 1 所示， 通常板 状电极 2都会大于像素单元 9(即板状电极 2延伸到像素单元 9的 夕卜围）， 而狭缝电极 1则与像素单元 9重合或略小于像素单元 9(即 狭缝电极 1的边界对应像素单元 9的边界或比其略小）。
发明人发现现有技术中至少存在如下问题： 在 FFS 模式或 ADS模式的液晶显示装置中， 狭缝电极与像素单元重合或比其略 小， 显然， 狭缝电极边缘处的电场与中部的电场分布肯定有所不 同， 其边缘处的电场易发生紊乱， 对液晶分子的驱动力较差， 这 导致像素单元边缘区 (对应狭缝电极的边缘处)的液晶效率低，并由 此降低整个显示装置的透过率。 发明内容
本发明所要解决的技术问题包括， 针对现有的 FFS 模式或 ADS模式的液晶显示装置透过率低的问题， 提供一种透过率高的 阵列基板和透过率。
解决本发明技术问题所采用的技术方案是一种阵列基板， 其 包括多个像素单元， 像素单元中设有板状电极和位于板状电极上 方的狭缝电极， 板状电极与狭缝电极间设有绝缘层； 且板状电极 延伸到像素单元外围；
所述狭缝电极延伸到像素单元外围；
狭缝电极和板状电极同时设置在所述像素单元的至少部分外 围区域中。
本发明的阵列基板中， 在像素单元的至少部分外围区域中设 有狭缝电极和板状电极， 因此对于与该外围区域相邻的像素单元 的边缘区， 使得其中产生的电场与像素单元中部区域产生的电场 不再有区别， 故在该边缘区电场的驱动能力得到增强， 使得液晶 效率高， 透过率高， 由此使液晶显示装置的整体透过率提高。 优选的是， 所述阵列基板还包括交叉设置的多条栅极线和数 据线， 其中以栅极线的设置方向为行方向， 数据线的设置方向为 列方向； 每两行相邻像素单元间设有 N条栅极线， 每行像素单元 中每 N个像素单元彼此交错地与 N条栅极线相连， N为大于等于 2的整数； 每隔 N列像素单元设有一条数据线， 每条数据线同时 与 N列像素单元相连。
其中 "以栅极线的设置方向为行方向， 数据线的设置方向为 列方向" 是指： 将栅极线的长度方向定义为 "行" 的方向， 而将 数据线的长度方向定义为 "列" 的方向， 即该 "行 /列方向" 是由 栅极线和数据线的方向决定的， 而与阵列基板的位置、 放置方式 等均无关系。 "每行像素单元中每 N个像素单元彼此交错地与该 行像素单元两侧的 N条栅极线相连" 是指， 对于同一行中的每 N 个像素单元来说， 在沿一定方向依次观察时彼此交错地连接到该 行像素单元两侧的 N条栅极线中的每一条， 即其中任意 N个相邻 的像素单元分别与 N条栅极线以一对一的方式连接； 例如， 若 N 等于 2,则某行像素单元中从左起的第一个像素单元与该行像素单 元一侧的第一条栅极线相连， 第二个像素单元与该行像素单元另 一侧的第二条栅极线相连， 第三个像素单元又与前述第一条栅极 线相连， 第四个像素单元再与第二条栅极线相连， 并依次类推； 又例如， 若 N等于 3, 每两行像素单元之间具有 3条栅极线， 则 某行像素单元中从左起的第一个像素单元与该行像素单元第一侧 的第一条栅极线相连， 第二个像素单元与该行像素单元第二侧的 第二条栅极线相连， 第三个像素单元与该行第一侧的第三条栅极 线相连， 然后第四个像素单元再与该行第一侧的第一条栅极线相 连， 第五个像素单元与该行第二侧的第二条栅极线相连， 第六个 像素单元与该行第一侧的第三条栅极线相连， 以此类推； 而以下 的 "每列像素单元中每 N个像素单元彼此交错地与该列像素单元 两侧的 N条数据线相连" 含义类似， 不再详细描述。
进一步优选的是， 狭缝电极和板状电极延伸到所述像素单元 在行方向上未与数据线相邻侧的外围区域中。
进一步优选的是， 所述板状电极为像素电极， 狭缝电极为公 共电极； 位于同一行中且之间无数据线的 N个相邻像素单元的狭 缝电极连接成一体结构。
进一步优选的是， 所述 N为 2; 每行像素单元中每 2个像素 单元彼此交错地与该行像素单元两侧的 2条栅极线相连； 每条数 据线同时与该数据线两侧的 2列像素单元相连。
优选的是， 所述阵列基板还包括交叉设置的多条栅极线和数 据线， 其中以栅极线的设置方向为行方向， 数据线的设置方向为 列方向； 每隔 N行像素单元设有一条栅极线， 每条栅极线同时与 N行像素单元相连， N为大于等于 2的整数； 每两列相邻像素单 元间设有 N条数据线， 每列像素单元中每 2个像素单元彼此交错 地与 N条数据线相连。
进一步优选的是， 狭缝电极和板状电极延伸到所述像素单元 在列方向上未与栅极线相邻侧的外围区域中。
进一步优选的是， 所述板状电极为像素电极， 狭缝电极为公 共电极； 位于同一列中且之间无栅极线的 N个相邻像素单元的狭 缝电极连接成一体结构。
进一步优选的是， 所述 N为 2; 每条栅极线同时与该栅极线 两侧的 2行像素单元相连； 每列像素单元中每 2个像素单元彼此 交错地与该列像素单元两侧的 2条数据线相连。
优选的是， 所述像素单元各方向的外围区域中均设有板状电 极和狭缝电极。
解决本发明技术问题所采用的技术方案是一种液晶显示装 置， 其包括上述的阵列基板。
由于本发明的液晶显示装置中具有上述阵列基板， 故其透过 率高。
本发明适用于 FFS模式或 ADS模式的液晶显示装置中，尤其 是用于采用 "双栅极线" 设计的液晶显示装置中。 附图说明
图 1为现有的 FFS模式或 ADS模式的阵列基板的局部俯视结 构示意图；
图 2为本发明的实施例 1的阵列基板的局部俯视结构示意图； 图 3为本发明的实施例 2的阵列基板的局部俯视结构示意图； 图 4为本发明的实施例 3的阵列基板的局部俯视结构示意图； 其中附图标记为： 1、 狭缝电极； 2、 板状电极； 31、 栅极线； 32、 数据线； 33、 公共电极线； 4、 薄膜晶体管； 9、 像素单元。 具体实施方式
为使本领域技术人员更好地理解本发明的技术方案， 下面结 合附图和具体实施方式对本发明作进一步详细描述。 实施例 1 :
如图 2所示， 本实施例提供一种阵列基板， 其包括交叉设置 的栅极线 31和数据线 32,栅极线 31和数据线 32的交叉处设有薄 膜晶体管 4, 并限定出像素单元 9, 每个像素单元 9用于独立显示 所需内容。
其中， 阵列基板为 FFS模式或 ADS模式， 即每个像素单元 9 中均设有板状电极 2和位于板状电极 2上方的狭缝电极 1 ,板状电 极 2与狭缝电极 1间设有绝缘层（图中未示出）以实现绝缘。
如图 2所示， 每个像素单元 9中的板状电极 2均延伸到像素 单元 9的外围， 即板状电极 2超出像素单元 9范围之外； 同时， 狭缝电极 1也延伸到像素单元 9之外， 且在像素单元 9的至少部 分外围区域中， 同时设有狭缝电极 1和板状电极 2。
也就是说， 狭缝电极 1和板状电极 2均有部分延伸到像素单 元 9之外， 且二者在像素单元 9的外围有重叠， 从而二者可在像 素单元 9的外围区域中产生驱动电场； 这样， 与该外围区域相邻 的像素单元 9的边缘区就不再对应狭缝电极 1的边缘处了， 其中 所产生的电场与像素单元中部区域产生的电场也不再有区别， 故 在像素单元 9 的边缘区中电场对液晶的驱动能力得到增强， 使得 液晶效率高， 透过率高， 从而整个显示装置的透过率较高。
优选的， 像素单元 9的各方向外围均设有板状电极 2和狭缝 电极 1。
也就是说， 如图 2所示， 与像素单元 9边缘的任意位置相邻 的外围区域中均设有板状电极 2和狭缝电极 1 , 或者说板状电极 2 和狭缝电极 1的重叠区域完全包围像素单元 9; 例如， 当像素单元 9为矩形时， 则其四条边和四个角的外侧均设有重叠的板状电极 2 和狭缝电极 1。如前所述，若在像素单元 9的外围某处设有板状电 极 2和狭缝电极 1 ,则像素单元 9中与该处相邻的边缘区的透过率 可获得提高； 因此， 优选在像素单元 9的外围均设置重叠的板状 电极 2和狭缝电极 1 ,从而使整个像素单元 9的全部边缘区的透过 率都获得提高， 达到最好的改善透过率的效果。
当然， 应当理解， 如果只在像素单元 9的部分外围区域中设 置板状电极 2和狭缝电极 1 , 也可达到提高透过率的效果。
优选的， 如图 2所示， 狭缝电极 1(和板状电极 2)超出像素单 元 9外的区域均不与栅极线 31、数据线 32等引线重叠， 因为如果 狭缝电极 1 等与引线重叠， 则会产生较大的寄生电容， 影响显示 质量。
当然， 应当理解， 如果狭缝电极 1 与栅极线 31、 数据线 32 等引线重叠设置， 只要其间设有绝缘层， 也是可行的。
在本实施例中， 以狭缝电极 1为公共电极， 而板状电极 2为 像素电极， 因此， 如图 2所示， 各狭缝电极 1均与公共电极线 33 电连接 (公共电极线 33还连接驱动芯片），且公共电极线 33与板状 电极 2间绝缘（当然各狭缝电极 1也可通过连接线等其他方式电连 接)， 而各板状电极 2则相互绝缘，并与各自的薄膜晶体管 4相连。
当然， 应当理解， 如果是以狭缝电极 1为像素电极， 而板状 电极 2为公共电极， 也是可行的。 实施例 2: 如图 3所示， 本实施例提供一种阵列基板， 其具有与以上实 施例 1的阵列基板类似的结构。
区别在于， 本实施例的阵列基板采用的是 "双栅极线"设计， 即其中栅极线 31的数量加倍而数据线 32的数量减半， 这种设计 可减少数据驱动芯片（Data Driver IC)数量、 降低成本。
具体的， 如图 3所示， 以栅极线 31的设置方向为行方向， 数 据线 32的设置方向为列方向； 则每两行相邻像素单元 9间设有两 条栅极线 31 , 而每行像素单元 9中的每两个像素单元 9彼此交错 地与该行像素单元 9两侧的两条栅极线 31相连； 每隔两列像素单 元 9设有一条数据线 32,每条数据线 32同时与该数据线两侧的两 列像素单元 9相连。
优选的，像素单元 9在行方向上未与数据线 32相邻侧的外围 区域中设有狭缝电极 1和板状电极 2。
也就是说， 优选在各像素单元 9 间没有数据线 32和栅极线 31一侧的外围区域中设置狭缝电极 1和板状电极 2, 其原因如下： 如前所述， 狭缝电极 1、 板状电极 2优选不与栅极线 31、 数 据线 32等引线重叠， 而随着分辨率的提高， 各引线与像素单元 9 间的间隙越来越小， 这导致若要狭缝电极 1、板状电极 2不与引线 重叠， 则在像素单元 9外围区域中能重叠设置狭缝电极 1和板状 电极 2的区域越来越小； 而根据以上方案， 由于采用了双栅极线 设计， 故部分像素单元 9间没有引线 (数据线 32), 这样这些像素 单元 9间就留出了足够的空间用于设置狭缝电极 1和板状电极 2, 使其设计、 制造等更加筒单， 提高透过率的效果更好。
进一步优选的， 当板状电极 2为像素电极， 而狭缝电极 1为 公共电极时， 如图 3所示， 位于同一行中且之间无数据线 32的两 个相邻像素单元 9的狭缝电极 1连接成一体结构。
通常而言， 如图 1所示， 当狭缝电极 1为公共电极时， 各像 素单元 9的狭缝电极 1间通过公共电极线 33等电连接， 但其狭缝 并不相通， 即各狭缝电极 1 仍是独立设置的。 而在本实施例中， 如图 3所示， 之间没有数据线 32的两个相邻像素单元 9的狭缝电 极 1形成一体结构（即其两个像素单元 9之间的部分也是狭缝电极 1), 或者说每个狭缝电极 1 同时覆盖两个相邻且之间没有数据线 32的像素单元 9。
如前所述， 当采用双栅极线设计时， 在行方向上部分相邻像 素单元 9间没有引线， 故在这些位置设置狭缝电极 1不会产生寄 生电容， 又由于此时狭缝电极 1是公共电极， 故为了更好的筒化 设计和制造工艺， 可将之间没有数据线 32的相邻像素单元 9的狭 缝电极 1直接连为一体结构， 形成覆盖两个像素单元 9的 "大狭 缝电极" 。
当然， 以上所述的是板状电极 2为像素电极， 而狭缝电极 1 为公共电极的情况； 但当板状电极 2为公共电极而狭缝电极 1为 像素电极时， 也可使位于同一行中且之间无数据线 32的 2个相邻 像素单元 9中的板状电极 2连接成一体结构， 在此不再详细描述。
应当理解， 本实施例中虽然以 "双栅极线" 的设计作为例子， 但若采用 "N栅极线" 的设计也是可行的； 也就是说， 可将栅极 线 31数量增加 N倍 (N可为 3、 4、 5等大于 2的整数)， 而数据线 32数量减小为 N分之一。 此时， 在行方向上， 会有更多相邻的像 素单元 9之间没有数据线 32, 故可在像素单元 9外围留出更多的 空间用于设置狭缝电极 1和板状电极 2, 且可将更多个像素单元 9 的狭逢电极 (或板状电极 2)连为一体。 当然， 当 N大于等于 3时， 必然会出现部分引线交叠， 此时需要设置额外的绝缘层， 在此不 再详细描述。 实施例 3:
如图 4所示， 本实施例提供一种阵列基板， 其具有与以上实 施例 2的阵列基板类似的结构。
区别在于， 本实施例采用的不是 "双栅极线" 的设计， 而是 "双数据线" 的设计。
也就是说， 如图 4所示， 本实施例的阵列基板中， 数据线 32 的数量加倍而栅极线 31的数量减半。 具体的， 以栅极线 31的设 置方向为行方向， 数据线 32的设置方向为列方向； 其中， 每隔两 行像素单元 9设有一条栅极线 31 ,每条栅极线 31同时与该栅极线 两侧的两行像素单元 9相连； 每两列相邻像素单元 9间设有两条 数据线 32, 每列像素单元 9中的每两个像素单元 9分别与该行像 素单元两侧的两条数据线 32相连。
优选的，像素单元 9在列方向上未与栅极线 31相邻侧的外围 区域中设有狭缝电极 1和板状电极 2。
显然， 如果采用 "双数据线" 的设计， 则在列方向上部分像 素单元 9之间没有栅极线 31 , 故其同样可为狭缝电极 1和板状电 极 2的设置留出更多的空间， 降低设计和制造难度。
进一步优选的， 当板状电极 2为像素电极， 狭缝电极 1为公 共电极， 则位于同一列中且之间无栅极线 31的两个相邻像素单元 9的狭缝电极 1连接成一体结构。
与实施例 2类似，可将之间没有栅极线 31的邻像素单元 9的 狭缝电极 1连接成一体结构， 以进一步降低设计和制造难度。
当然， 应当理解， 在板状电极 2为公共电极而狭缝电极 1为 像素电极时， 也可使位于同一列中且之间无栅极线 31的两个相邻 像素单元 9的板状电极 2连接成一体结构。
同时， 本实施例显然也可采用 "N数据线" 的设计， 即可将 数据线 32的数量增加 N倍 (N可为 3、 4、 5等大于 2的整数)， 而 栅极线 31数量减小为 N分之一； 此时， 在列方向上， 会有更多相 邻的像素单元 9之间没有栅极线 31 , 故可在像素单元 9外围留出 更多的空间用于设置狭缝电极 1和板状电极 2。 实施例 4:
本实施例提供一种液晶显示装置， 其包括上述的阵列基板。 当然，本实施例的液晶显示装置中还应包括其他的已知结构， 如电源单元、 驱动芯片、 彩膜基板、 背光源等。
本实施例的液晶显示装置可为液晶显示面板、 电子纸、 手机、 平板电脑、 电视机、 显示器、 笔记本电脑、 数码相框、 导航仪等 任何具有显示功能的产品或部件。
由于本实施例的液晶显示装置中具有上述阵列基板， 故其透 过率高。 可以理解的是， 以上实施方式仅仅是为了说明本发明的原理 而采用的示例性实施方式， 然而本发明并不局限于此。 对于本领 域内的普通技术人员而言， 在不脱离本发明的精神和实质的情况 下， 可以做出各种变型和改进， 这些变型和改进也视为本发明的 保护范围。

Claims

权 利 要 求 书
1. 一种阵列基板， 包括多个像素单元， 像素单元中设有板状 电极和位于板状电极上方的狭缝电极， 板状电极与狭缝电极间设 有绝缘层， 且板状电极延伸到像素单元的外围区域， 其特征在于， 所述狭缝电极延伸到像素单元的外围区域；
所述狭缝电极和板状电极同时设置在所述像素单元的至少部 分外围区域中。
2. 根据权利要求 1所述的阵列基板， 其特征在于， 还包括交 叉设置的多条栅极线和数据线， 其中
以栅极线的设置方向为行方向，数据线的设置方向为列方向； 每两行相邻像素单元间设有 N条栅极线， 每行像素单元中的 各个像素单元彼此交错地连接至该行像素单元两侧的 N 条栅极 线， N为大于等于 2的整数； 每隔 N列像素单元设有一条数据线， 每条数据线同时与 N列像素单元相连。
3. 根据权利要求 2所述的阵列基板， 其特征在于，
所述像素单元在行方向上未与数据线相邻侧的外围区域中设 有狭缝电极和板状电极。
4. 根据权利要求 3所述的阵列基板， 其特征在于，
所述板状电极为像素电极， 狭缝电极为公共电极；
位于同一行中且之间无数据线的 N个相邻像素单元的狭缝电 极连接成一体结构。
5. 根据权利要求 3所述的阵列基板， 其特征在于，
所述板状电极为公共电极， 狭缝电极为像素电极；
位于同一行中且之间无数据线的 N个相邻像素单元的板状电 极连接成一体结构。
6. 根据权利要求 2所述的阵列基板， 其特征在于,
所述 N为 2。
7. 根据权利要求 1所述的阵列基板， 其特征在于， 还包括交 叉设置的多条栅极线和数据线， 其中
以栅极线的设置方向为行方向，数据线的设置方向为列方向； 每隔 N行像素单元设有一条栅极线，每条栅极线同时与 N行 像素单元相连， N为大于等于 2的整数；
每两列相邻像素单元间设有 N条数据线， 每列像素单元中的 各个像素单元彼此交错地连接至该列像素单元两侧的 N 条数据 线。
8. 根据权利要求 7所述的阵列基板， 其特征在于，
所述像素单元在列方向上未与栅极线相邻侧的外围区域中设 有狭缝电极和板状电极。
9. 根据权利要求 8所述的阵列基板， 其特征在于，
所述板状电极为像素电极， 狭缝电极为公共电极；
位于同一列中且之间无栅极线的 N个相邻像素单元的狭缝电 极连接成一体结构。
10. 根据权利要求 8所述的阵列基板， 其特征在于， 所述板状电极为公共电极， 狭缝电极为像素电极；
位于同一列中且之间无栅极线的 N个相邻像素单元的板状电 极连接成一体结构。
11. 根据权利要求 7所述的阵列基板， 其特征在于, 所述 N为 2。
12. 据权利要求 1至 11中任意一项所述的阵列基板， 其特征 在于，
所述像素单元各方向的外围区域中均设有板状电极和狭缝电 极。
13. 一种液晶显示装置， 其特征在于， 包括：
权利要求 1至 12中任意一项所述的阵列基板。
PCT/CN2013/086921 2013-06-21 2013-11-12 阵列基板及液晶显示装置 Ceased WO2014201796A1 (zh)

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