WO2014201723A1 - 液晶阵列基板、电子装置及液晶阵列基板测试方法 - Google Patents

液晶阵列基板、电子装置及液晶阵列基板测试方法 Download PDF

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Publication number
WO2014201723A1
WO2014201723A1 PCT/CN2013/078535 CN2013078535W WO2014201723A1 WO 2014201723 A1 WO2014201723 A1 WO 2014201723A1 CN 2013078535 W CN2013078535 W CN 2013078535W WO 2014201723 A1 WO2014201723 A1 WO 2014201723A1
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area
sub
tft transistor
liquid crystal
common electrode
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PCT/CN2013/078535
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English (en)
French (fr)
Inventor
姚晓慧
许哲豪
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深圳市华星光电技术有限公司
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Priority to US13/983,777 priority Critical patent/US9405161B2/en
Publication of WO2014201723A1 publication Critical patent/WO2014201723A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • G02F1/1309—Repairing; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G09G2300/0447—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations for multi-domain technique to improve the viewing angle in a liquid crystal display, such as multi-vertical alignment [MVA]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared

Definitions

  • Liquid crystal array substrate Liquid crystal array substrate, electronic device and liquid crystal array substrate test method
  • the present invention relates to a substrate, and more particularly to a liquid crystal array substrate, an electronic device having the liquid crystal array substrate, and a liquid crystal array substrate testing method. Background technique
  • liquid crystal electronic devices such as liquid crystal televisions and liquid crystal displays are becoming more and more popular.
  • liquid crystal electronic devices have a multi-angle display mode.
  • color aberrations observed at a large viewing angle are caused by different orientations of liquid crystal molecules observed in different viewing angles.
  • one pixel is divided into two parts, one part is the main area and the other part is the sub area. Large viewing angle distortion is improved by controlling the voltages of the two zones.
  • the design of the main area and the sub-area is generally called LCS (Low Color Shift) design.
  • the invention provides a liquid crystal array substrate, an electronic device and a liquid crystal array substrate testing method, which can easily detect whether the liquid crystal array is qualified.
  • a liquid crystal array substrate includes a plurality of pixel regions including a main region, a sub-region, and a regulating TFT transistor, wherein the regulating TFT transistor is configured to adjust a voltage ratio of the main region and the sub-region to achieve a low color shift, wherein
  • the main area includes a first TFT transistor and a main area array electric common electrode trace
  • the sub-area includes a second TFT transistor and a sub-area array electric common electrode trace, wherein the main area array circuit common electrode trace
  • the sub-area array electro-electrode traces are electrically isolated from each other; wherein the gate of the first TFT transistor is connected to the first scan line, the source is connected to the data line, the drain is connected to the pixel electrode, and the main area array is electrically connected ⁇ ⁇ Common electrode trace is coupled, the gate of the second TFT transistor is connected to the first scan line, the source and the data a drain connection is coupled to the pixel electrode and coupled to the sub-area array circuit common electrode trace; the source of
  • the first scan line is used to generate an on or off signal to control the first TFT transistor to be turned on or off.
  • the data line is used to input a data driving signal when the first TFT transistor is turned on, and control the display of the main area.
  • the first scan line is used to generate an on or off signal to control the second TFT transistor to be turned on or off.
  • the data line is used to input a data driving signal when the second TFT transistor is turned on, and control the display of the sub-region.
  • An electronic device includes a liquid crystal array substrate, the liquid crystal array substrate includes a plurality of pixel regions, the pixel region includes a main region, a sub-region, and a regulating TFT transistor for regulating voltages of the main region and the sub-region
  • the main region includes a first TFT transistor and a main-region array electrode common electrode trace
  • the sub-region includes a second TFT transistor and a sub-area array electrode common electrode electrical isolation
  • a gate of the first TFT transistor is connected to the first scan line, a source is connected to the data line, a drain is connected to the pixel electrode, and is coupled to the common electrode trace of the main area array circuit
  • the gate of the second TFT transistor is first a scan line is connected, a source is connected to the data line, a drain is connected to the pixel electrode, and is coupled to the common electrode trace of the sub-area array circuit
  • a source of the control TFT transistor is electrically connected to a drain of the second TFT transistor, and is drained The pole
  • the first scan line is used to generate an on or off signal to control the first TFT transistor to be turned on or off.
  • the data line is used to input a data driving signal when the first TFT transistor is turned on, and control the display of the main area.
  • the first scan line is used to generate an on or off signal to control the second TFT transistor to be turned on or off.
  • the data line is used to input a data driving signal when the second TFT transistor is turned on, and the control subfield is Display.
  • the electronic device is a liquid crystal display or a liquid crystal television.
  • a method for testing a liquid crystal array substrate comprising the steps of: controlling a first TFT transistor and a second TFT transistor of a pixel region by a scan line input turn-off signal to be in a closed state; applying a first voltage to the main-region conductive sheet and a pair of sub-region conductive sheets Applying a second voltage; wherein, the main-region conductive sheet is electrically connected to the main-area array circuit common electrode trace of all the pixel regions, and the sub-region conductive sheet is electrically connected to the sub-area array circuit common electrode trace of all the pixel regions, wherein The common electrode trace of the main area array circuit is electrically isolated from the common electrode trace of the sub-area array circuit; detecting whether the voltages of the main area and the sub-area of the pixel area are the same; if yes, determining that the main area and the sub-area have a short circuit.
  • the method further comprises the step of: if the voltages of the main area and the sub-area of the pixel area are not the same, it is determined that there is no short circuit in the main area and the sub-area.
  • the step of "applying a first voltage to the main-region conductive sheet and applying the second voltage to the sub-region conductive sheet” comprises: applying a high potential to the main-region conductive sheet and applying a zero potential to the sub-region conductive sheet.
  • the step of "applying a first voltage to the main-region conductive sheet and applying the second voltage to the sub-region conductive sheet” comprises: applying a zero potential to the main-region conductive sheet and applying a high potential to the sub-region conductive sheet.
  • the method further includes: performing maintenance on a pixel area in which the liquid crystal array substrate has a short circuit.
  • the liquid crystal array of the present invention is reversed, the electronic device having a liquid crystal and a method of testing an array substrate of the liquid crystal array substrate, through a main ⁇ 1
  • FIG. 1 is a schematic view showing a liquid crystal array in an embodiment of the present invention.
  • FIG. 2 is a detailed schematic diagram of a pixel region in a liquid crystal array according to an embodiment of the present invention.
  • FIG. 3 is a schematic view of an electronic device having a liquid crystal array reversed in an embodiment of the present invention.
  • Fig. 4 is a flow chart showing a method of detecting a liquid crystal array in an embodiment of the present invention. detailed description
  • FIG. 1 is a schematic diagram of a reverse polarity of a liquid crystal array according to an embodiment of the present invention
  • FIG. 2 is a specific schematic diagram of a pixel region 1 included in the liquid crystal array.
  • the liquid crystal array substrate 100 is a liquid crystal array with a low color shift design.
  • the liquid crystal array includes a plurality of pixel regions 1 distributed in an array, the pixel region 1 including a main region 11, a sub-region 12, and a regulating TFT transistor T.
  • the main area 11 includes a first TFT (thin film transistor) transistor T1 and a main area array circuit common electrode trace MAcom.
  • the sub-region includes a second TFT transistor T2 and a sub-area array circuit common electrode trace SAcom.
  • the control TFT transistor T is used to adjust the voltage ratio of the main region 11 and the sub-region 12, and realizes a low color shift design of the liquid crystal array anti-100.
  • the gates of the first TFT transistor T1 and the second TFT transistor T2 in each of the pixel regions 1 are connected to the first scan line 111.
  • the sources of the first TFT transistor T1 and the second TFT transistor T2 are both connected to the data line 222.
  • the drain of the first TFT transistor T1 is coupled to the main-area array electrode common line MAcom, and the drain of the second TFT transistor T2 is coupled to the sub-area array circuit common electrode trace SAcom.
  • the drain of the first TFT transistor T1 is also connected to the corresponding pixel electrode P, and the drain of the second TFT transistor T2 is also electrically connected to the corresponding pixel electrode P.
  • the source of the TFT transistor T is coupled to the drain of the first TFT transistor T1, and the drain is electrically connected to the drain of the second TFT transistor T2.
  • the gate and the second scan of the TFT transistor T are controlled.
  • Line 112 is connected.
  • the regulating TFT transistor T is used to adjust the voltage ratio between the main region 11 and the sub-region 12, that is, to adjust the voltage ratio between the pixel electrode P connected to the first TFT transistor T1 and the pixel electrode P connected to the second TFT transistor T2. Low color shift. Since it is not related to the improvement of the present invention, it will not be described any more.
  • the main area array circuit common electrode trace MAcom and the sub-area array circuit common electrode trace SAcom are electrically isolated from each other.
  • the main-area array circuit common electrode trace MAcom in all the pixel regions 1 of the liquid crystal array is connected to a main-area conductive sheet MP 1 , and the sub-area array in all the pixel regions 1
  • the circuit common electrode traces SAcom are both connected to a sub-region conductive sheet SP1.
  • the first scan line 111 connected to the first TFT transistor T1 and the second TFT transistor T2 is used to generate an on or off signal to control the first TFT transistor T1 and the second TFT transistor T2 to be turned on or off.
  • the data line 222 is used to input a data driving signal when the first TFT transistor T1 and the second TFT transistor T2 are turned on, thereby controlling the display of the main area 11 and the sub-area 12, respectively.
  • the liquid crystal array substrate 100 further includes other components, such as a storage capacitor and a coupling capacitor, etc., which are not described herein because they are not related to the improvement of the present invention.
  • FIG. 3 is a schematic diagram of an electronic device 200 having a liquid crystal array inverse 100 according to the present invention.
  • the electricity The sub-device 200 includes the liquid crystal array substrate 100 and other necessary components.
  • the electronic device 200 can be a liquid crystal display, a liquid crystal television, or the like. Obviously, the electronic device 200 can also be any other electronic device having a liquid crystal display structure.
  • FIG. 4 is a flowchart of a test method for the liquid crystal array anti-100 of the present invention.
  • the first TFT transistor T2 and the second TFT transistor T2 which are input to the off signal control pixel region 1 through the first scanning line 111 are in the off/off state (S301).
  • first voltage is different from the second voltage, and in an embodiment, the first voltage To be high, the second voltage is zero potential, applying a first voltage to the main-region conductive sheet MP1 and applying a second voltage to the sub-region conductive sheet SP1 to: apply a high potential to the main-region conductive sheet MP1 and to the sub-region conductive sheet SP1
  • the first voltage is a zero potential
  • the second voltage is a high potential
  • a first voltage is applied to the main-region conductive sheet MP1
  • a second voltage is applied to the sub-region conductive sheet SP1:
  • the main-region conductive sheet MP1 applies a zero potential and applies a high potential to the sub-region conductive sheet SP1.
  • the liquid crystal array _3 ⁇ 4 ⁇ is 100-passed (S307).
  • the pixel region 1 in which the liquid crystal array substrate 100 is short-circuited is repaired (S311).
  • the main area array circuit common electrode trace MAcom and the sub-area array circuit common electrode trace SAcom are electrically isolated from each other, since the main area array electric common electrode trace MAcom is electrically connected to the main area 11,
  • the sub-area array circuit common electrode trace SAcom is electrically connected to the sub-area 12. Therefore, if there is no short circuit in the main region 11 and the sub-region 12, when the first voltage is applied to the main-region conductive sheet MP1 and the second voltage is applied to the sub-region conductive sheet SP1, the main region 11 and the sub-region 12 respectively have The first voltage and the second voltage are different in voltage. If there is a short circuit in the main zone 11 and the sub zone 12, the voltages of the main zone 11 and the sub zone 12 will be the same.
  • Whether or not the main area 11 and the sub-area 12 are short-circuited means whether there is a short circuit between the pixel electrode P connected to the first TFT transistor T1 of the main area 11 and the pixel electrode P connected to the second TFT transistor T2 of the sub-area 12.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Liquid Crystal (AREA)
  • Geometry (AREA)

Abstract

提供了一种液晶阵列基板（100）、电子装置（200）及液晶阵列基板（100）测试方法。液晶阵列基板（100）测试方法包括步骤：通过扫描线（111）输入关闭信号控制像素区域（1）的第一TFT晶体管（T1）以及第二TFT晶体管（T2）处于关闭状态（S301）；对主区导电片（MP1）施加第一电压以及对子区导电片（SP1）施加第二电压（S303）；其中主区导电片（MP1）与所有像素区域（1）的主区阵列电路公共电极走线（MAcom）电连接，子区导电片（SP1）与所有像素区域（1）的子区阵列电路公共电极走线（SAcom）电连接；侦测像素区域（1）的主区（11）以及子区（12）的电压是否相同（S305）；如果相同，则判定主区（11）以及子区（12）存在短路（S309）。该液晶阵列基板（100）及液晶阵列基板（100）测试方法，能够较易地检测出该液晶阵列基板（100）是否合格。

Description

液晶阵列基板、 电子装置及液晶阵列基板测试方法 技术领域
本发明涉及一种基板， 特别涉及一种液晶阵列基板、 具有该液晶阵列基板的 电子装置及液晶阵列基板测试方法。 背景技术
目前， 液晶电视、 液晶显示器等液晶电子装置越来越普遍。 一般的液晶电子 装置均具有多角度的显示模式， 在多角度的显示模式下， 由于在不同视角西观察 到的液晶分子的指向不同， 会导致大视角下观察到的颜色失真。 目前， 为了改善 大视角的颜色失身， 在液晶分子像素设计时， 会将一个像素分为两个部分， 一部 分为主（main ) 区， 另一部分为子（sub ) 区。 通过控制该两个区的电压来改善大 视角失真。 其中， 该分为主区以及子区的设计一般称为 LCS ( Low Color Shift, 低 色彩偏移） 设计。
相应地， 为了保证液晶电子装置的质量， 对其制造过程中的检测是必不可少 的。 为提高良率和降低成本， 在液晶阵列基板制造完成后， 会对其进行电性测试， 而对于有 LCS设计的像素， 常规手法 4艮难检测出主区以及子区的像素短路即不合 格， 而容易导致面板降等甚至报废。 发明内容
本发明提供一种液晶阵列基板、 电子装置及液晶阵列基板测试方法， 能够较 易地检测该液晶阵列 反是否合格。
一种液晶阵列基板， 包括多个像素区域， 该像素区域包括主区、 子区以及一 调控 TFT晶体管， 该调控 TFT晶体管用于调控主区与子区的电压比而实现低色彩 偏移， 其中， 主区包括第一 TFT晶体管以及主区阵列电^^共电极走线， 子区包 括第二 TFT晶体管以及子区阵列电^^共电极走线， 其中， 该主区阵列电路公共 电极走线以及子区阵列电^^共电极走线相互电隔离； 其中， 第一 TFT晶体管的 栅极与第一扫描线连接， 源极与数据线连接， 漏极与像素电极连接且与主区阵列 电^ ^共电极走线耦接， 第二 TFT晶体管的栅极与第一扫描线连接， 源极与数据 线连接， 漏极与像素电极连接且与子区阵列电路公共电极走线耦接； 该调控 TFT 晶体管的源极与该第二 TFT晶体管的漏极电连接， 漏极与第一 TFT晶体管的漏极 耦接， 该调控 TFT晶体管的栅极与第二扫描线连接； 该液晶阵列基板的所有像素 区域中的主区阵列电路公共电极走线均与一主区导电片连接， 所有像素区域中的 子区阵列电路公共电极走线均与一子区导电片连接。
其中， 该第一扫描线用于产生开启或关闭信号控制该第一 TFT晶体管导通或 关闭， 该数据线用于在第一 TFT晶体管导通时输入数据驱动信号， 而控制主区的 显示。
其中， 该第一扫描线用于产生开启或关闭信号控制该第二 TFT晶体管导通或 关闭， 该数据线用于在第二 TFT晶体管导通时输入数据驱动信号， 而控制子区的 显示。
一种电子装置， 包括一液晶阵列基板， 该液晶阵列基板包括多个像素区域， 该像素区域包括主区、 子区以及一调控 TFT晶体管， 该调控 TFT晶体管用于调控 主区与子区的电压比而实现低色彩偏移， 其中， 主区包括第一 TFT晶体管以及主 区阵列电^^共电极走线， 子区包括第二 TFT晶体管以及子区阵列电^^共电极 电隔离； 其中， 第一 TFT晶体管的栅极与第一扫描线连接， 源极与数据线连接， 漏极与像素电极连接且与主区阵列电路公共电极走线耦接， 第二 TFT晶体管的栅 极与第一扫描线连接， 源极与数据线连接， 漏极与像素电极连接且与子区阵列电 路公共电极走线耦接； 该调控 TFT晶体管的源极与该第二 TFT晶体管的漏极电连 接， 漏极与第一 TFT晶体管的漏极耦接， 该调控 TFT晶体管的栅极与第二扫描线 连接； 该液晶阵列 ^反的所有像素区域中的主区阵列电路公共电极走线均与一主 区导电片连接， 所有像素区域中的子区阵列电路公共电极走线均与一子区导电片 连接。
其中， 该第一扫描线用于产生开启或关闭信号控制该第一 TFT晶体管导通或 关闭， 该数据线用于在第一 TFT晶体管导通时输入数据驱动信号， 而控制主区的 显示。
其中， 该第一扫描线用于产生开启或关闭信号控制该第二 TFT晶体管导通或 关闭， 该数据线用于在第二 TFT晶体管导通时输入数据驱动信号， 而控制子区的 显示。
其中， 该电子装置为液晶显示器或液晶电视。
一种液晶阵列基板的测试方法， 包括步骤： 通过扫描线输入关闭信号控制像 素区域的第一 TFT晶体管以及第二 TFT晶体管处于关闭状态； 对主区导电片施加 第一电压以及对子区导电片施加第二电压； 其中， 该主区导电片与所有像素区域 的主区阵列电路公共电极走线电连接， 该子区导电片与所有像素区域的子区阵列 电路公共电极走线电连接， 其中该主区阵列电路公共电极走线与子区阵列电路公 共电极走线相互电隔离； 侦测像素区域的主区以及子区的电压是否相同； 如果有， 则判定主区以及子区存在短路。
其中， 该方法还包括步骤： 如果像素区域的主区以及子区的电压不相同， 则 判定主区以及子区不存在短路。
其中， 该步骤 "对主区导电片施加第一电压以及对子区导电片施加第二电压" 包括： 对主区导电片施加高电位以及对子区导电片施加零电位。
其中， 该步骤 "对主区导电片施加第一电压以及对子区导电片施加第二电压" 包括： 对主区导电片施加零电位以及对子区导电片施加高电位。
其中， 该方法还包括： 对液晶阵列基板存在短路的像素区域进行维修。
本发明的液晶阵列 反、 具有该液晶阵列基板的电子装置及液晶阵列基板测 试方法， 通过^ 1主
电隔离， 能够较易地检测出该液晶阵列 反是否合格。 附图说明
图 1是本发明一实施方式中的液晶阵列 ^反的示意图。
图 2是本发明一实施方式中的液晶阵列 ^反中的一个像素区域的具体示意图。 图 3是本发明一实施方式中具有液晶阵列 反的电子装置的示意图。
图 4是本发明一实施方式中的液晶阵列 ^反的检测方法的流程图。 具体实施方式
请一并参阅图 1及图 2,图 1为本发明一实施方式中液晶阵列 反 100的示意 图， 图 2为液晶阵列 ^反 100包括的一像素区域 1的具体示意图。 在本发明中，
3 该液晶阵列基板 100为低色偏设计的液晶阵列 ^反。 该液晶阵列 ^反 100包括多 个呈阵列分布的像素区域 1 , 该像素区域 1包括主区 11、 子区 12以及调控 TFT晶 体管 T。 其中， 主区 11包括第一 TFT ( thin film transistor, 薄膜晶体管） 晶体管 T1以及主区阵列电路公共电极走线 MAcom。子区包括第二 TFT晶体管 T2以及子 区阵列电路公共电极走线 SAcom。 其中， 该调控 TFT晶体管 T用于调控主区 11 与子区 12的电压比， 而实现液晶阵列 反 100的低色彩偏移设计。
其中，每一像素区域 1中的该第一 TFT晶体管 T1以及第二 TFT晶体管 T2的 栅极均与第一扫描线 111连接。该第一 TFT晶体管 T1以及第二 TFT晶体管 T2的 源极均与数据线 222连接。该第一 TFT晶体管 T1的漏极与主区阵列电^^共电极 走线 MAcom耦接， 该第二 TFT晶体管 T2的漏极与子区阵列电路公共电极走线 SAcom耦接。 其中， 该第一 TFT晶体管 T1的漏极还与对应的像素电极 P连接， 该第二 TFT晶体管 T2的漏极同样还与对应的像素电极 P电连接。
具体的， 该调控 TFT晶体管 T的源极与第一 TFT晶体管 T1的漏极耦接， 漏 极与该第二 TFT晶体管 T2的漏极电连接， 该调控 TFT晶体管 T的栅极与第二扫 描线 112连接。 该调控 TFT晶体管 T用于调控主区 11与子区 12的电压比， 即调 节第一 TFT晶体管 T1连接的像素电极 P以及该第二 TFT晶体管 T2连接的像素电 极 P之间的电压比， 实现低色彩偏移。 由于与本发明改进无关， 故不再多加描述。
其中，该主区阵列电路公共电极走线 MAcom以及子区阵列电路公共电极走线 SAcom相互电隔离。
其中， 如图 1所示， 该液晶阵列 ^反 100的所有像素区域 1中的主区阵列电 路公共电极走线 MAcom均与一主区导电片 MP 1连接， 所有像素区域 1中的子区 阵列电路公共电极走线 SAcom均与一子区导电片 SP1连接。
其中，与该第一 TFT晶体管 T1以及第二 TFT晶体管 T2连接的该第一扫描线 111用于产生开启或关闭信号控制该第一 TFT晶体管 T1以及第二 TFT晶体管 T2 导通或关闭。该数据线 222用于在第一 TFT晶体管 T1以及第二 TFT晶体管 T2导 通时输入数据驱动信号， 从而分别控制主区 11以及子区 12的显示。
其中， 该液晶阵列基板 100还包括其他元件， 例如存储电容以及耦合电容等， 由于与本发明的改进无关， 故未在此赘述。
请参阅图 3, 为本发明具有液晶阵列 反 100的电子装置 200的示意图。该电 子装置 200包括该液晶阵列基板 100以及其他必要元件。 其中， 该电子装置 200 可为液晶显示器、 液晶电视等。 显然， 该电子装置 200还可为其他任意具有液晶 显示结构的电子装置。
请一并参阅图 4, 为本发明的液晶阵列 反 100的测试方法的流程图。 首先， 通过第一扫描线 111输入关闭信号控制像素区域 1的第一 TFT晶体管 T2以及第二 TFT晶体管 T2处于关闭 /断开状态 (S301)。
然后， 对主区导电片 MP1施加第一电压以及对子区导电片 SP1施加第二电压 ( S303 )„ 其中， 该第一电压不同于该第二电压， 在一实施方式中， 该第一电压为 高电位， 第二电压为零电位， 对主区导电片 MP1施加第一电压以及对子区导电片 SP1施加第二电压为： 对主区导电片 MP1施加高电位以及对子区导电片 SP1施加 零电位。 在其他实施方式中， 该第一电压为零电位， 该第二电压为高电位， 对主 区导电片 MP1施加第一电压以及对子区导电片 SP1施加第二电压为： 对主区导电 片 MP1施加零电位以及对子区导电片 SP1施加高电位。
侦测像素区域 1的主区 11以及子区 12的电压是否相同 （ S305 )。
如果相同， 则判定主区 11以及子区 12不存在短路， 即， 该液晶阵列_¾^反100 合格 ( S307 )。
如果不相同， 则判定主区 11 以及子区 12存在短路， 即该液晶阵列基板 100 不合格 ( S309 )。 以及
对液晶阵列基板 100存在短路的像素区域 1进行维修 ( S311 )。
从而，本发明中，将该主区阵列电路公共电极走线 MAcom以及子区阵列电路 公共电极走线 SAcom相互电隔离， 由于主区阵列电^^共电极走线 MAcom与主 区 11电连接， 而子区阵列电路公共电极走线 SAcom又与子区 12电连接。 从而， 若主区 11以及子区 12不存在短路时， 当对主区导电片 MP1施加第一电压以及对 子区导电片 SP1施加第二电压， 则该主区 11 以及子区 12将分别具有该第一电压 以及第二电压而电压不相同。 如果主区 11以及子区 12存在短路， 主区 11以及子 区 12的电压将会相同。 其中， 该主区 11 以及子区 12是否存在短路是指： 主区 11的第一 TFT晶体管 T1连接的像素电极 P与子区 12的第二 TFT晶体管 T2连接 的像素电极 P是否存在短路。
以上具体实施方式对本发明进行了详细的说明， 但这些并非构成对本发明的 限制。 本发明的保护范围并不以上述实施方式为限， 但凡本领域普通技术人员根 据本发明所揭示内容所作的等效修饰或变化， 皆应纳入权利要求书中记载的保护 范围内。

Claims

权 利 要 求 书
1、 一种液晶阵列基板， 包括多个像素区域， 每一像素区域包括主区、 子区以及一 调控 TFT晶体管， 该调控 TFT晶体管用于调控主区与子区的电压比而实现低色彩 偏移， 其中：
主区包括第一 TFT 晶体管以及主区阵列电路公共电极走线， 子区包括第二 TFT 晶体管以及子区阵列电路公共电极走线， 其中， 该主区阵列电路公共电极走 线以及子区阵列电^ 共电极走线相互电隔离； 其中， 该第一 TFT晶体管的栅极 与第一扫描线连接， 源极与数据线连接， 漏极与像素电极连接且与主区阵列电路 公共电极走线耦接； 该第二 TFT晶体管的栅极与第一扫描线连接， 源极与数据线 连接， 漏极与像素电极连接且与子区阵列电路公共电极走线耦接； 该调控 TFT晶 体管的源极与该第二 TFT晶体管的漏极电连接， 漏极与第一 TFT晶体管的漏极耦 接， 该调控 TFT晶体管的栅极与第二扫描线连接； 该液晶阵列基板的所有像素区 域中的主区阵列电路公共电极走线均与一主区导电片连接， 该液晶阵列 反的所 有像素区域中的子区阵列电路公共电极走线均与一子区导电片连接。
2、 如权利要求 1所述的液晶阵列基板， 其中， 该第一扫描线用于产生开启或关闭 信号控制该第一 TFT晶体管导通或关闭， 该数据线用于在第一 TFT晶体管导通时 输入数据驱动信号， 而控制主区的显示。
3、 如权利要求 2所述的液晶阵列基板， 其中， 该第一扫描线还用于产生开启或关 闭信号控制该第二 TFT晶体管导通或关闭。
4、 如权利要求 3所述的液晶阵列基板， 其中， 该数据线还用于在第二 TFT晶体管 导通时输入数据驱动信号， 而控制子区的显示。
5、 一种电子装置， 包括一液晶阵列基板， 该液晶阵列基板包括多个像素区域， 每 一像素区域包括主区、 子区以及一调控 TFT晶体管， 该调控 TFT晶体管用于调控 主区与子区的电压比而实现低色彩偏移， 其中：
主区包括第一 TFT 晶体管以及主区阵列电路公共电极走线， 子区包括第二 TFT 晶体管以及子区阵列电路公共电极走线， 其中， 该主区阵列电路公共电极走 线以及子区阵列电^ 共电极走线相互电隔离； 其中， 该第一 TFT晶体管的栅极 与第一扫描线连接， 源极与数据线连接， 漏极与像素电极连接且与主区阵列电路 公共电极走线耦接； 该第二 TFT晶体管的栅极与第一扫描线连接， 源极与数据线 连接， 漏极与像素电极连接且与子区阵列电路公共电极走线耦接； 该调控 TFT晶 体管的源极与该第二 TFT晶体管的漏极电连接， 漏极与第一 TFT晶体管的漏极耦 接， 该调控 TFT晶体管的栅极与第二扫描线连接； 该液晶阵列基板的所有像素区 域中的主区阵列电路公共电极走线均与一主区导电片连接， 该液晶阵列 反的所 有像素区域中的子区阵列电路公共电极走线均与一子区导电片连接。
6、 如权利要求 5所述的电子装置， 其中， 该第一扫描线用于产生开启或关闭信号 控制该第一 TFT晶体管导通或关闭， 该数据线用于在第一 TFT晶体管导通时输入 数据驱动信号， 而控制主区的显示。
7、 如权利要求 6所述的电子装置， 其中， 该第一扫描线还用于产生开启或关闭信 号控制该第二 TFT晶体管导通或关闭。
8、 如权利要求 7所述的电子装置， 其中， 该数据线还用于在第二 TFT晶体管导通 时输入数据驱动信号， 而控制子区的显示。
9、 如权利要求 5所述的电子装置， 其中， 该电子装置为液晶显示器或液晶电视。
10、 一种液晶阵列基板的测试方法， 包括步骤：
通过扫描线输入关闭信号控制像素区域的第一 TFT晶体管以及第二 TFT晶体 管处于关闭状态；
对主区导电片施加第一电压以及对子区导电片施加第二电压； 其中， 该主区 导电片与所有像素区域的主区阵列电路公共电极走线电连接， 该子区导电片与所 有像素区域的子区阵列电路公共电极走线电连接， 其中该主区阵列电路公共电极 走线与子区阵列电路公共电极走线相互电隔离；
侦测像素区域的主区以及子区的电压是否相同；
如果相同， 则判定主区以及子区存在短路。
11、 如权利要求 10所述液晶阵列基板的测试方法， 其中， 还包括步骤：
如果像素区域的主区以及子区的电压不相同， 则判定主区以及子区不存在短 路。
12、 如权利要求 10所述液晶阵列 ^反的测试方法， 其中， 该步骤 "对主区导电片 施加第一电压以及对子区导电片施加第二电压" 包括：
对主区导电片施加高电位以及对子区导电片施加零电位。
13、 如权利要求 10所述液晶阵列 ^反的测试方法， 其中， 该步骤 "对主区导电片 施加第一电压以及对子区导电片施加第二电压" 包括： 对主区导电片施加零电位以及对子区导电片施加高电位。
、 如权利要求 10所述液晶阵列基板的测试方法， 其中， 该方法还包括： 对液晶阵列基板存在短路的像素区域进行维修。
PCT/CN2013/078535 2013-06-19 2013-06-30 液晶阵列基板、电子装置及液晶阵列基板测试方法 WO2014201723A1 (zh)

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