WO2014196180A1 - デジタルフィルタ装置及び信号処理方法 - Google Patents
デジタルフィルタ装置及び信号処理方法 Download PDFInfo
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- WO2014196180A1 WO2014196180A1 PCT/JP2014/002899 JP2014002899W WO2014196180A1 WO 2014196180 A1 WO2014196180 A1 WO 2014196180A1 JP 2014002899 W JP2014002899 W JP 2014002899W WO 2014196180 A1 WO2014196180 A1 WO 2014196180A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0248—Filters characterised by a particular frequency response or filtering method
- H03H17/0261—Non linear filters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/04—Recursive filters
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- the present invention relates to a digital filter device and a signal processing method of the digital filter, and more particularly to a digital filter used in an optical digital coherent transceiver.
- Non-linear distortion which is distortion occurring in a communication channel, arises mainly from the fact that polarization is not proportional to the electric field of light when the light intensity is high.
- Non-linear distortion includes self-phase modulation in which the phase changes according to the intensity of its own light, cross-phase modulation in which the phase changes with another light by wavelength division multiplexing, and two or more lights interact to generate new light There are four wave mixing etc.
- the digital signal processing unit can operate only at about several GHz (Gbps: Gigabits per second, GHz: Gigahertz). That is, optical communication is about 100 times faster than digital signal processing. In order to fill in the speed difference between optical communication and digital signal processing, it is necessary to arrange circuits that perform the same digital signal processing by the number of input signals arranged in parallel.
- FIG. 11 An example of a general FIR filter 110 is shown in FIG. 11 (FIR: Finite Impulse Response).
- the FIR filter 110 of FIG. 11 includes a delay group 111, a multiplier group 113, and an adder group 115.
- the delay unit group 111 includes a plurality of delay units (111-1, 111-2, 111-3,..., 111-N-1) (N is a natural number of 2 or more).
- the multiplier group 113 includes a plurality of multipliers (113-1, 113-2, ..., 113-N-1, 113-N).
- the adder group 115 includes a plurality of adders (115-1, 115-2,..., 115-N-2, 115-N-1).
- the circuit scale of the digital filter becomes several hundreds mega meters.
- FIG. 12 shows an example of a general IIR filter 120 (IIR: Infinite Impulse Response).
- the IIR filter 120 of FIG. 12 includes a delay group 121, a first multiplier group 123, a second multiplier group 124, a first adder group 125, and a second adder group 126; Composed of The delay unit group 121 includes a plurality of delay units (121-1, 121-2, ..., 121-N).
- the first multiplier group 123 includes a plurality of multipliers (123-1,..., 123-N-1, 123-N).
- the second multiplier group 124 includes a plurality of multipliers (124-1, 124-2, ..., 124-N, 124-N + 1).
- the first adder group 125 includes a plurality of adders (125-1, 125-2,..., 125-N).
- the second adder group 126 includes a plurality of adders (126-1, 126-2,..., 126-N).
- the IIR filter 120 shown in FIG. 12 it is possible to realize a filter with good amplitude characteristics with a smaller number of multipliers than the FIR filter.
- FIG. 13 shows a configuration example in which an IIR filter in which only a [1] is nonzero and all other than a [1] is 0 is realized by a system in which two signals are input in parallel.
- the IIR filter 130 of FIG. 13 includes adders 131 and 133, multipliers 132 and 134, and a delay unit 135.
- Back Propagation back propagation method
- Non-Patent Document 1 a method of compensating only self-phase modulation as in Non-Patent Document 1
- Non-patent Document 2 a method of compensating not only self-phase modulation but also cross-phase modulation of another polarization as in Non-patent Document 2.
- the IIR filter 120 as shown in FIG. 12 has a feedback type configuration, it is difficult to realize a filter to which signals are input in parallel.
- path critical paths 136 (dotted line) having the largest delay amount among LSIs are divided into two parallel components. And can not operate at high speed. That is, although an LSI processing optical communication exceeding 100 Gbps is required to operate at high speed because of the amount of signal processing, there is a problem that it can not be achieved in the case of an IIR filter.
- the tap length of the digital filter depends on various parameters such as the length of the communication path, the light intensity, and the type of fiber.
- the back propagation method shown in Non-Patent Documents 1 and 2 is effective in a long distance transmission optical communication system, its tap length becomes several hundred taps, and the circuit scale of LSI also becomes large. There is a problem.
- the present invention is intended to solve the above-mentioned problems, and it becomes possible to reduce the circuit scale without impairing the performance of the digital filter used in the nonlinear compensation, and realize the nonlinear compensation by LSI. To provide a digital filter device.
- the digital filter device performs data reordering means for executing reordering of input data to output reordered data, and intermediate data calculating means for processing the reordered data inputted at a specific time to generate intermediate data And filter output first calculating means for calculating a first output value at a specific time using intermediate data, delay means for delaying the rearranged data by the processing time in the intermediate data calculating means and the file output first calculating means, and The output value from the delay means and the first filter output calculation means, the second output value at a time other than a specific time is calculated, and the filter output value obtained by combining the first and second output values is output Filter output second calculation means.
- the input data is rearranged to output rearranged data
- the rearranged data input at a specific time is processed to generate intermediate data
- the intermediate data is used to specify the specific time.
- the present invention it is possible to obtain a digital filter device which can reduce the circuit scale without losing the performance of the digital filter used in the non-linear compensation, and realize the non-linear compensation in an LSI.
- the digital filter device 1 includes data rearrangement means 11, intermediate data calculation means 12, filter output first calculation means 13, and filter output second calculation means 14 and delay means 15.
- the data sorting means 11 sorts input data. In addition, the thing of the rearranged input data is called rearrangement data.
- the data rearrangement unit 11 outputs the rearranged data to the intermediate data calculation unit 12 and the delay unit 15.
- the data rearranging means 11 rearranges data aligned in the row direction so as to align in the column direction when a data group in which one frame is configured by L columns ⁇ M rows is input as input data, The input data is converted into data groups of L columns ⁇ M rows different in data arrangement. Further, the data rearranging means 11 may rearrange so that the head direction of the rearranging data is directed to the end direction when a data group in which one frame is configured by L columns ⁇ M rows is input.
- the data rearranging means 11 may generate rearranging data in which the number of rows is changed in accordance with the number of rearranging circuits that the data rearranging means 11 itself has.
- the rearrangement circuits can be efficiently used.
- the data sorting method by the data sorting means 11 is not limited to the example described here, and the data may be sorted so as to be an arrangement of data that can be easily calculated and processed in the components of the subsequent stage. At least the data rearranging means 11 may rearrange the data in such an arrangement that the intermediate data calculating means 12 can easily calculate the intermediate data.
- the impulse response h [n] of the data of data number n is nonzero in a specific time range and 0 in other time ranges (n: integer).
- the length of the impulse response h [n] is the above-described specific range.
- the impulse response h [n] may be non-zero in a non-continuous range. That is, times at which the impulse response h [n] is nonzero may be discrete.
- the filter output y [n] can be expressed by a difference equation in which the input signal is x [n]. Also, the difference equation can be expressed in the form of a recurrence equation using filter outputs and input signals before and after a specific time. Note that the recurrence formula may be an approximation formula as needed so that the configuration of the delay means 15 does not have to be large.
- the intermediate data calculation means 12 calculates intermediate data divided into specific numerical values for data to be simultaneously processed at a specific time.
- the specific time is a time included in the time when the impulse response becomes nonzero.
- the division of the intermediate data may be set to the same number of rows of the rearranged data input to the intermediate data calculation means 12.
- the intermediate processing data calculation means 12 will process M pieces of data out of the input data.
- the intermediate data calculation means 12 calculates partial values of the digital filter device 1. For example, the intermediate data calculation unit 12 calculates intermediate data for calculating the output value of the digital filter device 1 only for data of a specific time included in the time when the impulse response is nonzero. The intermediate data calculation means 12 outputs the calculated intermediate data to the filter output first calculation means 13.
- the filter output first calculator 13 uses the intermediate data calculated by the intermediate data calculator 12 to calculate an output value (first output value) of the digital filter device 1 at a specific time.
- the filter output first calculating unit 13 outputs the output value of the digital filter device 1 for the M-piece data input to the intermediate data calculating unit 12 at a specific time. Will be calculated.
- the delay means 15 delays the input data by the time when the intermediate data calculation means 12 calculates intermediate data and the filter output first calculation means 13 calculates the first output value, and the filter output second calculation means 14 Supply necessary input data at appropriate timing.
- the delay time by the delay means 15 is determined by the circuit length and processing performance of the intermediate data calculation means 12 and the calculation order of the filter output second calculation means 14 and the like.
- the filter output second calculation means 14 receives the rearranged data delayed by the delay means 15 and the output value of the digital filter device 1 calculated by the filter output first calculation means 13.
- the filter output second calculation means 14 calculates the output value of the digital filter device 1 using the recurrence formula obtained from the difference equation for the data of the time not processed by the filter output first calculation means 13. For example, if an output value at a specific time and an output value at a time other than the specific time are set in the form of a recurrence formula, an output value at a time other than the specific time (second Output value of) can be calculated.
- the filter output second calculation means 14 combines the output value at a specific time (first output value) and the output value at a time other than the specific time (second output value) and outputs it as a filter output.
- the input data is rearranged by the data rearrangement unit, and the data is distributed to the intermediate data calculation unit and the delay unit.
- the intermediate data calculation means converts the data input at a specific time into intermediate data
- the filter output first calculation means calculates the filter output using the intermediate data.
- the filter output second output means calculates the filter output calculated using the data input at a time other than the specific time and the intermediate data by the recurrence formula, and outputs the filter output. Therefore, according to the digital filter device according to the present embodiment, it is possible to obtain the filter output with less calculation processing compared to a general digital filter device, and it is possible to reduce the circuit scale.
- the circuit scale can be reduced without losing the performance of the digital filter used in the non-linear compensation, and a digital filter that can realize the non-linear compensation in an LSI can be obtained.
- the digital filter device it is possible to compensate, among distortions generated in the communication path, non-linear distortion which could not be compensated by the LSI.
- a signal processing method by the digital filter device according to the embodiment of the present invention and a program using the signal processing method are also included in the scope of the present invention.
- the configuration of the digital filter device according to the first embodiment is the configuration of the digital filter device 1 shown in FIG.
- a data group in which one frame is composed of L columns ⁇ M rows is input, it is described as a concrete numerical value such as 32 columns as L column and 128 rows as M row. Do.
- the data sorting means 11 sorts the input data 21 input in parallel as shown in FIG. 2 into the sort data 31 of the arrangement as shown in FIG.
- the numbers shown above the input data 21 represent time. At a certain time, data in the same column in the input data 21 is input to the data sorting means 11.
- ADC Analog Digital Converter
- the data input to the digital filter device according to the embodiment of the present invention may be input in parallel with data other than 128, and the numerical range is not limited.
- 0 represents the 0th data, 1 the 1st data,..., 4095 the 4095th data.
- the data input at time 1 is the 0th, 1st,..., 126, 127th data
- the data input at time 2 is 128, 129, 130,. ⁇ ⁇ ⁇ 254, 255th data.
- the number of rows and the number of columns of the frame are not changed.
- the data rearranging means 11 is a 128-jump array such as 0, 128, 256,... Like the input data 21 in FIG. 2 as 0 in the rearrange data 31 of FIG. Rearrange the order of the original data such as 1, 2, .... On the other hand, at time 1, data of an array of 0, 32, 64, ... and 32 jumps are output in parallel. That is, the data rearrangement unit 11 according to the present embodiment converts the input data 21 arranged in the column direction into the rearranged data 31 rearranged in the row direction and outputs the rearranged data 31.
- a linear compensation unit and a non-linear compensation unit are alternately processed.
- the linear compensation unit is generally processed in the frequency domain, it is configured as FFT, multiplication processing, IFFT (FFT: Fast Fourier Transform, IFFT: Inverse Fast Fourier Transform).
- the digital filter device in the non-linear compensation unit does not need the data rearrangement means 11. That is, in the back propagation method as in Non-Patent Document 1, the output of IFFT can be used as it is.
- Equation 1 the impulse response h [n] of the digital filter device is as shown in Equation 1.
- the filter output y [n] can be expressed by the difference equation as shown in Equation 2 when the input signal is x [n].
- k in Formula 2 is an integer.
- Equation 3 the value of the input signal may be substituted for x [n] and x [n-256] as it is, and the already obtained filter output may be substituted for y [n-1].
- the first output value is substituted into y [n-1] to calculate the second output value y [n].
- the next second output value is obtained. be able to. Therefore, by using the recurrence formula of Equation 3, for the data input at times other than the specific time, the second output value is gradually obtained using the first output value of the data input at the specific time. It can be calculated.
- an intermediate variable T [n] is defined as Expression 5 as intermediate data.
- y [n] can be expressed as Expression 6 using the intermediate variable T [n].
- the output value at n-32 may be y [n-32]
- the output value at n-64 may be y [n-64].
- the intermediate data calculation means 12 calculates the intermediate variable T [n] shown in Expression 5.
- the intermediate data calculation means 12 can be realized, for example, as a circuit 40 configured to include an adder 41 and a delay unit 42 as shown in FIG.
- the filter output first calculating means 13 uses the equation 6 to calculate the filter output value (first output value) y [n], y [n-32],.
- Calculate The filter output second calculating means 14 can be realized by a circuit 50 including a subtractor 51, an adder 52, and a delay device 53 as shown in FIG.
- the filter output second calculation means 14 receives the output data (first output value and rearrange data) of the filter output first calculation means 13 and the delay means 15.
- the filter output second calculation means 14 applies the recurrence formula of Equation 3 to the input data of the filter output first calculation means 13 and the delay means 15 and applies the filter at a time other than the specific time included in the range of the impulse response
- the output value (second output value) y [n] is calculated. That is, the filter output second calculation means 14 calculates y [n-1], y [n-2], ..., y [n-31], y [n-33], ....
- Equation 7 is an equation of impulse response, and corresponds to Equation 1.
- Equation 8 is a difference equation, which corresponds to Equation 2.
- the equation 9 is an equation for calculating intermediate data, and corresponds to the equation 5.
- Expression 10 is an expression for calculating an output value (first output value) at a specific time, and corresponds to expression 6.
- Formula 11 is a recurrence formula for calculating an output value (second output value) at a time other than the specific time, and corresponds to Formula 3.
- Equations 7 to 11 it is possible to calculate the filter output value from the rearranged data having a frame of L columns ⁇ M rows.
- the circuit scale can be reduced as compared with a general digital filter device.
- the first reason is that when calculating discrete filter output values at specific times, they are obtained by sharing necessary operations.
- the second reason is that the filter output value at a time other than the specific time is obtained by the recurrence formula using the discrete file output value obtained in the previous cycle.
- the digital filter device according to the first embodiment of the present invention, it is possible to compensate, among distortions generated in the communication path, non-linear distortion which could not be compensated by the LSI.
- the digital filter device can solve the above-mentioned problem that the installation cost is increased, and can implement non-linear compensation that does not impair the performance of the digital filter device.
- the present invention is not limited to the configuration of the digital filter device in non-linear compensation and the filter device in non-linear compensation, and can be used for digital filter devices in general, and further signal processing devices including digital filter devices. is there.
- a digital filter device according to a second embodiment of the present invention will be described.
- the configuration of the digital filter device according to the second embodiment is the same as that of the digital filter device according to the first embodiment shown in FIG.
- specific numerical values are described such as 32 columns as L columns and 128 rows as M rows. Do.
- the second embodiment is an example of the case where the impulse response h [n] of the digital filter device can be expressed by equation 12.
- a is a real number greater than 0 and less than 1 (a: real number: 0 ⁇ a ⁇ 1).
- the operations of the data rearrangement means 11 and the delay means 15 are the same as in the first embodiment.
- the filter output y [n] can be expressed in the form of a difference equation as shown in Equation 13 when the input signal is x [n].
- each term of the right side of Expression 15 is defined as Expression 16 as an intermediate variable T [n] which is intermediate data.
- y [n] can be expressed as Expression 17 using the intermediate variable T [n].
- the intermediate data calculation means 12 calculates the intermediate variable T [n] shown in Equation 16.
- the intermediate data calculation means 12 is realized by a circuit 60 including an adder 61, a delay device 62, and a multiplier 63 as shown in FIG.
- the filter output first calculation means 13 uses the equation 17 to calculate the filter output value (first output value) y [n], y [n-32],.
- the filter output second calculation means 14 is realized by a circuit 70 including a subtractor 71, a multiplier 72, an adder 73, a multiplier 74, and a delay device 75 as shown in FIG. .
- the filter output second calculation means 14 receives the output data (first output value and rearrange data) of the filter output first calculation means 13 and the delay means 15.
- the filter output second calculation means 14 applies the recurrence formula of the equation 14 to the input data of the filter output first calculation means 13 and the delay means 15, and the filter output value (second output) at a time other than a specific time Value) Calculate y [n].
- Equations 18 to 22 may be used.
- N is a natural number.
- Expression 18 is an expression of impulse response, and corresponds to expression 12.
- Equation 19 is a difference equation and corresponds to equation 15.
- Expression 20 is an expression for calculating intermediate data, and corresponds to expression 16.
- Expression 21 is an expression for calculating an output value (first output value) at a specific time, and corresponds to expression 17.
- Expression 22 is a recurrence expression for calculating an output value (second output value) at a time other than the specific time, and corresponds to Expression 14.
- the filter output value can be calculated from rearranged data having a frame of L columns ⁇ M rows by using the above-described equations (Equations 18 to 22).
- a memory for realizing the delay means 15 is separately required, but generally, the number of memories for realizing the delay means 15 exceeds the multiplier reduction amount. Absent.
- the circuit scale is reduced as compared with a general digital filter device. Can.
- the impulse response is limited to the one as shown in Equation 1, but according to the digital filter device according to the second embodiment, it is as shown in Equation 7. Calculations can also be performed on the impulse response.
- a digital filter device according to a third embodiment of the present invention will be described.
- the configuration of the digital filter device according to the third embodiment is the same as that of the digital filter device according to the first embodiment shown in FIG.
- specific numerical values are described such as 32 columns as L columns and 128 rows as M rows. Do.
- the third embodiment is an example where the impulse response h [n] of the digital filter device can be expressed by equation 23.
- a is a real number greater than 0 and less than 1 (a: real number: 0 ⁇ a ⁇ 1).
- the data rearranging means 11 outputs the rearranging data 91 shown in FIG. 9 in addition to the rearranging data 31 shown in FIG.
- the sort data 91 is data in which the input order of the sort data 31 is reversed.
- the operation of the delay means 15 is similar to that of the first embodiment, and only delays input data.
- the filter output y [n] can be expressed by the difference equation as shown in Expression 24 when the input signal is x [n].
- Expression 26 It can be expressed as a recurrence formula like the upper row of.
- the lower part of Expression 26 is an expression in which a ⁇ B [n ⁇ 1] is transposed from the left side to the right side in the upper-stage recurrence expression. In practice, the lower-stage recurrence formula of Equation 26 is used.
- Equation 25 since the 255th power of a is almost 0, the approximate expression which deleted the term of the 255th power of a is used. Also in Equation 26, similarly, an approximate expression in which the term of the 256th power of a is deleted is shown. Note that this approximation does not necessarily have to be performed, but if the approximation is not used in Equation 25, x [n + 255] is required when calculating y [n], and another delay means is used because 255 is not a multiple of 32. It will be necessary. Therefore, it is preferable to approximate as shown in Equation 25 and Equation 26.
- an intermediate variable S [n] is defined as Expression 28 as intermediate data.
- a [n] can be expressed using the intermediate variable S [n] as shown in equation 29.
- an intermediate variable T [n] is defined as Expression 31 as intermediate data.
- Equation 32 B [n] can be expressed using the intermediate variable T [n] as shown in Equation 32.
- the intermediate data calculation means 12 calculates intermediate variables S [n] and T [n] as shown in Equation 28 and Equation 31.
- the intermediate data calculation means 12 can be realized by using two circuits 60 of FIG. 6, and can calculate S [n] and T [n]. T [n] is calculated using the reordering data 31, and S [n] is calculated using the reordering data 91.
- the filter output first calculation means 13 uses the equations 29 and 32 to calculate the filter output value (first output value) y [n], y at a specific time from the intermediate variables S [n], T [n]. [N-32] can be calculated as it is.
- the filter output second calculation means 14 receives the filter output first calculation means 13 and the output data (first output value and rearranged data) of the delay means 15, and specifies using Equation 25 and Equation 26.
- the filter output second calculating unit 14 includes a subtractor 81, a multiplier 82, a delay 83, an adder 84, a multiplier 85, a delay 86, and an adder 87.
- a circuit 80 comprising
- Equations 33 to 43 may be used.
- N is a natural number.
- Equation 33 is an equation of impulse response and corresponds to equation 23.
- Equation 34 is a difference equation and corresponds to equation 24.
- the first term of the right side of equation 34 is A [n] as in equation 35, and the second term is B [n] as in equation 36.
- Equations 37 and 38 are equations for calculating the first intermediate data S [n] and the second intermediate data T [n], and correspond to the equations 28 and 31, respectively.
- Formula 39 and Formula 40 are formulas for calculating A [n] and B [n], and correspond to Formula 29 and Formula 31.
- Formula 41 is a formula for calculating an output value (first output value) at a specific time.
- Formula 42 and Formula 43 are recurrence formulas for calculating an output value (second output value) at a time other than a specific time, and are the same formulas as the lower formula of Formula 25 and Formula 26.
- Equations 33 to 43 it is possible to calculate the filter output value from the rearranged data having a frame of L columns ⁇ M rows.
- the impulse response shown in equation 13 when the impulse response shown in equation 13 is realized by an FIR digital filter device, it comprises N / 2 multipliers, 2N-1 adders, and N-1 delayers.
- N is an odd number
- the number of multipliers is N / 2 + 0.5.
- the number of memories for realizing the delay means 15 exceeds the multiplier reduction amount. There is no.
- the length of the impulse response is set to 256 and the length of one frame is set to 4096 as a result of emphasizing ease of understanding. Therefore, the length of the impulse response and the length of one frame can be changed as needed, and the scope of the present invention is not limited to the above-mentioned numerical values.
- a digital filter device according to a fourth embodiment of the present invention will be described.
- the configuration of the digital filter device according to the fourth embodiment is the same as that of the digital filter device according to the third embodiment, and the same as the third embodiment except for the operation of the filter output second calculation means and the delay means. It is.
- the filter output y [n] can be expressed by the difference equation as shown in Equation 24 shown in the third embodiment, where x [n] is an input signal.
- Equation 44 since the 255th power of a is almost 0, an approximate expression in which the term of the 255th power of a is deleted is used. Although this approximation does not necessarily have to be performed, if the approximation is not used in Equation 44, x [n + 255] is required when calculating y [n], and another delay means is required because 255 is not a multiple of 32. It will Therefore, it is preferable to approximate as shown in equation 44 and equation 26.
- the filter output second calculation unit 14 receives the output data of the filter output first calculation unit 13 and the delay unit 15, and uses Equations 44 and 26, the filter output value at a time other than a specific time Output value of 2) y [n] is calculated.
- X [30] is required to calculate + x [30]. That is, when calculating A [31], A [30], A [29],..., Data in reverse order such as x [32], x [31], x [30],.
- a term in which n is large is required.
- the delay means 15 delays the reordering data 91 shown in FIG. 9 as well as the reordering data 31 shown in FIG. Solve the problem.
- the filter output second calculating means 14 is realized by the circuit 100 including the first delay adjusting means 101 for adjusting the timing thereof and the second delay adjusting means 102 (FIG. 10).
- the circuit 100 of FIG. 10 is the same as the circuit 80 except that the multiplier 82 in the circuit 80 of FIG. 8 is replaced with the multiplier 103 and the first delay adjusting means 101 and the second delay adjusting means 102 are added. It is.
- the first output value and the second output value are calculated by the same calculation as that of the third embodiment except that Expression 26 is Expression 44. That is, in order to apply the fourth embodiment to rearranged data having L columns ⁇ M rows of frames, in the equations 33 to 43 shown in the third embodiment, the equation 43 is changed to the equation below the equation 44 All you have to do is replace it.
- the timings of calculating A [n] and B [n] are adjusted by the first delay adjusting means 101 and the second delay adjusting means 102.
- the circuit scale can be reduced to about 1/14 as in the third embodiment. Furthermore, when the number of loops is large, the filter output can be calculated more accurately than in the third embodiment.
- the first delay adjustment means 101, the second delay adjustment means 102, etc. are required separately, they generally do not exceed the multiplier reduction amount.
- the length of the impulse response is set to 256 and the length of one frame is set to 4096 as a result of emphasizing ease of understanding. Therefore, the length of the impulse response and the length of one frame can be changed as needed, and the scope of the present invention is not limited to the above-mentioned numerical values.
- the digital filter device according to the embodiment of the present invention can be applied to non-linear compensation of optical digital coherent communication. Further, the technology relating to the digital filter device according to the embodiment of the present invention can be applied to any system that uses the digital filter device, such as audio processing, image processing, wireless communication, and the like.
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Abstract
Description
まず、本発明の第1の実施形態に係るデジタルフィルタ装置について説明する。なお、第1の実施形態に係るデジタルフィルタ装置の構成は、図1に示したデジタルフィルタ装置1の構成をとる。なお、第1の実施形態においては、1フレームがL列×M行のデータからなるデータ群を入力する例において、L列として32列、M行として128行というように具体的な数値として説明する。
次に、本発明の第2の実施形態に係るデジタルフィルタ装置について説明する。なお、第2の実施形態に係るデジタルフィルタ装置の構成は、図1に示した第1の実施形態に係るデジタルフィルタ装置と同じである。なお、第2の実施形態においても、1フレームがL列×M行のデータからなるデータ群を入力する例において、L列として32列、M行として128行というように具体的な数値として説明する。
次に、本発明の第3の実施形態に係るデジタルフィルタ装置について説明する。なお、第3の実施形態に係るデジタルフィルタ装置の構成は、図1に示した第1の実施形態に係るデジタルフィルタ装置と同じである。なお、第3の実施形態においても、1フレームがL列×M行のデータからなるデータ群を入力する例において、L列として32列、M行として128行というように具体的な数値として説明する。
次に、本発明の第4の実施形態に係るデジタルフィルタ装置について説明する。なお、第4の実施形態に係るデジタルフィルタ装置の構成は第3の実施形態に係るデジタルフィルタ装置と同じであり、フィルタ出力第二計算手段及び遅延手段の動作以外は第3の実施形態と同じである。
11 データ並替手段
12 中間データ計算手段
13 フィルタ出力第一計算手段
14 フィルタ出力第二計算手段
15 遅延手段
21 入力データ
31、91 並替データ
40、50、60、70、80、100 回路
41、52、61、73、84、87 加算器
42、53、62、75、83、86 遅延器
51、71、81 減算器
63、72、74、82、85、103 乗算器
101 第一遅延調整手段
102 第二遅延調整手段
110 FIRフィルタ
111 遅延器群
113 乗算器群
115 加算器群
120、130 IIRフィルタ
121 遅延器群
123 第1の乗算器群
124 第2の乗算器群
125 第1の加算器群
126 第2の加算器群
131 加算器
132 乗算器
135 遅延器
Claims (10)
- 入力データの並び替えを実行して並替データを出力するデータ並替手段と、
特定時刻に入力した前記並替データを処理して中間データを生成する中間データ計算手段と、
前記中間データを用いて前記特定時刻における第1の出力値を計算するフィルタ出力第一計算手段と、
前記中間データ計算手段及び前記ファイル出力第一計算手段における処理時間だけ前記並替データを遅延させる遅延手段と、
前記遅延手段及び前記フィルタ出力第一計算手段からの出力値を入力し、前記特定時刻以外の時刻における第2の出力値を計算し、前記第1及び第2の出力値を合わせたフィルタ出力値を出力するフィルタ出力第二計算手段と、を備えることを特徴とするデジタルフィルタ装置。 - 前記データ並替手段は、
複数のデータを格子状にまとめたフレームを構成する前記入力データの異なる行にある前記データのうち同じ列にある前記データを同時刻に入力し、
前記入力データの行及び列の数を変更せずに前記フレームを構成する前記入力データの列と行を入れ替える並び替え処理を実行し、
前記中間データ計算手段は、
前記特定時刻において、前記並替データの同じ列の異なる行にある複数の前記データを用いて前記中間データを計算することを特徴とする請求項1に記載のデジタルフィルタ装置。 - 前記データ並替手段は、
複数のデータを格子状にまとめたフレームを構成する前記入力データの異なる行にある前記データのうち同じ列にある前記データを同時刻に入力し、
前記データ並替手段が有する並替回路の数に合わせるように前記入力データの行の数を変更し、
前記フレームを構成する前記入力データの列と行を入れ替える並び替え処理を実行し、
前記中間データ計算手段は、
前記特定時刻において、前記並替データの同じ列の異なる行にある複数の前記データを用いて前記中間データを計算することを特徴とする請求項1に記載のデジタルフィルタ装置。 - 前記フィルタ出力第一計算手段は、
入力信号を変数とする差分方程式を用いて前記第1の出力値を計算し、
前記フィルタ出力第二計算手段は、
前記差分方程式から導出される漸化式を用いて前記第2の出力値を計算することを特徴とする請求項1乃至3のいずれか一項に記載のデジタルフィルタ装置。 - 入力データの並び替えを実行して並替データを出力し、
特定時刻に入力した前記並替データを処理して中間データを生成し、
前記中間データを用いて前記特定時刻における第1の出力値を計算し、
前記中間データ及び前記第1の出力値を算出する処理時間だけ前記並替データを遅延させ、
遅延させた前記並べ替えデータ及び前記第1の出力値を入力し、前記特定時刻以外の時刻における第2の出力値を計算し、前記第1及び第2の出力値を合わせたフィルタ出力値を出力することを特徴とする信号処理方法。
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