WO2014188945A1 - Manufacturing method for wiring board - Google Patents

Manufacturing method for wiring board Download PDF

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Publication number
WO2014188945A1
WO2014188945A1 PCT/JP2014/062928 JP2014062928W WO2014188945A1 WO 2014188945 A1 WO2014188945 A1 WO 2014188945A1 JP 2014062928 W JP2014062928 W JP 2014062928W WO 2014188945 A1 WO2014188945 A1 WO 2014188945A1
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WO
WIPO (PCT)
Prior art keywords
solder resist
resist layer
exposed
thickness
connection pad
Prior art date
Application number
PCT/JP2014/062928
Other languages
French (fr)
Japanese (ja)
Inventor
豊田 裕二
寛彦 後閑
川合 宣行
中川 邦弘
Original Assignee
三菱製紙株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱製紙株式会社 filed Critical 三菱製紙株式会社
Priority to KR1020157030969A priority Critical patent/KR102076479B1/en
Priority to CN201480029187.6A priority patent/CN105210460B/en
Publication of WO2014188945A1 publication Critical patent/WO2014188945A1/en

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/288Removal of non-metallic coatings, e.g. for repairing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845Stepped hole, via, edge, bump or conductor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01Tools for processing; Objects used during processing
    • H05K2203/0104Tools for processing; Objects used during processing for patterning or coating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05Patterning and lithography; Masks; Details of resist
    • H05K2203/0502Patterning and lithography

Definitions

  • the present invention relates to a method for manufacturing a wiring board, and more particularly to a method for manufacturing a wiring board having a plurality of connection pads for connecting electronic components such as a semiconductor chip and other printed wiring boards.
  • a wiring board inside various electric devices has a circuit board having an insulating layer and a conductor wiring formed on the surface of the insulating layer on one or both surfaces thereof. Also, a solder resist layer is formed on the entire surface of the circuit board of the wiring board so that the solder does not adhere to the conductor wiring that does not require soldering.
  • the solder resist layer plays a role of preventing the conductor wiring from being oxidized, electrically insulating, and protecting from the external environment.
  • connection pads are formed on the surface of the wiring board for connecting to electronic components such as semiconductor chips and other printed wiring boards.
  • the connection pad is produced by exposing the whole or part of the conductor wiring on the surface of the circuit board from the solder resist layer.
  • the density of the connection pads has been increased, and the pitch between the connection pads to be arranged is narrow, for example, there is a narrow pitch of 50 ⁇ m or less.
  • connection pad for connecting an electronic component provided on the wiring board is exposed corresponding to the arrangement of the electrode terminals of the electronic component, and the exposed part of the connection pad for connecting the electronic component and the electronic component are connected. It means that the electrode terminals are opposed to each other and electrically connected via solder bumps.
  • connection pad the solder resist layer is partially removed to expose the whole or part of the connection pad surface, and the solder mask layer is partially removed to remove the connection pad.
  • NSMD Non Solder Mask Defined
  • FIG. 1A is a schematic cross-sectional view showing an example of a wiring board having an SMD structure.
  • a solder resist layer 2 is formed on the surface of the circuit board 1 provided with the conductor wiring 7 and the connection pads 3 which are part of the conductor wiring on the surface of the insulating layer 8.
  • the periphery of the connection pad 3 is covered with the solder resist layer 2. Therefore, there is an advantage that peeling of the connection pad 3 due to mechanical impact and disconnection of the neck portion in the lead-out wiring from the connection pad 3 are unlikely to occur.
  • FIG. 1B is a schematic cross-sectional view showing an example of a wiring board having an NSMD structure.
  • a solder resist layer 2 is formed on the surface of the circuit board 1 provided with the conductor wiring 7 and the connection pads 3 which are part of the conductor wiring on the surface of the insulating layer 8.
  • a plurality of connection pads 3 are arranged in the same opening of the solder resist layer 2, and these connection pads 3 are exposed from the solder resist layer 2.
  • the solder resist layer 2 in the vicinity of the connection pad 3 is completely removed, and the side surface of the connection pad 3 is completely exposed. Therefore, the bonding strength between the connection pad 3 and the solder can be ensured even with a small connection pad 3 as compared with the SMD structure.
  • connection pad 3 when the side surface of the connection pad 3 is completely exposed, the adhesive strength between the connection pad 3 and the insulating layer 8 may be reduced.
  • connection pads 3 arranged at a narrow pitch if a short circuit occurs between the connection pads 3 due to electroless nickel / gold plating in a later process, or if solder bumps are arranged on the connection pads 3, melting occurs. In some cases, the solder that has flowed out flows to the adjacent connection pads 3 and short-circuits between the connection pads 3.
  • an opening having a depth of about 0 to 15 ⁇ m is formed in a part of the solder resist layer provided on the circuit board surface by laser light irradiation.
  • a method of manufacturing a printed wiring board having a structure in which a part of the side surface of the connection pad is exposed from the solder resist layer has been proposed (for example, see Patent Document 1).
  • the connection pad and the insulating layer are compared with the printed wiring board in which the connection pad existing under the solder resist layer is completely exposed. It becomes possible to improve the adhesive strength between.
  • a method of manufacturing a wiring board in which the solder resist layer 2 is filled between adjacent connection pads 3 has been proposed (for example, a patent).
  • Reference 2 According to the method of Patent Document 2, as shown in FIG. 2, the solder resist layer 2 is filled between the connection pads 3, and the thickness of the filled solder resist layer 2 is equal to or less than the thickness of the connection pad 3.
  • An NSMD structure can be formed. Specifically, a solder resist layer 2 is formed on the circuit board 1, and after exposing portions other than the region to be thinned until the thickness of the solder resist layer 2 is equal to or less than the thickness of the connection pad 3, an alkaline aqueous solution is obtained.
  • solder resist layer 2 in the non-exposed portion is thinned with the thinning treatment liquid until the thickness of the connection pad 3 or less.
  • a solder resist layer 2 having a multi-stage structure including a portion less than the thickness of the connection pad 3 and a portion exceeding the thickness of the connection pad 3 is formed, and a part of the conductor wiring that becomes the connection pad 3 is exposed.
  • a wiring board can be manufactured.
  • connection pad for external connection is also produced by exposing a part of the conductor wiring on the back surface of the circuit board from the solder resist layer. The exposed portion of the connection pad for external connection and a conductor wiring of an external electric substrate such as a mother board are opposed to each other and electrically connected via solder bumps.
  • the thickness of the solder resist layer on the connection pad varies depending on the density of the surrounding conductor wiring including the connection pad. For example, when the density of the conductor wiring is small, the amount of the solder resist layer filled in the gap between the conductor wirings increases, and the thickness of the solder resist layer on the connection pad tends to be thin. On the other hand, when the density of the conductor wiring is large, the amount of the solder resist layer filled in the gap between the conductor wirings is reduced, and the thickness of the solder resist layer on the connection pad tends to be thick.
  • the density of the surrounding conductor wiring including the connection pads for external connection on the back surface is higher than the density of the surrounding conductor wiring including the connection pads for connecting electronic components on the front surface. May be large. Therefore, the thickness of the solder resist layer on the connection pad for external connection on the back surface may be thicker than the thickness of the solder resist layer on the connection pad for electronic component connection on the front surface. In the method of thinning the solder resist layer with the thinning solution and exposing the connection pads, the following problems may occur when attempting to thin the both surfaces simultaneously.
  • the solder resist layer 2 on the back surface is also thinned by the same amount as the surface at the same time.
  • the solder resist layer 2 on the back surface is thicker than the solder resist layer 2 on the front surface, the solder resist layer 2 remains as a residue on the connection pad 4 for external connection on the back surface, and this residue causes poor electrical insulation. There was a case where a problem arises (FIG. 3).
  • the solder resist layer 2 on the back surface is thinned to the thickness of the connection pad 4 for external connection or less
  • the solder resist layer 2 on the front surface is also thinned by the same amount as the back surface at the same time.
  • the thickness of the solder resist layer 2 filling the space between the connection pads 3 for connecting the electronic components on the front surface is larger than the desired thickness. In some cases, the thickness becomes thinner, causing a short circuit between adjacent connection pads 3 for connecting electronic components.
  • the gap between the electronic components and the circuit board is underfilled (sealing resin) in order to ensure the connection reliability between the electronic component and the circuit board. Fill with reinforced.
  • a sufficient amount of underfill must be filled in the gap between the electronic component and the circuit board.
  • the underfill may be a gap between the electronic component and the circuit board. In some cases, it overflowed to the surroundings and adversely affected the electrical operation. Therefore, a printed wiring board having a dam structure has been proposed in order to prevent the underfill from overflowing to the surroundings (see, for example, Patent Documents 3 to 5).
  • Patent Document 3 a solder resist layer is formed on a circuit board having a conductor circuit, and then a partial exposure is performed. Thereafter, an unexposed portion is developed to partially expose the upper portion of the connection pad from the solder resist layer.
  • a method of forming a dam shape by forming an opening to be formed, performing a second partial exposure, and then thinning an unexposed portion of the second partial exposure by a desmear process is disclosed. Since the opening of the solder resist layer by this method has an SMD structure, it is difficult to securely fix the electrical connection between the electrode terminal of the electronic component and the corresponding connection pad. In some cases, the electrical connection was insufficient. Moreover, since the dam structure is formed by the desmear process by this method, the strength of the solder resist layer is lowered by roughening the solder resist layer, and the reliability of the printed wiring board is sufficient. In some cases, it could not be secured.
  • Patent Document 4 discloses an opening that completely exposes a connection pad from a solder resist layer by forming a solder resist layer on a circuit board having a conductor circuit, performing partial exposure, and then developing the unexposed portion. Forming a second portion, then forming a second solder resist, then performing a second partial exposure in which an unexposed portion that is one size larger than the first partial exposure region is generated, and then developing the unexposed portion Discloses a method for forming a dam shape.
  • the opening of the solder resist layer by this method has an NSMD structure, and the connection pad is completely removed from the periphery of the solder resist layer, and the side surface of the connection pad is completely exposed. There is a risk that the adhesive strength between the two will decrease.
  • a solder resist layer is formed on a circuit board having a conductor circuit, and then a partial exposure process is performed, and then an unexposed portion of the solder resist layer is thinned so that openings and dams are formed in the solder resist layer.
  • a method of forming a shape is disclosed.
  • the opening of the solder resist layer by this method has an SMD structure, and the connection pad is covered with the solder resist layer in the vicinity of the periphery, so that the electrical connection between the electrode terminal of the electronic component and the corresponding connection pad is made. It is difficult to securely fix the connection, and the electrical connection between the connection pad and the solder ball may be insufficient.
  • An object of the present invention is to have a circuit board having an insulating layer and a connection pad formed on the surface of the insulating layer on both surfaces, and having a solder resist layer on both surfaces of the circuit board, and connecting from the solder resist layer
  • a circuit board having an insulating layer and a connection pad formed on the surface of the insulating layer on both surfaces, and having a solder resist layer on both surfaces of the circuit board, and connecting from the solder resist layer
  • An object of the present invention is to provide a method for manufacturing a wiring board in which no residue of a solder resist layer remains.
  • Another object of the present invention is to obtain a printed wiring board having high adhesion strength between a connection pad and an insulating layer and between the connection pad and solder, no electrical malfunction due to underfill outflow, and high solder resist layer strength. It is providing the manufacturing method of the printed wiring board which can be performed.
  • C1 A step in which a portion other than the region to be thinned in the step (B) which is a subsequent step is exposed to the solder resist layer on the first surface which is thinner than the solder resist layer on the second surface,
  • C2 A step of exposing a portion other than the region to be developed in step (D), which is a subsequent step, to the solder resist layer on the second surface, (B) On the first surface, the solder resist layer of the non-exposed part is thinned until the thickness of the connection pad becomes equal to or less than
  • step (C3) The step of exposing the area portion thinned in step (B) to the solder resist layer on the first surface, (D) the step of removing the solder resist layer of the non-exposed portion of the second surface with a developer;
  • a method for manufacturing a wiring board comprising:
  • step (C5) The step of exposing the thinned region in step (B2) to the solder resist layer on the first surface, (D) the step of removing the solder resist layer of the non-exposed portion of the second surface with a developer;
  • a method for manufacturing a wiring board comprising:
  • Process (C2) A step of exposing a portion other than the region to be developed in step (D1), which is a subsequent step, to the first solder resist layer on the second surface, (B) On the first surface, the first solder resist layer of the non-exposed part is thinned until the thickness of the connection pad is equal to or less than the thickness of the connection pad by the thinning treatment liquid, and a part of the connection pad is exposed; (C3) The step of exposing the region portion thinned in step (B) to the first solder resist layer on the first surface, (A2) A step of forming a second solder resist layer on the first solder resist layer on the first surface of the circuit board completed up to the step (C3), (C6) A step in which a portion other than a region to be developed in the step (D1) which is a subsequent step is exposed to the second solder resist layer on the first surface; (D1) a step of removing the second solder resist layer of the non-exposed portion of the first surface and the first solder
  • Process (C2) A step of exposing a portion other than a region to be developed in step (D), which is a subsequent step, to the first solder resist layer on the second surface; (B) On the first surface, the first solder resist layer of the non-exposed part is thinned until the thickness of the connection pad is equal to or less than the thickness of the connection pad by the thinning treatment liquid, and a part of the connection pad is exposed; (C3) The step of exposing the region portion thinned in step (B) to the first solder resist layer on the first surface, (D) the step of removing the first solder resist layer of the non-exposed portion of the second surface with a developer; (A2) A step in which a second solder resist layer is formed on the first solder resist layer on the first surface of the circuit board completed up to step (D), (C6) A step in which a portion other than the region to be developed in the step (D2) which is a subsequent step is exposed to the second solder resist layer on the first surface, (D2)
  • step (A1) a step in which first solder resist layers having different thicknesses are formed on both surfaces of a circuit board having an insulating layer and connection pads formed on the surfaces of the insulating layer on both surfaces;
  • step (C2) A step of exposing a portion other than the region to be developed in step (D1), which is a subsequent step, to the first solder resist layer on the second surface,
  • step (B) On the first surface, the first solder resist layer of the non-exposed part is thinned until the thickness of the connection pad is equal to or less than the thickness of the connection pad by the thinning treatment liquid, and a part of the connection pad is exposed;
  • step (C3) The step of exposing the region portion thinned in step (B) to the first solder resist layer on the first surface, (A2)
  • the exposure amount in the step (C3) is any one of the above (1), (3), (4), and (8), which is 1 to 5 times the exposure amount in the step (C1).
  • a method for manufacturing a wiring board (12) The method for producing a wiring board according to (5) or (9), wherein the exposure amount in the step (C3) and the step (C7) is 1 to 5 times the exposure amount in the step (C6).
  • the circuit board having the insulating layer and the connection pad formed on the surface of the insulating layer is provided on both surfaces, the solder resist layer is provided on both surfaces of the circuit board, and the connection is made from the solder resist layer.
  • the method of manufacturing a wiring board in which a part of the pad is exposed there is no electrical short circuit between the connection pads exposed from the solder resist layer on both surfaces of the wiring board, and the exposed connection pads It is possible to provide a method of manufacturing a wiring board in which no residue of the solder resist layer remains.
  • the present invention it is possible to obtain a printed wiring board having a high bonding strength between the connection pad and the insulating layer and the connection pad and the solder, no electrical malfunction due to an underfill outflow, and a high strength of the solder resist layer.
  • the manufacturing method of the printed wiring board which can be provided can be provided.
  • FIGS. 4A and 4B are cross-sectional process diagrams illustrating an example of the manufacturing method (1) of the wiring board.
  • a circuit board having the insulating layer 8 and the conductor wiring 7 formed on the surface of the insulating layer 8 on both surfaces is prepared. Part of the conductor wiring 7 is the connection pads 3 and 4.
  • a solder resist layer 2 is formed on both surfaces of the circuit board 1 so as to cover the entire surface.
  • the formation of the solder resist layer 2 on the first surface and the second surface may be performed simultaneously on both surfaces or on each side, but depending on the thickness of the solder resist layer to be formed, heating conditions are set so as not to overheat. There is a need to.
  • the thicknesses of the solder resist layers 2 on both surfaces are different.
  • the thinner one is the “first surface”, and the thicker one is the “second surface”.
  • the thickness of the solder resist layer 2 varies depending on the density of the conductor wiring 7 including the connection pads 3 and 4 on each surface. In FIG. 4-1, the density of the conductor wiring 7 is higher on the lower second surface than on the upper first surface, and the thickness of the solder resist layer 2 on the second surface conductor wiring 7 is It becomes thicker than the thickness of the solder resist layer 2 on the conductor wiring 7 on the first surface.
  • the peripheral conductor wiring 7 including the external connection connection pads 4 on the back surface is compared with the density of the surrounding conductor wiring 7 including the electronic component connection connection pads 3 on the front surface. May have a large density, the front surface being the first surface and the back surface being the second surface.
  • step (C1) the solder resist layer 2 on the first surface is exposed to a portion other than the region to be thinned in the subsequent step (B).
  • a process (C2) parts other than the area
  • the solder resist is photopolymerized and has resistance to the thinning process and the developing process.
  • the solder resist layer 2 in the non-exposed part is thinned by the thinning treatment solution until the thickness of the connection pad 3 becomes equal to or less, and a part of the connection pad 3 is exposed.
  • the connection pads 3 exposed in this step (B) are used as the connection pads 3 for connecting electronic components.
  • the solder resist layer 2 of the non-exposed portion on the second surface is also thinned simultaneously, but on the connection pad 4 on the second surface rather than the solder resist layer 2 on the connection pad 3 on the first surface. Since the solder resist layer 2 is thicker, a residue of the solder resist layer 2 remains on the connection pad 4.
  • step (C3) the solder resist layer 2 on the first surface is exposed to the region thinned in step (B). In the exposed portion of the solder resist layer 2, the solder resist is photopolymerized and has resistance to the development process.
  • step (D) on the second surface, the solder resist layer 2 in the non-exposed portion is removed with a developer, and a part of the connection pad 4 is exposed.
  • step (D) the residue of the solder resist layer 2 remaining on the connection pad 4 is removed.
  • the connection pads 4 exposed in this step (D) are used as connection pads 4 for external connection.
  • the solder resist layer 2 on the first surface the region thinned in the step (B) is exposed in the step (C3) performed before the step (D) and has resistance to the development step. , Not removed by developer.
  • the exposure area in the step (C1) can be changed to an arbitrary shape.
  • a wiring board having a cross-sectional shape shown in FIG. It is possible.
  • the convex part of the soldering resist layer 2 is formed between the connection pads 3 of the 1st surface.
  • the connection pads 3 exposed from the solder resist layer 2 and the conductor wirings 7 covered with the solder resist layer 2 are alternately arranged on the first surface.
  • FIG. 5-1, FIG. 5-2, and FIG. 5-3 are cross-sectional process diagrams illustrating an example of a method (2) for manufacturing a wiring board.
  • the difference from the manufacturing method (1) of the wiring board is that the exposure process and the thinning process of the solder resist layer 2 are added once each on the first surface.
  • step (A) a solder resist layer 2 is formed on both surfaces of the circuit board 1 so as to cover the entire surface.
  • a process (C1) parts other than the area
  • a process (C2) parts other than the area
  • step (B1) the solder resist layer 2 in the non-exposed part is thinned on the first surface with the thinning treatment solution in a range where the connection pads 3 are not exposed.
  • step (B1) the solder resist layer 2 of the non-exposed portion on the second surface is also thinned at the same time.
  • step (C4) the solder resist layer 2 on the first surface is exposed to a portion other than the region to be thinned in the subsequent step (B2).
  • the solder resist layer 2 in the non-exposed part is thinned by the thinning treatment liquid until the thickness of the connection pad 3 becomes equal to or less, and a part of the connection pad 3 is exposed.
  • the connection pads 3 exposed in this step (B2) are used as the connection pads 3 for connecting electronic components.
  • the solder resist layer 2 of the non-exposed portion on the second surface is also thinned simultaneously, but on the connection pad 4 on the second surface rather than the solder resist layer 2 on the connection pad 3 on the first surface. Since the solder resist layer 2 is thicker, a residue of the solder resist layer 2 remains on the connection pad 4.
  • step (C5) the solder resist layer 2 on the first surface is exposed to the region thinned in step (B2).
  • step (D) on the second surface, the solder resist layer 2 in the non-exposed portion is removed with a developer, and a part of the connection pad 4 is exposed. By the step (D), the residue of the solder resist layer 2 remaining on the connection pad 4 is removed. In the case of a wiring board on which electronic components are mounted, the connection pads 4 exposed in this step (D) are used as connection pads 4 for external connection.
  • the exposure area in the step (C4) can be changed to an arbitrary shape.
  • a wiring board having a cross-sectional shape shown in FIG. It is possible.
  • the convex portion of the solder resist layer 2 is formed between the connection pads 3 on the first surface.
  • the connection pads 3 exposed from the solder resist layer 2 and the conductor wirings 7 covered with the solder resist layer 2 are alternately arranged on the first surface.
  • FIGS. 6A, 6B, and 6C are cross-sectional process diagrams illustrating an example of a method (3) of manufacturing a wiring board.
  • the difference from the manufacturing method (2) of the wiring board is that the solder resist layer on the first surface is composed of the first solder resist layer 2-1 and the second solder resist layer 2-2.
  • the manufacturing method (3) of the wiring board after the thickness of the first solder resist layer 2-1 in the non-exposed portion of the first surface is reduced to be equal to or less than the thickness of the connection pad 3, the first solder resist layer After the second solder resist layer 2-2 is formed on the surface of 2-1 and exposed, the second solder resist layer 2-2 in the non-exposed portion is developed.
  • a two-stage solder resist layer having a dam structure for blocking an underfill filling between the electronic component and the wiring board is formed. Can do.
  • first solder resist layers 2-1 having different thicknesses are formed on the first surface and the second surface of the circuit board 1.
  • the first solder resist layer 2-1 on the first surface and the second surface may be formed on both surfaces at the same time or one surface at a time. However, depending on the thickness of the solder resist layer to be formed, it does not excessively heat cure. It is necessary to set the heating conditions.
  • step (C1) the first solder resist layer 2-1 on the first surface, which is thinner than the first solder resist layer 2-1 on the second surface, is thinned in the subsequent step (B). A portion other than the region to be converted is exposed.
  • step (C2) the first solder resist layer 2-1 on the second surface is exposed to a portion other than the region to be developed in the subsequent step (D1).
  • the first solder resist layer 2-1 in the non-exposed part is thinned with a thinning treatment solution until the thickness of the connection pad 3 is less than or equal to the thickness of the connection pad 3. Expose the part.
  • the first solder resist layer 2-1 in the non-exposed portion on the second surface is also thinned at the same time. However, the first solder resist layer 2-1 on the connection pad 4 on the second surface is thicker than the first solder resist layer 2-1 on the connection pad 3 on the first surface. A residue of one solder resist layer 2-1 remains.
  • step (C3) the first solder resist layer 2-1 on the first surface is exposed to the area portion thinned in step (B).
  • step (A2) a second solder resist layer 2-2 is formed on the first solder resist layer 2-1 on the first surface of the circuit board completed up to step (C3).
  • the heating condition applied to the second solder resist layer 2-2 on the first surface is adjusted so that the non-exposed portion of the first solder resist layer 2-1 on the second surface is not excessively cured.
  • step (C6) the second solder resist layer 2-2 on the first surface is exposed to a portion other than the region to be developed in the subsequent step (D1).
  • the second solder resist layer 2-2 in the non-exposed portion on the first surface and the first solder resist layer 2-1 in the non-exposed portion on the second surface are removed with a developer, and the connection pad 3 And a portion of 4 are exposed.
  • the residue of the first solder resist layer 2-1 remaining on the connection pad 4 is removed.
  • the connection pads 3 exposed in this step (D1) are used as the connection pads 3 for electronic component connection, and the connection pads 4 are used as the connection pads 4 for external connection.
  • FIGS. 7A, 7B, and 7C are cross-sectional process diagrams illustrating an example of a method (4) of manufacturing a wiring board.
  • the difference from the manufacturing method (3) of the wiring board is that the first solder resist layer 2-1 on the second surface is removed with a developer before the second solder resist layer 2-2 on the first surface is formed. It is.
  • the second solder resist layer 2-2 of the first surface is formed by removing the first solder resist layer 2-1 of the non-exposed portion of the second surface with a developing solution, It is not necessary to adjust the heating conditions so that the first solder resist layer 2-1 in the exposed area is simultaneously heated and is not excessively cured.
  • the wiring board manufacturing method (4) has a dam structure for damming the underfill filling between the electronic component and the wiring board as in the case of using the wiring board manufacturing methods (2) and (3).
  • a two-stage solder resist layer can be formed.
  • step (A1) first solder resist layers 2-1 having different thicknesses are formed on the first surface and the second surface of the circuit board 1.
  • step (C1) the first solder resist layer 2-1 on the first surface, which is thinner than the first solder resist layer 2-1 on the second surface, is thinned in the subsequent step (B). A portion other than the region to be converted is exposed.
  • step (C2) the first solder resist layer 2-1 on the second surface is exposed to a portion other than the region to be developed in the subsequent step (D).
  • the first solder resist layer 2-1 in the non-exposed part is thinned with a thinning treatment solution until the thickness of the connection pad 3 is less than or equal to the thickness of the connection pad 3. Expose the part.
  • the first solder resist layer 2-1 in the non-exposed portion on the second surface is also thinned at the same time. However, the first solder resist layer 2-1 on the connection pad 4 on the second surface is thicker than the first solder resist layer 2-1 on the connection pad 3 on the first surface. A residue of one solder resist layer 2-1 remains.
  • step (C3) the first solder resist layer 2-1 on the first surface is exposed to the area portion thinned in step (B).
  • step (D) the first solder resist layer 2-1 in the non-exposed portion on the second surface is removed with a developer, and a part of the connection pad 4 is exposed. By the step (D), the residue of the first solder resist layer 2-1 remaining on the connection pad 4 is removed. In the case of a wiring board on which electronic components are mounted, the connection pads 4 exposed in this step (D) are used as connection pads 4 for external connection.
  • step (A2) a second solder resist layer 2-2 is formed on the first solder resist layer 2-1 on the first surface of the circuit board completed up to step (D).
  • step (C6) the second solder resist layer 2-2 on the first surface is exposed to a portion other than the region to be developed in the subsequent step (D2).
  • step (D2) the second solder resist layer 2-2 in the non-exposed portion on the first surface is removed with a developer, and a part of the connection pad 3 is exposed.
  • the connection pads 3 exposed in this step (D2) are used as the connection pads 3 for connecting electronic components.
  • the exposure area in the step (C1) can be changed to an arbitrary shape.
  • the exposure area for example, the wiring having the cross-sectional shape shown in FIG. It is possible to produce a substrate.
  • the convex part of the 1st soldering resist layer 2-1 is formed between the connection pads 3 of the 1st surface.
  • the connection pads 3 exposed from the first solder resist layer 2-1 and the conductor wirings 7 covered with the first solder resist layer 2-1 are alternately arranged.
  • FIG. 8-1, FIG. 8-2, and FIG. 8-3 are cross-sectional process diagrams showing an example of a method (5) of manufacturing a wiring board.
  • the wiring board manufacturing method (5) on the first surface, the thickness of the first solder resist layer 2-1 becomes equal to or less than the thickness of the connection pad 3 before the first solder resist layer 2-1 is exposed. Thin film processing. Thereafter, a second solder resist layer 2-2 is formed on the surface of the first solder resist layer 2-1, and after exposure, the second solder resist layer 2-2 in the non-exposed part is thinned, Exposure is performed again, and the remaining second solder resist layer 2-2 in the unexposed area is developed.
  • the wiring board manufacturing method (5) has a dam structure for damming the underfill filling between the electronic component and the wiring board, as in the case of using the wiring board manufacturing methods (2) to (4).
  • a two-stage solder resist layer can be formed.
  • step (A1) first solder resist layers 2-1 having different thicknesses are formed on the first surface and the second surface of the circuit board 1.
  • step (C2) the first solder resist layer 2-1 on the second surface is exposed to a portion other than the region to be developed in the subsequent step (D1).
  • the first solder resist layer 2-1 in the non-exposed portion is thinned with the thinning treatment solution until the thickness of the connection pad 3 is less than or equal to all the connection pads 3
  • the first solder resist layer 2-1 in the non-exposed portion on the second surface is also thinned at the same time.
  • the first solder resist layer 2-1 on the connection pad 4 on the second surface is thicker than the first solder resist layer 2-1 on the connection pad 3 on the first surface. A residue of one solder resist layer 2-1 remains.
  • step (C3) the first solder resist layer 2-1 on the first surface is exposed to the area portion thinned in step (B).
  • step (A2) a second solder resist layer 2-2 is formed on the first solder resist layer 2-1 on the first surface of the circuit board completed up to step (C3).
  • step (C6) the second solder resist layer 2-2 on the first surface is exposed to a portion other than the region to be thinned in the subsequent step (B3).
  • step (B3) on the first surface, the second solder resist layer 2-2 in the non-exposed portion is thinned by the thinning treatment solution in a range where the connection pad 3 is not exposed.
  • step (B3) the first solder resist layer 2-1 in the non-exposed portion on the second surface is also thinned at the same time. However, a residue of the first solder resist layer 2-1 may remain on the connection pad 4.
  • step (C7) the second solder resist layer 2-2 on the first surface is exposed to a portion other than the region to be developed in the subsequent step (D1).
  • the second solder resist layer 2-2 in the non-exposed portion on the first surface and the first solder resist layer 2-1 in the non-exposed portion on the second surface are removed with a developer, and the connection pad 3 A part of the connection pad 4 is exposed again, and at the same time, a part of the connection pad 4 is exposed.
  • the residue of the first solder resist layer 2-1 remaining on the connection pad 4 is removed.
  • the connection pads 3 exposed in this step (D1) are used as the connection pads 3 for electronic component connection, and the connection pads 4 are used as the connection pads 4 for external connection.
  • the exposure area in the step (C7) can be changed to an arbitrary shape.
  • a wiring board having a cross-sectional shape shown in FIG. It is possible.
  • FIG. 12g a convex portion of the second solder resist layer 2-2 is formed between the connection pads 3 on the first surface.
  • the connection pads 3 exposed from the first solder resist layer 2-1 and the conductor wirings 7 covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 are alternately arranged. It is out.
  • the circuit board 1 according to the present invention includes an insulating layer 8 and connection pads 3 and 4 formed on the surface of the insulating layer 8. Conductor wiring 7 is formed on the surface of the insulating layer 8, and the connection pads 3 and 4 are part of the conductor wiring 7.
  • the wiring board according to the present invention has solder resist layers 2 on both surfaces of the circuit board 1, and part of the connection pads 3 and 4 are exposed from the solder resist layer 2.
  • the connection pads 3 for connecting electronic components are provided on the front surface, and the connection pads 4 for external connection are provided on the back surface.
  • the electronic component connecting connection pad 3 on the front surface and the electronic component are bonded, and the external connecting connection pad 4 on the back surface and the conductor wiring of the external electric substrate are bonded.
  • the circuit board according to the present invention is produced, for example, by alternately laminating build-up insulating layers and conductor wiring on an insulating substrate on which conductor wiring is disposed.
  • 13A and 13B are schematic cross-sectional views showing an example of a circuit board produced by alternately laminating build-up insulating layers and conductor wirings on an insulating board on which conductor wirings are arranged.
  • 4 to 8 are sectional process diagrams showing an example of a method for manufacturing a wiring board of the present invention
  • FIGS. 9 to 12 are schematic sectional views showing examples of a wiring board that can be manufactured according to the present invention.
  • the circuit board 1 having the conductor wiring 7 formed on both surfaces of the insulating layer 8 is described, the circuit board 1 used in the method for manufacturing a wiring board according to the present invention is shown in FIG.
  • the insulating layer 8 and the conductor wiring 7 formed on the surface of the insulating layer 8 are produced by alternately laminating build-up insulating layers and conductor wiring on the insulating substrate on which the conductor wiring is disposed.
  • the circuit board 1 having both of the surfaces is included.
  • the insulating substrate include a resin substrate made of an electrically insulating material in which a glass cloth is impregnated with a thermosetting resin such as a bismaleimide triazine resin or an epoxy resin.
  • an electrical insulating material in which a glass cloth is impregnated with a thermosetting resin as in the case of an insulating substrate, an inorganic filler such as silicon oxide is dispersed in a thermosetting resin such as an epoxy resin.
  • an inorganic filler such as silicon oxide is dispersed in a thermosetting resin such as an epoxy resin.
  • Examples include electrical insulating materials.
  • the conductor wiring is formed by, for example, a subtractive method, a semi-additive method, an additive method, or the like. In the subtractive method, for example, after forming a copper layer on an insulating layer, an etching resist layer is formed, and exposure, development, etching, and resist stripping are performed to form a conductor wiring.
  • a base metal layer for electrolytic copper plating is provided on the surface of the insulating layer by electroless copper plating.
  • a plating resist layer having an opening corresponding to the conductor wiring is formed, and an electrolytic copper plating layer is formed on the surface of the base metal layer exposed by electrolytic copper plating.
  • the plating resist layer is peeled off, and the exposed base metal layer is removed by flash etching to form a conductor wiring.
  • connection pad on the surface of the wiring board is a connection pad for connecting to the electronic component.
  • the electronic component is flip-chip mounted on the wiring board by being electrically connected to the connection pad via the solder bump.
  • the surface of the connection pad can be roughened or can be treated with a coupling agent.
  • the connection pad on the back surface of the wiring board is a connection pad for external connection. Flip chip mounting is performed on the mother board by electrically connecting the connection pads and conductor wiring of an external electric board such as the mother board through solder bumps.
  • an alkali developing type solder resist can be used. Further, it may be either a one-component or two-component liquid resist, or a dry film resist.
  • the solder resist contains, for example, an alkali-soluble resin, a monofunctional acrylic monomer, a polyfunctional acrylic monomer, a photopolymerization initiator, an epoxy resin, an inorganic filler, and the like.
  • alkali-soluble resin examples include alkali-soluble resins having both photo-curing properties and thermosetting properties.
  • a resin to which an acid anhydride has been added may be mentioned.
  • the polyfunctional acrylic monomer include trimethylolpropane triacrylate (Trimethylol Propane Triacrylate), dipentaerythritol hexaacrylate (Di-pentaerythritol Polyacrylate), and pentaerythritol triacrylate (Pentaerythritol Triacrylate).
  • Epoxy resin is used as a curing agent. It is cross-linked by reacting with carboxylic acid of alkali-soluble resin to improve heat resistance and chemical resistance, but carboxylic acid and epoxy react at room temperature, so the storage stability is poor and alkaline
  • the development type solder resist often takes a two-component form to be mixed before use.
  • the inorganic filler include talc, silica, barium sulfate, titanium oxide, and zinc oxide.
  • the solder resist layer is formed so as to cover the entire surface on both surfaces of the circuit board.
  • the solder resist layer for example, if it is a liquid resist, screen printing method, roll coating method, spray method, dipping method, curtain coating method, bar coating method, air knife method, hot melt method, gravure coating method, brush A coating method or an offset printing method can be used.
  • a laminating method or a vacuum laminating method is used.
  • solder resist layer 2 formed in step (A) in wiring board manufacturing methods (1) and (2), and first formed in steps (A1) in wiring board manufacturing methods (3) to (5).
  • the solder resist layer 2-1 has different thicknesses on both surfaces of the circuit board. The thinner one is the “first surface” and the thicker one is the “second surface”.
  • the same conditions are generally set on both surfaces. This is because the solder resist has thermosetting properties. In the case of a liquid resist, it is necessary to heat and dry to remove the solvent after coating. Therefore, if the coating amount is different on each surface, the drying conditions must be changed on each surface. Such a condition must be set.
  • the thickness of the solder resist layer varies depending on the density of the surrounding conductor wiring including the connection pads on each surface.
  • the back surface is compared with the density of the surrounding conductor wiring including the connection pads for electronic component connection on the front surface.
  • the density of the surrounding conductor wiring including the external connection pad is increased.
  • the thickness of the solder resist layer on the external connection connection pad on the back surface is larger than the thickness of the solder resist layer on the electronic component connection connection pad on the front surface.
  • the front surface is the first surface and the back surface is the second surface.
  • the process in which the solder resist layer according to the present invention is thinned is a micellization process (thinning process) in which the solder resist layer components in the non-exposed area are micellized with a thinning solution, and then the micelles are removed with a micelle removal solution. It is a process including the micelle removal process to remove. Further, it may include a washing process for washing away the micelles that could not be removed, the remaining thinning treatment liquid and the micelle removal liquid by washing with water, and a drying process for removing the washing water.
  • the thinning treatment is a treatment in which the solder resist layer components in the non-exposed part are micelleed with a thinning treatment solution and the micelles are insolubilized in the thinning treatment solution.
  • Alkaline aqueous solutions can be used for the thinning solution according to the present invention.
  • Alkaline aqueous solutions that can be used as the thinning solution include alkali metal silicate (Alkali Metal Silicate), alkali metal hydroxide (Alkali Metal Hydroxide), alkali metal phosphate (Alkali Metal Phosphate), alkali metal carbonate ( Alkali Metal Carbonate), aqueous solutions of inorganic alkaline compounds such as ammonium phosphate and ammonium carbonate; monoethanolamine, diethanolamine, triethanolamine, methylamine, dimethylamine, ethylamine, diethylamine, triethylamine, cyclohexylamine, tetramethylammonium hydroxy (Tetramethylammonium Hydroxide, T AH), tetraethylammonium hydroxide, trimethyl-2-hydroxyethyl ammonium hydroxide (choline, include aqueous solutions of organic
  • sulfates and sulfites can be added to the thinning solution.
  • the sulfate or sulfite include alkali metal sulfates or sulfites such as lithium, sodium or potassium, and alkaline earth metal sulfates or sulfites such as magnesium and calcium.
  • an inorganic alkaline compound selected from alkali metal carbonates, alkali metal phosphates, alkali metal hydroxides, alkali metal silicates, and TMAH (tetramethylammonium hydroxide) As the thinning treatment liquid, among these, an inorganic alkaline compound selected from alkali metal carbonates, alkali metal phosphates, alkali metal hydroxides, alkali metal silicates, and TMAH (tetramethylammonium hydroxide) ), A thinning solution containing at least one of the organic alkaline compounds selected from choline and containing 3 to 25% by mass of the inorganic alkaline compound and the organic alkaline compound has a more uniform surface. Can be preferably used. If it is less than 3% by mass, unevenness may easily occur in the thinning process.
  • the content of the alkaline compound is more preferably 5 to 20% by mass, and further preferably 7 to 15% by mass.
  • the pH of the thinning treatment solution is preferably 10 or more. Further, a surfactant, an antifoaming agent, a solvent and the like can be added as appropriate.
  • the presence of inorganic fillers that are insoluble in the thinning solution contained in the solder resist layer cannot be ignored.
  • the size of the inorganic filler depends on its type, but it has a certain particle size distribution from submicron order called nanofiller to several tens of microns, and it is 30-70% by mass in the layer. Present in content. Thinning proceeds after the alkaline compound penetrates into the solder resist layer and then proceeds through the process of micelle formation and micelle removal of the solder resist layer components, but the presence of insoluble inorganic filler suppresses the penetration of the alkaline compound, resulting in thinning. The speed may be slow.
  • the pH of the thinning solution is preferably 12.5 or more, and more preferably 13.0 or more, with respect to the inhibition of the penetration of the alkaline compound by such an inorganic filler.
  • the higher the pH of the thinning solution the greater the swelling of the solder resist layer when the alkaline compound penetrates, and the less the influence of the penetration inhibition by the inorganic filler.
  • the exposed connection pad when a part of the connection pad on the first surface is exposed by thinning, the exposed connection pad can be used as a connection pad for connecting an electronic component.
  • the surface of the connection pad is roughened, and the anchor effect improves the adhesion between the connection pad and the solder resist layer, and high insulation reliability is maintained for a long time.
  • solder resist pattern formation when removing the solder resist layer and exposing the connection pad surface, it is common to use a low-concentration sodium carbonate aqueous solution with excellent dispersion ability as the developer. Almost no residue of the solder resist layer is generated. However, if the solder resist layer is thinned using a low-concentration sodium carbonate aqueous solution, it cannot be uniformly thinned in the surface, and in-plane unevenness occurs.
  • the temperature of the thinning treatment liquid is preferably 15 to 35 ° C, more preferably 20 to 30 ° C. If the temperature is too low, the penetration rate of the alkaline compound into the solder resist layer may be slow, and it takes a long time to reduce the desired thickness. On the other hand, if the temperature is too high, the micelle removal process proceeds simultaneously with the micelle formation of the solder resist layer components, which may cause uneven film thickness in the surface, which is not preferable.
  • thinning treatment using the thinning treatment liquid methods such as immersion treatment, paddle treatment, spray treatment, brushing, and scraping can be used, but immersion treatment is preferred.
  • immersion treatment is preferred.
  • bubbles are likely to be generated in the thinning treatment liquid, and the generated bubbles may adhere to the surface of the solder resist layer during the thinning, resulting in uneven film thickness.
  • spraying or the like it is preferable to make the spray pressure as small as possible so that bubbles are not generated.
  • the micelles are dissolved all at once by spraying the micelle removal solution in the micelle removal treatment that removes the micelles of the solder resist layer components insolubilized in the thinning solution. Remove.
  • the micelle removal liquid tap water, industrial water, pure water or the like can be used. Further, by using an aqueous solution having a pH of 5 to 10 containing at least one of inorganic alkaline compounds selected from alkali metal carbonates, alkali metal phosphates, and alkali metal silicates as a micelle removal solution, a thinning treatment is performed. The solder resist layer component insolubilized with the liquid is easily redispersed. When the pH of the micelle removal solution is less than 5, the solder resist layer components aggregate and become insoluble sludge, which may adhere to the surface of the solder resist layer that has been thinned.
  • the pH of the micelle removal solution exceeds 10
  • micelle formation of the solder resist layer component and the micelle removal process are promoted at the same time, and uneven film thickness tends to occur in the surface.
  • the pH of the micelle removal solution can be adjusted using sulfuric acid, phosphoric acid, hydrochloric acid, or the like.
  • the spray conditions in the micelle removal process will be described.
  • the spray conditions (temperature, time, spray pressure) are appropriately adjusted according to the dissolution rate of the solder resist layer to be thinned.
  • the treatment temperature is preferably 10 to 50 ° C., more preferably 22 to 50 ° C. If the temperature of the aqueous solution is less than 10 ° C., poor dissolution of the solder resist layer components may occur, and the solder resist layer residue may easily remain on the roughened connection pad surface. On the other hand, when the temperature exceeds 50 ° C., problems such as evaporation of the aqueous solution, temperature management in continuous operation, and restrictions on the device design may occur, which is not preferable.
  • the spray pressure is preferably 0.01 to 0.5 MPa, more preferably 0.1 to 0.3 MPa.
  • the supply flow rate of the micelle removal liquid is preferably 0.030 to 1.0 L / min, more preferably 0.050 to 1.0 L / min, and further 0.10 to 1.0 L / min per 1 cm 2 of the solder resist layer. preferable. When the supply flow rate is within this range, the micelles can be removed substantially uniformly in the surface without leaving insoluble components on the surface of the solder resist layer after thinning. When the supply flow rate per 1 cm 2 of the solder resist layer is less than 0.030 L / min, insoluble components of the solder resist layer may remain.
  • the amount of thin film can be adjusted as appropriate within a range of 0.01 to 500 ⁇ m.
  • the height from the surface of the solder resist layer 2 or the first solder resist layer 2-1 that has been thinned until the thickness of the connection pad becomes equal to or less than the thickness of the connection pad 3 exposed as appropriate depends on the amount of solder required later. adjust.
  • the thickness of the solder resist layer 2, the first solder resist layer 2-1, and the second solder resist layer 2-2 which are part of the dam for underfill damming, determines the size of the electronic component and the connection of the electronic component. It is adjusted as appropriate according to the size of the terminal and the amount of underfill filled between the electronic component and the wiring board.
  • the process (C2) is performed before the process (C1) in the wiring board manufacturing methods (1) to (4).
  • the steps (C1) and (C2) are simultaneously performed in the wiring board manufacturing methods (1) to (4).
  • the order of the step (C1) and the step (C2) can be interchanged, or the step (C1) and the step (C2) can be performed simultaneously. it can.
  • step (C1) in the manufacturing method (1) of the wiring substrate the solder resist layer 2 on the first surface is selectively exposed to a portion other than the region to be thinned in the subsequent step (B).
  • step (C1) in the manufacturing method (2) of the wiring board the solder resist layer 2 on the first surface is selectively exposed to a portion other than the region to be thinned in the subsequent step (B1).
  • step (C1) in the manufacturing methods (3) and (4) of the wiring board the first solder resist layer 2-1 on the first surface is other than the region to be thinned in the subsequent step (B). Are selectively exposed.
  • step (C4) in the manufacturing method (2) of the wiring board the solder resist layer 2 on the first surface is selectively exposed to a portion other than the region to be thinned in the subsequent step (B2).
  • step (C6) in the method (3) for manufacturing the wiring board and the step (C7) in the method (5) for manufacturing the wiring substrate a step that is a subsequent step with respect to the second solder resist layer 2-2 on the first surface.
  • step (D1) a portion other than the region to be developed is selectively exposed.
  • step (C6) in the method (4) of manufacturing the wiring board a portion other than the region developed in the subsequent step (D2) is selectively selected with respect to the second solder resist layer 2-2 on the first surface. To expose.
  • step (C6) in the method (5) of manufacturing the wiring substrate the second solder resist layer 2-2 on the first surface is exposed to a portion other than the region to be thinned in the subsequent step (B3).
  • the exposed solder resist is photopolymerized, and the solder resist layer 2, the first solder resist layer 2-1, and the second solder resist layer 2-2 are cured.
  • the actinic ray 6 is exposed through the photomask 5, but it may be performed by a direct drawing method.
  • Examples include an exposure method.
  • the “region to be thinned” on the first surface is, for example, a region around the connection pad including on the connection pad and between the connection pads. More specifically, a mounting area for mounting an electronic component and its surroundings.
  • the portion other than the region developed in the process (D) which is a subsequent process is selective to the solder resist layer 2 on the second surface. To be exposed.
  • step (C2) in the manufacturing method (4) of the wiring board the portion other than the region developed in step (D), which is a subsequent step, is selective to the first solder resist layer 2-1 on the second surface. To be exposed.
  • step (C2) in the manufacturing methods (3) and (5) of the wiring board the region other than the region developed in the subsequent step (D1) with respect to the first solder resist layer 2-1 on the second surface. A portion is selectively exposed.
  • the exposed solder resist is photopolymerized, and the solder resist layer 2 and the first solder resist layer 2-1 are cured.
  • a method similar to the step (C1) in the wiring substrate manufacturing method (1) described above can be used.
  • the “region to be developed” on the second surface is, for example, a region around the connection pad including on the connection pad and between the connection pads. More specifically, it is a circular opening region that exposes a part of connection pads arranged in an area array type for mounting with conductor wiring of an external electric substrate.
  • step (C3) of the wiring board manufacturing method (1) the solder resist layer 2 on the first surface is exposed to the region thinned in the step (B).
  • step (C3) in the manufacturing methods (3) to (5) of the wiring board the first solder resist layer 2-1 on the first surface is exposed to the area portion thinned in step (B).
  • step (C5) in the manufacturing method (2) of the wiring board the area portion thinned in step (B2) is exposed to the solder resist layer 2 on the first surface.
  • a method similar to the step (C1) in the wiring substrate manufacturing method (1) described above can be used.
  • the part exposed in step (C3) in the method (1), (3), (4) of manufacturing the wiring board includes at least the region thinned in step (B), and the part exposed in step (C1) It is preferable to include a boundary with the region thinned in the step (B). Further, the portion exposed in step (C5) in the manufacturing method (2) of the wiring board includes at least the region thinned in step (B2), the portion exposed in step (C4) and the thin film in step (B2). It is preferable to include a boundary portion with the normalized region.
  • the exposure amount in step (C7) in 5) is appropriately determined according to the photosensitivity of the solder resist.
  • the solder resist is photopolymerized and cured to the extent that the solder resist does not dissolve or swell with respect to the developer used in the step (D1) in 5) and the step (D2) in the manufacturing method (4) of the wiring board.
  • it is 100 to 600 mJ / cm 2 .
  • the exposure in (C3) and step (C7) is preferably performed by a non-contact exposure method in an oxygen atmosphere.
  • the non-contact exposure method include a proximity method, a projection method, and a direct drawing method that does not use a photo mask, in which a gap is provided between the photo mask and the wiring board to perform non-contact exposure.
  • the surface layer of each solder resist layer Photopolymerization in the vicinity is inhibited by the influence of oxygen to become an uncured portion, and only the portion away from the surface layer is cured.
  • the steps (D) and (D2) in the manufacturing method (4) of step (D1) in the manufacturing method (5) of the wiring board remove the uncured portion near the surface layer, and the solder resist layer 2 and the first solder resist The surfaces of the layer 2-1 and the second solder resist layer 2-2 are roughened.
  • the adhesiveness with the underfill becomes stronger when the surface is roughened.
  • connection reliability is further improved.
  • Adhesion with the underfill is improved by roughening the surfaces of the solder resist layer 2, the first solder resist layer 2-1, and the second solder resist layer 2-2 by non-contact exposure in an oxygen atmosphere.
  • high connection reliability can be obtained.
  • the surface roughness Ra of the solder resist layer preferable for improving the adhesion with the underfill is 0.30 ⁇ m or more and 0.50 ⁇ m or less. When the surface roughness Ra exceeds 0.50 ⁇ m, the strength of the solder resist is lowered and insulation reliability may not be obtained.
  • the surface roughness Ra is an arithmetic average surface roughness.
  • the exposure amount in the step (C3) in the method (1), (3), (4) for manufacturing the wiring substrate and the steps (C4) and (C5) in the method (2) for manufacturing the wiring substrate are the exposure amounts in the step (C1).
  • the amount is preferably 1 to 5 times, more preferably 1.5 to 3 times the amount.
  • the exposure amount in the step (C3) and the step (C7) in the manufacturing method (5) of the wiring board is preferably 1 to 5 times the exposure amount in the step (C6), more preferably It is 1.5 times or more and 3 times or less.
  • the amount of exposure required to cure the solder resist to such an extent that the solder resist does not dissolve or swell is given to prevent polymerization by oxygen on the surface of the solder resist layer. Can be minimized.
  • the larger the exposure amount the more effective the suppression of polymerization inhibition is.
  • too much exposure amount is not preferable because not only the resolution of the solder resist deteriorates but also the exposure time becomes too long. .
  • the connection pad is formed on the first surface with the thinning treatment liquid.
  • the solder resist layer 2 and the first solder resist layer 2-1 in the non-exposed part are thinned until the thickness becomes 3 or less, and a part of the connection pad 3 is exposed.
  • the first surface is not exposed to the extent that the connection pad 3 is not exposed by the thinning solution.
  • the solder resist layer 2 and the second solder resist layer 2-2 in the exposed portion are thinned. When a film-like resist is used and a support layer film is provided, the support layer film is peeled off before thinning.
  • the solder resist layer 2 and the first solder resist after thinning Thinning is performed until the thickness of the layer 2-1 is equal to or less than the thickness of the connection pad 3 exposed on the first surface. If the thickness of the solder resist layer 2 and the first solder resist layer 2-1 after thinning is too thin, the electrical insulation between the exposed connection pads 3 becomes insufficient, and an electroless nickel / gold plating short circuit occurs. Or a short circuit may occur between the connection pads 3 due to solder. Therefore, the thickness of the solder resist layer 2 and the first solder resist layer 2-1 after thinning is preferably at least one third of the thickness of the connection pad 3, more preferably at least two thirds. It is good to be.
  • step (B) in the manufacturing method (1) of the wiring substrate and the steps (B1) and (B2) in the manufacturing method (2) of the wiring substrate when the solder resist layer 2 of the non-exposed portion on the first surface is thinned, The solder resist layer 2 on the non-exposed portion on the second surface is also thinned at the same time.
  • step (B) in the manufacturing methods (3) to (5) of the wiring board when the first solder resist layer 2-1 in the non-exposed portion on the first surface is thinned, the first in the non-exposed portion on the second surface is obtained.
  • the solder resist layer 2-1 is also thinned at the same time.
  • step (B3) in the method (5) of manufacturing the wiring board when the second solder resist layer 2-2 in the non-exposed portion on the first surface is thinned, the first solder resist layer 2 in the non-exposed portion on the second surface is formed. -1 is also thinned at the same time.
  • the amount of thinning of the second surface varies depending on the heat-cured state of the solder resist layer 2 and the first solder resist layer 2-1 in the non-exposed portion on the second surface, but the solder resist layer 2 under the same heating conditions on both surfaces,
  • the solder resist layer 2 and the first solder resist layer 2-1 in the non-exposed portion of the first surface and the second surface are usually thinned in the same amount at the same time. .
  • the thinning treatment is preferably performed with the first surface facing up.
  • dipping treatment is effective because bubbles are not easily generated in the thinning treatment solution. In the unlikely event that bubbles are generated in the thinning solution, the bubbles will rise in the thinning solution and adhere to the solder resist layer 2 on the lower surface (second surface) and the surface of the first solder resist layer 2-1. To do. Due to the adhesion of the bubbles, the film thickness after thinning on the second surface may become non-uniform.
  • the manufacturing method (1), (2), and (4) of the wiring board which is a subsequent process
  • the step (D2) in the method (4) the solder resist layer 2 and the first solder resist layer 2-1 in the non-exposed portion on the second surface are developed and removed, and therefore, unevenness of the film thickness eventually becomes a problem. There is no.
  • step (D) in the manufacturing method (1) and (2) of the wiring board the solder resist layer 2 in the non-exposed part on the second surface is removed by development.
  • step (D) in the manufacturing method (4) of the wiring board the first solder resist layer 2-1 in the non-exposed portion on the second surface is removed by development.
  • step (D1) in the manufacturing methods (3) and (5) of the wiring substrate the second solder resist layer 2-2 in the non-exposed portion on the first surface and the first solder in the non-exposed portion on the second surface are developed by development.
  • the resist layer 2-1 is removed.
  • step (D2) in the method (4) for manufacturing the wiring board the second solder resist layer 2-2 in the non-exposed portion on the first surface is removed by development.
  • a developer corresponding to the solder resist to be used is used, spray is sprayed on both surfaces of the circuit board, and unnecessary portions of each solder resist layer are removed.
  • a dilute alkaline aqueous solution is used as the developer, and generally a 0.3 to 3 mass% sodium carbonate aqueous solution or potassium carbonate aqueous solution is used.
  • Examples 1 to 6 are examples relating to the manufacturing method (1) of the wiring board shown in FIGS. 4-1 and 4-2.
  • Example 1 Using a semi-additive method, a circuit board 1 (area 170 mm ⁇ 200 mm, conductor thickness 15 ⁇ m, board thickness 0.4 mm) having conductor wirings 7 formed on both surfaces was produced. On the front surface (first surface) side, there is a conductor wiring having a line width of 25 ⁇ m and an interval of 50 ⁇ m used as the connection pad 3 for connecting electronic components. A circular conductor wiring having a diameter of 600 ⁇ m used as the external connection pad 4 is formed on the back surface (second surface) side.
  • solder resist film manufactured by Taiyo Ink Manufacturing Co., Ltd., trade name: PFR-800 AUS410
  • laminate temperature 75 ° C.
  • suction time 30 seconds
  • pressurization time 10 seconds pressurization time 10 seconds
  • the thickness from the surface of the insulating layer 8 was 38 ⁇ m, and the thickness on the connection pad 4 for external connection was 23 ⁇ m.
  • the thickness of the solder resist layer 2 is 8 ⁇ m thinner than on the second surface where the density of the conductor wiring is larger.
  • the contact exposure was performed at an exposure amount of 200 mJ / cm 2 .
  • C2 A photomask having a pattern in which actinic rays 6 are irradiated in areas other than the circular opening area in order to provide a circular opening area having a diameter of 500 ⁇ m on the external connection pad 4 for the solder resist layer 2 on the second surface. 5 was used for contact exposure at an exposure amount of 200 mJ / cm 2 .
  • the solder resist layer 2 having an average of 20 ⁇ m was thinned to 5.0 ⁇ m below the surface of the connection pad 3 for connection.
  • the surface of the solder resist layer 2 on the first surface was free from uneven processing, and good in-plane uniformity was obtained.
  • the solder resist layer 2 having an average thickness of 20 ⁇ m was also thinned on the second surface, but bubbles in the thinning treatment liquid adhered to the solder resist layer 2 in the non-exposed area on the second surface, and the film thickness was not improved. There was a uniform spot. Further, a residue of about 3 ⁇ m of the solder resist layer 2 remained on the connection pad 4 for external connection.
  • the non-contact exposure in the oxygen atmosphere in the step (C3) suppresses the photopolymerization of the surface of the solder resist layer 2 between the connection pads 3 for connecting electronic components, and as a result, the thickness of the solder resist layer 2 is 0.5 ⁇ m. It was decreasing.
  • the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was.
  • the conductor wiring 7 having a thickness of 15 ⁇ m is covered with the solder resist layer 2 having a thickness of 30 ⁇ m, and the connection pad 3 for connecting an electronic component having a thickness of 15 ⁇ m is exposed.
  • the solder resist layer 2 having a thickness of 9.5 ⁇ m was filled between the connection pads 3 for connecting electronic components.
  • a circular opening of the solder resist layer 2 having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m is formed on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. A part of was exposed.
  • the surface roughness of the solder resist layer 2 between adjacent connection pads 3 for connecting electronic components was measured.
  • the surface roughness was measured using an ultra-deep shape measuring microscope (manufactured by Keyence Corporation, product number “VK-8500”), the surface roughness Ra was 0.40 ⁇ m.
  • the arithmetic average surface roughness Ra by an ultra-deep shape measuring microscope uses a calculation formula according to JIS B0601-1994 surface roughness-definition.
  • the measurement area was 900 ⁇ m 2 and the reference length was 40 ⁇ m.
  • Example 2 The steps (A) to (D) were performed in the same manner as in Example 1 except that the order of the steps (C1) and (C2) was changed. As a result of observation with an optical microscope, no residue of the solder resist layer 2 was found on the connection pads 3 for connecting electronic components and the connection pads 4 for external connection on both the first surface and the second surface. Further, on the first surface, the solder resist layer 2 was filled between the connection pads 3 for connecting electronic components up to 5.5 ⁇ m below the surface of the connection pads 3 for connecting electronic components.
  • the non-contact exposure in the oxygen atmosphere in the step (C3) suppresses photopolymerization of the surface of the solder resist layer 2 between the connection pads 3 for connecting electronic components, and as a result, the thickness of the solder resist layer 2 is reduced by 0.5 ⁇ m. Was.
  • the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was.
  • the conductor wiring 7 having a thickness of 15 ⁇ m is covered with the solder resist layer 2 having a thickness of 30 ⁇ m, and the connection pad 3 for connecting an electronic component having a thickness of 15 ⁇ m is exposed.
  • the solder resist layer 2 having a thickness of 9.5 ⁇ m was filled between the connection pads 3 for connecting electronic components.
  • a circular opening of a solder resist layer having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m is formed on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. Some were exposed.
  • the surface roughness Ra 0.40 ⁇ m.
  • Steps (A) to (D) were performed in the same manner as in Example 1 except that the exposure amount in step (C3) was 200 mJ / cm 2 .
  • the exposure amount in step (C3) was 200 mJ / cm 2 .
  • no residue of the solder resist layer 2 was found on the connection pads 3 for connecting electronic components and the connection pads 4 for external connection on both the first surface and the second surface.
  • the solder resist layer 2 was filled between the connection pads 3 for electronic component connection up to 6.0 ⁇ m below the surface of the connection pads 3 for electronic component connection.
  • the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was.
  • the conductor wiring 7 having a thickness of 15 ⁇ m is covered with the solder resist layer 2 having a thickness of 30 ⁇ m, and the connection pad 3 for connecting an electronic component having a thickness of 15 ⁇ m is exposed.
  • the solder resist layer 2 having a thickness of 9.0 ⁇ m was filled between the connection pads 3 for connecting the electronic components.
  • a circular opening of the solder resist layer 2 having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m is formed on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. A part of was exposed.
  • the surface roughness Ra was 0.50 ⁇ m.
  • Example 4 Steps (A) to (D) were performed in the same manner as in Example 1 except that the exposure amount in step (C3) was 1000 mJ / cm 2 .
  • the exposure amount in step (C3) was 1000 mJ / cm 2 .
  • no residue of the solder resist layer 2 was found on the connection pads 3 for connecting electronic components and the connection pads 4 for external connection on both the first surface and the second surface.
  • the solder resist layer 2 was filled between the connection pads 3 for electronic component connection up to 5.0 ⁇ m below the surface of the connection pads 3 for electronic component connection. No film loss of the solder resist layer 2 on the first surface due to inhibition of oxygen polymerization in the step (C3) was confirmed.
  • the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was.
  • the conductor wiring 7 having a thickness of 15 ⁇ m is covered with the solder resist layer 2 having a thickness of 30 ⁇ m, and the connection pads 3 for connecting an electronic component having a thickness of 15 ⁇ m are exposed.
  • the solder resist layer 2 having a thickness of 10.0 ⁇ m was filled between the connection pads 3 for connecting electronic components.
  • a circular opening of the solder resist layer 2 having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m is formed on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. A part of was exposed.
  • the surface roughness Ra 0.30 ⁇ m.
  • Example 5 The same method as in Example 1 except that the exposure in the step (C3) was performed at an exposure amount of 400 mJ / cm 2 using a direct drawing apparatus (trade name: LI-8500, manufactured by Dainippon Screen Mfg. Co., Ltd.) in an oxygen atmosphere. Then, steps (A) to (D) were carried out. As a result of observation with an optical microscope, no residue of the solder resist layer 2 was found on the connection pads 3 for connecting electronic components and the connection pads 4 for external connection on both the first surface and the second surface. On the first surface, the solder resist layer 2 was filled between the connection pads 3 for electronic component connection up to 5.5 ⁇ m below the surface of the connection pads 3 for electronic component connection.
  • a direct drawing apparatus trade name: LI-8500, manufactured by Dainippon Screen Mfg. Co., Ltd.
  • the non-contact exposure in the oxygen atmosphere in the step (C3) suppresses photopolymerization of the surface of the solder resist layer 2 between the connection pads 3 for connecting electronic components, and as a result, the thickness of the solder resist layer 2 is reduced by 0.5 ⁇ m. Was.
  • the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was.
  • the conductor wiring 7 having a thickness of 15 ⁇ m is covered with the solder resist layer 2 having a thickness of 30 ⁇ m, and the connection pad 3 for connecting an electronic component having a thickness of 15 ⁇ m is exposed.
  • the solder resist layer 2 having a thickness of 9.5 ⁇ m was filled between the connection pads 3 for connecting electronic components.
  • a circular opening of a solder resist layer having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m is formed on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. Some were exposed.
  • the surface roughness Ra 0.40 ⁇ m.
  • Steps (A) to (D) were carried out in the same manner as in Example 1 except that in the step (C3), the exposure was performed by the contact exposure method.
  • the solder resist layer 2 was filled between the connection pads 3 for electronic component connection up to 5.0 ⁇ m below the surface of the connection pads 3 for electronic component connection.
  • the surface of the solder resist layer 2 is not roughened because the exposure is performed in a non-oxygen atmosphere by sufficiently releasing the air during the contact exposure, and as a result, the thickness of the solder resist layer 2 is increased. Did not decrease.
  • the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was.
  • the conductor wiring 7 having a thickness of 15 ⁇ m is covered with the solder resist layer 2 having a thickness of 30 ⁇ m, and the connection pad 3 for connecting an electronic component having a thickness of 15 ⁇ m is exposed.
  • the solder resist layer 2 having a thickness of 10 ⁇ m was filled between the connection pads 3 for connecting electronic components.
  • a circular opening of the solder resist layer 2 having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m is formed in a part on the external connection pad 4 having a thickness of 15 ⁇ m so that the conductor pad 4 is exposed. It was.
  • the surface roughness Ra was 0.10 ⁇ m.
  • Examples 1 to 6 since there is a solder resist layer 2 having a sufficient thickness between adjacent connection pads 3 for connecting electronic components, it is ensured that an electrical short circuit due to solder occurs when electronic components are mounted. I was able to prevent it. In addition, since there is no residue of the solder resist layer 2 on the connection pads 4 for external connection, a highly reliable wiring board that does not cause poor electrical insulation even when mounted on an external electric board could be produced. . Comparing Examples 1 to 6, the wiring manufactured in Examples 1 to 5 is more preferable than the wiring board manufactured in Example 6 in which the surface of the solder resist layer 2 between the connection pads 3 for connecting electronic components is smooth. The board had higher adhesion to the underfill and better connection reliability.
  • solder resist film manufactured by Taiyo Ink Manufacturing Co., Ltd., trade name: PFR-800 AUS410
  • laminate temperature 75 ° C.
  • suction time 30 seconds
  • pressurization time 10 seconds pressurization time 10 seconds
  • the thickness from the surface of the insulating layer 8 was 38 ⁇ m, and the thickness on the connection pad 4 for external connection was 23 ⁇ m.
  • the thickness of the solder resist layer 2 is 8 ⁇ m thinner than on the second surface where the density of the conductor wiring is larger.
  • the contact exposure was performed at an exposure amount of 200 mJ / cm 2 .
  • C2 A photomask having a pattern in which actinic rays 6 are irradiated in areas other than the circular opening area in order to provide a circular opening area having a diameter of 500 ⁇ m on the external connection pad 4 for the solder resist layer 2 on the second surface. 5 was used for contact exposure at an exposure amount of 200 mJ / cm 2 .
  • the solder resist layer 2 having an average of 20 ⁇ m was thinned to 5.0 ⁇ m below the surface of the connection pad 3 for connection.
  • the surface of the solder resist layer 2 on the first surface was free from uneven processing, and good in-plane uniformity was obtained.
  • the solder resist layer 2 on the second surface was also thinned by an average of 20 ⁇ m, but bubbles in the thinning treatment liquid adhered to the solder resist layer 2 on the non-exposed portion of the second surface, resulting in non-uniform film thickness. There was a place. Further, the residue of the solder resist layer 2 of about 3 ⁇ m remained on the connection pad 4 for external connection.
  • the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was.
  • the conductor wiring 7 having a thickness of 15 ⁇ m is covered with the solder resist layer 2 having a thickness of 30 ⁇ m, and the connection pads 3 for connecting an electronic component having a thickness of 15 ⁇ m are exposed.
  • the solder resist layer 2 having a thickness of 10.0 ⁇ m was filled between the connection pads 3 for connecting electronic components.
  • the second surface was formed with a circular opening of the solder resist layer 2 having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. Residue of the solder resist layer 2 having a thickness of 3 ⁇ m remained on the top.
  • solder resist layer 2 When mounting an electronic component, there was a solder resist layer 2 of sufficient thickness between adjacent connection pads 3 for connecting an electronic component, and an electrical short circuit due to solder could be reliably prevented. When mounting, due to the residue of the solder resist layer 2 remaining on the connection pad 4 for external connection, an electrical insulation failure occurred in the solder bump connection.
  • the surface roughness of the solder resist layer 2 between the adjacent connection pads 3 for connecting electronic components was measured, the surface roughness Ra was 0.03 ⁇ m.
  • the wiring board manufactured in Examples 1 to 5 has better adhesion to the underfill than the wiring board manufactured in Comparative Example 1 in which the solder resist surface between the connection pads 3 for connecting electronic components is smooth. High connection reliability.
  • Examples 7 to 11 are examples relating to the method (2) for manufacturing the wiring board shown in FIGS. 5-1, 5-2, and 5-3.
  • Example 7 Using a semi-additive method, a circuit board 1 (area 170 mm ⁇ 200 mm, conductor thickness 15 ⁇ m, board thickness 0.4 mm) having conductor wirings 7 formed on both surfaces was produced. On the surface (first surface), there is a conductor wiring having a line width of 25 ⁇ m and an interval of 50 ⁇ m used as the connection pad 3 for connecting electronic components. A circular conductor wiring having a diameter of 600 ⁇ m used as the external connection pad 4 is formed on the back surface (second surface).
  • solder resist film manufactured by Taiyo Ink Manufacturing Co., Ltd., trade name: PFR-800 AUS410
  • laminate temperature 75 ° C.
  • suction time 30 seconds
  • pressurization time 10 seconds pressurization time 10 seconds
  • the thickness from the surface of the insulating layer 8 was 38 ⁇ m, and the thickness on the connection pad 4 for external connection was 23 ⁇ m.
  • the thickness of the solder resist layer 2 is 8 ⁇ m thinner than on the second surface where the density of the conductor wiring is larger.
  • the contact exposure was performed at an exposure amount of 200 mJ / cm 2 .
  • C2 A photomask having a pattern in which actinic rays 6 are irradiated in areas other than the circular opening area in order to provide a circular opening area having a diameter of 500 ⁇ m on the external connection pad 4 for the solder resist layer 2 on the second surface. 5 was used for contact exposure at an exposure amount of 200 mJ / cm 2 .
  • the solder resist layer 2 having an average of 10 ⁇ m was thinned to 5.0 ⁇ m on the surface of the connection pad 3 for connection.
  • the surface of the solder resist layer 2 on the first surface was free from uneven processing, and good in-plane uniformity was obtained.
  • the solder resist layer 2 on the second surface was also thinned by an average of 10 ⁇ m, but bubbles in the thinning treatment liquid adhered to the solder resist layer 2 on the non-exposed portion of the second surface, resulting in non-uniform film thickness. There was a place. Further, the residue of the solder resist layer 2 of about 13 ⁇ m remained on the connection pad 4 for external connection.
  • solder resist layer 2 on the first surface When observed with an optical microscope, the surface of the solder resist layer 2 on the first surface was free from uneven processing, and good in-plane uniformity was obtained.
  • solder resist layer 2 on the second surface was also thinned by an average of 10 ⁇ m, but bubbles in the thinning treatment liquid adhered to the solder resist layer 2 on the non-exposed portion of the second surface, resulting in non-uniform film thickness. There was a place. Further, the residue of the solder resist layer 2 of about 3 ⁇ m remained on the connection pad 4 for external connection.
  • the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was.
  • a conductor wiring 7 with a thickness of 15 ⁇ m is covered with a solder resist layer 2 with a thickness of 30 ⁇ m and 19.5 ⁇ m, and an underfill weir with a thickness of 10.5 ⁇ m corresponding to the step.
  • a stop dam was formed.
  • the electronic component connecting connection pads 3 having a thickness of 15 ⁇ m were exposed, and the solder resist layer 2 having a thickness of 9.5 ⁇ m was filled between the adjacent electronic component connecting connection pads 3.
  • a circular opening of the solder resist layer 2 having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m is formed on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. A part of was exposed.
  • a solder having a thickness of 19.5 ⁇ m in a region between the outer periphery 200 ⁇ m away from the ends of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 ⁇ m away from the ends When the surface roughness of the resist layer 2 was measured, the surface roughness Ra was 0.40 ⁇ m. Moreover, when the surface roughness of the soldering resist layer 2 between the adjacent connection pads 3 for electronic component connection was measured, the surface roughness Ra was 0.40 ⁇ m.
  • Example 8 Steps (A) to (D) were performed in the same manner as in Example 7 except that the order of the steps (C1) and (C2) was changed. As a result of observation with an optical microscope, no residue of the solder resist layer 2 was found on the connection pads 3 for connecting electronic components and the connection pads 4 for external connection on both the first surface and the second surface. Further, the solder resist layer 2 was filled up to 5.5 ⁇ m below the surface of the connection pad 3 for connecting electronic components arranged on the first surface.
  • the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was.
  • a conductor wiring 7 with a thickness of 15 ⁇ m is covered with a solder resist layer 2 with a thickness of 30 ⁇ m and 19.5 ⁇ m, and an underfill weir with a thickness of 10.5 ⁇ m corresponding to the step.
  • a stop dam was formed.
  • the electronic component connecting connection pads 3 having a thickness of 15 ⁇ m were exposed, and the solder resist layer 2 having a thickness of 9.5 ⁇ m was filled between the adjacent electronic component connecting connection pads 3.
  • a circular opening of the solder resist layer 2 having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m is formed on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. A part of was exposed.
  • a solder having a thickness of 19.5 ⁇ m in a region between the outer periphery 200 ⁇ m away from the ends of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 ⁇ m away from the ends When the surface roughness of the resist layer 2 was measured, the surface roughness Ra was 0.40 ⁇ m. Moreover, when the surface roughness of the soldering resist layer 2 between the adjacent connection pads 3 for electronic component connection was measured, the surface roughness Ra was 0.40 ⁇ m.
  • Example 9 Steps (A) to (D) were carried out in the same manner as in Example 7 except that the exposure dose in steps (C4) and (C5) was 200 mJ / cm 2 .
  • the exposure dose in steps (C4) and (C5) was 200 mJ / cm 2 .
  • the solder resist layer 2 was filled up to 6.0 ⁇ m below the surface of the connection pad 3 for connecting electronic components arranged on the first surface.
  • the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was.
  • a conductor wiring 7 with a thickness of 15 ⁇ m is covered with a solder resist layer 2 with a thickness of 30 ⁇ m and a thickness of 19 ⁇ m.
  • the connection pad 3 for connecting an electronic component having a thickness of 15 ⁇ m was exposed, and the solder resist layer 2 having a thickness of 9.0 ⁇ m was filled between adjacent connection pads 3 for connecting an electronic component.
  • a circular opening of the solder resist layer 2 having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m is formed on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. A part of was exposed.
  • a 19 ⁇ m thick solder resist layer in a region between the outer periphery 200 ⁇ m away from the ends of the plurality of connection pads 3 for connecting electronic components disposed on the first surface and the outer periphery 400 ⁇ m away from the ends When the surface roughness 2 was measured, the surface roughness Ra was 0.50 ⁇ m. Further, when the surface roughness of the solder resist layer 2 between the adjacent connection pads 3 for connecting electronic components was measured, the surface roughness Ra was 0.50 ⁇ m.
  • Steps (A) to (D) were performed in the same manner as in Example 6 except that the exposure dose in steps (C4) and (C5) was 1000 mJ / cm 2 .
  • the exposure dose in steps (C4) and (C5) was 1000 mJ / cm 2 .
  • the solder resist layer 2 is filled up to 5.0 ⁇ m below the surface of the connection pad 3 for connecting electronic components arranged on the first surface, and the first surface due to the inhibition of oxygen polymerization in the steps (C4) and (C5) The film loss of the solder resist layer 2 was not confirmed.
  • the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was.
  • a conductor wiring 7 with a thickness of 15 ⁇ m is covered with a solder resist layer 2 with a thickness of 30 ⁇ m and a thickness of 20 ⁇ m.
  • the connection pad 3 for connecting an electronic component having a thickness of 15 ⁇ m was exposed, and the solder resist layer 2 having a thickness of 10.0 ⁇ m was filled between adjacent connection pads 3 for connecting an electronic component.
  • a circular opening of the solder resist layer 2 having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m is formed on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. A part of was exposed.
  • a solder resist layer having a thickness of 20 ⁇ m in a region between the outer periphery 200 ⁇ m away from the ends of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 ⁇ m away from the ends When the surface roughness 2 was measured, the surface roughness Ra was 0.30 ⁇ m. Further, when the surface roughness of the solder resist layer 2 between the adjacent connection pads 3 for connecting electronic components was measured, the surface roughness Ra was 0.30 ⁇ m.
  • Example 11 In the steps (C4) and (C5), the steps (A) to (D) were carried out in the same manner as in Example 7 except that the exposure was performed by the contact exposure method. As a result of observation with an optical microscope, no residue of the solder resist layer 2 was found on the connection pads 3 for connecting electronic components and the connection pads 4 for external connection on both the first surface and the second surface. On the first surface, the solder resist layer 2 was filled between the connection pads 3 for electronic component connection up to 5.0 ⁇ m below the surface of the connection pads 3 for electronic component connection. In the steps (C4) and (C5), the surface of the solder resist layer 2 was not roughened because exposure was performed in a non-oxygen atmosphere by sufficiently releasing air during contact exposure. As a result, the solder resist layer was not roughened. The thickness of 2 did not decrease.
  • the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was.
  • a conductor wiring 7 with a thickness of 15 ⁇ m is covered with a solder resist layer 2 with a thickness of 30 ⁇ m and a thickness of 20 ⁇ m.
  • the connection pad 3 for connecting an electronic component having a thickness of 15 ⁇ m was exposed, and the solder resist layer 2 having a thickness of 10.0 ⁇ m was filled between adjacent connection pads 3 for connecting an electronic component.
  • a circular opening of the solder resist layer 2 having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m is formed on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. A part of was exposed.
  • a solder resist layer having a thickness of 20 ⁇ m in a region between the outer periphery 200 ⁇ m away from the ends of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 ⁇ m away from the ends When the surface roughness 2 was measured, the surface roughness Ra was 0.10 ⁇ m. Further, when the surface roughness of the solder resist layer 2 between the adjacent connection pads 3 for connecting electronic components was measured, the surface roughness Ra was 0.10 ⁇ m.
  • Examples 7 to 11 since there is a solder resist layer 2 having a sufficient thickness between adjacent connection pads 3 for connecting electronic components, it is ensured that an electrical short circuit due to solder occurs when the electronic components are mounted. I was able to prevent it. Since there is no residue of the solder resist layer 2 on the connection pad 4 for external connection, a highly reliable wiring board that does not cause an electrical insulation failure when mounted on the external electric board can be produced. Comparing Examples 7 to 11, it is manufactured in Examples 7 to 10 rather than the wiring board manufactured in Example 11 in which the surface of the solder resist layer 2 between and around the connection pads 3 for connecting electronic components is smooth. The printed wiring board had higher adhesion to the underfill and better connection reliability.
  • solder resist film manufactured by Taiyo Ink Manufacturing Co., Ltd., trade name: PFR-800 AUS410
  • laminate temperature 75 ° C.
  • suction time 30 seconds
  • pressurization time 10 seconds pressurization time 10 seconds
  • the thickness from the surface of the insulating layer 8 was 38 ⁇ m, and the thickness on the connection pad 4 for external connection was 23 ⁇ m.
  • the thickness of the solder resist layer 2 is 8 ⁇ m thinner than on the second surface where the density of the conductor wiring is larger.
  • the contact exposure was performed at an exposure amount of 200 mJ / cm 2 .
  • C2 A photomask having a pattern in which actinic rays 6 are irradiated in areas other than the circular opening area in order to provide a circular opening area having a diameter of 500 ⁇ m on the external connection pad 4 for the solder resist layer 2 on the second surface. 5 was used for contact exposure at an exposure amount of 200 mJ / cm 2 .
  • the solder resist layer 2 having an average of 10 ⁇ m was thinned to 5.0 ⁇ m on the surface of the connection pad 3 for connection.
  • the surface of the solder resist layer 2 on the first surface was free from uneven processing, and good in-plane uniformity was obtained.
  • the solder resist layer 2 on the second surface was also thinned by an average of 10 ⁇ m, but bubbles in the thinning treatment liquid adhered to the solder resist layer 2 on the non-exposed portion of the second surface, resulting in non-uniform film thickness. There was a place. Further, the residue of the solder resist layer 2 of about 13 ⁇ m remained on the connection pad 4 for external connection.
  • the actinic ray 6 irradiates the area between the outer periphery 200 ⁇ m away from the ends of the plurality of connection pads 3 for connecting electronic components and the outer periphery 400 ⁇ m away from the ends of the solder resist layer 2 on the first surface.
  • exposure was performed at a dose of 400 mJ / cm 2 by non-contact exposure in an oxygen atmosphere.
  • solder resist layer 2 on the first surface When observed with an optical microscope, the surface of the solder resist layer 2 on the first surface was free from uneven processing, and good in-plane uniformity was obtained.
  • solder resist layer 2 on the second surface was also thinned by an average of 10 ⁇ m, but bubbles in the thinning treatment liquid adhered to the solder resist layer 2 on the non-exposed portion of the second surface, resulting in non-uniform film thickness. There was a place. Further, the residue of the solder resist layer 2 of about 3 ⁇ m remained on the connection pad 4 for external connection.
  • the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was.
  • a conductor wiring 7 with a thickness of 15 ⁇ m is covered with a solder resist layer 2 with a thickness of 30 ⁇ m and 19.5 ⁇ m, and an underfill weir with a thickness of 10.5 ⁇ m corresponding to the step.
  • a stop dam was formed.
  • the electronic component connecting connection pads 3 having a thickness of 15 ⁇ m were exposed, and the solder resist layer 2 having a thickness of 9.5 ⁇ m was filled between the adjacent electronic component connecting connection pads 3.
  • the second surface has a circular opening of the solder resist layer 2 having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m formed on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. Residue of 3 ⁇ m solder resist layer 2 remained on the top.
  • solder resist layer 2 When mounting electronic components, there is a solder resist layer 2 of sufficient thickness between adjacent connection pads 3 for connecting electronic components, which can prevent electrical short circuit due to soldering, but can be mounted on an external electric board. At this time, due to the residue of the solder resist layer 2 remaining on the connection pads 4 for external connection, an electrical insulation failure occurred in the solder bump connection.
  • the surface roughness of the solder resist layer 2 between the adjacent connection pads 3 for connecting electronic components was measured, the surface roughness Ra was 0.03 ⁇ m.
  • the wiring board manufactured in Examples 7 to 11 has better adhesion to the underfill than the wiring board manufactured in Comparative Example 2 in which the solder resist surface between the connection pads 3 for connecting electronic components is smooth. High connection reliability.
  • Examples 12 to 16 are examples relating to the manufacturing method (3) of the wiring board shown in FIGS. 6-1, 6-2, and 6-3.
  • Example 12 Using a semi-additive method, a circuit board 1 (area 170 mm ⁇ 200 mm, conductor thickness 15 ⁇ m, board thickness 0.4 mm) having conductor wirings 7 formed on both surfaces was produced. On the surface (first surface), there is a conductor wiring having a line width of 25 ⁇ m and an interval of 50 ⁇ m used as the connection pad 3 for connecting electronic components. A circular conductor wiring having a diameter of 600 ⁇ m used as the external connection pad 4 is formed on the back surface (second surface).
  • the thickness from the surface of the insulating layer 8 was 20 ⁇ m, and the thickness on the connection pad 3 for connecting electronic components was 5 ⁇ m.
  • the thickness from the surface of the insulating layer 8 was 38 ⁇ m, and the thickness on the connection pad 4 for external connection was 23 ⁇ m.
  • the first solder resist layer 2-1 on the first surface has a pattern in which actinic rays 6 are irradiated to a region outside the outer periphery that is 200 ⁇ m away from the ends of the plurality of connection pads 3 for connecting electronic components. Using the photomask 5, contact exposure was performed with an exposure amount of 200 mJ / cm 2 .
  • the micelle removal treatment by spraying the micelle removal liquid (liquid temperature 25 ° C.), the water washing treatment (liquid temperature 25 ° C.) and the drying treatment are performed, and the thickness of the first solder resist layer 2-1 in the non-exposed portion of the first surface
  • the first solder resist layer 2-1 having an average of 10 ⁇ m was thinned until the thickness became 5.0 ⁇ m below the surface of the connection pad 3 for connecting electronic parts.
  • the surface of the first solder resist layer 2-1 on the first surface was not uneven and good in-plane uniformity was obtained.
  • the first solder resist layer 2-1 on the second surface was also thinned by an average of 10 ⁇ m, but bubbles in the thinning treatment liquid adhered to the first solder resist layer 2-1 on the non-exposed portion of the second surface. However, there was a portion where the film thickness was non-uniform. Further, the residue of the first solder resist layer 2-1 of about 13 ⁇ m remained on the connection pad 4 for external connection.
  • ⁇ Process (C6)> A photo of a pattern in which the active light beam 6 is irradiated to a region outside the outer periphery 400 ⁇ m away from the end of the connection pad 3 for connecting the electronic component to the second solder resist layer 2-2 on the first surface. Using mask 5, contact exposure was performed at an exposure amount of 200 mJ / cm 2 .
  • the first solder resist layer 2-1 and the second solder resist layer 2-2 on the connection pads 3 for electronic component connection and the connection pads 4 for external connection on both the first surface and the second surface were not seen. Further, the first solder resist layer 2-1 was filled up to 5.5 ⁇ m below the surface of the connection pad 3 for connecting electronic parts arranged on the first surface.
  • the step (C3) By non-contact exposure in an oxygen atmosphere in the step (C3), photopolymerization of the surface of the first solder resist layer 2-1 between the connection pads 3 for connecting electronic components arranged on the first surface is suppressed, and as a result, The thickness of the first solder resist layer 2-1 on the first surface was reduced by 0.5 ⁇ m.
  • the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 .
  • the substrate was exposed and subsequently subjected to thermosetting at 150 ° C. for 60 minutes to obtain a wiring board.
  • the conductor wiring 7 with a thickness of 15 ⁇ m is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 with a thickness of 30 ⁇ m and 20 ⁇ m, and the step is A corresponding underfill dam with a thickness of 10 ⁇ m was formed.
  • the electronic component connecting connection pads 3 having a thickness of 15 ⁇ m were exposed, and the first solder resist layer 2-1 having a thickness of 9.5 ⁇ m was filled between the adjacent electronic component connecting connection pads 3.
  • a circular opening of the first solder resist layer 2-1 having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m is formed on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. A part of the connection pad 4 was exposed.
  • a first solder having a thickness of 20 ⁇ m in a region between the outer periphery 200 ⁇ m away from the end of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 ⁇ m away from the end When the surface roughness of the resist layer 2-1 was measured, the surface roughness Ra was 0.05 ⁇ m. Further, when the surface roughness of the first solder resist layer 2-1 in the region between adjacent electronic component connection pads 3 was measured, the surface roughness Ra was 0.40 ⁇ m.
  • Example 13 The steps (A1) to (D1) were carried out in the same manner as in Example 12 except that the order of the steps (C1) and (C2) was changed.
  • residues of the first solder resist layer 2-1 and the second solder resist layer 2-2 on the connection pads 3 for electronic component connection and the connection pads 4 for external connection on both the first surface and the second surface was not seen.
  • the first solder resist layer 2-1 was filled up to 5.5 ⁇ m below the surface of the connection pad 3 for connecting electronic parts arranged on the first surface.
  • the photopolymerization of the surface of the first solder resist layer 2-1 between the connection pads 3 for connecting electronic components arranged on the first surface is suppressed, and as a result, The thickness of the first solder resist layer 2-1 was reduced by 0.5 ⁇ m.
  • the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 .
  • the substrate was exposed and subsequently subjected to thermosetting at 150 ° C. for 60 minutes to obtain a wiring board.
  • the conductor wiring 7 with a thickness of 15 ⁇ m is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 with a thickness of 30 ⁇ m and 20 ⁇ m, and the step is A corresponding underfill dam with a thickness of 10 ⁇ m was formed.
  • the electronic component connecting connection pads 3 having a thickness of 15 ⁇ m were exposed, and the first solder resist layer 2-1 having a thickness of 9.5 ⁇ m was filled between the adjacent electronic component connecting connection pads 3.
  • a circular opening of the first solder resist layer 2-1 having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m is formed on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. A part of the connection pad 4 was exposed.
  • a first solder having a thickness of 20 ⁇ m in a region between the outer periphery 200 ⁇ m away from the end of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 ⁇ m away from the end When the surface roughness of the resist layer 2-1 was measured, the surface roughness Ra was 0.05 ⁇ m. Further, when the surface roughness of the first solder resist layer 2-1 in the region between adjacent electronic component connection pads 3 was measured, the surface roughness Ra was 0.40 ⁇ m.
  • Steps (A1) to (D1) were performed in the same manner as in Example 12 except that the exposure dose in step (C3) was 200 mJ / cm 2 .
  • the exposure dose in step (C3) was 200 mJ / cm 2 .
  • residues of the first solder resist layer 2-1 and the second solder resist layer 2-2 on the connection pads 3 for electronic component connection and the connection pads 4 for external connection on both the first surface and the second surface was not seen.
  • the first solder resist layer 2-1 was filled up to 6.0 ⁇ m below the surface of the connection pad 3 for connecting electronic components arranged on the first surface.
  • the photopolymerization of the surface of the first solder resist layer 2-1 between the connection pads 3 for connecting electronic components arranged on the first surface is suppressed, and as a result, The thickness of the first solder resist layer 2-1 was reduced by 1.0 ⁇ m.
  • the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 .
  • the substrate was exposed and subsequently subjected to thermosetting at 150 ° C. for 60 minutes to obtain a wiring board.
  • the conductor wiring 7 with a thickness of 15 ⁇ m is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 with a thickness of 30 ⁇ m and 20 ⁇ m, and the step is A corresponding underfill dam with a thickness of 10 ⁇ m was formed.
  • connection pad 3 for connecting an electronic component having a thickness of 15 ⁇ m was exposed, and the first solder resist layer 2-1 having a thickness of 9.0 ⁇ m was filled between adjacent connection pads 3 for connecting an electronic component.
  • a circular opening of the first solder resist layer 2-1 having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m is formed on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. A part of the connection pad 4 was exposed.
  • a first solder having a thickness of 20 ⁇ m in a region between the outer periphery 200 ⁇ m away from the end of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 ⁇ m away from the end When the surface roughness of the resist layer 2-1 was measured, the surface roughness Ra was 0.05 ⁇ m. Further, when the surface roughness of the first solder resist layer 2-1 in the region between adjacent electronic component connection pads 3 was measured, the surface roughness Ra was 0.50 ⁇ m.
  • Steps (A1) to (D1) were performed in the same manner as in Example 12 except that the exposure dose in step (C3) was 1000 mJ / cm 2 .
  • the exposure dose in step (C3) was 1000 mJ / cm 2 .
  • residues of the first solder resist layer 2-1 and the second solder resist layer 2-2 on the connection pads 3 for electronic component connection and the connection pads 4 for external connection on both the first surface and the second surface was not seen.
  • the first solder resist layer 2-1 is filled up to 5.0 ⁇ m below the surface of the connection pad 3 for connecting electronic components arranged on the first surface, and the first surface due to inhibition of oxygen polymerization in the step (C3) No film loss of the first solder resist layer 2-1 was confirmed.
  • the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 .
  • the exposure was followed by a thermosetting treatment at 150 ° C. for 60 minutes.
  • the conductor wiring 7 with a thickness of 15 ⁇ m is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 with a thickness of 30 ⁇ m and 20 ⁇ m, and the step is A corresponding underfill dam with a thickness of 10 ⁇ m was formed.
  • connection pad 3 for connecting an electronic component having a thickness of 15 ⁇ m was exposed, and the first solder resist layer 2-1 having a thickness of 10.0 ⁇ m was filled between adjacent connection pads 3 for connecting an electronic component.
  • a circular opening of the first solder resist layer 2-1 having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m is formed on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. A part of the connection pad 4 was exposed.
  • a first solder having a thickness of 20 ⁇ m in a region between the outer periphery 200 ⁇ m away from the end of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 ⁇ m away from the end When the surface roughness of the resist layer 2-1 was measured, the surface roughness Ra was 0.05 ⁇ m. Further, when the surface roughness of the first solder resist layer 2-1 in the region between the adjacent electronic component connection pads 3 was measured, the surface roughness Ra was 0.30 ⁇ m.
  • Step (A1) to Step (D1) were carried out in the same manner as in Example 12 except that the exposure in the contact exposure method was performed in Step (C3).
  • the first solder resist layer 2-1 and the second solder resist layer 2-2 on the connection pads 3 for electronic component connection and the connection pads 4 for external connection on both the first surface and the second surface were not seen.
  • the first solder resist layer 2-1 was filled up to 5.0 ⁇ m below the surface of the connection pad 3 for connecting electronic parts arranged on the first surface.
  • step (C3) the surface of the first solder resist layer 2-1 was not roughened because the exposure was performed in a non-oxygen atmosphere by sufficiently releasing the air during contact exposure. As a result, the first solder resist layer 2-1 was not roughened. The thickness of the resist layer 2-1 did not decrease.
  • the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 .
  • the exposure was followed by a thermosetting treatment at 150 ° C. for 60 minutes.
  • the conductor wiring 7 with a thickness of 15 ⁇ m is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 with a thickness of 30 ⁇ m and 20 ⁇ m, and the step is A corresponding underfill dam with a thickness of 10 ⁇ m was formed.
  • connection pad 3 for connecting an electronic component having a thickness of 15 ⁇ m was exposed, and the first solder resist layer 2-1 having a thickness of 10.0 ⁇ m was filled between adjacent connection pads 3 for connecting an electronic component.
  • a circular opening of the first solder resist layer 2-1 having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m is formed on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. A part of the connection pad 4 was exposed.
  • a first solder having a thickness of 20 ⁇ m in a region between the outer periphery 200 ⁇ m away from the end of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 ⁇ m away from the end When the surface roughness of the resist layer 2-1 was measured, the surface roughness Ra was 0.05 ⁇ m. Further, when the surface roughness of the first solder resist layer 2-1 between the adjacent connection pads 3 for connecting electronic components was measured, the surface roughness Ra was 0.10 ⁇ m.
  • Examples 12 to 16 since the first solder resist layer 2-1 having a sufficient thickness is provided between the adjacent connection pads 3 for connecting electronic components, an electrical short circuit due to solder occurs when the electronic components are mounted. It was possible to prevent this reliably. Since there is no residue of the first solder resist layer 2-1 on the connection pad 4 for external connection, it is possible to manufacture a highly reliable wiring board that does not cause an electrical insulation failure even when mounted on the external electric board. did it. Comparing the examples 12 to 16, the examples 12 to 15 are more suitable than the wiring board manufactured in the example 16 in which the surface of the first solder resist layer 2-1 between the connection pads 3 for connecting the electronic parts is smooth. The manufactured wiring board had higher adhesion to the underfill and better connection reliability.
  • Examples 17 to 21 are examples relating to the method (4) of manufacturing the wiring board shown in FIGS. 7-1, 7-2 and 7-3.
  • Example 17 ⁇ Process (A1)> Using a semi-additive method, a circuit board 1 (area 170 mm ⁇ 200 mm, conductor thickness 15 ⁇ m, board thickness 0.4 mm) having conductor wirings 7 formed on both surfaces was produced. On the surface (first surface), there is a conductor wiring having a line width of 25 ⁇ m and an interval of 50 ⁇ m used as the connection pad 3 for connecting electronic components. A circular conductor wiring having a diameter of 600 ⁇ m used as the external connection pad 4 is formed on the back surface (second surface).
  • the thickness from the surface of the insulating layer 8 was 20 ⁇ m, and the thickness on the connection pad 3 for connecting electronic components was 5 ⁇ m.
  • the thickness from the surface of the insulating layer 8 was 38 ⁇ m, and the thickness on the connection pad 4 for external connection was 23 ⁇ m.
  • the first solder resist layer 2-1 on the first surface has a pattern in which actinic rays 6 are irradiated to a region outside the outer periphery that is 200 ⁇ m away from the ends of the plurality of connection pads 3 for connecting electronic components. Using the photomask 5, contact exposure was performed with an exposure amount of 200 mJ / cm 2 .
  • the micelle removal treatment by spraying the micelle removal liquid (liquid temperature 25 ° C.), the water washing treatment (liquid temperature 25 ° C.) and the drying treatment are performed, and the thickness of the first solder resist layer 2-1 in the non-exposed portion of the first surface
  • the first solder resist layer 2-1 having an average of 10 ⁇ m was thinned until the thickness became 5.0 ⁇ m below the surface of the connection pad 3 for connecting electronic parts.
  • the surface of the first solder resist layer 2-1 on the first surface was not uneven and good in-plane uniformity was obtained.
  • the first solder resist layer 2-1 on the second surface was also thinned by an average of 10 ⁇ m, but bubbles in the thinning treatment liquid adhered to the first solder resist layer 2-1 on the non-exposed portion of the second surface. However, there was a portion where the film thickness was non-uniform. Further, the residue of the first solder resist layer 2-1 of about 13 ⁇ m remained on the connection pad 4 for external connection.
  • ⁇ Process (A2)> The first solder on the first surface of the circuit board 1 that has been processed up to the step (D) by using a vacuum laminator to complete a solder resist film having a thickness of 15 ⁇ m (trade name: PFR-800 AUS410, manufactured by Taiyo Ink Manufacturing Co., Ltd.) A vacuum thermocompression bonding was performed on the resist layer 2-1 (lamination temperature 75 ° C., suction time 30 seconds, pressurization time 10 seconds). As a result, the second solder resist layer 2-2 on the first surface was formed. In the second solder resist layer 2-2 on the first surface, the thickness from the surface of the insulating layer 8 was 30 ⁇ m.
  • ⁇ Process (C6)> A photo of a pattern in which the active light beam 6 is irradiated to a region outside the outer periphery 400 ⁇ m away from the end of the connection pad 3 for connecting the electronic component to the second solder resist layer 2-2 on the first surface. Using mask 5, contact exposure was performed at an exposure amount of 200 mJ / cm 2 .
  • the first solder resist layer 2-1 was filled up to 5.5 ⁇ m below the surface of the connection pad 3 for connecting electronic parts arranged on the first surface.
  • photopolymerization of the surface of the first solder resist layer 2-1 between the connection pads 3 for connecting electronic components arranged on the first surface is suppressed, and as a result, The thickness of the first solder resist layer 2-1 on the first surface was reduced by 0.5 ⁇ m.
  • the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 .
  • the substrate was exposed and subsequently subjected to thermosetting at 150 ° C. for 60 minutes to obtain a wiring board.
  • the conductor wiring 7 with a thickness of 15 ⁇ m is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 with a thickness of 30 ⁇ m and 20 ⁇ m, and the step is A corresponding underfill dam with a thickness of 10 ⁇ m was formed.
  • the electronic component connecting connection pads 3 having a thickness of 15 ⁇ m were exposed, and the first solder resist layer 2-1 having a thickness of 9.5 ⁇ m was filled between the adjacent electronic component connecting connection pads 3.
  • a circular opening of the first solder resist layer 2-1 having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m is formed on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. A part of the connection pad 4 was exposed.
  • a first solder having a thickness of 20 ⁇ m in a region between the outer periphery 200 ⁇ m away from the end of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 ⁇ m away from the end When the surface roughness of the resist layer 2-1 was measured, the surface roughness Ra was 0.05 ⁇ m. Further, when the surface roughness of the first solder resist layer 2-1 in the region between adjacent electronic component connection pads 3 was measured, the surface roughness Ra was 0.40 ⁇ m.
  • Example 18 The steps (A1) to (D2) were performed in the same manner as in Example 17 except that the order of the steps (C1) and (C2) was changed.
  • residues of the first solder resist layer 2-1 and the second solder resist layer 2-2 on the connection pads 3 for electronic component connection and the connection pads 4 for external connection on both the first surface and the second surface was not seen.
  • the first solder resist layer 2-1 was filled up to 5.5 ⁇ m below the surface of the connection pad 3 for connecting electronic parts arranged on the first surface.
  • the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 .
  • the substrate was exposed and subsequently subjected to thermosetting at 150 ° C. for 60 minutes to obtain a wiring board.
  • the conductor wiring 7 with a thickness of 15 ⁇ m is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 with a thickness of 30 ⁇ m and 20 ⁇ m, and the step is A corresponding underfill dam with a thickness of 10 ⁇ m was formed.
  • the electronic component connecting connection pads 3 having a thickness of 15 ⁇ m were exposed, and the first solder resist layer 2-1 having a thickness of 9.5 ⁇ m was filled between the adjacent electronic component connecting connection pads 3.
  • a circular opening of the first solder resist layer 2-1 having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m is formed on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. A part of the connection pad 4 was exposed.
  • a first solder having a thickness of 20 ⁇ m in a region between the outer periphery 200 ⁇ m away from the end of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 ⁇ m away from the end When the surface roughness of the resist layer 2-1 was measured, the surface roughness Ra was 0.05 ⁇ m. Further, when the surface roughness of the first solder resist layer 2-1 in the region between adjacent electronic component connection pads 3 was measured, the surface roughness Ra was 0.40 ⁇ m.
  • Steps (A1) to (D2) were carried out in the same manner as in Example 17 except that the exposure amount in step (C3) was 200 mJ / cm 2 .
  • the exposure amount in step (C3) was 200 mJ / cm 2 .
  • residues of the first solder resist layer 2-1 and the second solder resist layer 2-2 on the connection pads 3 for electronic component connection and the connection pads 4 for external connection on both the first surface and the second surface was not seen.
  • the first solder resist layer 2-1 was filled up to 6.0 ⁇ m below the surface of the connection pad 3 for connecting electronic components arranged on the first surface.
  • the photopolymerization of the surface of the first solder resist layer 2-1 between the connection pads 3 for connecting electronic components arranged on the first surface is suppressed, and as a result, The thickness of the first solder resist layer 2-1 on the first surface was reduced by 1.0 ⁇ m.
  • the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 .
  • the substrate was exposed and subsequently subjected to thermosetting at 150 ° C. for 60 minutes to obtain a wiring board.
  • the conductor wiring 7 with a thickness of 15 ⁇ m is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 with a thickness of 30 ⁇ m and 20 ⁇ m, and the step is A corresponding underfill dam with a thickness of 10 ⁇ m was formed.
  • connection pad 3 for connecting an electronic component having a thickness of 15 ⁇ m was exposed, and the first solder resist layer 2-1 having a thickness of 9.0 ⁇ m was filled between adjacent connection pads 3 for connecting an electronic component.
  • a circular opening of the first solder resist layer 2-1 having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m is formed on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. A part of the connection pad 4 was exposed.
  • a first solder having a thickness of 20 ⁇ m in a region between the outer periphery 200 ⁇ m away from the end of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 ⁇ m away from the end When the surface roughness of the resist layer 2-1 was measured, the surface roughness Ra was 0.05 ⁇ m. Further, when the surface roughness of the first solder resist layer 2-1 in the region between adjacent electronic component connection pads 3 was measured, the surface roughness Ra was 0.50 ⁇ m.
  • Steps (A1) to (D2) were carried out in the same manner as in Example 17 except that the exposure dose in step (C3) was 1000 mJ / cm 2 .
  • the exposure dose in step (C3) was 1000 mJ / cm 2 .
  • residues of the first solder resist layer 2-1 and the second solder resist layer 2-2 on the connection pads 3 for electronic component connection and the connection pads 4 for external connection on both the first surface and the second surface was not seen.
  • the first solder resist layer 2-1 is filled up to 5.0 ⁇ m below the surface of the connection pad 3 for connecting electronic components arranged on the first surface, and the first surface due to inhibition of oxygen polymerization in the step (C3) No film loss of the first solder resist layer 2-1 was confirmed.
  • the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 .
  • the substrate was exposed and subsequently subjected to thermosetting at 150 ° C. for 60 minutes to obtain a wiring board.
  • the conductor wiring 7 with a thickness of 15 ⁇ m is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 with a thickness of 30 ⁇ m and 20 ⁇ m, and the step is A corresponding underfill dam with a thickness of 10 ⁇ m was formed.
  • connection pad 3 for connecting an electronic component having a thickness of 15 ⁇ m was exposed, and the first solder resist layer 2-1 having a thickness of 10.0 ⁇ m was filled between adjacent connection pads 3 for connecting an electronic component.
  • a circular opening of the first solder resist layer 2-1 having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m is formed on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. A part of the connection pad 4 was exposed.
  • a first solder having a thickness of 20 ⁇ m in a region between the outer periphery 200 ⁇ m away from the end of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 ⁇ m away from the end When the surface roughness of the resist layer 2-1 was measured, the surface roughness Ra was 0.05 ⁇ m. Further, when the surface roughness of the first solder resist layer 2-1 in the region between the adjacent electronic component connection pads 3 was measured, the surface roughness Ra was 0.30 ⁇ m.
  • Step (A1) to Step (D2) were carried out in the same manner as in Example 17 except that the exposure in the contact exposure method was performed in Step (C3).
  • the first solder resist layer 2-1 was filled up to 5.0 ⁇ m below the surface of the connection pad 3 for connecting electronic parts arranged on the first surface.
  • step (C3) the surface of the first solder resist layer 2-1 was not roughened because the exposure was performed in a non-oxygen atmosphere by sufficiently releasing the air during contact exposure. As a result, the first solder resist layer 2-1 was not roughened. The thickness of the resist layer 2-1 did not decrease.
  • the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 .
  • the exposure was followed by a thermosetting treatment at 150 ° C. for 60 minutes.
  • the conductor wiring 7 with a thickness of 15 ⁇ m is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 with a thickness of 30 ⁇ m and 20 ⁇ m, and the step is A corresponding underfill dam with a thickness of 10 ⁇ m was formed.
  • connection pad 3 for connecting an electronic component having a thickness of 15 ⁇ m was exposed, and the first solder resist layer 2-1 having a thickness of 10.0 ⁇ m was filled between adjacent connection pads 3 for connecting an electronic component.
  • a circular opening of the first solder resist layer 2-1 having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m is formed on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. A part of the connection pad 4 was exposed.
  • a first solder having a thickness of 20 ⁇ m in a region between the outer periphery 200 ⁇ m away from the end of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 ⁇ m away from the end When the surface roughness of the resist layer 2-1 was measured, the surface roughness Ra was 0.05 ⁇ m. Further, when the surface roughness of the first solder resist layer 2-2 between the adjacent connection pads 3 for connecting electronic components was measured, the surface roughness Ra was 0.10 ⁇ m.
  • Examples 17 to 21 since the first solder resist layer 2-1 having a sufficient thickness is provided between adjacent connection pads 3 for connecting electronic components, an electrical short circuit due to solder occurs when the electronic components are mounted. It was possible to prevent this reliably. Since there is no residue of the first solder resist layer 2-1 on the connection pad 4 for external connection, it is possible to manufacture a highly reliable wiring board that does not cause an electrical insulation failure even when mounted on the external electric board. did it. Comparing Examples 17 to 21, in Examples 17 to 20, the surface of the first solder resist layer 2-1 between the connection pads 3 for connecting electronic components is smoother than the wiring board manufactured in Example 21. The manufactured wiring board had higher adhesion to the underfill and better connection reliability.
  • Examples 22 to 25 are examples relating to the manufacturing method (5) of the wiring board shown in FIGS. 8-1, FIG. 8-2, and FIG. 8-3.
  • Example 22 ⁇ Process (A1)> Using a semi-additive method, a circuit board 1 (area 170 mm ⁇ 200 mm, conductor thickness 15 ⁇ m, board thickness 0.4 mm) having conductor wirings 7 formed on both surfaces was produced. On the surface (first surface), there is a conductor wiring having a line width of 25 ⁇ m and an interval of 50 ⁇ m used as the connection pad 3 for connecting electronic components. A circular conductor wiring having a diameter of 600 ⁇ m used as the external connection pad 4 is formed on the back surface (second surface).
  • the thickness from the surface of the insulating layer 8 was 20 ⁇ m, and the thickness on the connection pad 3 for connecting electronic components was 5 ⁇ m.
  • the thickness from the surface of the insulating layer 8 was 38 ⁇ m, and the thickness on the connection pad 4 for external connection was 23 ⁇ m.
  • the micelle removal treatment by spraying the micelle removal liquid (liquid temperature 25 ° C.), the water washing treatment (liquid temperature 25 ° C.) and the drying treatment are performed, and the thickness of the first solder resist layer 2-1 in the non-exposed portion of the first surface
  • the first solder resist layer 2-1 having an average of 10 ⁇ m was thinned until the thickness became 5.0 ⁇ m below the surface of the connection pad 3 for connecting electronic parts.
  • the surface of the first solder resist layer 2-1 on the first surface was not uneven and good in-plane uniformity was obtained.
  • the first solder resist layer 2-1 on the second surface was also thinned by an average of 10 ⁇ m, but bubbles in the thinning treatment liquid adhered to the first solder resist layer 2-1 on the non-exposed portion of the second surface. However, there was a portion where the film thickness was non-uniform. Further, the residue of the first solder resist layer 2-1 of about 13 ⁇ m remained on the connection pad 4 for external connection.
  • ⁇ Process (A2)> The first solder on the first surface of the circuit board 1 that has completed the process up to step (C) using a vacuum laminator to complete a 20 ⁇ m thick solder resist film (manufactured by Taiyo Ink Manufacturing Co., Ltd., product name: PFR-800 AUS410).
  • a vacuum thermocompression bonding was performed on the resist layer 2-1 (lamination temperature 75 ° C., suction time 30 seconds, pressurization time 10 seconds).
  • the second solder resist layer 2-2 on the first surface was formed.
  • the thickness from the surface of the insulating layer 8 was 30 ⁇ m.
  • ⁇ Process (C6)> A photo of a pattern in which the active light beam 6 is irradiated to a region outside the outer periphery 400 ⁇ m away from the end of the connection pad 3 for connecting the electronic component to the second solder resist layer 2-2 on the first surface. Using mask 5, contact exposure was performed at an exposure amount of 200 mJ / cm 2 .
  • the micelle removal treatment by spraying the micelle removal solution (liquid temperature 25 ° C.), the water washing treatment (liquid temperature 25 ° C.) and the drying treatment are performed, and the thickness of the second solder resist layer 2-2 in the non-exposed portion of the first surface
  • the second solder resist layer 2-2 having an average thickness of 10 ⁇ m was thinned until the thickness became 5.0 ⁇ m on the surface of the connection pad 3 for connecting electronic components.
  • the surface of the second solder resist layer 2-2 on the first surface was not uneven and good in-plane uniformity was obtained.
  • the first solder resist layer 2-1 on the second surface was also thinned by an average of 10 ⁇ m, but bubbles in the thinning treatment liquid adhered to the first solder resist layer 2-1 on the non-exposed portion of the second surface. However, there was a portion where the film thickness was non-uniform. Further, the residue of the first solder resist layer 2-1 of about 3 ⁇ m remained on the connection pad 4 for external connection.
  • ⁇ Process (C7)> A photo of a pattern in which the active light beam 6 is irradiated to a region outside the outer periphery 200 ⁇ m away from the end of the connection pad 3 for connecting the electronic component to the second solder resist layer 2-2 on the first surface
  • the mask 5 was used for exposure at an exposure amount of 400 mJ / cm 2 by non-contact exposure in an oxygen atmosphere.
  • the first solder resist layer 2-1 and the second solder resist layer 2-2 on the connection pads 3 for electronic component connection and the connection pads 4 for external connection on both the first surface and the second surface were not seen. Further, the first solder resist layer 2-1 was filled up to 5.5 ⁇ m below the surface of the connection pad 3 for connecting electronic parts arranged on the first surface.
  • the step (C3) By non-contact exposure in an oxygen atmosphere in the step (C3), photopolymerization of the surface of the first solder resist layer 2-1 between the connection pads 3 for connecting electronic components arranged on the first surface is suppressed, and as a result, The thickness of the first solder resist layer 2-1 on the first surface was reduced by 0.5 ⁇ m.
  • the outer periphery separated from the ends of the plurality of connection pads 3 for connecting electronic components arranged on the first surface by 200 ⁇ m and the outer periphery separated from the ends by 400 ⁇ m The photopolymerization of the surface of the second solder resist layer 2-2 having a thickness of 20 ⁇ m in the region between the second solder resist layer 2-2 is suppressed, and as a result, the thickness of the surface of the second solder resist layer 2-2 having a thickness of 20 ⁇ m is reduced to 0. It was reduced by 5 ⁇ m.
  • the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 .
  • the substrate was exposed and subsequently subjected to thermosetting at 150 ° C. for 60 minutes to obtain a wiring board.
  • the conductor wiring 7 having a thickness of 15 ⁇ m is covered with the second solder resist layer 2-2 having a thickness of 30 ⁇ m and 19.5 ⁇ m, and the thickness corresponding to the step is 10.5 ⁇ m.
  • An underfill weir dam was formed.
  • the electronic component connecting connection pads 3 having a thickness of 15 ⁇ m were exposed, and the first solder resist layer 2-1 having a thickness of 9.5 ⁇ m was filled between the adjacent electronic component connecting connection pads 3.
  • a circular opening of the first solder resist layer 2-1 having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m is formed on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. A part of the connection pad 4 was exposed.
  • the surface roughness of the two solder resist layer 2-2 was measured, the surface roughness Ra was 0.40 ⁇ m.
  • the surface roughness of the first solder resist layer 2-1 in the region between adjacent electronic component connection pads 3 was measured, the surface roughness Ra was 0.40 ⁇ m.
  • Steps (A1) to (D1) were performed in the same manner as in Example 22 except that the exposure dose in steps (C3) and (C7) was 200 mJ / cm 2 .
  • the exposure dose in steps (C3) and (C7) was 200 mJ / cm 2 .
  • residues of the first solder resist layer 2-1 and the second solder resist layer 2-2 on the connection pads 3 for electronic component connection and the connection pads 4 for external connection on both the first surface and the second surface was not seen.
  • the first solder resist layer 2-1 was filled up to 6.0 ⁇ m below the surface of the connection pad 3 for connecting electronic components arranged on the first surface.
  • the photopolymerization of the surface of the first solder resist layer 2-1 between the connection pads 3 for connecting electronic components arranged on the first surface is suppressed, and as a result, The thickness of the first solder resist layer 2-1 on the first surface was reduced by 1.0 ⁇ m.
  • the outer periphery separated from the ends of the plurality of connection pads 3 for connecting electronic components arranged on the first surface by 200 ⁇ m and the outer periphery separated from the ends by 400 ⁇ m
  • the photopolymerization of the surface of the second solder resist layer 2-2 having a thickness of 20 ⁇ m in the region between the first and second layers is suppressed. As a result, the thickness of the surface of the second solder resist layer 2-2 having a thickness of 20 ⁇ m is reduced to 1. It was reduced by 0.0 ⁇ m.
  • the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and subsequently 150 A wiring board was obtained by performing a thermosetting treatment at 60 ° C. for 60 minutes.
  • the conductor wiring 7 having a thickness of 15 ⁇ m is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 having a thickness of 30 ⁇ m and 19 ⁇ m, and the step is A corresponding underfill weir dam with a thickness of 11 ⁇ m was formed.
  • connection pad 3 for connecting an electronic component having a thickness of 15 ⁇ m was exposed, and the first solder resist layer 2-1 having a thickness of 9.0 ⁇ m was filled between adjacent connection pads 3 for connecting an electronic component.
  • a circular opening of the first solder resist layer 2-1 having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m is formed on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. A part of the connection pad 4 was exposed.
  • a second solder having a thickness of 19 ⁇ m in a region between the outer periphery 200 ⁇ m away from the ends of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 ⁇ m away from the ends
  • the surface roughness Ra was 0.50 ⁇ m.
  • the surface roughness of the first solder resist layer 2-1 in the region between adjacent electronic component connection pads 3 was measured, the surface roughness Ra was 0.50 ⁇ m.
  • Steps (A1) to (D1) were performed in the same manner as in Example 22 except that the exposure dose in steps (C3) and (C7) was 1000 mJ / cm 2 .
  • the exposure dose in steps (C3) and (C7) was 1000 mJ / cm 2 .
  • the first solder resist layer 2-1 is filled up to 5.0 ⁇ m below the surface of the connection pad 3 for connecting the electronic parts arranged on the first surface, and oxygen polymerization inhibition in the steps (C3) and (C7) No film loss of the first solder resist layer 2-1 on the first surface and the second solder resist layer 2-2 on the first surface due to was confirmed.
  • the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 .
  • the substrate was exposed and subsequently subjected to thermosetting at 150 ° C. for 60 minutes to obtain a wiring board.
  • the conductor wiring 7 with a thickness of 15 ⁇ m is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 with a thickness of 30 ⁇ m and 20 ⁇ m, and the step is A corresponding underfill dam with a thickness of 10 ⁇ m was formed.
  • connection pad 3 for connecting an electronic component having a thickness of 15 ⁇ m was exposed, and the first solder resist layer 2-1 having a thickness of 10.0 ⁇ m was filled between adjacent connection pads 3 for connecting an electronic component.
  • a circular opening of the first solder resist layer 2-1 having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m is formed on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. A part of the connection pad 4 was exposed.
  • a second solder having a thickness of 20 ⁇ m in a region between the outer periphery 200 ⁇ m away from the end of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 ⁇ m away from the end
  • the surface roughness Ra was 0.30 ⁇ m.
  • the surface roughness of the first solder resist layer 2-1 in the region between the adjacent electronic component connection pads 3 was measured, the surface roughness Ra was 0.30 ⁇ m.
  • steps (C3) and (C7) steps (A1) to (D1) were performed in the same manner as in Example 22 except that the exposure was performed by the contact exposure method.
  • steps (C3) and (C7) residues of the first solder resist layer 2-1 and the second solder resist layer 2-2 on the connection pads 3 for electronic component connection and the connection pads 4 for external connection on both the first surface and the second surface was not seen.
  • the first solder resist layer 2-1 was filled up to 5.0 ⁇ m below the surface of the connection pad 3 for connecting electronic parts arranged on the first surface.
  • the surface of the solder resist layer 2 was not roughened because the exposure was performed in a non-oxygen atmosphere by sufficiently releasing the air during contact exposure. The thicknesses of the first solder resist layer 2-1 and the second solder resist layer 2-2 on the first surface did not decrease.
  • the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 .
  • the exposure was followed by a thermosetting treatment at 150 ° C. for 60 minutes.
  • the conductor wiring 7 with a thickness of 15 ⁇ m is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 with a thickness of 30 ⁇ m and 20 ⁇ m, and the step is A corresponding underfill dam with a thickness of 10 ⁇ m was formed.
  • connection pad 3 for connecting an electronic component having a thickness of 15 ⁇ m was exposed, and the first solder resist layer 2-1 having a thickness of 10 ⁇ m was filled between the connection pads 3 for connecting an electronic component adjacent to each other.
  • a circular opening of the first solder resist layer 2-1 having a thickness of 38 ⁇ m and a diameter of 500 ⁇ m is formed on a part of the connection pad 4 for external connection having a thickness of 15 ⁇ m. A part of the connection pad 4 was exposed.
  • a second solder having a thickness of 20 ⁇ m in a region between the outer periphery 200 ⁇ m away from the end of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 ⁇ m away from the end
  • the surface roughness Ra was 0.10 ⁇ m.
  • the surface roughness of the first solder resist layer 2-1 between the adjacent connection pads 3 for connecting electronic components was measured, the surface roughness Ra was 0.10 ⁇ m.
  • Examples 22 to 25 since the first solder resist layer 2-1 having a sufficient thickness is provided between the adjacent connection pads 3 for connecting electronic components, an electrical short circuit due to solder occurs when the electronic components are mounted. It was possible to prevent this reliably. Since there is no residue of the first solder resist layer 2-1 on the connection pad 4 for external connection, it is possible to manufacture a highly reliable wiring board that does not cause an electrical insulation failure even when mounted on the external electric board. did it. Comparing Examples 22 to 25, the surfaces of the first solder resist layer 2-1 between the electronic component connecting connection pads 3 and the second solder resist layer 2-2 around the electronic component connecting connection pads 3 are smooth. Compared to the wiring board manufactured in Example 25, the wiring boards manufactured in Examples 22 to 24 had higher adhesion to the underfill and better connection reliability.
  • connection pads 3 for connecting electronic components on the first surface is exposed from the solder resist layer 2.
  • the solder resist layer 2 is provided, it is possible to reliably prevent an electrical short circuit due to solder when the electronic component is mounted. Further, the adhesive strength between the insulating layer 8 and the connection pad 3 for connecting electronic parts and the adhesive strength between the connection pad 3 for connecting electronic parts and solder are increased, and high connection reliability is obtained.
  • the exposure in the step (C3) is performed by a non-contact exposure method in an oxygen atmosphere, so the surface of the solder resist layer 2 around the connection pad 3 for connecting electronic parts is sufficiently roughened, so Good adhesion to the fill and high connection reliability. Moreover, since there is no residue of the solder resist layer 2 on the surface of the external connection pad 4 on the second surface, there is no electrical insulation failure in solder connection when mounting on an external substrate, and high connection reliability is achieved. can get.
  • connection pads 3 for connecting electronic components As described above, in the wiring boards manufactured according to Examples 7 to 26, part of the connection pads 3 for connecting electronic components is exposed from the solder resist layer 2 (first solder resist layer 2-1). And an underfill dam for preventing underfill formed by the two-stage solder resist layer 2 (the first solder resist layer 2-1 and the second solder resist layer 2-2).
  • an underfill dam for preventing underfill formed by the two-stage solder resist layer 2 the first solder resist layer 2-1 and the second solder resist layer 2-2.
  • the connection pads 3 for connecting electronic components are arranged at high density, a solder resist layer 2 (first solder resist layer 2-1) having a sufficient thickness between the adjacent connection pads 3 for connecting electronic components.
  • the adhesive strength between the insulating layer 8 and the connection pad 3 for connecting electronic parts and the adhesive strength between the connection pad 3 for connecting electronic parts and solder are increased, and high connection reliability is obtained. Further, the steps (C4) and (C5) of the method (2) for manufacturing the wiring substrate, the methods (3), (4), (5) for manufacturing the wiring substrate (C3), and the method (5) for manufacturing the wiring substrate.
  • the exposure in the step (C7) is performed by a non-contact exposure method in an oxygen atmosphere, the solder resist layer 2 (first solder resist layer 2-1) between or around the connection pads 3 for connecting electronic components is used.
  • Second solder resist layer 2-2 Since the surface is sufficiently roughened, adhesion to the underfill is good and high connection reliability is obtained. Further, since there is no residue of the first solder resist layer 2-1 on the surface of the external connection pad 4 on the second surface, there is no occurrence of electrical insulation failure in solder connection when mounted on the external substrate. Connection reliability can be obtained.
  • the method for manufacturing a wiring board according to the present invention can be applied, for example, to an application for manufacturing a wiring board having a plurality of connection pads for connecting electronic components such as semiconductor chips and other printed wiring boards.
  • Circuit Board 2 Solder Resist Layer 2-1 First Solder Resist Layer 2-2 Second Solder Resist Layer 3 Electronic Component Connection Pad, First Side Connection Pad 4 External Connection Connection Pad, Second Side Connection Pad 5
  • Photomask 6 Actinic ray 7 Conductor wiring 8 Insulating layer

Abstract

The present invention is a manufacturing method for a wiring board, which is characterized in including steps for: (A) forming solder mask layers of different thickness on both surfaces of a circuit board; (C1) for a solder mask layer of a first surface which is of thinner thickness than a solder mask layer of a second surface, exposing portions other than areas to be thinned in step (B), which is a later step; (C2) for the solder mask layer of the second surface, exposing portions other than areas to be developed in step (D), which is a later step; (B) by way of a thin-film processing solution, thinning the solder mask layer of the first surface of the non-exposed portions until reaching thicknesses that are less than or equal to connection pads; (C3) for the solder mask layer of the first surface, exposing the area-portions that have been thinned in step (B); and (D) removing, by way of a developer solution, the solder mask layers of the non-exposed portions of the second surface.

Description

配線基板の製造方法Wiring board manufacturing method
 本発明は配線基板の製造方法に関し、より詳しくは、半導体チップや他のプリント配線板等の電子部品を接続するための複数の接続パッドを有する配線基板の製造方法に関する。 The present invention relates to a method for manufacturing a wiring board, and more particularly to a method for manufacturing a wiring board having a plurality of connection pads for connecting electronic components such as a semiconductor chip and other printed wiring boards.
 各種電気機器内部の配線基板は、その片表面又は両表面に、絶縁層と、絶縁層の表面に形成された導体配線とを有する回路基板を有している。また、配線基板の回路基板表面には、半田付け不要な導体配線に半田が付着しないようにするために、半田付けされない部分全面にソルダーレジスト層が形成されている。このソルダーレジスト層は、導体配線の酸化防止、電気絶縁及び外部環境からの保護という役割を果たしている。 A wiring board inside various electric devices has a circuit board having an insulating layer and a conductor wiring formed on the surface of the insulating layer on one or both surfaces thereof. Also, a solder resist layer is formed on the entire surface of the circuit board of the wiring board so that the solder does not adhere to the conductor wiring that does not require soldering. The solder resist layer plays a role of preventing the conductor wiring from being oxidized, electrically insulating, and protecting from the external environment.
 また、配線基板上に半導体チップ等の電子部品を搭載する場合、配線基板の表面には、半導体チップ、他のプリント配線板等の電子部品と接続するための多数の接続パッドが形成されている。接続パッドは、回路基板表面の導体配線の全体又は一部をソルダーレジスト層から露出させることにより作製されている。近年、この接続パッドの高密度化が進んでおり、配置される接続パッド同士のピッチが狭くなっていて、例えば50μm以下の狭ピッチもある。 When mounting electronic components such as semiconductor chips on a wiring board, a large number of connection pads are formed on the surface of the wiring board for connecting to electronic components such as semiconductor chips and other printed wiring boards. . The connection pad is produced by exposing the whole or part of the conductor wiring on the surface of the circuit board from the solder resist layer. In recent years, the density of the connection pads has been increased, and the pitch between the connection pads to be arranged is narrow, for example, there is a narrow pitch of 50 μm or less.
 高密度に配置された接続パッドに電子部品を搭載する方法として、フリップチップ接続による方法がある。フリップチップ接続とは、配線基板上に設けた電子部品接続用接続パッドの一部を電子部品の電極端子の配置に対応した並びに露出させ、この電子部品接続用接続パッドの露出部と電子部品の電極端子とを対向させ、半田バンプを介して電気的に接続することをいう。 As a method of mounting electronic components on connection pads arranged at high density, there is a method by flip chip connection. In flip chip connection, a part of the connection pad for connecting an electronic component provided on the wiring board is exposed corresponding to the arrangement of the electrode terminals of the electronic component, and the exposed part of the connection pad for connecting the electronic component and the electronic component are connected. It means that the electrode terminals are opposed to each other and electrically connected via solder bumps.
 接続パッドには、ソルダーレジスト層を部分的に除去し、接続パッド表面の全体又は一部を露出させているSMD(Solder Mask Defined)構造と、ソルダーレジスト層を部分的に除去し、接続パッドを完全に露出させているNSMD(Non Solder Mask Defined)構造がある。 For the connection pad, the solder resist layer is partially removed to expose the whole or part of the connection pad surface, and the solder mask layer is partially removed to remove the connection pad. There is an NSMD (Non Solder Mask Defined) structure that is completely exposed.
 図1Aは、SMD構造を有する配線基板の一例を示す概略断面図である。絶縁層8表面に導体配線7と導体配線の一部である接続パッド3が設けられた回路基板1表面にソルダーレジスト層2が形成されている。接続パッド3はその周辺近傍がソルダーレジスト層2によって被覆されている。そのため、機械的衝撃による接続パッド3の剥れや接続パッド3からの引き出し配線におけるネック部の断線が起こりにくいという利点がある。その反面、電子部品の電極端子とこれに対応する接続パッド3との電気的な接続を確実に固定するために、接続パッド3の露出面に形成する接合部に必要な半田量を確保する必要があり、接続パッド3が大型化してしまうため、電子部品の小型化及び高性能化に伴う接続パッド3の高密度化の要求に対応することが難しくなってきている。 FIG. 1A is a schematic cross-sectional view showing an example of a wiring board having an SMD structure. A solder resist layer 2 is formed on the surface of the circuit board 1 provided with the conductor wiring 7 and the connection pads 3 which are part of the conductor wiring on the surface of the insulating layer 8. The periphery of the connection pad 3 is covered with the solder resist layer 2. Therefore, there is an advantage that peeling of the connection pad 3 due to mechanical impact and disconnection of the neck portion in the lead-out wiring from the connection pad 3 are unlikely to occur. On the other hand, in order to securely fix the electrical connection between the electrode terminal of the electronic component and the corresponding connection pad 3, it is necessary to secure the amount of solder necessary for the joint formed on the exposed surface of the connection pad 3. Since the size of the connection pad 3 is increased, it is difficult to meet the demand for higher density of the connection pad 3 due to the downsizing and higher performance of electronic components.
 図1Bは、NSMD構造を有する配線基板の一例を示す概略断面図である。絶縁層8表面に導体配線7と導体配線の一部である接続パッド3が設けられた回路基板1表面にソルダーレジスト層2が形成されている。ソルダーレジスト層2の同一開口内に複数の接続パッド3が配置されていて、これらの接続パッド3はソルダーレジスト層2から露出している。NSMD構造では、接続パッド3は、その周辺近傍のソルダーレジスト層2が完全に除去され、接続パッド3の側面が完全に露出している。そのため、SMD構造と比較して、小さな接続パッド3でも接続パッド3と半田との接着強度を確保することができる。その反面、接続パッド3の側面が完全に露出することによって、接続パッド3と絶縁層8との間の接着強度が低下するおそれがある。また、狭ピッチで配置した接続パッド3では、後工程における無電解ニッケル/金めっきで、接続パッド3間で短絡が発生する場合や、接続パッド3上に半田バンプを配設しようとすると、溶融した半田が隣接する接続パッド3にまで流出し、接続パッド3間で短絡する場合がある。 FIG. 1B is a schematic cross-sectional view showing an example of a wiring board having an NSMD structure. A solder resist layer 2 is formed on the surface of the circuit board 1 provided with the conductor wiring 7 and the connection pads 3 which are part of the conductor wiring on the surface of the insulating layer 8. A plurality of connection pads 3 are arranged in the same opening of the solder resist layer 2, and these connection pads 3 are exposed from the solder resist layer 2. In the NSMD structure, the solder resist layer 2 in the vicinity of the connection pad 3 is completely removed, and the side surface of the connection pad 3 is completely exposed. Therefore, the bonding strength between the connection pad 3 and the solder can be ensured even with a small connection pad 3 as compared with the SMD structure. On the other hand, when the side surface of the connection pad 3 is completely exposed, the adhesive strength between the connection pad 3 and the insulating layer 8 may be reduced. In addition, in the connection pads 3 arranged at a narrow pitch, if a short circuit occurs between the connection pads 3 due to electroless nickel / gold plating in a later process, or if solder bumps are arranged on the connection pads 3, melting occurs. In some cases, the solder that has flowed out flows to the adjacent connection pads 3 and short-circuits between the connection pads 3.
 接続パッドと絶縁層との間の接着強度の問題を解決するために、レーザー光照射によって回路基板表面に設けたソルダーレジスト層の一部に深さ0~15μm程度の開口部を形成することにより、接続パッド側面の一部がソルダーレジスト層から露出した構造をもつプリント配線板を製造する方法が提案されている(例えば、特許文献1参照)。特許文献1に記載された方法で得られたプリント配線板を用いることによって、ソルダーレジスト層の下部に存在する接続パッドを完全に露出させたプリント配線板と比較して、接続パッドと絶縁層との間の接着強度を向上させることが可能となる。 In order to solve the problem of the adhesive strength between the connection pad and the insulating layer, an opening having a depth of about 0 to 15 μm is formed in a part of the solder resist layer provided on the circuit board surface by laser light irradiation. A method of manufacturing a printed wiring board having a structure in which a part of the side surface of the connection pad is exposed from the solder resist layer has been proposed (for example, see Patent Document 1). By using the printed wiring board obtained by the method described in Patent Document 1, the connection pad and the insulating layer are compared with the printed wiring board in which the connection pad existing under the solder resist layer is completely exposed. It becomes possible to improve the adhesive strength between.
 また、狭ピッチで配置した接続パッド3における短絡の問題を解決するために、隣接する接続パッド3間にソルダーレジスト層2が充填された配線基板を製造する方法が提案されている(例えば、特許文献2参照)。特許文献2の方法によると、図2に示すような、接続パッド3間にソルダーレジスト層2が充填され、かつ、充填されているソルダーレジスト層2の厚さが接続パッド3の厚さ以下であるNSMD構造を形成することができる。具体的には、回路基板1上にソルダーレジスト層2を形成し、ソルダーレジスト層2の厚さが接続パッド3の厚さ以下になるまで薄膜化される領域以外の部分を露光後、アルカリ水溶液である薄膜化処理液によって、接続パッド3の厚さ以下になるまで非露光部のソルダーレジスト層2を薄膜化する。これにより、接続パッド3の厚さ以下の部分と接続パッド3の厚さ超の部分を含む多段構造を有するソルダーレジスト層2が形成され、接続パッド3となる一部の導体配線が露出している配線基板を製造することができる。 In order to solve the problem of short circuit in the connection pads 3 arranged at a narrow pitch, a method of manufacturing a wiring board in which the solder resist layer 2 is filled between adjacent connection pads 3 has been proposed (for example, a patent). Reference 2). According to the method of Patent Document 2, as shown in FIG. 2, the solder resist layer 2 is filled between the connection pads 3, and the thickness of the filled solder resist layer 2 is equal to or less than the thickness of the connection pad 3. An NSMD structure can be formed. Specifically, a solder resist layer 2 is formed on the circuit board 1, and after exposing portions other than the region to be thinned until the thickness of the solder resist layer 2 is equal to or less than the thickness of the connection pad 3, an alkaline aqueous solution is obtained. The solder resist layer 2 in the non-exposed portion is thinned with the thinning treatment liquid until the thickness of the connection pad 3 or less. As a result, a solder resist layer 2 having a multi-stage structure including a portion less than the thickness of the connection pad 3 and a portion exceeding the thickness of the connection pad 3 is formed, and a part of the conductor wiring that becomes the connection pad 3 is exposed. A wiring board can be manufactured.
 通常、電子部品を搭載する配線基板では、裏面には外部接続用接続パッドが高密度で多数形成されている。外部接続用接続パッドも、回路基板裏面の導体配線の一部がソルダーレジスト層から露出することにより作製されている。この外部接続用接続パッドの露出部とマザーボード等の外部電気基板の導体配線とを対向させ、半田バンプを介して電気的に接続する。 Usually, in a wiring board on which electronic parts are mounted, a large number of external connection pads are formed on the back surface at high density. The connection pad for external connection is also produced by exposing a part of the conductor wiring on the back surface of the circuit board from the solder resist layer. The exposed portion of the connection pad for external connection and a conductor wiring of an external electric substrate such as a mother board are opposed to each other and electrically connected via solder bumps.
 回路基板の両面にソルダーレジスト層を形成する場合、接続パッド上のソルダーレジスト層の厚さは、接続パッドを含むその周囲の導体配線の密度によって変化する。例えば、導体配線の密度が小さい場合、導体配線間の隙間に充填されるソルダーレジスト層の量が多くなり、接続パッド上のソルダーレジスト層の厚さは薄くなる傾向がある。一方、導体配線の密度が大きい場合、導体配線間の隙間に充填されるソルダーレジスト層の量が少なくなり、接続パッド上のソルダーレジスト層の厚さは厚くなる傾向がある。 When the solder resist layer is formed on both sides of the circuit board, the thickness of the solder resist layer on the connection pad varies depending on the density of the surrounding conductor wiring including the connection pad. For example, when the density of the conductor wiring is small, the amount of the solder resist layer filled in the gap between the conductor wirings increases, and the thickness of the solder resist layer on the connection pad tends to be thin. On the other hand, when the density of the conductor wiring is large, the amount of the solder resist layer filled in the gap between the conductor wirings is reduced, and the thickness of the solder resist layer on the connection pad tends to be thick.
 フリップチップ接続により電子部品を搭載する配線基板の場合、表面の電子部品接続用接続パッドを含むその周囲の導体配線の密度に比べ、裏面の外部接続用接続パッドを含むその周囲の導体配線の密度が大きい場合がある。そのため、裏面の外部接続用接続パッド上のソルダーレジスト層の厚さが、表面の電子部品接続用接続パッド上のソルダーレジスト層の厚さよりも厚くなる場合がある。薄膜化処理液によってソルダーレジスト層を薄膜化して接続パッドを露出させる方法において、両面同時に薄膜化しようとした場合、次のような問題が生じる場合があった。 In the case of a wiring board on which electronic components are mounted by flip chip connection, the density of the surrounding conductor wiring including the connection pads for external connection on the back surface is higher than the density of the surrounding conductor wiring including the connection pads for connecting electronic components on the front surface. May be large. Therefore, the thickness of the solder resist layer on the connection pad for external connection on the back surface may be thicker than the thickness of the solder resist layer on the connection pad for electronic component connection on the front surface. In the method of thinning the solder resist layer with the thinning solution and exposing the connection pads, the following problems may occur when attempting to thin the both surfaces simultaneously.
 まず、表面のソルダーレジスト層2を電子部品接続用接続パッド3の厚さ以下になるまで薄膜化することを基準とした場合、裏面のソルダーレジスト層2も同時に表面と同じ量だけ薄膜化されるが、裏面のソルダーレジスト層2が表面のソルダーレジスト層2よりも厚いことから、裏面の外部接続用接続パッド4上にソルダーレジスト層2が残渣として残り、この残渣によって電気的絶縁不良が発生するという問題が生じる場合があった(図3)。 First, when it is based on thinning the solder resist layer 2 on the front surface until the thickness of the connection pad 3 for connecting electronic components is less than the thickness, the solder resist layer 2 on the back surface is also thinned by the same amount as the surface at the same time. However, since the solder resist layer 2 on the back surface is thicker than the solder resist layer 2 on the front surface, the solder resist layer 2 remains as a residue on the connection pad 4 for external connection on the back surface, and this residue causes poor electrical insulation. There was a case where a problem arises (FIG. 3).
 反対に、裏面のソルダーレジスト層2を外部接続用接続パッド4の厚さ以下になるまで薄膜化することを基準とした場合、表面のソルダーレジスト層2も同時に裏面と同じ量だけ薄膜化されるが、裏面のソルダーレジスト層2が表面のソルダーレジスト層2よりも厚いことから、表面の電子部品接続用接続パッド3間を充填しているソルダーレジスト層2の厚さが、所望の厚さよりも薄くなってしまい、隣接する電子部品接続用接続パッド3間の短絡が発生するという問題が生じる場合があった。 On the contrary, when it is assumed that the solder resist layer 2 on the back surface is thinned to the thickness of the connection pad 4 for external connection or less, the solder resist layer 2 on the front surface is also thinned by the same amount as the back surface at the same time. However, since the solder resist layer 2 on the back surface is thicker than the solder resist layer 2 on the front surface, the thickness of the solder resist layer 2 filling the space between the connection pads 3 for connecting the electronic components on the front surface is larger than the desired thickness. In some cases, the thickness becomes thinner, causing a short circuit between adjacent connection pads 3 for connecting electronic components.
 ところで、回路基板上に電子部品をフリップチップ接続したプリント配線板では、電子部品と回路基板との接続信頼性を確保するために、電子部品と回路基板との空隙をアンダーフィル(封止樹脂)で充填して補強する。補強効果を確保するためには、電子部品と回路基板の空隙に充分な量のアンダーフィルを充填しなければならない。しかしながら、特許文献1によって得られるプリント配線板を使用してフリップチップ接続を行った場合、補強効果を確保するために充分なアンダーフィルを充填した際に、アンダーフィルが電子部品と回路基板の空隙から周囲へ溢れてしまい、電気的な作動に悪影響を及ぼす場合があった。そのため、アンダーフィルが周囲に溢れてしまうことを防止するために、ダム構造を有するプリント配線板が提案されている(例えば、特許文献3~5参照)。 By the way, in a printed wiring board in which electronic components are flip-chip connected to a circuit board, the gap between the electronic components and the circuit board is underfilled (sealing resin) in order to ensure the connection reliability between the electronic component and the circuit board. Fill with reinforced. In order to ensure the reinforcing effect, a sufficient amount of underfill must be filled in the gap between the electronic component and the circuit board. However, when the flip-chip connection is performed using the printed wiring board obtained by Patent Document 1, when the underfill is filled with sufficient underfill to ensure the reinforcing effect, the underfill may be a gap between the electronic component and the circuit board. In some cases, it overflowed to the surroundings and adversely affected the electrical operation. Therefore, a printed wiring board having a dam structure has been proposed in order to prevent the underfill from overflowing to the surroundings (see, for example, Patent Documents 3 to 5).
 特許文献3には、導体回路を有する回路基板上にソルダーレジスト層を形成した後、部分露光を行い、その後未露光部を現像処理することで、ソルダーレジスト層から接続パッド上部を部分的に露出させる開口部を形成し、次に2回目の部分露光を行い、その後2回目の部分露光の未露光部をデスミア処理によって薄膜化し、ダム形状を形成する方法が開示されている。この方法によるソルダーレジスト層の開口部は、SMD構造であるため、電子部品の電極端子とこれに対応する接続パッドとの電気的な接続を確実に固定することが難しく、接続パッドと半田ボールの電気的な接続が不十分となる場合があった。また、この方法によるダム構造の形成はデスミア処理によって行われているため、ソルダーレジスト層が粗面化されることでソルダーレジスト層の強度が低下してしまい、プリント配線板の信頼性が充分に確保できない場合があった。 In Patent Document 3, a solder resist layer is formed on a circuit board having a conductor circuit, and then a partial exposure is performed. Thereafter, an unexposed portion is developed to partially expose the upper portion of the connection pad from the solder resist layer. A method of forming a dam shape by forming an opening to be formed, performing a second partial exposure, and then thinning an unexposed portion of the second partial exposure by a desmear process is disclosed. Since the opening of the solder resist layer by this method has an SMD structure, it is difficult to securely fix the electrical connection between the electrode terminal of the electronic component and the corresponding connection pad. In some cases, the electrical connection was insufficient. Moreover, since the dam structure is formed by the desmear process by this method, the strength of the solder resist layer is lowered by roughening the solder resist layer, and the reliability of the printed wiring board is sufficient. In some cases, it could not be secured.
 特許文献4には、導体回路を有する回路基板上にソルダーレジスト層を形成した後、部分露光を行い、その後未露光部を現像処理することで、ソルダーレジスト層から接続パッドを完全に露出させる開口部を形成し、次に2回目のソルダーレジストを形成した後、1回目の部分露光領域よりも1回り大きな未露光部が発生する2回目の部分露光を行い、その後未露光部を現像することによってダム形状を形成する方法が開示されている。この方法によるソルダーレジスト層の開口部は、NSMD構造であり、接続パッドはその周辺近傍のソルダーレジスト層が完全に除去され、接続パッドの側面が完全に露出することによって、接続パッドと絶縁層との間の接着強度が低下するおそれがある。 Patent Document 4 discloses an opening that completely exposes a connection pad from a solder resist layer by forming a solder resist layer on a circuit board having a conductor circuit, performing partial exposure, and then developing the unexposed portion. Forming a second portion, then forming a second solder resist, then performing a second partial exposure in which an unexposed portion that is one size larger than the first partial exposure region is generated, and then developing the unexposed portion Discloses a method for forming a dam shape. The opening of the solder resist layer by this method has an NSMD structure, and the connection pad is completely removed from the periphery of the solder resist layer, and the side surface of the connection pad is completely exposed. There is a risk that the adhesive strength between the two will decrease.
 特許文献5には、導体回路を有する回路基板上にソルダーレジスト層を形成した後、部分露光工程を行い、その後未露光部のソルダーレジスト層を薄膜化することでソルダーレジスト層に開口部とダム形状を形成する方法が開示されている。この方法によるソルダーレジスト層の開口部は、SMD構造であり、接続パッドはその周辺近傍がソルダーレジスト層に被覆されているため、電子部品の電極端子とこれに対応する接続パッドとの電気的な接続を確実に固定することが難しく、接続パッドと半田ボールの電気的な接続が不十分となる場合があった。 In Patent Document 5, a solder resist layer is formed on a circuit board having a conductor circuit, and then a partial exposure process is performed, and then an unexposed portion of the solder resist layer is thinned so that openings and dams are formed in the solder resist layer. A method of forming a shape is disclosed. The opening of the solder resist layer by this method has an SMD structure, and the connection pad is covered with the solder resist layer in the vicinity of the periphery, so that the electrical connection between the electrode terminal of the electronic component and the corresponding connection pad is made. It is difficult to securely fix the connection, and the electrical connection between the connection pad and the solder ball may be insufficient.
特許3346263号公報Japanese Patent No. 3346263 国際公開第2012/043201号パンフレットInternational Publication No. 2012/043201 Pamphlet 特開2012-238668号公報JP 2012-238668 A 特開平05-226505号公報JP 05-226505 A 特開2011-77191号公報JP 2011-77191 A
 本発明の課題は、絶縁層と、絶縁層の表面に形成された接続パッドとを両表面に有する回路基板を有し、回路基板の両表面にソルダーレジスト層を有し、ソルダーレジスト層から接続パッドの一部が露出している配線基板の製造方法において、配線基板の両表面で、ソルダーレジスト層から露出している接続パッド間で電気的な短絡がなく、露出している接続パッド上にソルダーレジスト層の残渣が残らない配線基板の製造方法を提供することである。また、本発明の他の課題は、接続パッドと絶縁層及び接続パッドと半田との接着強度が高く、アンダーフィル流出による電気的作動不良が無く、ソルダーレジスト層の強度が高いプリント配線板を得ることができるプリント配線板の製造方法を提供することである。 An object of the present invention is to have a circuit board having an insulating layer and a connection pad formed on the surface of the insulating layer on both surfaces, and having a solder resist layer on both surfaces of the circuit board, and connecting from the solder resist layer In the method of manufacturing a wiring board in which a part of the pad is exposed, there is no electrical short circuit between the connection pads exposed from the solder resist layer on both surfaces of the wiring board, and on the exposed connection pads. An object of the present invention is to provide a method for manufacturing a wiring board in which no residue of a solder resist layer remains. Another object of the present invention is to obtain a printed wiring board having high adhesion strength between a connection pad and an insulating layer and between the connection pad and solder, no electrical malfunction due to underfill outflow, and high solder resist layer strength. It is providing the manufacturing method of the printed wiring board which can be performed.
 本発明者らは、上記課題を解決するために鋭意検討した結果、下記発明によって、上記課題を解決できることを見出した。 As a result of intensive studies to solve the above problems, the present inventors have found that the above problems can be solved by the following invention.
(1)絶縁層と、絶縁層の表面に形成された接続パッドとを両表面に有する回路基板を有し、回路基板の両表面にソルダーレジスト層を有し、ソルダーレジスト層から接続パッドの一部が露出している配線基板の製造方法において、
(A)絶縁層と、絶縁層の表面に形成された接続パッドとを両表面に有する回路基板の両表面に、厚さの異なるソルダーレジスト層が形成される工程、
(C1)第二面のソルダーレジスト層よりも厚さが薄い第一面のソルダーレジスト層に対して、後工程である工程(B)において薄膜化される領域以外の部分が露光される工程、
(C2)第二面のソルダーレジスト層に対して、後工程である工程(D)において現像される領域以外の部分が露光される工程、
(B)第一面において、薄膜化処理液によって、接続パッドの厚さ以下になるまで、非露光部のソルダーレジスト層が薄膜化されて、接続パッドの一部を露出する工程、
(C3)第一面のソルダーレジスト層に対して、工程(B)において薄膜化された領域部分が露光される工程、
(D)第二面の非露光部のソルダーレジスト層が、現像液によって除去される工程、
を含むことを特徴とする配線基板の製造方法。
(1) It has a circuit board which has an insulating layer and a connection pad formed on the surface of the insulating layer on both surfaces, and has a solder resist layer on both surfaces of the circuit board. In the method of manufacturing a wiring board in which a part is exposed,
(A) a step in which solder resist layers having different thicknesses are formed on both surfaces of a circuit board having an insulating layer and a connection pad formed on the surface of the insulating layer on both surfaces;
(C1) A step in which a portion other than the region to be thinned in the step (B) which is a subsequent step is exposed to the solder resist layer on the first surface which is thinner than the solder resist layer on the second surface,
(C2) A step of exposing a portion other than the region to be developed in step (D), which is a subsequent step, to the solder resist layer on the second surface,
(B) On the first surface, the solder resist layer of the non-exposed part is thinned until the thickness of the connection pad becomes equal to or less than the thickness of the connection pad by the thinning treatment solution, and a part of the connection pad is exposed.
(C3) The step of exposing the area portion thinned in step (B) to the solder resist layer on the first surface,
(D) the step of removing the solder resist layer of the non-exposed portion of the second surface with a developer;
A method for manufacturing a wiring board, comprising:
(2)絶縁層と、絶縁層の表面に形成された接続パッドとを両表面に有する回路基板を有し、回路基板の両表面にソルダーレジスト層を有し、ソルダーレジスト層から接続パッドの一部が露出している配線基板の製造方法において、
(A)絶縁層と、絶縁層の表面に形成された接続パッドとを両表面に有する回路基板の両表面に、厚さの異なるソルダーレジスト層が形成される工程、
(C1)第二面のソルダーレジスト層よりも厚さが薄い第一面のソルダーレジスト層に対して、後工程である工程(B1)において薄膜化される領域以外の部分が露光される工程、
(C2)第二面のソルダーレジスト層に対して、後工程である工程(D)において現像される領域以外の部分が露光される工程、
(B1)第一面において、薄膜化処理液によって、接続パッドが露出しない範囲で、非露光部のソルダーレジスト層が薄膜化される工程、
(C4)第一面のソルダーレジスト層に対して、後工程である工程(B2)において薄膜化される領域以外の部分が露光される工程、
(B2)第一面において、薄膜化処理液によって、接続パッドの厚さ以下になるまで、非露光部のソルダーレジスト層が薄膜化されて、接続パッドの一部を露出する工程、
(C5)第一面のソルダーレジスト層に対して、工程(B2)において薄膜化された領域部分が露光される工程、
(D)第二面の非露光部のソルダーレジスト層が、現像液によって除去される工程、
を含むことを特徴とする配線基板の製造方法。
(2) It has a circuit board which has an insulating layer and a connection pad formed on the surface of the insulating layer on both surfaces, has a solder resist layer on both surfaces of the circuit board, and one of the connection pads from the solder resist layer. In the manufacturing method of the wiring board in which the part is exposed,
(A) a step in which solder resist layers having different thicknesses are formed on both surfaces of a circuit board having an insulating layer and a connection pad formed on the surface of the insulating layer on both surfaces;
(C1) A step of exposing a portion other than the region to be thinned in the step (B1), which is a subsequent step, to the solder resist layer on the first surface that is thinner than the solder resist layer on the second surface,
(C2) A step of exposing a portion other than the region to be developed in step (D), which is a subsequent step, to the solder resist layer on the second surface,
(B1) In the first surface, the step in which the solder resist layer of the non-exposed part is thinned by the thinning treatment liquid in a range where the connection pad is not exposed,
(C4) A step of exposing a portion other than the region to be thinned in the step (B2), which is a subsequent step, to the solder resist layer on the first surface,
(B2) On the first surface, the solder resist layer of the non-exposed portion is thinned until the thickness of the connection pad becomes equal to or less than the thickness of the connection pad by the thinning treatment solution, and a part of the connection pad is exposed.
(C5) The step of exposing the thinned region in step (B2) to the solder resist layer on the first surface,
(D) the step of removing the solder resist layer of the non-exposed portion of the second surface with a developer;
A method for manufacturing a wiring board, comprising:
(3)絶縁層と、絶縁層の表面に形成された接続パッドとを両表面に有する回路基板を有し、回路基板の両表面にソルダーレジスト層を有し、ソルダーレジスト層から接続パッドの一部が露出している配線基板の製造方法において、
(A1)絶縁層と、絶縁層の表面に形成された接続パッドとを両表面に有する回路基板の両表面に、厚さの異なる第一ソルダーレジスト層が形成される工程、
(C1)第二面の第一ソルダーレジスト層よりも厚さが薄い第一面の第一ソルダーレジスト層に対して、後工程である工程(B)において薄膜化される領域以外の部分が露光される工程、
(C2)第二面の第一ソルダーレジスト層に対して、後工程である工程(D1)において現像される領域以外の部分が露光される工程、
(B)第一面において、薄膜化処理液によって、接続パッドの厚さ以下になるまで、非露光部の第一ソルダーレジスト層が薄膜化されて、接続パッドの一部を露出する工程、
(C3)第一面の第一ソルダーレジスト層に対して、工程(B)において薄膜化された領域部分が露光される工程、
(A2)(C3)工程まで完了した回路基板の第一面の第一ソルダーレジスト層上に、第二ソルダーレジスト層が形成される工程、
(C6)第一面の第二ソルダーレジスト層に対して、後工程である工程(D1)において現像される領域以外の部分が露光される工程、
(D1)第一面の非露光部の第二ソルダーレジスト層及び第二面の非露光部の第一ソルダーレジスト層が、現像液によって除去される工程、
を含むことを特徴とする配線基板の製造方法。
(3) It has a circuit board which has an insulating layer and a connection pad formed on the surface of the insulating layer on both surfaces, a solder resist layer on both surfaces of the circuit board, and one of the connection pads from the solder resist layer. In the method of manufacturing a wiring board in which a part is exposed,
(A1) a step in which first solder resist layers having different thicknesses are formed on both surfaces of a circuit board having an insulating layer and connection pads formed on the surfaces of the insulating layer on both surfaces;
(C1) The first solder resist layer on the first surface, which is thinner than the first solder resist layer on the second surface, is exposed to a portion other than the region to be thinned in the subsequent step (B). Process
(C2) A step of exposing a portion other than the region to be developed in step (D1), which is a subsequent step, to the first solder resist layer on the second surface,
(B) On the first surface, the first solder resist layer of the non-exposed part is thinned until the thickness of the connection pad is equal to or less than the thickness of the connection pad by the thinning treatment liquid, and a part of the connection pad is exposed;
(C3) The step of exposing the region portion thinned in step (B) to the first solder resist layer on the first surface,
(A2) A step of forming a second solder resist layer on the first solder resist layer on the first surface of the circuit board completed up to the step (C3),
(C6) A step in which a portion other than a region to be developed in the step (D1) which is a subsequent step is exposed to the second solder resist layer on the first surface;
(D1) a step of removing the second solder resist layer of the non-exposed portion of the first surface and the first solder resist layer of the non-exposed portion of the second surface with a developer;
A method for manufacturing a wiring board, comprising:
(4)絶縁層と、絶縁層の表面に形成された接続パッドとを両表面に有する回路基板を有し、回路基板の両表面にソルダーレジスト層を有し、ソルダーレジスト層から接続パッドの一部が露出している配線基板の製造方法において、
(A1)絶縁層と、絶縁層の表面に形成された接続パッドとを両表面に有する回路基板の両表面に、厚さの異なる第一ソルダーレジスト層が形成される工程、
(C1)第二面の第一ソルダーレジスト層よりも厚さが薄い第一面の第一ソルダーレジスト層に対して、後工程である工程(B)において薄膜化される領域以外の部分が露光される工程、
(C2)第二面の第一ソルダーレジスト層に対して、後工程である工程(D)において現像される領域以外の部分が露光される工程、
(B)第一面において、薄膜化処理液によって、接続パッドの厚さ以下になるまで、非露光部の第一ソルダーレジスト層が薄膜化されて、接続パッドの一部を露出する工程、
(C3)第一面の第一ソルダーレジスト層に対して、工程(B)において薄膜化された領域部分が露光される工程、
(D)第二面の非露光部の第一ソルダーレジスト層が、現像液によって除去される工程、
(A2)(D)工程まで完了した回路基板の第一面の第一ソルダーレジスト層上に、第二ソルダーレジスト層が形成される工程、
(C6)第一面の第二ソルダーレジスト層に対して、後工程である工程(D2)において現像される領域以外の部分が露光される工程、
(D2)第一面の非露光部の第二ソルダーレジスト層が、現像液によって除去される工程、
を含むことを特徴とする配線基板の製造方法。
(4) It has a circuit board which has an insulating layer and a connection pad formed on the surface of the insulating layer on both surfaces, has a solder resist layer on both surfaces of the circuit board, and one of the connection pads from the solder resist layer. In the method of manufacturing a wiring board in which a part is exposed,
(A1) a step in which first solder resist layers having different thicknesses are formed on both surfaces of a circuit board having an insulating layer and connection pads formed on the surfaces of the insulating layer on both surfaces;
(C1) The first solder resist layer on the first surface, which is thinner than the first solder resist layer on the second surface, is exposed to a portion other than the region to be thinned in the subsequent step (B). Process
(C2) A step of exposing a portion other than a region to be developed in step (D), which is a subsequent step, to the first solder resist layer on the second surface;
(B) On the first surface, the first solder resist layer of the non-exposed part is thinned until the thickness of the connection pad is equal to or less than the thickness of the connection pad by the thinning treatment liquid, and a part of the connection pad is exposed;
(C3) The step of exposing the region portion thinned in step (B) to the first solder resist layer on the first surface,
(D) the step of removing the first solder resist layer of the non-exposed portion of the second surface with a developer;
(A2) A step in which a second solder resist layer is formed on the first solder resist layer on the first surface of the circuit board completed up to step (D),
(C6) A step in which a portion other than the region to be developed in the step (D2) which is a subsequent step is exposed to the second solder resist layer on the first surface,
(D2) a step of removing the second solder resist layer of the non-exposed portion of the first surface with a developer;
A method for manufacturing a wiring board, comprising:
(5)絶縁層と、絶縁層の表面に形成された接続パッドとを両表面に有する回路基板を有し、回路基板の両表面にソルダーレジスト層を有し、ソルダーレジスト層から接続パッドの一部が露出している配線基板の製造方法において、
(A1)絶縁層と、絶縁層の表面に形成された接続パッドとを両表面に有する回路基板の両表面に、厚さの異なる第一ソルダーレジスト層が形成される工程、
(C2)第二面の第一ソルダーレジスト層に対して、後工程である工程(D1)において現像される領域以外の部分が露光される工程、
(B)第一面において、薄膜化処理液によって、接続パッドの厚さ以下になるまで、非露光部の第一ソルダーレジスト層が薄膜化されて、接続パッドの一部を露出する工程、
(C3)第一面の第一ソルダーレジスト層に対して、工程(B)において薄膜化された領域部分が露光される工程、
(A2)(C3)工程まで完了した回路基板の第一面の第一ソルダーレジスト層上に、第二ソルダーレジスト層が形成される工程、
(C6)第一面の第二ソルダーレジスト層に対して、後工程である工程(B3)において薄膜化される領域以外の部分が露光される工程、
(B3)第一面において、薄膜化処理液によって、接続パッドが露出しない範囲で、非露光部の第二ソルダーレジスト層が薄膜化される工程、
(C7)第一面の第二ソルダーレジスト層に対して、後工程である工程(D1)において現像される領域以外の部分が露光される工程、
(D1)第一面の非露光部の第二ソルダーレジスト層及び第二面の非露光部の第一ソルダーレジスト層が、現像液によって除去される工程、
を含むことを特徴とする配線基板の製造方法。
(5) a circuit board having an insulating layer and a connection pad formed on the surface of the insulating layer on both surfaces; a solder resist layer on both surfaces of the circuit board; In the method of manufacturing a wiring board in which a part is exposed,
(A1) a step in which first solder resist layers having different thicknesses are formed on both surfaces of a circuit board having an insulating layer and connection pads formed on the surfaces of the insulating layer on both surfaces;
(C2) A step of exposing a portion other than the region to be developed in step (D1), which is a subsequent step, to the first solder resist layer on the second surface,
(B) On the first surface, the first solder resist layer of the non-exposed part is thinned until the thickness of the connection pad is equal to or less than the thickness of the connection pad by the thinning treatment liquid, and a part of the connection pad is exposed;
(C3) The step of exposing the region portion thinned in step (B) to the first solder resist layer on the first surface,
(A2) A step of forming a second solder resist layer on the first solder resist layer on the first surface of the circuit board completed up to the step (C3),
(C6) A step of exposing a portion other than the region to be thinned in the subsequent step (B3) to the second solder resist layer on the first surface;
(B3) On the first surface, the second solder resist layer of the non-exposed part is thinned by the thinning treatment liquid in a range where the connection pad is not exposed,
(C7) A step in which a portion other than the region to be developed in the step (D1) which is a subsequent step is exposed to the second solder resist layer on the first surface;
(D1) a step of removing the second solder resist layer of the non-exposed portion of the first surface and the first solder resist layer of the non-exposed portion of the second surface with a developer;
A method for manufacturing a wiring board, comprising:
・(6)工程(C1)の前に工程(C2)を行う上記(1)~(4)のいずれかに記載の配線基板の製造方法。
・(7)工程(C1)と工程(C2)を同時に行う上記(1)~(4)のいずれかに記載の配線基板の製造方法。
(6) The method for manufacturing a wiring board according to any one of (1) to (4), wherein the step (C2) is performed before the step (C1).
(7) The method for manufacturing a wiring board according to any one of (1) to (4), wherein the step (C1) and the step (C2) are performed simultaneously.
(8)工程(C3)における露光が、酸素雰囲気下での非接触露光方式によって行われる上記(1)、(3)、(4)のいずれかに記載の配線基板の製造方法。
(9)工程(C3)及び工程(C7)における露光が、酸素雰囲気下での非接触露光方式によって行われる上記(5)記載の配線基板の製造方法。
(10)工程(C4)及び工程(C5)における露光が、酸素雰囲気下での非接触露光方式によって行われる上記(2)に記載の配線基板の製造方法。
(8) The method for manufacturing a wiring board according to any one of (1), (3), and (4), wherein the exposure in the step (C3) is performed by a non-contact exposure method in an oxygen atmosphere.
(9) The method for manufacturing a wiring board according to (5), wherein the exposure in the step (C3) and the step (C7) is performed by a non-contact exposure method in an oxygen atmosphere.
(10) The method for manufacturing a wiring board according to (2), wherein the exposure in the step (C4) and the step (C5) is performed by a non-contact exposure method in an oxygen atmosphere.
(11)工程(C3)における露光量が、工程(C1)における露光量の1倍以上5倍以下である上記(1)、(3)、(4)、(8)のいずれかに記載の配線基板の製造方法。
(12)工程(C3)及び工程(C7)における露光量が、工程(C6)における露光量の1倍以上5倍以下である上記(5)又は(9)記載の配線基板の製造方法。
(13)工程(C4)及び工程(C5)における露光量が、工程(C1)における露光量の1倍以上5倍以下である上記(2)又は(10)に記載の配線基板の製造方法。
(11) The exposure amount in the step (C3) is any one of the above (1), (3), (4), and (8), which is 1 to 5 times the exposure amount in the step (C1). A method for manufacturing a wiring board.
(12) The method for producing a wiring board according to (5) or (9), wherein the exposure amount in the step (C3) and the step (C7) is 1 to 5 times the exposure amount in the step (C6).
(13) The method for producing a wiring board according to (2) or (10), wherein the exposure amount in the step (C4) and the step (C5) is 1 to 5 times the exposure amount in the step (C1).
(14)工程(B)におけるソルダーレジスト層の薄膜化処理が、薄膜化処理面を上にして行われる上記(1)、(3)、(4)、(8)、(11)のいずれかに記載の配線基板の製造方法。
(15)工程(B)及び工程(B3)におけるソルダーレジスト層の薄膜化処理が、薄膜化処理面を上にして行われる上記(5)、(9)、(12)のいずれかに記載の配線基板の製造方法。
(16)工程(B1)及び工程(B2)におけるソルダーレジスト層の薄膜化処理が、薄膜化処理面を上にして行われる上記(2)、(10)、(13)のいずれかに記載の配線基板の製造方法。
(14) Any of (1), (3), (4), (8), and (11) above, wherein the thinning process of the solder resist layer in the step (B) is performed with the thinning process surface facing up. The manufacturing method of the wiring board as described in 2 ..
(15) The solder resist layer thinning process in the step (B) and the step (B3) is performed with the thinning processing surface facing up, according to any one of the above (5), (9), and (12) A method for manufacturing a wiring board.
(16) The solder resist layer thinning process in the step (B1) and the step (B2) is performed with the thinning processing surface facing up, according to any one of the above (2), (10), and (13) A method for manufacturing a wiring board.
 本発明によれば、絶縁層と、絶縁層の表面に形成された接続パッドとを両表面に有する回路基板を有し、回路基板の両表面にソルダーレジスト層を有し、ソルダーレジスト層から接続パッドの一部が露出している配線基板の製造方法において、配線基板の両表面で、ソルダーレジスト層から露出している接続パッド間で電気的な短絡がなく、また、露出している接続パッド上にソルダーレジスト層の残渣が残らない配線基板の製造方法を提供することができる。また、本発明によれば、接続パッドと絶縁層及び接続パッドと半田との接着強度が高く、アンダーフィル流出による電気的作動不良が無く、ソルダーレジスト層の強度が高いプリント配線板を得ることができるプリント配線板の製造方法を提供することができる。 According to the present invention, the circuit board having the insulating layer and the connection pad formed on the surface of the insulating layer is provided on both surfaces, the solder resist layer is provided on both surfaces of the circuit board, and the connection is made from the solder resist layer. In the method of manufacturing a wiring board in which a part of the pad is exposed, there is no electrical short circuit between the connection pads exposed from the solder resist layer on both surfaces of the wiring board, and the exposed connection pads It is possible to provide a method of manufacturing a wiring board in which no residue of the solder resist layer remains. In addition, according to the present invention, it is possible to obtain a printed wiring board having a high bonding strength between the connection pad and the insulating layer and the connection pad and the solder, no electrical malfunction due to an underfill outflow, and a high strength of the solder resist layer. The manufacturing method of the printed wiring board which can be provided can be provided.
配線基板の一例を示す概略断面図である。It is a schematic sectional drawing which shows an example of a wiring board. 配線基板の一例を示す概略断面図である。It is a schematic sectional drawing which shows an example of a wiring board. 配線基板の一例を示す概略断面図である。It is a schematic sectional drawing which shows an example of a wiring board. 本発明の配線基板の製造方法の一例を示す断面工程図である。It is sectional process drawing which shows an example of the manufacturing method of the wiring board of this invention. 本発明の配線基板の製造方法の一例を示す断面工程図である。It is sectional process drawing which shows an example of the manufacturing method of the wiring board of this invention. 本発明の配線基板の製造方法の一例を示す断面工程図である。It is sectional process drawing which shows an example of the manufacturing method of the wiring board of this invention. 本発明の配線基板の製造方法の一例を示す断面工程図である。It is sectional process drawing which shows an example of the manufacturing method of the wiring board of this invention. 本発明の配線基板の製造方法の一例を示す断面工程図である。It is sectional process drawing which shows an example of the manufacturing method of the wiring board of this invention. 本発明によって製造できる配線基板の一例を示す概略断面図である。It is a schematic sectional drawing which shows an example of the wiring board which can be manufactured by this invention. 本発明によって製造できる配線基板の一例を示す概略断面図である。It is a schematic sectional drawing which shows an example of the wiring board which can be manufactured by this invention. 本発明によって製造できる配線基板の一例を示す概略断面図である。It is a schematic sectional drawing which shows an example of the wiring board which can be manufactured by this invention. 本発明によって製造できる配線基板の一例を示す概略断面図である。It is a schematic sectional drawing which shows an example of the wiring board which can be manufactured by this invention. 多層回路基板の一例を示す概略断面図である。It is a schematic sectional drawing which shows an example of a multilayer circuit board.
 以下、本発明の配線基板の製造方法について詳細に説明する。 Hereinafter, the manufacturing method of the wiring board of the present invention will be described in detail.
 図4-1および図4-2は、配線基板の製造方法(1)の一例を示す断面工程図である。絶縁層8と、絶縁層8の表面に形成された導体配線7とを両表面に有する回路基板を準備する。導体配線7の一部は、接続パッド3及び4である。工程(A)では、回路基板1の両表面において、全面を覆うようにソルダーレジスト層2を形成する。第一面と第二面のソルダーレジスト層2の形成は、両表面同時でも、片面ずつでもよいが、形成するソルダーレジスト層の厚さに応じて、過剰に熱硬化しないような加熱条件を設定する必要がある。両表面におけるソルダーレジスト層2の厚さは異なっており、厚さの薄い方が「第一面」であり、厚さの厚い方が「第二面」である。両表面において、ソルダーレジスト層2を同じ条件で形成した場合、ソルダーレジスト層2の厚さは、各面の接続パッド3及び4を含む導体配線7の密度によって変化する。図4-1では、上側の第一面に比べて、下側の第二面の方が導体配線7の密度が大きく、第二面の導体配線7上のソルダーレジスト層2の厚さが、第一面の導体配線7上のソルダーレジスト層2の厚さよりも厚くなる。なお、電子部品を搭載する配線基板の場合、表面の電子部品接続用接続パッド3を含むその周囲の導体配線7の密度に比べ、裏面の外部接続用接続パッド4を含むその周囲の導体配線7の密度が大きい場合があり、表面が第一面であり、裏面が第二面である。 FIGS. 4A and 4B are cross-sectional process diagrams illustrating an example of the manufacturing method (1) of the wiring board. A circuit board having the insulating layer 8 and the conductor wiring 7 formed on the surface of the insulating layer 8 on both surfaces is prepared. Part of the conductor wiring 7 is the connection pads 3 and 4. In the step (A), a solder resist layer 2 is formed on both surfaces of the circuit board 1 so as to cover the entire surface. The formation of the solder resist layer 2 on the first surface and the second surface may be performed simultaneously on both surfaces or on each side, but depending on the thickness of the solder resist layer to be formed, heating conditions are set so as not to overheat. There is a need to. The thicknesses of the solder resist layers 2 on both surfaces are different. The thinner one is the “first surface”, and the thicker one is the “second surface”. When the solder resist layer 2 is formed under the same conditions on both surfaces, the thickness of the solder resist layer 2 varies depending on the density of the conductor wiring 7 including the connection pads 3 and 4 on each surface. In FIG. 4-1, the density of the conductor wiring 7 is higher on the lower second surface than on the upper first surface, and the thickness of the solder resist layer 2 on the second surface conductor wiring 7 is It becomes thicker than the thickness of the solder resist layer 2 on the conductor wiring 7 on the first surface. In the case of a wiring board on which electronic components are mounted, the peripheral conductor wiring 7 including the external connection connection pads 4 on the back surface is compared with the density of the surrounding conductor wiring 7 including the electronic component connection connection pads 3 on the front surface. May have a large density, the front surface being the first surface and the back surface being the second surface.
 工程(C1)では、第一面のソルダーレジスト層2に対して、後工程である工程(B)において薄膜化される領域以外の部分を露光する。工程(C2)では、第二面のソルダーレジスト層2に対して、後工程である工程(D)において現像される領域以外の部分を露光する。ソルダーレジスト層2の露光された部分は、ソルダーレジストが光重合し、薄膜化工程及び現像工程に対して耐性を有するようになる。 In step (C1), the solder resist layer 2 on the first surface is exposed to a portion other than the region to be thinned in the subsequent step (B). At a process (C2), parts other than the area | region developed in the process (D) which is a post process are exposed with respect to the soldering resist layer 2 of a 2nd surface. In the exposed portion of the solder resist layer 2, the solder resist is photopolymerized and has resistance to the thinning process and the developing process.
 工程(B)では、第一面において、薄膜化処理液によって、接続パッド3の厚さ以下になるまで、非露光部のソルダーレジスト層2を薄膜化して、接続パッド3の一部を露出させる。電子部品を搭載する配線基板の場合、この工程(B)において露出した接続パッド3が電子部品接続用接続パッド3として使用される。工程(B)では、第二面の非露光部のソルダーレジスト層2も同時に薄膜化されるが、第一面の接続パッド3上のソルダーレジスト層2よりも第二面の接続パッド4上のソルダーレジスト層2の方が厚いため、接続パッド4上にソルダーレジスト層2の残渣が残る。 In the step (B), on the first surface, the solder resist layer 2 in the non-exposed part is thinned by the thinning treatment solution until the thickness of the connection pad 3 becomes equal to or less, and a part of the connection pad 3 is exposed. . In the case of a wiring board on which electronic components are mounted, the connection pads 3 exposed in this step (B) are used as the connection pads 3 for connecting electronic components. In the step (B), the solder resist layer 2 of the non-exposed portion on the second surface is also thinned simultaneously, but on the connection pad 4 on the second surface rather than the solder resist layer 2 on the connection pad 3 on the first surface. Since the solder resist layer 2 is thicker, a residue of the solder resist layer 2 remains on the connection pad 4.
 工程(C3)では、第一面のソルダーレジスト層2に対して、工程(B)で薄膜化された領域部分を露光する。ソルダーレジスト層2の露光された部分は、ソルダーレジストが光重合し、現像工程に対して耐性を有するようになる。 In step (C3), the solder resist layer 2 on the first surface is exposed to the region thinned in step (B). In the exposed portion of the solder resist layer 2, the solder resist is photopolymerized and has resistance to the development process.
 工程(D)では、第二面において、非露光部のソルダーレジスト層2を、現像液によって除去し、接続パッド4の一部を露出させる。工程(D)により、接続パッド4上に残っていたソルダーレジスト層2の残渣が除去される。電子部品を搭載する配線基板の場合、この工程(D)において露出した接続パッド4が外部接続用接続パッド4として使用される。第一面のソルダーレジスト層2において、工程(B)で薄膜化された領域部分は、工程(D)の前に行われる工程(C3)において露光され、現像工程に対する耐性を有しているので、現像液によって除去されない。 In step (D), on the second surface, the solder resist layer 2 in the non-exposed portion is removed with a developer, and a part of the connection pad 4 is exposed. By the step (D), the residue of the solder resist layer 2 remaining on the connection pad 4 is removed. In the case of a wiring board on which electronic components are mounted, the connection pads 4 exposed in this step (D) are used as connection pads 4 for external connection. In the solder resist layer 2 on the first surface, the region thinned in the step (B) is exposed in the step (C3) performed before the step (D) and has resistance to the development step. , Not removed by developer.
 配線基板の製造方法(1)では、工程(C1)の露光領域を任意の形状に変化させることが可能であり、露光領域の変更により、例えば、図9に示す断面形状の配線基板を作製することが可能である。図9のaでは、第一面の接続パッド3の間にソルダーレジスト層2の凸部が形成されている。図9のbでは、第一面において、ソルダーレジスト層2から露出した接続パッド3とソルダーレジスト層2で被覆されている導体配線7が交互に並んでいる。 In the manufacturing method (1) of the wiring board, the exposure area in the step (C1) can be changed to an arbitrary shape. By changing the exposure area, for example, a wiring board having a cross-sectional shape shown in FIG. It is possible. In a of FIG. 9, the convex part of the soldering resist layer 2 is formed between the connection pads 3 of the 1st surface. In FIG. 9 b, the connection pads 3 exposed from the solder resist layer 2 and the conductor wirings 7 covered with the solder resist layer 2 are alternately arranged on the first surface.
 図5-1、図5-2および図5-3は、配線基板の製造方法(2)の一例を示す断面工程図である。配線基板の製造方法(1)との違いは、第一面において、ソルダーレジスト層2の露光工程と薄膜化工程がそれぞれ一回ずつ追加されている点である。フリップチップ接続により電子部品を配線基板に搭載する場合、電子部品と配線基板の熱膨張係数の差によって、熱衝撃が加わった際、接続部に応力が集中し、接続部の変形や破壊が起こることがある。接続部へ応力が集中するのを防ぎ、接続信頼性を向上させるために、電子部品と配線基板の間がアンダーフィルと呼ばれる樹脂組成物で封止されるのが一般的である。配線基板の製造方法(2)によって、電子部品と配線基板の間に充填するアンダーフィルを堰き止めるためのダム構造を有する二段構造のソルダーレジスト層を形成することができる。 5-1, FIG. 5-2, and FIG. 5-3 are cross-sectional process diagrams illustrating an example of a method (2) for manufacturing a wiring board. The difference from the manufacturing method (1) of the wiring board is that the exposure process and the thinning process of the solder resist layer 2 are added once each on the first surface. When electronic components are mounted on a wiring board by flip chip connection, due to the difference in thermal expansion coefficient between the electronic components and the wiring board, when a thermal shock is applied, stress concentrates on the connecting portion, causing deformation or destruction of the connecting portion. Sometimes. In order to prevent stress from concentrating on the connection portion and improve connection reliability, it is common to seal between the electronic component and the wiring board with a resin composition called underfill. By the wiring board manufacturing method (2), it is possible to form a two-stage solder resist layer having a dam structure for blocking an underfill filling between the electronic component and the wiring board.
 工程(A)では、回路基板1の両表面において、全面を覆うようにソルダーレジスト層2を形成する。工程(C1)では、第一面のソルダーレジスト層2に対して、後工程である工程(B1)において薄膜化される領域以外の部分を露光する。工程(C2)では、第二面のソルダーレジスト層2に対して、後工程である工程(D)において現像される領域以外の部分を露光する。 In step (A), a solder resist layer 2 is formed on both surfaces of the circuit board 1 so as to cover the entire surface. At a process (C1), parts other than the area | region thinned in the process (B1) which is a post process are exposed with respect to the soldering resist layer 2 of a 1st surface. At a process (C2), parts other than the area | region developed in the process (D) which is a post process are exposed with respect to the soldering resist layer 2 of a 2nd surface.
 工程(B1)では、第一面において、薄膜化処理液によって、接続パッド3が露出しない範囲で、非露光部のソルダーレジスト層2を薄膜化する。工程(B1)では、第二面の非露光部のソルダーレジスト層2も同時に薄膜化される。 In step (B1), the solder resist layer 2 in the non-exposed part is thinned on the first surface with the thinning treatment solution in a range where the connection pads 3 are not exposed. In the step (B1), the solder resist layer 2 of the non-exposed portion on the second surface is also thinned at the same time.
 工程(C4)では、第一面のソルダーレジスト層2に対して、後工程である工程(B2)において薄膜化される領域以外の部分を露光する。 In step (C4), the solder resist layer 2 on the first surface is exposed to a portion other than the region to be thinned in the subsequent step (B2).
 工程(B2)では、第一面において、薄膜化処理液によって、接続パッド3の厚さ以下になるまで、非露光部のソルダーレジスト層2を薄膜化して、接続パッド3の一部を露出させる。電子部品を搭載する配線基板の場合、この工程(B2)において露出した接続パッド3が電子部品接続用接続パッド3として使用される。工程(B2)では、第二面の非露光部のソルダーレジスト層2も同時に薄膜化されるが、第一面の接続パッド3上のソルダーレジスト層2よりも第二面の接続パッド4上のソルダーレジスト層2の方が厚いため、接続パッド4上にソルダーレジスト層2の残渣が残る。 In the step (B2), on the first surface, the solder resist layer 2 in the non-exposed part is thinned by the thinning treatment liquid until the thickness of the connection pad 3 becomes equal to or less, and a part of the connection pad 3 is exposed. . In the case of a wiring board on which electronic components are mounted, the connection pads 3 exposed in this step (B2) are used as the connection pads 3 for connecting electronic components. In the step (B2), the solder resist layer 2 of the non-exposed portion on the second surface is also thinned simultaneously, but on the connection pad 4 on the second surface rather than the solder resist layer 2 on the connection pad 3 on the first surface. Since the solder resist layer 2 is thicker, a residue of the solder resist layer 2 remains on the connection pad 4.
 工程(C5)では、第一面のソルダーレジスト層2に対して、工程(B2)で薄膜化された領域部分を露光する。 In step (C5), the solder resist layer 2 on the first surface is exposed to the region thinned in step (B2).
 工程(D)では、第二面において、非露光部のソルダーレジスト層2を、現像液によって除去し、接続パッド4の一部を露出させる。工程(D)により、接続パッド4上に残っていたソルダーレジスト層2の残渣が除去される。電子部品を搭載する配線基板の場合、この工程(D)において露出した接続パッド4が外部接続用接続パッド4として使用される。 In step (D), on the second surface, the solder resist layer 2 in the non-exposed portion is removed with a developer, and a part of the connection pad 4 is exposed. By the step (D), the residue of the solder resist layer 2 remaining on the connection pad 4 is removed. In the case of a wiring board on which electronic components are mounted, the connection pads 4 exposed in this step (D) are used as connection pads 4 for external connection.
 配線基板の製造方法(2)では、工程(C4)の露光領域を任意の形状に変化させることが可能であり、露光領域の変更により、例えば、図10に示す断面形状の配線基板を作製することが可能である。図10のcでは、第一面の接続パッド3の間にソルダーレジスト層2の凸部が形成されている。図10のdでは、第一面において、ソルダーレジスト層2から露出した接続パッド3とソルダーレジスト層2で被覆されている導体配線7が交互に並んでいる。 In the manufacturing method (2) of the wiring board, the exposure area in the step (C4) can be changed to an arbitrary shape. By changing the exposure area, for example, a wiring board having a cross-sectional shape shown in FIG. It is possible. In FIG. 10 c, the convex portion of the solder resist layer 2 is formed between the connection pads 3 on the first surface. In FIG. 10 d, the connection pads 3 exposed from the solder resist layer 2 and the conductor wirings 7 covered with the solder resist layer 2 are alternately arranged on the first surface.
 図6-1、図6-2および図6-3は、配線基板の製造方法(3)の一例を示す断面工程図である。配線基板の製造方法(2)との違いは、第一面のソルダーレジスト層が第一ソルダーレジスト層2-1と第二ソルダーレジスト層2-2から構成されている点である。配線基板の製造方法(3)では、第一面の非露光部の第一ソルダーレジスト層2-1の厚さを接続パッド3の厚さ以下になるまで薄膜化した後、第一ソルダーレジスト層2-1の表面上に第二ソルダーレジスト層2-2を形成し、露光した後、非露光部の第二ソルダーレジスト層2-2を現像処理する。これによって、配線基板の製造方法(2)を用いた場合と同じく、電子部品と配線基板の間に充填するアンダーフィルを堰き止めるためのダム構造を有する二段構造のソルダーレジスト層を形成することができる。 FIGS. 6A, 6B, and 6C are cross-sectional process diagrams illustrating an example of a method (3) of manufacturing a wiring board. The difference from the manufacturing method (2) of the wiring board is that the solder resist layer on the first surface is composed of the first solder resist layer 2-1 and the second solder resist layer 2-2. In the manufacturing method (3) of the wiring board, after the thickness of the first solder resist layer 2-1 in the non-exposed portion of the first surface is reduced to be equal to or less than the thickness of the connection pad 3, the first solder resist layer After the second solder resist layer 2-2 is formed on the surface of 2-1 and exposed, the second solder resist layer 2-2 in the non-exposed portion is developed. Thus, as in the case of using the wiring board manufacturing method (2), a two-stage solder resist layer having a dam structure for blocking an underfill filling between the electronic component and the wiring board is formed. Can do.
 工程(A1)では、回路基板1の第一面と第二面において、厚さの異なる第一ソルダーレジスト層2-1を形成する。第一面と第二面の第一ソルダーレジスト層2-1の形成は、両表面同時でも、片面ずつでもよいが、形成するソルダーレジスト層の厚さに応じて、過剰に熱硬化しないような加熱条件を設定する必要がある。 In step (A1), first solder resist layers 2-1 having different thicknesses are formed on the first surface and the second surface of the circuit board 1. The first solder resist layer 2-1 on the first surface and the second surface may be formed on both surfaces at the same time or one surface at a time. However, depending on the thickness of the solder resist layer to be formed, it does not excessively heat cure. It is necessary to set the heating conditions.
 工程(C1)では、第二面の第一ソルダーレジスト層2-1よりも厚さが薄い第一面の第一ソルダーレジスト層2-1に対して、後工程である工程(B)において薄膜化される領域以外の部分を露光する。工程(C2)では、第二面の第一ソルダーレジスト層2-1に対して、後工程である工程(D1)において現像される領域以外の部分を露光する。 In step (C1), the first solder resist layer 2-1 on the first surface, which is thinner than the first solder resist layer 2-1 on the second surface, is thinned in the subsequent step (B). A portion other than the region to be converted is exposed. In the step (C2), the first solder resist layer 2-1 on the second surface is exposed to a portion other than the region to be developed in the subsequent step (D1).
 工程(B)では、第一面において、薄膜化処理液によって、接続パッド3の厚さ以下になるまで、非露光部の第一ソルダーレジスト層2-1を薄膜化して、接続パッド3の一部を露出させる。工程(B)では、第二面の非露光部の第一ソルダーレジスト層2-1も同時に薄膜化される。しかし、第一面の接続パッド3上の第一ソルダーレジスト層2-1よりも第二面の接続パッド4上の第一ソルダーレジスト層2-1の方が厚いため、接続パッド4上に第一ソルダーレジスト層2-1の残渣が残る。 In the step (B), on the first surface, the first solder resist layer 2-1 in the non-exposed part is thinned with a thinning treatment solution until the thickness of the connection pad 3 is less than or equal to the thickness of the connection pad 3. Expose the part. In the step (B), the first solder resist layer 2-1 in the non-exposed portion on the second surface is also thinned at the same time. However, the first solder resist layer 2-1 on the connection pad 4 on the second surface is thicker than the first solder resist layer 2-1 on the connection pad 3 on the first surface. A residue of one solder resist layer 2-1 remains.
 工程(C3)では、第一面の第一ソルダーレジスト層2-1に対して、工程(B)において薄膜化された領域部分を露光する。 In step (C3), the first solder resist layer 2-1 on the first surface is exposed to the area portion thinned in step (B).
 工程(A2)では、工程(C3)まで完了した回路基板の第一面の第一ソルダーレジスト層2-1上に、第二ソルダーレジスト層2-2を形成する。この時、第一面の第二ソルダーレジスト層2-2にかかる加熱条件を調整して、第二面の第一ソルダーレジスト層2-1の非露光部が過剰に熱硬化しないようにする。 In step (A2), a second solder resist layer 2-2 is formed on the first solder resist layer 2-1 on the first surface of the circuit board completed up to step (C3). At this time, the heating condition applied to the second solder resist layer 2-2 on the first surface is adjusted so that the non-exposed portion of the first solder resist layer 2-1 on the second surface is not excessively cured.
 工程(C6)では、第一面の第二ソルダーレジスト層2-2に対して、後工程である工程(D1)において現像される領域以外の部分を露光する。 In step (C6), the second solder resist layer 2-2 on the first surface is exposed to a portion other than the region to be developed in the subsequent step (D1).
 工程(D1)では、第一面の非露光部の第二ソルダーレジスト層2-2及び第二面の非露光部の第一ソルダーレジスト層2-1を、現像液によって除去し、接続パッド3及び4の一部を露出させる。工程(D1)により、接続パッド4上に残っていた第一ソルダーレジスト層2-1の残渣が除去される。電子部品を搭載する配線基板の場合、この工程(D1)において露出した接続パッド3が電子部品接続用接続パッド3として使用され、接続パッド4が外部接続用接続パッド4として使用される。 In the step (D1), the second solder resist layer 2-2 in the non-exposed portion on the first surface and the first solder resist layer 2-1 in the non-exposed portion on the second surface are removed with a developer, and the connection pad 3 And a portion of 4 are exposed. By the step (D1), the residue of the first solder resist layer 2-1 remaining on the connection pad 4 is removed. In the case of a wiring board on which electronic components are mounted, the connection pads 3 exposed in this step (D1) are used as the connection pads 3 for electronic component connection, and the connection pads 4 are used as the connection pads 4 for external connection.
 図7-1、図7-2および図7-3は、配線基板の製造方法(4)の一例を示す断面工程図である。配線基板の製造方法(3)との違いは、第一面の第二ソルダーレジスト層2-2を形成する前に、第二面の第一ソルダーレジスト層2-1を現像液によって除去する点である。先に第二面の非露光部の第一ソルダーレジスト層2-1を現像液によって除去することによって、第一面の第二ソルダーレジスト層2-2を形成する際に、第二面の非露光部の第一ソルダーレジスト層2-1が同時に加熱されて過剰に熱硬化しないように加熱条件を調整する必要がなくなる。配線基板の製造方法(4)では、配線基板の製造方法(2)及び(3)を用いた場合と同じく、電子部品と配線基板の間に充填するアンダーフィルを堰き止めるためのダム構造を有する二段構造のソルダーレジスト層を形成することができる。 FIGS. 7A, 7B, and 7C are cross-sectional process diagrams illustrating an example of a method (4) of manufacturing a wiring board. The difference from the manufacturing method (3) of the wiring board is that the first solder resist layer 2-1 on the second surface is removed with a developer before the second solder resist layer 2-2 on the first surface is formed. It is. First, when the second solder resist layer 2-2 of the first surface is formed by removing the first solder resist layer 2-1 of the non-exposed portion of the second surface with a developing solution, It is not necessary to adjust the heating conditions so that the first solder resist layer 2-1 in the exposed area is simultaneously heated and is not excessively cured. The wiring board manufacturing method (4) has a dam structure for damming the underfill filling between the electronic component and the wiring board as in the case of using the wiring board manufacturing methods (2) and (3). A two-stage solder resist layer can be formed.
 工程(A1)では、回路基板1の第一面と第二面において、厚さの異なる第一ソルダーレジスト層2-1を形成する。工程(C1)では、第二面の第一ソルダーレジスト層2-1よりも厚さが薄い第一面の第一ソルダーレジスト層2-1に対して、後工程である工程(B)において薄膜化される領域以外の部分を露光する。工程(C2)では、第二面の第一ソルダーレジスト層2-1に対して、後工程である工程(D)において現像される領域以外の部分を露光する。 In step (A1), first solder resist layers 2-1 having different thicknesses are formed on the first surface and the second surface of the circuit board 1. In step (C1), the first solder resist layer 2-1 on the first surface, which is thinner than the first solder resist layer 2-1 on the second surface, is thinned in the subsequent step (B). A portion other than the region to be converted is exposed. In the step (C2), the first solder resist layer 2-1 on the second surface is exposed to a portion other than the region to be developed in the subsequent step (D).
 工程(B)では、第一面において、薄膜化処理液によって、接続パッド3の厚さ以下になるまで、非露光部の第一ソルダーレジスト層2-1を薄膜化して、接続パッド3の一部を露出させる。工程(B)では、第二面の非露光部の第一ソルダーレジスト層2-1も同時に薄膜化される。しかし、第一面の接続パッド3上の第一ソルダーレジスト層2-1よりも第二面の接続パッド4上の第一ソルダーレジスト層2-1の方が厚いため、接続パッド4上に第一ソルダーレジスト層2-1の残渣が残る。 In the step (B), on the first surface, the first solder resist layer 2-1 in the non-exposed part is thinned with a thinning treatment solution until the thickness of the connection pad 3 is less than or equal to the thickness of the connection pad 3. Expose the part. In the step (B), the first solder resist layer 2-1 in the non-exposed portion on the second surface is also thinned at the same time. However, the first solder resist layer 2-1 on the connection pad 4 on the second surface is thicker than the first solder resist layer 2-1 on the connection pad 3 on the first surface. A residue of one solder resist layer 2-1 remains.
 工程(C3)では、第一面の第一ソルダーレジスト層2-1に対して、工程(B)において薄膜化された領域部分を露光する。 In step (C3), the first solder resist layer 2-1 on the first surface is exposed to the area portion thinned in step (B).
 工程(D)では、第二面の非露光部の第一ソルダーレジスト層2-1を、現像液によって除去し、接続パッド4の一部を露出させる。工程(D)により、接続パッド4上に残っていた第一ソルダーレジスト層2-1の残渣が除去される。電子部品を搭載する配線基板の場合、この工程(D)において露出した接続パッド4が外部接続用接続パッド4として使用される。 In step (D), the first solder resist layer 2-1 in the non-exposed portion on the second surface is removed with a developer, and a part of the connection pad 4 is exposed. By the step (D), the residue of the first solder resist layer 2-1 remaining on the connection pad 4 is removed. In the case of a wiring board on which electronic components are mounted, the connection pads 4 exposed in this step (D) are used as connection pads 4 for external connection.
 工程(A2)では、工程(D)まで完了した回路基板の第一面の第一ソルダーレジスト層2-1上に、第二ソルダーレジスト層2-2を形成する。 In step (A2), a second solder resist layer 2-2 is formed on the first solder resist layer 2-1 on the first surface of the circuit board completed up to step (D).
 工程(C6)では、第一面の第二ソルダーレジスト層2-2に対して、後工程である工程(D2)において現像される領域以外の部分を露光する。 In step (C6), the second solder resist layer 2-2 on the first surface is exposed to a portion other than the region to be developed in the subsequent step (D2).
 工程(D2)では、第一面の非露光部の第二ソルダーレジスト層2-2を、現像液によって除去し、接続パッド3の一部を露出させる。電子部品を搭載する配線基板の場合、この工程(D2)において露出した接続パッド3が電子部品接続用接続パッド3として使用される。 In step (D2), the second solder resist layer 2-2 in the non-exposed portion on the first surface is removed with a developer, and a part of the connection pad 3 is exposed. In the case of a wiring board on which electronic components are mounted, the connection pads 3 exposed in this step (D2) are used as the connection pads 3 for connecting electronic components.
 配線基板の製造方法(3)及び(4)では、工程(C1)の露光領域を任意の形状に変化させることが可能であり、露光領域の変更により、例えば、図11に示す断面形状の配線基板を作製することが可能である。図11のeでは、第一面の接続パッド3の間に第一ソルダーレジスト層2-1の凸部が形成されている。図11のfでは、第一ソルダーレジスト層2-1から露出した接続パッド3と第一ソルダーレジスト層2-1で被覆されている導体配線7が交互に並んでいる。 In the wiring board manufacturing methods (3) and (4), the exposure area in the step (C1) can be changed to an arbitrary shape. By changing the exposure area, for example, the wiring having the cross-sectional shape shown in FIG. It is possible to produce a substrate. In e of FIG. 11, the convex part of the 1st soldering resist layer 2-1 is formed between the connection pads 3 of the 1st surface. In FIG. 11f, the connection pads 3 exposed from the first solder resist layer 2-1 and the conductor wirings 7 covered with the first solder resist layer 2-1 are alternately arranged.
 図8-1、図8-2および図8-3は、配線基板の製造方法(5)の一例を示す断面工程図である。配線基板の製造方法(5)では、第一面において、第一ソルダーレジスト層2-1に露光を行う前に第一ソルダーレジスト層2-1の厚さを接続パッド3の厚さ以下になるまで薄膜化処理する。その後、第一ソルダーレジスト層2-1の表面上に第二ソルダーレジスト層2-2を形成し、露光した後、非露光部の第二ソルダーレジスト層2-2を薄膜化処理し、その後、再度露光を行い、残った非露光部の第二ソルダーレジスト層2-2を現像処理する。配線基板の製造方法(5)では、配線基板の製造方法(2)~(4)を用いた場合と同じく、電子部品と配線基板の間に充填するアンダーフィルを堰き止めるためのダム構造を有する二段構造のソルダーレジスト層を形成することができる。 8-1, FIG. 8-2, and FIG. 8-3 are cross-sectional process diagrams showing an example of a method (5) of manufacturing a wiring board. In the wiring board manufacturing method (5), on the first surface, the thickness of the first solder resist layer 2-1 becomes equal to or less than the thickness of the connection pad 3 before the first solder resist layer 2-1 is exposed. Thin film processing. Thereafter, a second solder resist layer 2-2 is formed on the surface of the first solder resist layer 2-1, and after exposure, the second solder resist layer 2-2 in the non-exposed part is thinned, Exposure is performed again, and the remaining second solder resist layer 2-2 in the unexposed area is developed. The wiring board manufacturing method (5) has a dam structure for damming the underfill filling between the electronic component and the wiring board, as in the case of using the wiring board manufacturing methods (2) to (4). A two-stage solder resist layer can be formed.
 工程(A1)では、回路基板1の第一面と第二面において、厚さの異なる第一ソルダーレジスト層2-1を形成する。工程(C2)では、第二面の第一ソルダーレジスト層2-1に対して、後工程である工程(D1)において現像される領域以外の部分を露光する。 In step (A1), first solder resist layers 2-1 having different thicknesses are formed on the first surface and the second surface of the circuit board 1. In the step (C2), the first solder resist layer 2-1 on the second surface is exposed to a portion other than the region to be developed in the subsequent step (D1).
 工程(B)では、第一面において、薄膜化処理液によって、接続パッド3の厚さ以下になるまで、非露光部の第一ソルダーレジスト層2-1を薄膜化して、全ての接続パッド3の一部を露出させる。工程(B)では、第二面の非露光部の第一ソルダーレジスト層2-1も同時に薄膜化される。しかし、第一面の接続パッド3上の第一ソルダーレジスト層2-1よりも第二面の接続パッド4上の第一ソルダーレジスト層2-1の方が厚いため、接続パッド4上に第一ソルダーレジスト層2-1の残渣が残る。 In the step (B), on the first surface, the first solder resist layer 2-1 in the non-exposed portion is thinned with the thinning treatment solution until the thickness of the connection pad 3 is less than or equal to all the connection pads 3 To expose a part of In the step (B), the first solder resist layer 2-1 in the non-exposed portion on the second surface is also thinned at the same time. However, the first solder resist layer 2-1 on the connection pad 4 on the second surface is thicker than the first solder resist layer 2-1 on the connection pad 3 on the first surface. A residue of one solder resist layer 2-1 remains.
 工程(C3)では、第一面の第一ソルダーレジスト層2-1に対して、工程(B)において薄膜化された領域部分を露光する。 In step (C3), the first solder resist layer 2-1 on the first surface is exposed to the area portion thinned in step (B).
 工程(A2)では、工程(C3)まで完了した回路基板の第一面の第一ソルダーレジスト層2-1上に、第二ソルダーレジスト層2-2を形成する。 In step (A2), a second solder resist layer 2-2 is formed on the first solder resist layer 2-1 on the first surface of the circuit board completed up to step (C3).
 工程(C6)では、第一面の第二ソルダーレジスト層2-2に対して、後工程である工程(B3)において薄膜化される領域以外の部分を露光する。 In step (C6), the second solder resist layer 2-2 on the first surface is exposed to a portion other than the region to be thinned in the subsequent step (B3).
 工程(B3)では、第一面において、薄膜化処理液によって、接続パッド3が露出しない範囲で、非露光部の第二ソルダーレジスト層2-2を薄膜化する。工程(B3)では、第二面の非露光部の第一ソルダーレジスト層2-1も同時に薄膜化される。しかし、接続パッド4上に第一ソルダーレジスト層2-1の残渣が残る場合がある。 In step (B3), on the first surface, the second solder resist layer 2-2 in the non-exposed portion is thinned by the thinning treatment solution in a range where the connection pad 3 is not exposed. In the step (B3), the first solder resist layer 2-1 in the non-exposed portion on the second surface is also thinned at the same time. However, a residue of the first solder resist layer 2-1 may remain on the connection pad 4.
 工程(C7)では、第一面の第二ソルダーレジスト層2-2に対して、後工程である工程(D1)において現像される領域以外の部分を露光する。 In step (C7), the second solder resist layer 2-2 on the first surface is exposed to a portion other than the region to be developed in the subsequent step (D1).
 工程(D1)では、第一面の非露光部の第二ソルダーレジスト層2-2及び第二面の非露光部の第一ソルダーレジスト層2-1を、現像液によって除去し、接続パッド3の一部を再び露出させ、同時に接続パッド4の一部を露出させる。工程(D1)により、接続パッド4上に残っていた第一ソルダーレジスト層2-1の残渣が除去される。電子部品を搭載する配線基板の場合、この工程(D1)において露出した接続パッド3が電子部品接続用接続パッド3として使用され、接続パッド4が外部接続用接続パッド4として使用される。 In the step (D1), the second solder resist layer 2-2 in the non-exposed portion on the first surface and the first solder resist layer 2-1 in the non-exposed portion on the second surface are removed with a developer, and the connection pad 3 A part of the connection pad 4 is exposed again, and at the same time, a part of the connection pad 4 is exposed. By the step (D1), the residue of the first solder resist layer 2-1 remaining on the connection pad 4 is removed. In the case of a wiring board on which electronic components are mounted, the connection pads 3 exposed in this step (D1) are used as the connection pads 3 for electronic component connection, and the connection pads 4 are used as the connection pads 4 for external connection.
 配線基板の製造方法(5)では、工程(C7)の露光領域を任意の形状に変化させることが可能であり、露光領域の変更により、例えば、図12に示す断面形状の配線基板を作製することが可能である。図12のgでは、第一面の接続パッド3の間に第二ソルダーレジスト層2-2の凸部が形成されている。図12のhでは、第一ソルダーレジスト層2-1から露出した接続パッド3と第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2で被覆されている導体配線7が交互に並んでいる。 In the manufacturing method (5) of the wiring board, the exposure area in the step (C7) can be changed to an arbitrary shape. By changing the exposure area, for example, a wiring board having a cross-sectional shape shown in FIG. It is possible. In FIG. 12g, a convex portion of the second solder resist layer 2-2 is formed between the connection pads 3 on the first surface. In h of FIG. 12, the connection pads 3 exposed from the first solder resist layer 2-1 and the conductor wirings 7 covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 are alternately arranged. It is out.
 本発明に係わる回路基板1とは、絶縁層8と、絶縁層8の表面に形成された接続パッド3及び4とを有する。絶縁層8の表面には、導体配線7が形成されていて、接続パッド3及び4は導体配線7の一部である。本発明に係わる配線基板は、回路基板1の両表面にソルダーレジスト層2を有し、ソルダーレジスト層2から接続パッド3及び4の一部が露出している。電子部品を搭載する配線基板の場合、表面に電子部品接続用接続パッド3を有し、裏面に外部接続用接続パッド4を有する。表面の電子部品接続用接続パッド3と電子部品を接合し、裏面の外部接続用接続パッド4と外部電気基板の導体配線を接合する。 The circuit board 1 according to the present invention includes an insulating layer 8 and connection pads 3 and 4 formed on the surface of the insulating layer 8. Conductor wiring 7 is formed on the surface of the insulating layer 8, and the connection pads 3 and 4 are part of the conductor wiring 7. The wiring board according to the present invention has solder resist layers 2 on both surfaces of the circuit board 1, and part of the connection pads 3 and 4 are exposed from the solder resist layer 2. In the case of a wiring board on which electronic components are mounted, the connection pads 3 for connecting electronic components are provided on the front surface, and the connection pads 4 for external connection are provided on the back surface. The electronic component connecting connection pad 3 on the front surface and the electronic component are bonded, and the external connecting connection pad 4 on the back surface and the conductor wiring of the external electric substrate are bonded.
 本発明に係わる回路基板は、例えば、導体配線が配設された絶縁基板にビルドアップ用の絶縁層や導体配線を交互に積層して作製される。図13A,Bは、導体配線が配設された絶縁基板にビルドアップ用の絶縁層や導体配線を交互に積層して作製された回路基板の一例を示す概略断面図である。本発明の配線基板の製造方法の一例を示した断面工程図である図4~8、本発明によって製造できる配線基板の一例を示す概略断面図である図9~12には、絶縁層8を一層有し、絶縁層8の両表面に形成された導体配線7を有する回路基板1が記載されているが、本発明の配線基板の製造方法に使用される回路基板1としては、図13A,Bのように、導体配線が配設された絶縁基板にビルドアップ用の絶縁層や導体配線を交互に積層して作製され、絶縁層8と、絶縁層8の表面に形成された導体配線7とを両表面に有する回路基板1が含まれる。絶縁基板としては、例えば、ガラスクロスにビスマレイミドトリアジン樹脂やエポキシ樹脂等の熱硬化性樹脂を含浸させた電気絶縁材料等からなる樹脂製基板が挙げられる。ビルドアップ用の絶縁層としては、例えば、絶縁基板と同様にガラスクロスに熱硬化性樹脂を含浸させた電気絶縁材料、エポキシ樹脂等の熱硬化性樹脂に酸化ケイ素等の無機フィラーを分散させた電気絶縁材料等が挙げられる。導体配線は、例えば、サブトラクティブ法、セミアディティブ法、アディティブ法等によって形成される。サブトラクティブ法では、例えば、絶縁層上に銅層を形成した後にエッチングレジスト層を形成し、露光、現像、エッチング、レジスト剥離を実施して、導体配線を形成する。セミアディティブ法では、絶縁層の表面に無電解銅めっきにより電解銅めっき用の下地金属層を設ける。次に、導体配線に対応した開口を有するめっきレジスト層を形成し、電解銅めっきによって露出した下地金属層の表面に電解銅めっき層を形成する。その後、めっきレジスト層を剥離し、露出した下地金属層をフラッシュエッチングで除去することによって導体配線を形成する。 The circuit board according to the present invention is produced, for example, by alternately laminating build-up insulating layers and conductor wiring on an insulating substrate on which conductor wiring is disposed. 13A and 13B are schematic cross-sectional views showing an example of a circuit board produced by alternately laminating build-up insulating layers and conductor wirings on an insulating board on which conductor wirings are arranged. 4 to 8 are sectional process diagrams showing an example of a method for manufacturing a wiring board of the present invention, and FIGS. 9 to 12 are schematic sectional views showing examples of a wiring board that can be manufactured according to the present invention. Although the circuit board 1 having the conductor wiring 7 formed on both surfaces of the insulating layer 8 is described, the circuit board 1 used in the method for manufacturing a wiring board according to the present invention is shown in FIG. As shown in B, the insulating layer 8 and the conductor wiring 7 formed on the surface of the insulating layer 8 are produced by alternately laminating build-up insulating layers and conductor wiring on the insulating substrate on which the conductor wiring is disposed. The circuit board 1 having both of the surfaces is included. Examples of the insulating substrate include a resin substrate made of an electrically insulating material in which a glass cloth is impregnated with a thermosetting resin such as a bismaleimide triazine resin or an epoxy resin. As an insulating layer for buildup, for example, an electrical insulating material in which a glass cloth is impregnated with a thermosetting resin, as in the case of an insulating substrate, an inorganic filler such as silicon oxide is dispersed in a thermosetting resin such as an epoxy resin. Examples include electrical insulating materials. The conductor wiring is formed by, for example, a subtractive method, a semi-additive method, an additive method, or the like. In the subtractive method, for example, after forming a copper layer on an insulating layer, an etching resist layer is formed, and exposure, development, etching, and resist stripping are performed to form a conductor wiring. In the semi-additive method, a base metal layer for electrolytic copper plating is provided on the surface of the insulating layer by electroless copper plating. Next, a plating resist layer having an opening corresponding to the conductor wiring is formed, and an electrolytic copper plating layer is formed on the surface of the base metal layer exposed by electrolytic copper plating. Thereafter, the plating resist layer is peeled off, and the exposed base metal layer is removed by flash etching to form a conductor wiring.
 電子部品を搭載する配線基板の場合、配線基板の表面の接続パッドは、電子部品と接続するための接続用パッドである。電子部品は、この接続パッドと半田バンプを介して電気的に接続されることにより、配線基板にフリップチップ実装される。ソルダーレジスト層との密着性を向上させるために、接続パッド表面を粗面化処理することもできるし、カップリング剤処理することもできる。配線基板の裏面の接続パッドは、外部接続するための接続用パッドである。半田バンプを介して、この接続パッドとマザーボード等の外部電気基板の導体配線を電気的に接続させることにより、マザーボードにフリップチップ実装される。 In the case of a wiring board on which an electronic component is mounted, the connection pad on the surface of the wiring board is a connection pad for connecting to the electronic component. The electronic component is flip-chip mounted on the wiring board by being electrically connected to the connection pad via the solder bump. In order to improve the adhesion with the solder resist layer, the surface of the connection pad can be roughened or can be treated with a coupling agent. The connection pad on the back surface of the wiring board is a connection pad for external connection. Flip chip mounting is performed on the mother board by electrically connecting the connection pads and conductor wiring of an external electric board such as the mother board through solder bumps.
 本発明に係わるソルダーレジストとしては、アルカリ現像型のソルダーレジストが使用できる。また、1液性、2液性、どちらの液状レジストであってもよく、ドライフィルム状レジストであってもよい。ソルダーレジストは、例えば、アルカリ可溶性樹脂、単官能アクリルモノマー、多官能アクリルモノマー、光重合開始剤、エポキシ樹脂、無機フィラー等を含有してなる。 As the solder resist according to the present invention, an alkali developing type solder resist can be used. Further, it may be either a one-component or two-component liquid resist, or a dry film resist. The solder resist contains, for example, an alkali-soluble resin, a monofunctional acrylic monomer, a polyfunctional acrylic monomer, a photopolymerization initiator, an epoxy resin, an inorganic filler, and the like.
 アルカリ可溶性樹脂としては、光硬化性と熱硬化性の両方の特性を持つアルカリ可溶性樹脂が挙げられ、例えば、ノボラック型エポキシ樹脂にアクリル酸を付加させてエポキシアクリレート化した樹脂の2級の水酸基に酸無水物を付加させた樹脂が挙げられる。多官能アクリルモノマーとしては、例えば、トリメチロールプロパントリアクリレート(Trimethylol Propane Triacrylate)、ジペンタエリスリトールヘキサアクリレート(Di-pentaerythritol Polyacrylate)、ペンタエリスリトールトリアクリレート(Pentaerythritol Triacrylate)等が挙げられる。光重合開始剤としては、2-メチル-1-(4-メチルチオフェニル)-2-モルフォリノプロパン-1-オン(2-Methyl-1-(4-Methylthiophenyl)-2-Morpholinopropan-1-one)等が挙げられる。エポキシ樹脂は、硬化剤として用いられる。アルカリ可溶性樹脂のカルボン酸と反応させることで架橋させ、耐熱性や耐薬品性の特性の向上を図っているが、カルボン酸とエポキシは常温でも反応が進むために、保存安定性が悪く、アルカリ現像型ソルダーレジストは一般的に使用前に混合する2液性の形態をとっている場合が多い。無機フィラーとしては、例えば、タルク、シリカ、硫酸バリウム、酸化チタン、酸化亜鉛等が挙げられる。 Examples of the alkali-soluble resin include alkali-soluble resins having both photo-curing properties and thermosetting properties. For example, a secondary hydroxyl group of a resin obtained by adding acrylic acid to a novolak-type epoxy resin to form an epoxy acrylate. A resin to which an acid anhydride has been added may be mentioned. Examples of the polyfunctional acrylic monomer include trimethylolpropane triacrylate (Trimethylol Propane Triacrylate), dipentaerythritol hexaacrylate (Di-pentaerythritol Polyacrylate), and pentaerythritol triacrylate (Pentaerythritol Triacrylate). As a photopolymerization initiator, 2-methyl-1- (4-methylthiophenyl) -2-morpholinopropan-1-one (2-Methyl-1- (4-Methylthiophenyl) -2-Morpholinopropan-1-one) Etc. Epoxy resin is used as a curing agent. It is cross-linked by reacting with carboxylic acid of alkali-soluble resin to improve heat resistance and chemical resistance, but carboxylic acid and epoxy react at room temperature, so the storage stability is poor and alkaline In general, the development type solder resist often takes a two-component form to be mixed before use. Examples of the inorganic filler include talc, silica, barium sulfate, titanium oxide, and zinc oxide.
 ソルダーレジスト層は、回路基板の両表面において、全面を覆うようにして形成される。ソルダーレジスト層の形成には、例えば、液状レジストであれば、スクリーン印刷法、ロールコート法、スプレー法、浸漬法、カーテンコート法、バーコート法、エアナイフ法、ホットメルト法、グラビアコート法、刷毛塗り法、オフセット印刷法を用いることができる。また、フィルム状レジストであれば、ラミネート法や真空ラミネート法が用いられる。 The solder resist layer is formed so as to cover the entire surface on both surfaces of the circuit board. For forming the solder resist layer, for example, if it is a liquid resist, screen printing method, roll coating method, spray method, dipping method, curtain coating method, bar coating method, air knife method, hot melt method, gravure coating method, brush A coating method or an offset printing method can be used. In the case of a film-like resist, a laminating method or a vacuum laminating method is used.
 配線基板の製造方法(1)及び(2)における工程(A)で形成されるソルダーレジスト層2と、配線基板の製造方法(3)~(5)における工程(A1)で形成される第一ソルダーレジスト層2-1は、回路基板の両表面において厚さが異なっていて、厚さの薄い方が「第一面」であり、厚さの厚い方が「第二面」である。回路基板の両表面にソルダーレジスト層を形成させる際、両表面で同じ条件を設定するのが一般的である。これは、ソルダーレジストが熱硬化性を持つことに由来する。液状レジストの場合、塗布後に脱溶媒のための加熱乾燥が必要となるため、各表面で塗布量が異なると、各表面で乾燥条件を変更しなければならないが、その際に過剰に熱硬化しないような条件を設定しなければならない。また、ドライフィルム状レジストの場合、ラミネート時に加熱が必要となるため、各表面で厚さが違うドライフィルム状レジストを使用すると、各表面でラミネート時の加熱条件を変えなければならないが、その際に過剰に熱硬化しないような条件を設定しなければならない。このように各表面におけるソルダーレジスト層の厚さ、加熱乾燥条件等を変えるのではなく、両表面におけるソルダーレジスト層の種類、厚さ、加熱乾燥条件等を同条件にした方が、作業工程を簡易にすることができて好ましい。 Solder resist layer 2 formed in step (A) in wiring board manufacturing methods (1) and (2), and first formed in steps (A1) in wiring board manufacturing methods (3) to (5). The solder resist layer 2-1 has different thicknesses on both surfaces of the circuit board. The thinner one is the “first surface” and the thicker one is the “second surface”. When forming solder resist layers on both surfaces of a circuit board, the same conditions are generally set on both surfaces. This is because the solder resist has thermosetting properties. In the case of a liquid resist, it is necessary to heat and dry to remove the solvent after coating. Therefore, if the coating amount is different on each surface, the drying conditions must be changed on each surface. Such a condition must be set. In the case of dry film resists, heating is required during lamination, so if dry film resists with different thicknesses are used on each surface, the heating conditions during lamination must be changed on each surface. The conditions must be set so as not to overheat. Instead of changing the thickness of the solder resist layer on each surface, heat drying conditions, etc. in this way, it is better to make the type, thickness, heat drying conditions, etc. of the solder resist layer on both surfaces the same conditions. This is preferable because it can be simplified.
 回路基板の両表面にソルダーレジスト層を同条件で形成した場合、ソルダーレジスト層の厚さは、各面の接続パッドを含むその周囲の導体配線の密度によって変化する。例えば、電子部品を搭載する配線基板において、裏面の外部接続用接続パッドがエリアアレイ型に配列されている場合、表面の電子部品接続用接続パッドを含むその周囲の導体配線の密度に比べ、裏面の外部接続用接続パッドを含むその周囲の導体配線の密度が大きくなる。その結果、裏面の外部接続用接続パッド上のソルダーレジスト層の厚さは、表面の電子部品接続用接続パッド上のソルダーレジスト層の厚さよりも厚くなる。この場合、表面が第一面であり、裏面が第二面である。 When the solder resist layer is formed on both surfaces of the circuit board under the same conditions, the thickness of the solder resist layer varies depending on the density of the surrounding conductor wiring including the connection pads on each surface. For example, in a wiring board on which electronic components are mounted, when the external connection connection pads on the back surface are arranged in an area array type, the back surface is compared with the density of the surrounding conductor wiring including the connection pads for electronic component connection on the front surface. The density of the surrounding conductor wiring including the external connection pad is increased. As a result, the thickness of the solder resist layer on the external connection connection pad on the back surface is larger than the thickness of the solder resist layer on the electronic component connection connection pad on the front surface. In this case, the front surface is the first surface and the back surface is the second surface.
 本発明に係わるソルダーレジスト層が薄膜化される工程とは、薄膜化処理液によって非露光部のソルダーレジスト層成分をミセル化させるミセル化処理(薄膜化処理)、次にミセル除去液によってミセルを除去するミセル除去処理を含む工程である。さらに、除去しきれなかったミセルや残存している薄膜化処理液及びミセル除去液を水洗によって洗い流す水洗処理、水洗水を除去する乾燥処理を含んでもよい。 The process in which the solder resist layer according to the present invention is thinned is a micellization process (thinning process) in which the solder resist layer components in the non-exposed area are micellized with a thinning solution, and then the micelles are removed with a micelle removal solution. It is a process including the micelle removal process to remove. Further, it may include a washing process for washing away the micelles that could not be removed, the remaining thinning treatment liquid and the micelle removal liquid by washing with water, and a drying process for removing the washing water.
 薄膜化処理(ミセル化処理)とは、薄膜化処理液によって、非露光部のソルダーレジスト層成分をミセル化し、このミセルを薄膜化処理液に対して不溶化する処理である。 The thinning treatment (micellar treatment) is a treatment in which the solder resist layer components in the non-exposed part are micelleed with a thinning treatment solution and the micelles are insolubilized in the thinning treatment solution.
 本発明に係わる薄膜化処理液には、アルカリ水溶液を使用することができる。薄膜化処理液として使用できるアルカリ水溶液としては、アルカリ金属ケイ酸塩(Alkali Metal Silicate)、アルカリ金属水酸化物(Alkali Metal Hydroxide)、アルカリ金属リン酸塩(Alkali Metal Phosphate)、アルカリ金属炭酸塩(Alkali Metal Carbonate)、アンモニウムリン酸塩、アンモニウム炭酸塩等の無機アルカリ性化合物の水溶液;モノエタノールアミン、ジエタノールアミン、トリエタノールアミン、メチルアミン、ジメチルアミン、エチルアミン、ジエチルアミン、トリエチルアミン、シクロヘキシルアミン、テトラメチルアンモニウムヒドロキシド(Tetramethylammonium Hydroxide、TMAH)、テトラエチルアンモニウムヒドロキシド、トリメチル-2-ヒドロキシエチルアンモニウムヒドロキサイド(コリン、Choline)等の有機アルカリ性化合物の水溶液が挙げられる。アルカリ金属としては、リチウム、ナトリウム、カリウム等が挙げられる。上記無機アルカリ性化合物及び有機アルカリ性化合物は、単独で用いてもよいし、複数組み合わせて用いてもよい。無機アルカリ性化合物と有機アルカリ性化合物を組み合わせて用いてもよい。 An alkaline aqueous solution can be used for the thinning solution according to the present invention. Alkaline aqueous solutions that can be used as the thinning solution include alkali metal silicate (Alkali Metal Silicate), alkali metal hydroxide (Alkali Metal Hydroxide), alkali metal phosphate (Alkali Metal Phosphate), alkali metal carbonate ( Alkali Metal Carbonate), aqueous solutions of inorganic alkaline compounds such as ammonium phosphate and ammonium carbonate; monoethanolamine, diethanolamine, triethanolamine, methylamine, dimethylamine, ethylamine, diethylamine, triethylamine, cyclohexylamine, tetramethylammonium hydroxy (Tetramethylammonium Hydroxide, T AH), tetraethylammonium hydroxide, trimethyl-2-hydroxyethyl ammonium hydroxide (choline, include aqueous solutions of organic alkaline compounds such as Choline). Examples of the alkali metal include lithium, sodium, and potassium. The inorganic alkaline compound and organic alkaline compound may be used alone or in combination. Inorganic alkaline compounds and organic alkaline compounds may be used in combination.
 また、ソルダーレジスト層表面をより均一に薄膜化するために、薄膜化処理液に、硫酸塩、亜硫酸塩を添加することもできる。硫酸塩又は亜硫酸塩としては、リチウム、ナトリウム又はカリウム等のアルカリ金属硫酸塩又は亜硫酸塩、マグネシウム、カルシウム等のアルカリ土類金属硫酸塩又は亜硫酸塩が挙げられる。 Also, in order to make the surface of the solder resist layer more uniform, sulfates and sulfites can be added to the thinning solution. Examples of the sulfate or sulfite include alkali metal sulfates or sulfites such as lithium, sodium or potassium, and alkaline earth metal sulfates or sulfites such as magnesium and calcium.
 薄膜化処理液としては、これらの中でも特に、アルカリ金属炭酸塩、アルカリ金属リン酸塩、アルカリ金属水酸化物、アルカリ金属ケイ酸塩から選ばれる無機アルカリ性化合物、及び、TMAH(テトラメチルアンモニウムヒドロキシド)、コリンから選ばれる有機アルカリ性化合物のうち少なくともいずれか1種を含み、該無機アルカリ性化合物及び有機アルカリ性化合物の含有量が3~25質量%である薄膜化処理液が、表面をより均一に薄膜化できるため、好適に使用できる。3質量%未満では、薄膜化する処理でムラが発生しやすくなる場合がある。また、25質量%を超えると、無機アルカリ性化合物の析出が起こりやすく、液の経時安定性、作業性に劣る場合がある。アルカリ性化合物の含有量は5~20質量%がより好ましく、7~15質量%がさらに好ましい。薄膜化処理液のpHは10以上とすることが好ましい。また、界面活性剤、消泡剤、溶剤等を適宜添加することもできる。 Among these, as the thinning treatment liquid, among these, an inorganic alkaline compound selected from alkali metal carbonates, alkali metal phosphates, alkali metal hydroxides, alkali metal silicates, and TMAH (tetramethylammonium hydroxide) ), A thinning solution containing at least one of the organic alkaline compounds selected from choline and containing 3 to 25% by mass of the inorganic alkaline compound and the organic alkaline compound has a more uniform surface. Can be preferably used. If it is less than 3% by mass, unevenness may easily occur in the thinning process. Moreover, when it exceeds 25 mass%, precipitation of an inorganic alkaline compound will occur easily and it may be inferior to the temporal stability of a liquid, and workability | operativity. The content of the alkaline compound is more preferably 5 to 20% by mass, and further preferably 7 to 15% by mass. The pH of the thinning treatment solution is preferably 10 or more. Further, a surfactant, an antifoaming agent, a solvent and the like can be added as appropriate.
 ソルダーレジスト層の薄膜化においては、ソルダーレジスト層中に含まれる薄膜化処理液に不溶な無機フィラーの存在が無視できない。無機フィラーのサイズはその種類にもよるが、ナノフィラーと呼ばれるサブミクロンオーダーのものから、大きいものでは数十ミクロンのものまで、ある程度の粒度分布を持って、層中に30~70質量%の含有量で存在している。薄膜化は、アルカリ性化合物がソルダーレジスト層中に浸透した後、ソルダーレジスト層成分のミセル化とミセル除去過程によって進行するが、不溶性の無機フィラーの存在により、アルカリ性化合物の浸透が抑制され、薄膜化速度が遅くなることがある。 In the thinning of the solder resist layer, the presence of inorganic fillers that are insoluble in the thinning solution contained in the solder resist layer cannot be ignored. The size of the inorganic filler depends on its type, but it has a certain particle size distribution from submicron order called nanofiller to several tens of microns, and it is 30-70% by mass in the layer. Present in content. Thinning proceeds after the alkaline compound penetrates into the solder resist layer and then proceeds through the process of micelle formation and micelle removal of the solder resist layer components, but the presence of insoluble inorganic filler suppresses the penetration of the alkaline compound, resulting in thinning. The speed may be slow.
 このような無機フィラーによるアルカリ性化合物の浸透阻害に対し、薄膜化処理液のpHは12.5以上とするのが良く、13.0以上とするのがさらに好ましい。薄膜化処理液のpHが高いほど、アルカリ性化合物が浸透した際のソルダーレジスト層の膨潤が大きくなり、無機フィラーによる浸透阻害の影響を受けにくくなる。 The pH of the thinning solution is preferably 12.5 or more, and more preferably 13.0 or more, with respect to the inhibition of the penetration of the alkaline compound by such an inorganic filler. The higher the pH of the thinning solution, the greater the swelling of the solder resist layer when the alkaline compound penetrates, and the less the influence of the penetration inhibition by the inorganic filler.
 本発明において、薄膜化によって、第一面の接続パッドの一部を露出させる場合、この露出した接続パッドは電子部品接続用接続パッドとして使用できる。通常、接続パッド表面は粗面化され、そのアンカー効果によって接続パッドとソルダーレジスト層の密着性が向上し、長時間に渡って高い絶縁信頼性が維持される。従来のソルダーレジストパターン形成では、ソルダーレジスト層を除去して接続パッド表面を露出させる際、分散能力に優れた低濃度の炭酸ナトリウム水溶液を現像液として用いるのが一般的で、接続パッド表面にはソルダーレジスト層の残渣はほとんど発生しない。しかし、低濃度の炭酸ナトリウム水溶液を用いてソルダーレジスト層の薄膜化を行うと、面内均一に薄膜化することができず、面内ムラが発生する。 In the present invention, when a part of the connection pad on the first surface is exposed by thinning, the exposed connection pad can be used as a connection pad for connecting an electronic component. Usually, the surface of the connection pad is roughened, and the anchor effect improves the adhesion between the connection pad and the solder resist layer, and high insulation reliability is maintained for a long time. In conventional solder resist pattern formation, when removing the solder resist layer and exposing the connection pad surface, it is common to use a low-concentration sodium carbonate aqueous solution with excellent dispersion ability as the developer. Almost no residue of the solder resist layer is generated. However, if the solder resist layer is thinned using a low-concentration sodium carbonate aqueous solution, it cannot be uniformly thinned in the surface, and in-plane unevenness occurs.
 薄膜化処理液の温度は、15~35℃が好ましく、さらに好ましくは20~30℃である。温度が低すぎると、ソルダーレジスト層へのアルカリ性化合物の浸透速度が遅くなる場合があり、所望の厚さを薄膜化するのに長時間を要する。一方、温度が高すぎると、ソルダーレジスト層成分のミセル化と同時にミセル除去過程が進行することにより、面内で膜厚ムラが発生しやすくなる場合があるため好ましくない。 The temperature of the thinning treatment liquid is preferably 15 to 35 ° C, more preferably 20 to 30 ° C. If the temperature is too low, the penetration rate of the alkaline compound into the solder resist layer may be slow, and it takes a long time to reduce the desired thickness. On the other hand, if the temperature is too high, the micelle removal process proceeds simultaneously with the micelle formation of the solder resist layer components, which may cause uneven film thickness in the surface, which is not preferable.
 薄膜化処理液による薄膜化処理では、浸漬処理、パドル処理、スプレー処理、ブラッシング、スクレーピング等の方法を用いることができるが、浸漬処理が好ましい。浸漬処理以外の処理方法は、薄膜化処理液中に気泡が発生しやすく、その発生した気泡が薄膜化中にソルダーレジスト層表面に付着して、膜厚が不均一となる場合がある。スプレー処理等を使用する場合には、気泡が発生しないように、スプレー圧をできるだけ小さくすることが好ましい。 In the thinning treatment using the thinning treatment liquid, methods such as immersion treatment, paddle treatment, spray treatment, brushing, and scraping can be used, but immersion treatment is preferred. In the treatment methods other than the immersion treatment, bubbles are likely to be generated in the thinning treatment liquid, and the generated bubbles may adhere to the surface of the solder resist layer during the thinning, resulting in uneven film thickness. When spraying or the like is used, it is preferable to make the spray pressure as small as possible so that bubbles are not generated.
 薄膜化処理液による薄膜化処理の後には、薄膜化処理液に対して不溶化されたソルダーレジスト層成分のミセルを除去するミセル除去処理において、ミセル除去液をスプレーすることによって、一挙にミセルを溶解除去する。 After the thinning treatment with the thinning solution, the micelles are dissolved all at once by spraying the micelle removal solution in the micelle removal treatment that removes the micelles of the solder resist layer components insolubilized in the thinning solution. Remove.
 ミセル除去液としては、水道水、工業用水、純水等を用いることができる。また、アルカリ金属炭酸塩、アルカリ金属リン酸塩、アルカリ金属ケイ酸塩から選ばれる無機アルカリ性化合物のうち少なくともいずれか1種を含むpH5~10の水溶液をミセル除去液として用いることによって、薄膜化処理液で不溶化されたソルダーレジスト層成分が再分散しやすくなる。ミセル除去液のpHが5未満の場合、ソルダーレジスト層成分が凝集し、不溶性のスラッジとなって、薄膜化したソルダーレジスト層表面に付着するおそれがある。一方、ミセル除去液のpHが10を超えた場合、ソルダーレジスト層成分のミセル化とミセル除去過程が同時に促進され、面内で膜厚ムラが発生しやすくなることがある。また、ミセル除去液は、硫酸、リン酸、塩酸などを用いて、pHを調整することができる。 As the micelle removal liquid, tap water, industrial water, pure water or the like can be used. Further, by using an aqueous solution having a pH of 5 to 10 containing at least one of inorganic alkaline compounds selected from alkali metal carbonates, alkali metal phosphates, and alkali metal silicates as a micelle removal solution, a thinning treatment is performed. The solder resist layer component insolubilized with the liquid is easily redispersed. When the pH of the micelle removal solution is less than 5, the solder resist layer components aggregate and become insoluble sludge, which may adhere to the surface of the solder resist layer that has been thinned. On the other hand, when the pH of the micelle removal solution exceeds 10, micelle formation of the solder resist layer component and the micelle removal process are promoted at the same time, and uneven film thickness tends to occur in the surface. In addition, the pH of the micelle removal solution can be adjusted using sulfuric acid, phosphoric acid, hydrochloric acid, or the like.
 ミセル除去処理におけるスプレーの条件について説明する。スプレーの条件(温度、時間、スプレー圧)は、薄膜化処理されるソルダーレジスト層の溶解速度に合わせて適宜調整される。具体的には、処理温度は10~50℃が好ましく、より好ましくは22~50℃である。水溶液の温度が10℃未満ではソルダーレジスト層成分の溶解不良が起こり、粗面化された接続パッド表面にソルダーレジスト層の残渣が残りやすい場合がある。一方、50℃を超えると、水溶液の蒸発や連続運転での温度管理の問題、装置設計上の制約が発生する場合があり好ましくない。また、スプレー圧は0.01~0.5MPaとするのが好ましく、より好ましくは0.1~0.3MPaがより好ましい。ミセル除去液の供給流量は、ソルダーレジスト層1cm当たり0.030~1.0L/minが好ましく、0.050~1.0L/minがより好ましく、0.10~1.0L/minがさらに好ましい。供給流量がこの範囲であると、薄膜化後のソルダーレジスト層表面に不溶解成分を残すことなく、面内略均一にミセルを除去することができる。ソルダーレジスト層1cm当たりの供給流量が0.030L/min未満では、ソルダーレジスト層の不溶解成分が残る場合がある。一方、供給流量が1.0L/minを超えると、供給のために必要なポンプなどの部品が巨大になり、大掛かりな装置が必要となる場合がある。さらに、1.0L/minを超えた供給量では、ソルダーレジスト層成分の溶解除去に与える効果が変わらなくなることがある。 The spray conditions in the micelle removal process will be described. The spray conditions (temperature, time, spray pressure) are appropriately adjusted according to the dissolution rate of the solder resist layer to be thinned. Specifically, the treatment temperature is preferably 10 to 50 ° C., more preferably 22 to 50 ° C. If the temperature of the aqueous solution is less than 10 ° C., poor dissolution of the solder resist layer components may occur, and the solder resist layer residue may easily remain on the roughened connection pad surface. On the other hand, when the temperature exceeds 50 ° C., problems such as evaporation of the aqueous solution, temperature management in continuous operation, and restrictions on the device design may occur, which is not preferable. The spray pressure is preferably 0.01 to 0.5 MPa, more preferably 0.1 to 0.3 MPa. The supply flow rate of the micelle removal liquid is preferably 0.030 to 1.0 L / min, more preferably 0.050 to 1.0 L / min, and further 0.10 to 1.0 L / min per 1 cm 2 of the solder resist layer. preferable. When the supply flow rate is within this range, the micelles can be removed substantially uniformly in the surface without leaving insoluble components on the surface of the solder resist layer after thinning. When the supply flow rate per 1 cm 2 of the solder resist layer is less than 0.030 L / min, insoluble components of the solder resist layer may remain. On the other hand, when the supply flow rate exceeds 1.0 L / min, parts such as a pump necessary for supply become enormous and a large-scale device may be required. Furthermore, when the supply amount exceeds 1.0 L / min, the effect of dissolving and removing the solder resist layer components may not change.
 配線基板の製造方法(1)及び(2)における工程(A)、配線基板の製造方法(3)~(5)における工程(A1)及び(A2)において、第一面に形成されたソルダーレジスト層2、第一ソルダーレジスト層2-1、第二ソルダーレジスト層2-2の厚さと、配線基板の製造方法(1)、(3)~(5)における工程(B)、配線基板の製造方法(2)における工程(B1)及び(B2)、配線基板の製造方法(5)における工程(B3)において、第一面の非露光部のソルダーレジスト層2、第一ソルダーレジスト層2-1、第二ソルダーレジスト層2-2を薄膜化した量とによって、第一面の露出した接続パッド3周囲のソルダーレジスト層2、第一ソルダーレジスト層2-1の厚さ及びアンダーフィル堰き止め用のダムの一部となるソルダーレジスト層2、第一ソルダーレジスト層2-1、第二ソルダーレジスト層2-2の厚さが決定される。また、本発明では、0.01~500μmの範囲で薄膜化量を適宜自由に調整することができる。接続パッドの厚さ以下になるまで薄膜化されたソルダーレジスト層2、第一ソルダーレジスト層2-1表面から露出した接続パッド3表面までの高さは、後で必要な半田量に応じて適宜調整する。また、アンダーフィル堰き止め用のダムの一部となるソルダーレジスト層2、第一ソルダーレジスト層2-1、第二ソルダーレジスト層2-2の厚さは、電子部品の大きさや電子部品の接続端子の大きさや電子部品と配線基板間に充填するアンダーフィルの量に応じて適宜調整する。 Solder resist formed on the first surface in step (A) in wiring board manufacturing methods (1) and (2) and in steps (A1) and (A2) in wiring board manufacturing methods (3) to (5) Layer 2, first solder resist layer 2-1, second solder resist layer 2-2 thickness, wiring board manufacturing method (1), steps (B) in (3) to (5), wiring board manufacturing In the steps (B1) and (B2) in the method (2) and the step (B3) in the manufacturing method (5) of the wiring board, the solder resist layer 2 and the first solder resist layer 2-1 in the non-exposed portion of the first surface Depending on the thickness of the second solder resist layer 2-2, the thickness of the solder resist layer 2 around the connection pad 3 exposed on the first surface, the thickness of the first solder resist layer 2-1, and underfill damming Part of the dam and That the solder resist layer 2, the first solder resist layer 2-1, the thickness of the second solder resist layer 2-2 is determined. In the present invention, the amount of thin film can be adjusted as appropriate within a range of 0.01 to 500 μm. The height from the surface of the solder resist layer 2 or the first solder resist layer 2-1 that has been thinned until the thickness of the connection pad becomes equal to or less than the thickness of the connection pad 3 exposed as appropriate depends on the amount of solder required later. adjust. Also, the thickness of the solder resist layer 2, the first solder resist layer 2-1, and the second solder resist layer 2-2, which are part of the dam for underfill damming, determines the size of the electronic component and the connection of the electronic component. It is adjusted as appropriate according to the size of the terminal and the amount of underfill filled between the electronic component and the wiring board.
 配線基板の製造方法(6)は、配線基板の製造方法(1)~(4)において、工程(C1)の前に工程(C2)を行う。また、配線基板の製造方法(7)は、配線基板の製造方法(1)~(4)において、工程(C1)と工程(C2)を同時に行う。このように、配線基板の製造方法(1)~(4)では、工程(C1)と工程(C2)の順番を入れ替えることもできるし、工程(C1)と工程(C2)を同時に行うこともできる。 In the wiring board manufacturing method (6), the process (C2) is performed before the process (C1) in the wiring board manufacturing methods (1) to (4). Also, in the wiring board manufacturing method (7), the steps (C1) and (C2) are simultaneously performed in the wiring board manufacturing methods (1) to (4). As described above, in the wiring board manufacturing methods (1) to (4), the order of the step (C1) and the step (C2) can be interchanged, or the step (C1) and the step (C2) can be performed simultaneously. it can.
 配線基板の製造方法(1)における工程(C1)では、第一面のソルダーレジスト層2に対して、後工程である工程(B)において薄膜化される領域以外の部分が選択的に露光される。配線基板の製造方法(2)における工程(C1)では、第一面のソルダーレジスト層2に対して、後工程である工程(B1)において薄膜化される領域以外の部分が選択的に露光される。配線基板の製造方法(3)及び(4)における工程(C1)では、第一面の第一ソルダーレジスト層2-1に対して、後工程である工程(B)において薄膜化される領域以外の部分が選択的に露光される。配線基板の製造方法(2)における工程(C4)では、第一面のソルダーレジスト層2に対して、後工程である工程(B2)において薄膜化される領域以外の部分が選択的に露光される。配線基板の製造方法(3)における工程(C6)及び配線基板の製造方法(5)における工程(C7)では、第一面の第二ソルダーレジスト層2-2に対して、後工程である工程(D1)において現像される領域以外の部分を選択的に露光する。配線基板の製造方法(4)における工程(C6)では、第一面の第二ソルダーレジスト層2-2に対して、後工程である工程(D2)において現像される領域以外の部分を選択的に露光する。配線基板の製造方法(5)における工程(C6)では、第一面の第二ソルダーレジスト層2-2に対して、後工程である工程(B3)において薄膜化される領域以外の部分を露光する。露光されたソルダーレジストは光重合し、ソルダーレジスト層2、第一ソルダーレジスト層2-1、第二ソルダーレジスト層2-2が硬化する。図4-1~図8-3では、フォトマスク5を介して活性光線6を露光しているが、直接描画方式で行ってもよい。露光方式としては、例えば、キセノンランプ、高圧水銀灯、低圧水銀灯、超高圧水銀灯、UV蛍光灯を光源とした反射画像露光方式、フォトマスクを用いた密着露光方式、プロキシミティ方式、プロジェクション方式やレーザー走査露光方式等が挙げられる。第一面において「薄膜化される領域」とは、例えば、接続パッド上や接続パッド間を含む接続パッド周囲の領域である。より具体的には、電子部品を搭載するための実装領域とその周囲である。 In step (C1) in the manufacturing method (1) of the wiring substrate, the solder resist layer 2 on the first surface is selectively exposed to a portion other than the region to be thinned in the subsequent step (B). The In step (C1) in the manufacturing method (2) of the wiring board, the solder resist layer 2 on the first surface is selectively exposed to a portion other than the region to be thinned in the subsequent step (B1). The In the step (C1) in the manufacturing methods (3) and (4) of the wiring board, the first solder resist layer 2-1 on the first surface is other than the region to be thinned in the subsequent step (B). Are selectively exposed. In step (C4) in the manufacturing method (2) of the wiring board, the solder resist layer 2 on the first surface is selectively exposed to a portion other than the region to be thinned in the subsequent step (B2). The In the step (C6) in the method (3) for manufacturing the wiring board and the step (C7) in the method (5) for manufacturing the wiring substrate, a step that is a subsequent step with respect to the second solder resist layer 2-2 on the first surface. In (D1), a portion other than the region to be developed is selectively exposed. In step (C6) in the method (4) of manufacturing the wiring board, a portion other than the region developed in the subsequent step (D2) is selectively selected with respect to the second solder resist layer 2-2 on the first surface. To expose. In step (C6) in the method (5) of manufacturing the wiring substrate, the second solder resist layer 2-2 on the first surface is exposed to a portion other than the region to be thinned in the subsequent step (B3). To do. The exposed solder resist is photopolymerized, and the solder resist layer 2, the first solder resist layer 2-1, and the second solder resist layer 2-2 are cured. In FIGS. 4A to 8C, the actinic ray 6 is exposed through the photomask 5, but it may be performed by a direct drawing method. As the exposure method, for example, a xenon lamp, a high-pressure mercury lamp, a low-pressure mercury lamp, an ultra-high pressure mercury lamp, a reflected image exposure method using a UV fluorescent lamp as a light source, a contact exposure method using a photomask, a proximity method, a projection method, or a laser scanning Examples include an exposure method. The “region to be thinned” on the first surface is, for example, a region around the connection pad including on the connection pad and between the connection pads. More specifically, a mounting area for mounting an electronic component and its surroundings.
 配線基板の製造方法(1)及び(2)における工程(C2)では、第二面のソルダーレジスト層2に対して、後工程である工程(D)において現像される領域以外の部分が選択的に露光される。配線基板の製造方法(4)における工程(C2)では、第二面の第一ソルダーレジスト層2-1に対して、後工程である工程(D)において現像される領域以外の部分が選択的に露光される。配線基板の製造方法(3)及び(5)における工程(C2)では、第二面の第一ソルダーレジスト層2-1に対して、後工程である工程(D1)において現像される領域以外の部分が選択的に露光される。露光されたソルダーレジストは光重合し、ソルダーレジスト層2、第一ソルダーレジスト層2-1が硬化する。露光方式としては、上述した配線基板の製造方法(1)における工程(C1)等と同様の方式を使用することができる。第二面において「現像される領域」とは、例えば、接続パッド上や接続パッド間を含む接続パッド周囲の領域である。より具体的には、外部電気基板の導体配線と実装するためにエリアアレイ(Area array)型に配置された接続パッドの一部を露出させる円形の開口部領域である。 In the process (C2) in the manufacturing methods (1) and (2) of the wiring board, the portion other than the region developed in the process (D) which is a subsequent process is selective to the solder resist layer 2 on the second surface. To be exposed. In step (C2) in the manufacturing method (4) of the wiring board, the portion other than the region developed in step (D), which is a subsequent step, is selective to the first solder resist layer 2-1 on the second surface. To be exposed. In the step (C2) in the manufacturing methods (3) and (5) of the wiring board, the region other than the region developed in the subsequent step (D1) with respect to the first solder resist layer 2-1 on the second surface. A portion is selectively exposed. The exposed solder resist is photopolymerized, and the solder resist layer 2 and the first solder resist layer 2-1 are cured. As the exposure method, a method similar to the step (C1) in the wiring substrate manufacturing method (1) described above can be used. The “region to be developed” on the second surface is, for example, a region around the connection pad including on the connection pad and between the connection pads. More specifically, it is a circular opening region that exposes a part of connection pads arranged in an area array type for mounting with conductor wiring of an external electric substrate.
 配線基板の製造方法(1)における工程(C3)では、第一面のソルダーレジスト層2に対して、工程(B)において薄膜化された領域部分が露光される。配線基板の製造方法(3)~(5)における工程(C3)では、第一面の第一ソルダーレジスト層2-1に対して、工程(B)において薄膜化された領域部分が露光される。配線基板の製造方法(2)における工程(C5)では、第一面のソルダーレジスト層2に対して、工程(B2)において薄膜化された領域部分が露光される。露光方式としては、上述した配線基板の製造方法(1)における工程(C1)等と同様の方式を使用することができる。配線基板の製造方法(1)、(3)~(5)における工程(C3)や配線基板の製造方法(2)における工程(C5)の後には、非露光部のソルダーレジスト層2、第一ソルダーレジスト層2-1、第二ソルダーレジスト層2-2が現像除去される工程(配線基板の製造方法(1)、(2)及び(4)における工程(D)、配線基板の製造方法(3)及び(5)における工程(D1)、配線基板の製造方法(4)における工程(D2))があるため、最終的にソルダーレジスト層を形成させる領域を露光してソルダーレジストを光重合させる必要がある。配線基板の製造方法(1)、(3)、(4)における工程(C3)において露光する部分は、少なくとも工程(B)で薄膜化された領域を含み、工程(C1)で露光した部分と工程(B)で薄膜化された領域との境界部を含めることが好ましい。また、配線基板の製造方法(2)における工程(C5)において露光する部分は、少なくとも工程(B2)で薄膜化された領域を含み、工程(C4)で露光した部分と工程(B2)で薄膜化された領域との境界部を含めることが好ましい。 In the step (C3) of the wiring board manufacturing method (1), the solder resist layer 2 on the first surface is exposed to the region thinned in the step (B). In step (C3) in the manufacturing methods (3) to (5) of the wiring board, the first solder resist layer 2-1 on the first surface is exposed to the area portion thinned in step (B). . In step (C5) in the manufacturing method (2) of the wiring board, the area portion thinned in step (B2) is exposed to the solder resist layer 2 on the first surface. As the exposure method, a method similar to the step (C1) in the wiring substrate manufacturing method (1) described above can be used. After the step (C3) in the manufacturing method (1), (3) to (5) of the wiring substrate and the step (C5) in the manufacturing method (2) of the wiring substrate, the solder resist layer 2 of the non-exposed portion, the first The process of developing and removing the solder resist layer 2-1 and the second solder resist layer 2-2 (process (D) in the manufacturing method (1), (2) and (4) of the wiring board, the manufacturing method of the wiring board ( 3) and (5), there is a step (D1) and a step (D2)) in the manufacturing method (4) of the wiring board, so that the region where the solder resist layer is finally formed is exposed to photopolymerize the solder resist. There is a need. The part exposed in step (C3) in the method (1), (3), (4) of manufacturing the wiring board includes at least the region thinned in step (B), and the part exposed in step (C1) It is preferable to include a boundary with the region thinned in the step (B). Further, the portion exposed in step (C5) in the manufacturing method (2) of the wiring board includes at least the region thinned in step (B2), the portion exposed in step (C4) and the thin film in step (B2). It is preferable to include a boundary portion with the normalized region.
 配線基板の製造方法(1)~(4)における工程(C1)、配線基板の製造方法(1)、(3)~(5)における工程(C3)、配線基板の製造方法(1)~(5)における工程(C2)、配線基板の製造方法(2)における工程(C4)及び(C5)、配線基板の製造方法(3)~(5)における工程(C6)、配線基板の製造方法(5)における工程(C7)における露光量は、ソルダーレジストの感光感度に応じて適宜決定される。より詳しくは、配線基板の製造方法(1)、(3)~(5)における工程(B)、配線基板の製造方法(2)における工程(B1)及び(B2)、配線基板の製造方法(5)における工程(B3)において使用される薄膜化処理液、又は、配線基板の製造方法(1)、(2)、(4)における工程(D)、配線基板の製造方法(3)及び(5)における工程(D1)、配線基板の製造方法(4)における工程(D2)において使用される現像液に対して、ソルダーレジストが溶解又は膨潤しない程度に、ソルダーレジストを光重合させて硬化させることができればよく、通常100~600mJ/cmである。 Step (C1) in wiring board manufacturing method (1) to (4), wiring board manufacturing method (1), step (C3) in (3) to (5), wiring board manufacturing method (1) to ( Step (C2) in Step 5), Steps (C4) and (C5) in Method (2) for Manufacturing the Wiring Board, Step (C6) in Methods (3) to (5) for Manufacturing the Wiring Board, The exposure amount in step (C7) in 5) is appropriately determined according to the photosensitivity of the solder resist. More specifically, the wiring board manufacturing method (1), the steps (B) in (3) to (5), the steps (B1) and (B2) in the wiring board manufacturing method (2), the wiring board manufacturing method ( The thinning solution used in the step (B3) in 5) or the manufacturing method (1), (2), (4) of the wiring substrate, the manufacturing method (3) and (3) of the wiring substrate in (4) The solder resist is photopolymerized and cured to the extent that the solder resist does not dissolve or swell with respect to the developer used in the step (D1) in 5) and the step (D2) in the manufacturing method (4) of the wiring board. Usually, it is 100 to 600 mJ / cm 2 .
 配線基板の製造方法(1)、(3)、(4)における工程(C3)、配線基板の製造方法(2)における工程(C4)及び(C5)、配線基板の製造方法(5)における工程(C3)及び工程(C7)における露光は、酸素雰囲気下での非接触露光方式で行うことが好ましい。非接触露光方式としては、フォトマスクと配線基板の間に隙間を設けて非接触で露光を行うプロキシミティ方式、プロジェクション方式や、フォトマスクを用いない直接描画方式が挙げられる。ソルダーレジスト層2、第一ソルダーレジスト層2-1、第二ソルダーレジスト層2-2上に支持層フィルムがない状態で酸素雰囲気下での非接触露光を行うことによって、各ソルダーレジスト層の表層付近(ソルダーレジスト層表面からの深さが0~0.5μm程度)の光重合が酸素の影響により阻害されて未硬化部分となり、表層から離れた部位のみが硬化する。そのため、配線基板の製造方法(1)における工程(D)、配線基板の製造方法(2)における工程(B2)及び(D)、配線基板の製造方法(3)における工程(D1)、配線基板の製造方法(4)における工程(D)及び(D2)、配線基板の製造方法(5)における工程(D1)によって、表層付近の未硬化部分が除去され、ソルダーレジスト層2、第一ソルダーレジスト層2-1、第二ソルダーレジスト層2-2の表面が粗面化する。配線基板の表面にある電子部品接続用接続パッドの周囲のソルダーレジスト層表面が平滑な場合よりも粗面化された場合の方が、アンダーフィルとの密着性がより強固になり、結果として熱衝撃によって電子部品と配線基板の接続部に応力が集中するのを防ぐことができ、接続信頼性がより高くなる。酸素雰囲気下での非接触方式露光によってソルダーレジスト層2、第一ソルダーレジスト層2-1、第二ソルダーレジスト層2-2の表面が粗面化することにより、アンダーフィルとの密着性が向上し、高い接続信頼性が得られる。アンダーフィルとの密着性を向上させるのに好ましいソルダーレジスト層の表面粗さRaは、0.30μm以上0.50μm以下である。表面粗さRaが0.50μmを超えると、ソルダーレジストの強度が低くなって、絶縁信頼性が得られなくなる場合がある。表面粗さRaは算術平均表面粗さである。 Step (C3) in wiring board manufacturing method (1), (3), (4), steps (C4) and (C5) in wiring board manufacturing method (2), and wiring board manufacturing method (5) The exposure in (C3) and step (C7) is preferably performed by a non-contact exposure method in an oxygen atmosphere. Examples of the non-contact exposure method include a proximity method, a projection method, and a direct drawing method that does not use a photo mask, in which a gap is provided between the photo mask and the wiring board to perform non-contact exposure. By performing non-contact exposure in an oxygen atmosphere in the absence of a support layer film on the solder resist layer 2, the first solder resist layer 2-1, and the second solder resist layer 2-2, the surface layer of each solder resist layer Photopolymerization in the vicinity (depth from the solder resist layer surface of about 0 to 0.5 μm) is inhibited by the influence of oxygen to become an uncured portion, and only the portion away from the surface layer is cured. Therefore, step (D) in the manufacturing method (1) of the wiring substrate, steps (B2) and (D) in the manufacturing method (2) of the wiring substrate, the step (D1) in the manufacturing method (3) of the wiring substrate, the wiring substrate The steps (D) and (D2) in the manufacturing method (4) of step (D1) in the manufacturing method (5) of the wiring board remove the uncured portion near the surface layer, and the solder resist layer 2 and the first solder resist The surfaces of the layer 2-1 and the second solder resist layer 2-2 are roughened. When the surface of the solder resist layer around the connection pads for connecting electronic components on the surface of the wiring board is roughened, the adhesiveness with the underfill becomes stronger when the surface is roughened. It is possible to prevent stress from being concentrated on the connection part between the electronic component and the wiring board due to the impact, and the connection reliability is further improved. Adhesion with the underfill is improved by roughening the surfaces of the solder resist layer 2, the first solder resist layer 2-1, and the second solder resist layer 2-2 by non-contact exposure in an oxygen atmosphere. In addition, high connection reliability can be obtained. The surface roughness Ra of the solder resist layer preferable for improving the adhesion with the underfill is 0.30 μm or more and 0.50 μm or less. When the surface roughness Ra exceeds 0.50 μm, the strength of the solder resist is lowered and insulation reliability may not be obtained. The surface roughness Ra is an arithmetic average surface roughness.
 配線基板の製造方法(1)、(3)、(4)における工程(C3)、配線基板の製造方法(2)における工程(C4)及び(C5)における露光量は、工程(C1)における露光量の1倍以上5倍以下であることが好ましく、さらに好ましくは、1.5倍以上3倍以下である。同様に、配線基板の製造方法(5)における工程(C3)及び工程(C7)における露光量は、工程(C6)における露光量の1倍以上5倍以下であることが好ましく、さらに好ましくは、1.5倍以上3倍以下である。酸素雰囲気下での非接触露光において、ソルダーレジストが溶解又は膨潤しない程度に硬化させるのに必要な露光量に対し、さらに多くの露光量を与えることによって、ソルダーレジスト層の表面の酸素による重合阻害を必要最小限に抑えることができる。露光量は多いほど、重合阻害の抑制には効果があるが、一方で、露光量が多くなりすぎると、ソルダーレジストの解像性が悪化するだけでなく、露光時間が長くなりすぎるため好ましくない。 The exposure amount in the step (C3) in the method (1), (3), (4) for manufacturing the wiring substrate and the steps (C4) and (C5) in the method (2) for manufacturing the wiring substrate are the exposure amounts in the step (C1). The amount is preferably 1 to 5 times, more preferably 1.5 to 3 times the amount. Similarly, the exposure amount in the step (C3) and the step (C7) in the manufacturing method (5) of the wiring board is preferably 1 to 5 times the exposure amount in the step (C6), more preferably It is 1.5 times or more and 3 times or less. In non-contact exposure in an oxygen atmosphere, the amount of exposure required to cure the solder resist to such an extent that the solder resist does not dissolve or swell is given to prevent polymerization by oxygen on the surface of the solder resist layer. Can be minimized. The larger the exposure amount, the more effective the suppression of polymerization inhibition is. On the other hand, too much exposure amount is not preferable because not only the resolution of the solder resist deteriorates but also the exposure time becomes too long. .
 配線基板の製造方法(1)、(3)~(5)における工程(B)、配線基板の製造方法(2)における工程(B2)では、第一面において、薄膜化処理液によって、接続パッド3の厚さ以下になるまで、非露光部のソルダーレジスト層2、第一ソルダーレジスト層2-1が薄膜化されて、接続パッド3の一部を露出させる。配線基板の製造方法(2)における工程(B1)、配線基板の製造方法(5)における工程(B3)では、第一面において、薄膜化処理液によって、接続パッド3が露出しない範囲で、非露光部のソルダーレジスト層2、第二ソルダーレジスト層2-2が薄膜化される。フィルム状レジストを使用し、支持層フィルムが設けられている場合には、支持層フィルムを剥がしてから薄膜化を行う。 In the step (B) in the manufacturing method (1), (3) to (5) of the wiring substrate and the step (B2) in the manufacturing method (2) of the wiring substrate, the connection pad is formed on the first surface with the thinning treatment liquid. The solder resist layer 2 and the first solder resist layer 2-1 in the non-exposed part are thinned until the thickness becomes 3 or less, and a part of the connection pad 3 is exposed. In the step (B1) in the manufacturing method (2) of the wiring substrate and the step (B3) in the manufacturing method (5) of the wiring substrate, the first surface is not exposed to the extent that the connection pad 3 is not exposed by the thinning solution. The solder resist layer 2 and the second solder resist layer 2-2 in the exposed portion are thinned. When a film-like resist is used and a support layer film is provided, the support layer film is peeled off before thinning.
 配線基板の製造方法(1)、(3)~(5)における工程(B)、配線基板の製造方法(2)における工程(B2)では、薄膜化後のソルダーレジスト層2、第一ソルダーレジスト層2-1の厚さが、第一面の露出した接続パッド3の厚さと同じか、それよりも薄くなるまで薄膜化を行う。薄膜化後のソルダーレジスト層2、第一ソルダーレジスト層2-1の厚さが薄すぎると、露出した接続パッド3間の電気絶縁が不十分になり、無電解ニッケル/金めっきの短絡が発生する場合や、接続パッド3間で半田による短絡が発生する場合がある。そのため、薄膜化後のソルダーレジスト層2、第一ソルダーレジスト層2-1の厚さは、接続パッド3の厚さの3分の1以上であることが好ましく、より好ましくは3分の2以上であるのがよい。 In the step (B) in the wiring board manufacturing method (1), (3) to (5) and in the step (B2) in the wiring board manufacturing method (2), the solder resist layer 2 and the first solder resist after thinning Thinning is performed until the thickness of the layer 2-1 is equal to or less than the thickness of the connection pad 3 exposed on the first surface. If the thickness of the solder resist layer 2 and the first solder resist layer 2-1 after thinning is too thin, the electrical insulation between the exposed connection pads 3 becomes insufficient, and an electroless nickel / gold plating short circuit occurs. Or a short circuit may occur between the connection pads 3 due to solder. Therefore, the thickness of the solder resist layer 2 and the first solder resist layer 2-1 after thinning is preferably at least one third of the thickness of the connection pad 3, more preferably at least two thirds. It is good to be.
 配線基板の製造方法(1)における工程(B)、配線基板の製造方法(2)における工程(B1)及び(B2)において、第一面の非露光部のソルダーレジスト層2を薄膜化すると、第二面の非露光部のソルダーレジスト層2も同時に薄膜化される。配線基板の製造方法(3)~(5)における工程(B)において、第一面の非露光部の第一ソルダーレジスト層2-1を薄膜化すると、第二面の非露光部の第一ソルダーレジスト層2-1も同時に薄膜化される。配線基板の製造方法(5)における工程(B3)において、第一面の非露光部の第二ソルダーレジスト層2-2を薄膜化すると、第二面の非露光部の第一ソルダーレジスト層2-1も同時に薄膜化される。第二面の薄膜化量は、第二面における非露光部のソルダーレジスト層2、第一ソルダーレジスト層2-1の熱硬化状態によって異なるが、両表面において同じ加熱条件でソルダーレジスト層2、第一ソルダーレジスト層2-1が形成されている場合、通常、第一面と第二面の非露光部のソルダーレジスト層2、第一ソルダーレジスト層2-1は同時に同量薄膜化される。 In the step (B) in the manufacturing method (1) of the wiring substrate and the steps (B1) and (B2) in the manufacturing method (2) of the wiring substrate, when the solder resist layer 2 of the non-exposed portion on the first surface is thinned, The solder resist layer 2 on the non-exposed portion on the second surface is also thinned at the same time. In the step (B) in the manufacturing methods (3) to (5) of the wiring board, when the first solder resist layer 2-1 in the non-exposed portion on the first surface is thinned, the first in the non-exposed portion on the second surface is obtained. The solder resist layer 2-1 is also thinned at the same time. In the step (B3) in the method (5) of manufacturing the wiring board, when the second solder resist layer 2-2 in the non-exposed portion on the first surface is thinned, the first solder resist layer 2 in the non-exposed portion on the second surface is formed. -1 is also thinned at the same time. The amount of thinning of the second surface varies depending on the heat-cured state of the solder resist layer 2 and the first solder resist layer 2-1 in the non-exposed portion on the second surface, but the solder resist layer 2 under the same heating conditions on both surfaces, When the first solder resist layer 2-1 is formed, the solder resist layer 2 and the first solder resist layer 2-1 in the non-exposed portion of the first surface and the second surface are usually thinned in the same amount at the same time. .
 配線基板の製造方法(1)、(3)~(5)における工程(B)、配線基板の製造方法(2)における工程(B1)及び(B2)、配線基板の製造方法(5)における工程(B3)において、薄膜化処理は、第一面を上にして行うことが好ましい。薄膜化処理の処理方式としては、薄膜化処理液中に気泡が発生しにくいため、浸漬処理が有効である。万が一、薄膜化処理液中に気泡が発生した場合には、気泡は薄膜化処理液中を浮上し、下面(第二面)のソルダーレジスト層2、第一ソルダーレジスト層2-1表面に付着する。この気泡の付着によって、第二面における薄膜化後の膜厚が不均一となる場合がある。しかし、後工程である配線基板の製造方法(1)、(2)、(4)における工程(D)、配線基板の製造方法(3)及び(5)における工程(D1)、配線基板の製造方法(4)における工程(D2)において、第二面の非露光部のソルダーレジスト層2、第一ソルダーレジスト層2-1は現像除去されるため、最終的に膜厚ムラが問題となることはない。 Step (B) in wiring board manufacturing method (1), (3) to (5), step (B1) and (B2) in wiring board manufacturing method (2), step in wiring board manufacturing method (5) In (B3), the thinning treatment is preferably performed with the first surface facing up. As a processing method for the thinning treatment, dipping treatment is effective because bubbles are not easily generated in the thinning treatment solution. In the unlikely event that bubbles are generated in the thinning solution, the bubbles will rise in the thinning solution and adhere to the solder resist layer 2 on the lower surface (second surface) and the surface of the first solder resist layer 2-1. To do. Due to the adhesion of the bubbles, the film thickness after thinning on the second surface may become non-uniform. However, the manufacturing method (1), (2), and (4) of the wiring board, which is a subsequent process, the process (D1) in the manufacturing methods (3) and (5) of the wiring board, and the manufacturing of the wiring board In the step (D2) in the method (4), the solder resist layer 2 and the first solder resist layer 2-1 in the non-exposed portion on the second surface are developed and removed, and therefore, unevenness of the film thickness eventually becomes a problem. There is no.
 配線基板の製造方法(1)及び(2)における工程(D)では、現像によって、第二面の非露光部のソルダーレジスト層2を除去する。配線基板の製造方法(4)における工程(D)では、現像によって、第二面の非露光部の第一ソルダーレジスト層2-1を除去する。配線基板の製造方法(3)及び(5)における工程(D1)では、現像によって、第一面の非露光部の第二ソルダーレジスト層2-2及び第二面の非露光部の第一ソルダーレジスト層2-1を除去する。配線基板の製造方法(4)における工程(D2)では、現像によって、第一面の非露光部の第二ソルダーレジスト層2-2を除去する。現像方法としては、使用するソルダーレジストに見合った現像液を用い、回路基板の両表面にスプレーを噴射して、各ソルダーレジスト層の不要な部分を除去する。現像液には、希薄なアルカリ水溶液が使用され、一般的には、0.3~3質量%の炭酸ナトリウム水溶液や炭酸カリウム水溶液が使用される。 In the step (D) in the manufacturing method (1) and (2) of the wiring board, the solder resist layer 2 in the non-exposed part on the second surface is removed by development. In the step (D) in the manufacturing method (4) of the wiring board, the first solder resist layer 2-1 in the non-exposed portion on the second surface is removed by development. In the step (D1) in the manufacturing methods (3) and (5) of the wiring substrate, the second solder resist layer 2-2 in the non-exposed portion on the first surface and the first solder in the non-exposed portion on the second surface are developed by development. The resist layer 2-1 is removed. In step (D2) in the method (4) for manufacturing the wiring board, the second solder resist layer 2-2 in the non-exposed portion on the first surface is removed by development. As a developing method, a developer corresponding to the solder resist to be used is used, spray is sprayed on both surfaces of the circuit board, and unnecessary portions of each solder resist layer are removed. A dilute alkaline aqueous solution is used as the developer, and generally a 0.3 to 3 mass% sodium carbonate aqueous solution or potassium carbonate aqueous solution is used.
 以下、実施例によって本発明をさらに詳しく説明するが、本発明はこの実施例に限定されるものではない。 Hereinafter, the present invention will be described in more detail with reference to examples, but the present invention is not limited to these examples.
 実施例1~6は、図4-1および図4-2に示した配線基板の製造方法(1)に関する例である。 Examples 1 to 6 are examples relating to the manufacturing method (1) of the wiring board shown in FIGS. 4-1 and 4-2.
(実施例1)
<工程(A)>
 セミアディティブ法を用いて、両表面に導体配線7が形成された回路基板1(面積170mm×200mm、導体厚さ15μm、基板厚さ0.4mm)を作製した。表面(第一面)側には電子部品接続用接続パッド3として使用される線幅25μm、間隔50μmの導体配線がある。裏面(第二面)側には外部接続用接続パッド4として使用される直径600μmの円形状の導体配線が形成されている。次に、真空ラミネータを用いて、厚さ25μmのソルダーレジストフィルム(太陽インキ製造(株)製、商品名:PFR-800 AUS410)を上記回路基板1の両表面に真空熱圧着させた(ラミネート温度75℃、吸引時間30秒、加圧時間10秒)。これにより、ソルダーレジスト層2が形成された。第一面のソルダーレジスト層2では、絶縁層8表面からの厚さが30μmであり、電子部品接続用接続パッド3上の厚さは15μmであった。第二面のソルダーレジスト層2では、絶縁層8表面からの厚さが38μmであり、外部接続用接続パッド4上の厚さが23μmであった。導体配線の密度がより小さい第一面では、導体配線の密度がより大きい第二面に比べ、ソルダーレジスト層2の厚さが8μm薄くなっていた。
(Example 1)
<Process (A)>
Using a semi-additive method, a circuit board 1 (area 170 mm × 200 mm, conductor thickness 15 μm, board thickness 0.4 mm) having conductor wirings 7 formed on both surfaces was produced. On the front surface (first surface) side, there is a conductor wiring having a line width of 25 μm and an interval of 50 μm used as the connection pad 3 for connecting electronic components. A circular conductor wiring having a diameter of 600 μm used as the external connection pad 4 is formed on the back surface (second surface) side. Next, using a vacuum laminator, a 25 μm thick solder resist film (manufactured by Taiyo Ink Manufacturing Co., Ltd., trade name: PFR-800 AUS410) was vacuum thermocompression bonded to both surfaces of the circuit board 1 (lamination temperature). 75 ° C., suction time 30 seconds, pressurization time 10 seconds). Thereby, the soldering resist layer 2 was formed. In the solder resist layer 2 on the first surface, the thickness from the surface of the insulating layer 8 was 30 μm, and the thickness on the connection pad 3 for connecting electronic components was 15 μm. In the solder resist layer 2 on the second surface, the thickness from the surface of the insulating layer 8 was 38 μm, and the thickness on the connection pad 4 for external connection was 23 μm. On the first surface where the density of the conductor wiring is smaller, the thickness of the solder resist layer 2 is 8 μm thinner than on the second surface where the density of the conductor wiring is larger.
<工程(C1)>
 第一面のソルダーレジスト層2に対して、複数の電子部品接続用接続パッド3の端部から200μm離れた外周よりも外側の領域に活性光線6が照射されるようなパターンのフォトマスク5を用いて、露光量200mJ/cmで密着露光を行った。
<Process (C1)>
A photomask 5 having a pattern in which actinic rays 6 are irradiated to a region outside the outer periphery 200 μm away from the end portions of the plurality of connection pads 3 for connecting electronic components to the solder resist layer 2 on the first surface. The contact exposure was performed at an exposure amount of 200 mJ / cm 2 .
<工程(C2)>
 第二面のソルダーレジスト層2に対して、外部接続用接続パッド4上に直径500μmの円形開口部領域を設けるべく、円形開口部領域以外に活性光線6が照射されるようなパターンのフォトマスク5を用いて、露光量200mJ/cmで密着露光を行った。
<Process (C2)>
A photomask having a pattern in which actinic rays 6 are irradiated in areas other than the circular opening area in order to provide a circular opening area having a diameter of 500 μm on the external connection pad 4 for the solder resist layer 2 on the second surface. 5 was used for contact exposure at an exposure amount of 200 mJ / cm 2 .
<工程(B)>
 第一面及び第二面のソルダーレジスト層2上の支持層フィルムを剥離した後、10質量%のメタケイ酸ナトリウム水溶液(液温25℃)を薄膜化処理液として用いて、第一面を上にして薄膜化処理液に回路基板1を50秒間浸漬させてミセル化処理(薄膜化処理)を行った。その後、ミセル除去液(液温25℃)のスプレーによるミセル除去処理、水洗処理(液温25℃)及び乾燥処理を行い、第一面の非露光部のソルダーレジスト層2の厚さが電子部品接続用接続パッド3の表面下5.0μmになるまで、平均20μmのソルダーレジスト層2を薄膜化した。光学顕微鏡で観察したところ、第一面のソルダーレジスト層2の表面に処理ムラはなく、良好な面内均一性が得られた。一方、第二面においても、平均20μmのソルダーレジスト層2が薄膜化されていたが、薄膜化処理液中の気泡が第二面の非露光部のソルダーレジスト層2に付着し、膜厚不均一となっている箇所があった。また、外部接続用接続パッド4上には約3μmのソルダーレジスト層2の残渣が残っていた。
<Process (B)>
After peeling off the support layer film on the solder resist layer 2 on the first surface and the second surface, 10% by mass of sodium metasilicate aqueous solution (liquid temperature 25 ° C.) is used as the thinning treatment solution, Then, the circuit board 1 was immersed in the thinning treatment solution for 50 seconds to perform micellization treatment (thinning treatment). Thereafter, the micelle removal treatment by spraying the micelle removal liquid (liquid temperature 25 ° C.), the water washing treatment (liquid temperature 25 ° C.) and the drying treatment are performed, and the thickness of the solder resist layer 2 of the non-exposed portion on the first surface is the electronic component. The solder resist layer 2 having an average of 20 μm was thinned to 5.0 μm below the surface of the connection pad 3 for connection. When observed with an optical microscope, the surface of the solder resist layer 2 on the first surface was free from uneven processing, and good in-plane uniformity was obtained. On the other hand, the solder resist layer 2 having an average thickness of 20 μm was also thinned on the second surface, but bubbles in the thinning treatment liquid adhered to the solder resist layer 2 in the non-exposed area on the second surface, and the film thickness was not improved. There was a uniform spot. Further, a residue of about 3 μm of the solder resist layer 2 remained on the connection pad 4 for external connection.
<工程(C3)>
 第一面のソルダーレジスト層2に対して、工程(B)において薄膜化された領域部分及びその薄膜化された領域の境界部から200μm外側までの領域に、活性光線6が照射されるようなパターンのフォトマスク5を用いて、酸素雰囲気下での非接触露光により、露光量400mJ/cmで露光を行った。
<Process (C3)>
The actinic ray 6 is irradiated to the solder resist layer 2 on the first surface to the region portion thinned in the step (B) and the region from the boundary portion of the thinned region to the outside of 200 μm. Using a photomask 5 having a pattern, exposure was performed at an exposure amount of 400 mJ / cm 2 by non-contact exposure in an oxygen atmosphere.
<工程(D)>
 1質量%の炭酸ナトリウム水溶液(液温度30℃、スプレー圧0.15MPa)を用いて30秒間現像を行い、第二面の非露光部のソルダーレジスト層2を除去した。光学顕微鏡で観察した結果、第一面及び第二面ともに、電子部品接続用接続パッド3及び外部接続用接続パッド4上にソルダーレジスト層2の残渣は見られなかった。また、第一面では、電子部品接続用接続パッド3の表面下5.5μmまで、電子部品接続用接続パッド3間にソルダーレジスト層2が充填されていた。工程(C3)における酸素雰囲気下での非接触露光により、電子部品接続用接続パッド3間のソルダーレジスト層2表面の光重合が抑制され、結果として、ソルダーレジスト層2の厚さが0.5μm減少していた。
<Process (D)>
Development was performed for 30 seconds using a 1% by mass aqueous sodium carbonate solution (liquid temperature 30 ° C., spray pressure 0.15 MPa), and the solder resist layer 2 in the non-exposed area on the second surface was removed. As a result of observation with an optical microscope, no residue of the solder resist layer 2 was found on the connection pad 3 for connecting electronic parts and the connection pad 4 for external connection on both the first surface and the second surface. On the first surface, the solder resist layer 2 was filled between the connection pads 3 for electronic component connection up to 5.5 μm below the surface of the connection pads 3 for electronic component connection. The non-contact exposure in the oxygen atmosphere in the step (C3) suppresses the photopolymerization of the surface of the solder resist layer 2 between the connection pads 3 for connecting electronic components, and as a result, the thickness of the solder resist layer 2 is 0.5 μm. It was decreasing.
 次に、第一面及び第二面のソルダーレジスト層2を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施して、配線基板を得た。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmのソルダーレジスト層2によって被覆され、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ9.5μmのソルダーレジスト層2が充填されていた。また、第二面では、厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmのソルダーレジスト層2の円形開口部が形成されていて、外部接続用接続パッド4の一部が露出していた。 Next, in order to cure the solder resist layer 2 on the first surface and the second surface, the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was. As a result of observation with an optical microscope, on the first surface, the conductor wiring 7 having a thickness of 15 μm is covered with the solder resist layer 2 having a thickness of 30 μm, and the connection pad 3 for connecting an electronic component having a thickness of 15 μm is exposed. The solder resist layer 2 having a thickness of 9.5 μm was filled between the connection pads 3 for connecting electronic components. On the second surface, a circular opening of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm is formed on a part of the connection pad 4 for external connection having a thickness of 15 μm. A part of was exposed.
 次に、隣接する電子部品接続用接続パッド3間のソルダーレジスト層2の表面粗さを測定した。超深度形状測定顕微鏡(株式会社キーエンス(KEYENCE)製、品番「VK-8500」)を用いて表面粗さを測定したところ、表面粗さRaは0.40μmであった。 Next, the surface roughness of the solder resist layer 2 between adjacent connection pads 3 for connecting electronic components was measured. When the surface roughness was measured using an ultra-deep shape measuring microscope (manufactured by Keyence Corporation, product number “VK-8500”), the surface roughness Ra was 0.40 μm.
 超深度形状測定顕微鏡(株式会社キーエンス製、品番「VK-8500」)による算術平均表面粗さRaは、JIS B0601-1994 表面粗さ-定義に準じた計算式を用いている。なお、測定領域は900μm、基準長さは40μmとした。 The arithmetic average surface roughness Ra by an ultra-deep shape measuring microscope (manufactured by Keyence Corporation, product number “VK-8500”) uses a calculation formula according to JIS B0601-1994 surface roughness-definition. The measurement area was 900 μm 2 and the reference length was 40 μm.
(実施例2)
 工程(C1)と工程(C2)の順番を入れ替えた以外は実施例1と同じ方法で、工程(A)~工程(D)までを実施した。光学顕微鏡で観察した結果、第一面及び第二面ともに電子部品接続用接続パッド3及び外部接続用接続パッド4上にソルダーレジスト層2の残渣は見られなかった。また、また、第一面では、電子部品接続用接続パッド3の表面下5.5μmまで、電子部品接続用接続パッド3間にソルダーレジスト層2が充填されていた。工程(C3)における酸素雰囲気下での非接触露光により、電子部品接続用接続パッド3間のソルダーレジスト層2表面の光重合が抑制され、結果としてソルダーレジスト層2の厚さが0.5μm減少していた。
(Example 2)
The steps (A) to (D) were performed in the same manner as in Example 1 except that the order of the steps (C1) and (C2) was changed. As a result of observation with an optical microscope, no residue of the solder resist layer 2 was found on the connection pads 3 for connecting electronic components and the connection pads 4 for external connection on both the first surface and the second surface. Further, on the first surface, the solder resist layer 2 was filled between the connection pads 3 for connecting electronic components up to 5.5 μm below the surface of the connection pads 3 for connecting electronic components. The non-contact exposure in the oxygen atmosphere in the step (C3) suppresses photopolymerization of the surface of the solder resist layer 2 between the connection pads 3 for connecting electronic components, and as a result, the thickness of the solder resist layer 2 is reduced by 0.5 μm. Was.
 次に、第一面及び第二面のソルダーレジスト層2を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施して、配線基板を得た。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmのソルダーレジスト層2によって被覆され、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ9.5μmのソルダーレジスト層2が充填されていた。また、第二面では、厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmのソルダーレジスト層の円形開口部が形成されていて、外部接続用接続パッド4の一部が露出していた。 Next, in order to cure the solder resist layer 2 on the first surface and the second surface, the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was. As a result of observation with an optical microscope, on the first surface, the conductor wiring 7 having a thickness of 15 μm is covered with the solder resist layer 2 having a thickness of 30 μm, and the connection pad 3 for connecting an electronic component having a thickness of 15 μm is exposed. The solder resist layer 2 having a thickness of 9.5 μm was filled between the connection pads 3 for connecting electronic components. On the second surface, a circular opening of a solder resist layer having a thickness of 38 μm and a diameter of 500 μm is formed on a part of the connection pad 4 for external connection having a thickness of 15 μm. Some were exposed.
 次に、隣接する電子部品接続用接続パッド3間のソルダーレジスト層2の表面粗さを測定したところ、表面粗さRaは0.40μmであった。 Next, when the surface roughness of the solder resist layer 2 between the adjacent connection pads 3 for connecting electronic components was measured, the surface roughness Ra was 0.40 μm.
(実施例3)
 工程(C3)における露光量を200mJ/cmとした以外は実施例1と同じ方法で、工程(A)~工程(D)までを実施した。光学顕微鏡で観察した結果、第一面及び第二面ともに電子部品接続用接続パッド3及び外部接続用接続パッド4上にソルダーレジスト層2の残渣は見られなかった。第一面では、電子部品接続用接続パッド3の表面下6.0μmまで、電子部品接続用接続パッド3間にソルダーレジスト層2が充填されていた。工程(C3)における酸素雰囲気下での非接触露光により、電子部品接続用接続パッド3間のソルダーレジスト層2表面の光重合が抑制され、結果としてソルダーレジスト層2の厚さが1.0μm減少していた。
(Example 3)
Steps (A) to (D) were performed in the same manner as in Example 1 except that the exposure amount in step (C3) was 200 mJ / cm 2 . As a result of observation with an optical microscope, no residue of the solder resist layer 2 was found on the connection pads 3 for connecting electronic components and the connection pads 4 for external connection on both the first surface and the second surface. On the first surface, the solder resist layer 2 was filled between the connection pads 3 for electronic component connection up to 6.0 μm below the surface of the connection pads 3 for electronic component connection. By the non-contact exposure in the oxygen atmosphere in the step (C3), photopolymerization of the surface of the solder resist layer 2 between the connection pads 3 for connecting electronic components is suppressed, and as a result, the thickness of the solder resist layer 2 is reduced by 1.0 μm. Was.
 次に、第一面及び第二面のソルダーレジスト層2を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施して、配線基板を得た。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmのソルダーレジスト層2によって被覆され、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ9.0μmのソルダーレジスト層2が充填されていた。また、第二面では、厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmのソルダーレジスト層2の円形開口部が形成されていて、外部接続用接続パッド4の一部が露出していた。 Next, in order to cure the solder resist layer 2 on the first surface and the second surface, the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was. As a result of observation with an optical microscope, on the first surface, the conductor wiring 7 having a thickness of 15 μm is covered with the solder resist layer 2 having a thickness of 30 μm, and the connection pad 3 for connecting an electronic component having a thickness of 15 μm is exposed. The solder resist layer 2 having a thickness of 9.0 μm was filled between the connection pads 3 for connecting the electronic components. On the second surface, a circular opening of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm is formed on a part of the connection pad 4 for external connection having a thickness of 15 μm. A part of was exposed.
 次に、隣接する電子部品接続用接続パッド3間のソルダーレジスト層2の表面粗さを測定したところ、表面粗さRaは0.50μmであった。 Next, when the surface roughness of the solder resist layer 2 between the adjacent connection pads 3 for connecting electronic components was measured, the surface roughness Ra was 0.50 μm.
(実施例4)
 工程(C3)における露光量を1000mJ/cmとした以外は実施例1と同じ方法で、工程(A)~工程(D)までを実施した。光学顕微鏡で観察した結果、第一面及び第二面ともに電子部品接続用接続パッド3及び外部接続用接続パッド4上にソルダーレジスト層2の残渣は見られなかった。また、第一面では、電子部品接続用接続パッド3の表面下5.0μmまで、電子部品接続用接続パッド3間にソルダーレジスト層2が充填されていた。工程(C3)における酸素の重合阻害による第一面のソルダーレジスト層2の膜減りは確認されなかった。
Example 4
Steps (A) to (D) were performed in the same manner as in Example 1 except that the exposure amount in step (C3) was 1000 mJ / cm 2 . As a result of observation with an optical microscope, no residue of the solder resist layer 2 was found on the connection pads 3 for connecting electronic components and the connection pads 4 for external connection on both the first surface and the second surface. On the first surface, the solder resist layer 2 was filled between the connection pads 3 for electronic component connection up to 5.0 μm below the surface of the connection pads 3 for electronic component connection. No film loss of the solder resist layer 2 on the first surface due to inhibition of oxygen polymerization in the step (C3) was confirmed.
 次に、第一面及び第二面のソルダーレジスト層2を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施して、配線基板を得た。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmのソルダーレジスト層2によって被覆され、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ10.0μmのソルダーレジスト層2が充填されていた。また、第二面では、厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmのソルダーレジスト層2の円形開口部が形成されていて、外部接続用接続パッド4の一部が露出していた。 Next, in order to cure the solder resist layer 2 on the first surface and the second surface, the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was. As a result of observation with an optical microscope, on the first surface, the conductor wiring 7 having a thickness of 15 μm is covered with the solder resist layer 2 having a thickness of 30 μm, and the connection pads 3 for connecting an electronic component having a thickness of 15 μm are exposed. The solder resist layer 2 having a thickness of 10.0 μm was filled between the connection pads 3 for connecting electronic components. On the second surface, a circular opening of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm is formed on a part of the connection pad 4 for external connection having a thickness of 15 μm. A part of was exposed.
 次に、隣接する電子部品接続用接続パッド3間のソルダーレジスト層2の表面粗さを測定したところ、表面粗さRaは0.30μmであった。 Next, when the surface roughness of the solder resist layer 2 between the adjacent connection pads 3 for connecting electronic components was measured, the surface roughness Ra was 0.30 μm.
(実施例5)
 工程(C3)における露光を、酸素雰囲気下において直接描画装置(商品名:LI-8500、大日本スクリーン製造社製)を用いて露光量400mJ/cmで行った以外は実施例1と同じ方法で、工程(A)~工程(D)までを実施した。光学顕微鏡で観察した結果、第一面及び第二面ともに電子部品接続用接続パッド3及び外部接続用接続パッド4上にソルダーレジスト層2の残渣は見られなかった。また、第一面では、電子部品接続用接続パッド3の表面下5.5μmまで、電子部品接続用接続パッド3間にソルダーレジスト層2が充填されていた。工程(C3)における酸素雰囲気下での非接触露光により、電子部品接続用接続パッド3間のソルダーレジスト層2表面の光重合が抑制され、結果としてソルダーレジスト層2の厚さが0.5μm減少していた。
(Example 5)
The same method as in Example 1 except that the exposure in the step (C3) was performed at an exposure amount of 400 mJ / cm 2 using a direct drawing apparatus (trade name: LI-8500, manufactured by Dainippon Screen Mfg. Co., Ltd.) in an oxygen atmosphere. Then, steps (A) to (D) were carried out. As a result of observation with an optical microscope, no residue of the solder resist layer 2 was found on the connection pads 3 for connecting electronic components and the connection pads 4 for external connection on both the first surface and the second surface. On the first surface, the solder resist layer 2 was filled between the connection pads 3 for electronic component connection up to 5.5 μm below the surface of the connection pads 3 for electronic component connection. The non-contact exposure in the oxygen atmosphere in the step (C3) suppresses photopolymerization of the surface of the solder resist layer 2 between the connection pads 3 for connecting electronic components, and as a result, the thickness of the solder resist layer 2 is reduced by 0.5 μm. Was.
 次に、第一面及び第二面のソルダーレジスト層2を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施して、配線基板を得た。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmのソルダーレジスト層2によって被覆され、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ9.5μmのソルダーレジスト層2が充填されていた。また、第二面では、厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmのソルダーレジスト層の円形開口部が形成されていて、外部接続用接続パッド4の一部が露出していた。 Next, in order to cure the solder resist layer 2 on the first surface and the second surface, the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was. As a result of observation with an optical microscope, on the first surface, the conductor wiring 7 having a thickness of 15 μm is covered with the solder resist layer 2 having a thickness of 30 μm, and the connection pad 3 for connecting an electronic component having a thickness of 15 μm is exposed. The solder resist layer 2 having a thickness of 9.5 μm was filled between the connection pads 3 for connecting electronic components. On the second surface, a circular opening of a solder resist layer having a thickness of 38 μm and a diameter of 500 μm is formed on a part of the connection pad 4 for external connection having a thickness of 15 μm. Some were exposed.
 次に、隣接する電子部品接続用接続パッド3間のソルダーレジスト層2の表面粗さを測定したところ、表面粗さRaは0.40μmであった。 Next, when the surface roughness of the solder resist layer 2 between the adjacent connection pads 3 for connecting electronic components was measured, the surface roughness Ra was 0.40 μm.
(実施例6)
 工程(C3)において、密着露光方式にて露光を行った以外は、実施例1と同じ方法で、工程(A)~工程(D)までを実施した。光学顕微鏡で観察した結果、第一面及び第二面ともに電子部品接続用接続パッド3及び外部接続用接続パッド4上にソルダーレジスト層2の残渣は見られなかった。また、第一面では、電子部品接続用接続パッド3の表面下5.0μmまで、電子部品接続用接続パッド3間にソルダーレジスト層2が充填されていた。工程(C3)において、密着露光時のエア抜きを十分行うことにより、非酸素雰囲気下で露光を行ったため、ソルダーレジスト層2表面が粗面化せず、結果として、ソルダーレジスト層2の厚さは減少しなかった。
(Example 6)
Steps (A) to (D) were carried out in the same manner as in Example 1 except that in the step (C3), the exposure was performed by the contact exposure method. As a result of observation with an optical microscope, no residue of the solder resist layer 2 was found on the connection pads 3 for connecting electronic components and the connection pads 4 for external connection on both the first surface and the second surface. On the first surface, the solder resist layer 2 was filled between the connection pads 3 for electronic component connection up to 5.0 μm below the surface of the connection pads 3 for electronic component connection. In the step (C3), the surface of the solder resist layer 2 is not roughened because the exposure is performed in a non-oxygen atmosphere by sufficiently releasing the air during the contact exposure, and as a result, the thickness of the solder resist layer 2 is increased. Did not decrease.
 次に、第一面及び第二面のソルダーレジスト層2を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施して、配線基板を得た。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmのソルダーレジスト層2によって被覆され、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ10μmのソルダーレジスト層2が充填されていた。また、第二面では、厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmのソルダーレジスト層2の円形開口部が形成されていて、導体パッド4が露出していた。 Next, in order to cure the solder resist layer 2 on the first surface and the second surface, the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was. As a result of observation with an optical microscope, on the first surface, the conductor wiring 7 having a thickness of 15 μm is covered with the solder resist layer 2 having a thickness of 30 μm, and the connection pad 3 for connecting an electronic component having a thickness of 15 μm is exposed. The solder resist layer 2 having a thickness of 10 μm was filled between the connection pads 3 for connecting electronic components. On the second surface, a circular opening of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm is formed in a part on the external connection pad 4 having a thickness of 15 μm so that the conductor pad 4 is exposed. It was.
 次に、隣接する電子部品接続用接続パッド3間のソルダーレジスト層2の表面粗さを測定したところ、表面粗さRaは0.10μmであった。 Next, when the surface roughness of the solder resist layer 2 between the adjacent connection pads 3 for connecting electronic components was measured, the surface roughness Ra was 0.10 μm.
 実施例1~6では、隣接する電子部品接続用接続パッド3間に十分な厚さのソルダーレジスト層2があるため、電子部品を実装する際に半田による電気的な短絡が起きるのを確実に防ぐことができた。また、外部接続用接続パッド4上にソルダーレジスト層2の残渣が存在しないため、外部電気基板に実装する際にも電気的絶縁不良が発生しない信頼性の高い配線基板を作製することができた。実施例1~6を比較すると、電子部品接続用接続パッド3間のソルダーレジスト層2の表面が平滑である実施例6で製造された配線基板よりも、実施例1~5で製造された配線基板の方が、アンダーフィルとの密着性が高く、接続信頼性が優れていた。 In Examples 1 to 6, since there is a solder resist layer 2 having a sufficient thickness between adjacent connection pads 3 for connecting electronic components, it is ensured that an electrical short circuit due to solder occurs when electronic components are mounted. I was able to prevent it. In addition, since there is no residue of the solder resist layer 2 on the connection pads 4 for external connection, a highly reliable wiring board that does not cause poor electrical insulation even when mounted on an external electric board could be produced. . Comparing Examples 1 to 6, the wiring manufactured in Examples 1 to 5 is more preferable than the wiring board manufactured in Example 6 in which the surface of the solder resist layer 2 between the connection pads 3 for connecting electronic components is smooth. The board had higher adhesion to the underfill and better connection reliability.
(比較例1)
<工程(A)>
 セミアディティブ法を用いて、両表面に導体配線7が形成された回路基板1(面積170mm×200mm、導体厚さ15μm、基板厚さ0.4mm)を作製した。表面(第一面)には電子部品接続用接続パッド3として使用される線幅25μm、間隔50μmの導体配線がある。裏面(第二面)には外部接続用接続パッド4として使用される直径600μmの円形状の導体配線が形成されている。次に、真空ラミネータを用いて、厚さ25μmのソルダーレジストフィルム(太陽インキ製造(株)製、商品名:PFR-800 AUS410)を上記回路基板1の両表面に真空熱圧着させた(ラミネート温度75℃、吸引時間30秒、加圧時間10秒)。これにより、ソルダーレジスト層2が形成された。第一面のソルダーレジスト層2では、絶縁層8表面からの厚さが30μmであり、電子部品接続用接続パッド3上の厚さは15μmであった。第二面のソルダーレジスト層2では、絶縁層8表面からの厚さが38μmであり、外部接続用接続パッド4上の厚さが23μmであった。導体配線の密度がより小さい第一面では、導体配線の密度がより大きい第二面に比べ、ソルダーレジスト層2の厚さが8μm薄くなっていた。
(Comparative Example 1)
<Process (A)>
Using a semi-additive method, a circuit board 1 (area 170 mm × 200 mm, conductor thickness 15 μm, board thickness 0.4 mm) having conductor wirings 7 formed on both surfaces was produced. On the surface (first surface), there is a conductor wiring having a line width of 25 μm and an interval of 50 μm used as the connection pad 3 for connecting electronic components. A circular conductor wiring having a diameter of 600 μm used as the external connection pad 4 is formed on the back surface (second surface). Next, using a vacuum laminator, a 25 μm thick solder resist film (manufactured by Taiyo Ink Manufacturing Co., Ltd., trade name: PFR-800 AUS410) was vacuum thermocompression bonded to both surfaces of the circuit board 1 (lamination temperature). 75 ° C., suction time 30 seconds, pressurization time 10 seconds). Thereby, the soldering resist layer 2 was formed. In the solder resist layer 2 on the first surface, the thickness from the surface of the insulating layer 8 was 30 μm, and the thickness on the connection pad 3 for connecting electronic components was 15 μm. In the solder resist layer 2 on the second surface, the thickness from the surface of the insulating layer 8 was 38 μm, and the thickness on the connection pad 4 for external connection was 23 μm. On the first surface where the density of the conductor wiring is smaller, the thickness of the solder resist layer 2 is 8 μm thinner than on the second surface where the density of the conductor wiring is larger.
<工程(C1)>
 第一面のソルダーレジスト層2に対して、複数の電子部品接続用接続パッド3の端部から200μm離れた外周よりも外側の領域に活性光線6が照射されるようなパターンのフォトマスク5を用いて、露光量200mJ/cmで密着露光を行った。
<Process (C1)>
A photomask 5 having a pattern in which actinic rays 6 are irradiated to a region outside the outer periphery 200 μm away from the end portions of the plurality of connection pads 3 for connecting electronic components to the solder resist layer 2 on the first surface. The contact exposure was performed at an exposure amount of 200 mJ / cm 2 .
<工程(C2)>
 第二面のソルダーレジスト層2に対して、外部接続用接続パッド4上に直径500μmの円形開口部領域を設けるべく、円形開口部領域以外に活性光線6が照射されるようなパターンのフォトマスク5を用いて、露光量200mJ/cmで密着露光を行った。
<Process (C2)>
A photomask having a pattern in which actinic rays 6 are irradiated in areas other than the circular opening area in order to provide a circular opening area having a diameter of 500 μm on the external connection pad 4 for the solder resist layer 2 on the second surface. 5 was used for contact exposure at an exposure amount of 200 mJ / cm 2 .
<工程(B)>
 第一面及び第二面のソルダーレジスト層2上の支持層フィルムを剥離した後、10質量%のメタケイ酸ナトリウム水溶液(液温25℃)を薄膜化処理液として用いて、第一面を上にして薄膜化処理液に回路基板1を50秒間浸漬させてミセル化処理(薄膜化処理)を行った。その後、ミセル除去液(液温25℃)のスプレーによるミセル除去処理、水洗処理(液温25℃)及び乾燥処理を行い、第一面の非露光部のソルダーレジスト層2の厚さが電子部品接続用接続パッド3の表面下5.0μmになるまで、平均20μmのソルダーレジスト層2を薄膜化した。光学顕微鏡で観察したところ、第一面のソルダーレジスト層2の表面に処理ムラはなく、良好な面内均一性が得られた。一方、第二面のソルダーレジスト層2も平均20μm薄膜化されていたが、薄膜化処理液中の気泡が第二面の非露光部のソルダーレジスト層2に付着し、膜厚不均一となっている箇所があった。また、外部接続用接続パッド4には約3μmのソルダーレジスト層2の残渣が残っていた。
<Process (B)>
After peeling off the support layer film on the solder resist layer 2 on the first surface and the second surface, 10% by mass of sodium metasilicate aqueous solution (liquid temperature 25 ° C.) is used as the thinning treatment solution, Then, the circuit board 1 was immersed in the thinning treatment solution for 50 seconds to perform micellization treatment (thinning treatment). Thereafter, the micelle removal treatment by spraying the micelle removal liquid (liquid temperature 25 ° C.), the water washing treatment (liquid temperature 25 ° C.) and the drying treatment are performed, and the thickness of the solder resist layer 2 of the non-exposed portion on the first surface is the electronic component. The solder resist layer 2 having an average of 20 μm was thinned to 5.0 μm below the surface of the connection pad 3 for connection. When observed with an optical microscope, the surface of the solder resist layer 2 on the first surface was free from uneven processing, and good in-plane uniformity was obtained. On the other hand, the solder resist layer 2 on the second surface was also thinned by an average of 20 μm, but bubbles in the thinning treatment liquid adhered to the solder resist layer 2 on the non-exposed portion of the second surface, resulting in non-uniform film thickness. There was a place. Further, the residue of the solder resist layer 2 of about 3 μm remained on the connection pad 4 for external connection.
 次に、第一面及び第二面のソルダーレジスト層2を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施して、配線基板を得た。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmのソルダーレジスト層2によって被覆され、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ10.0μmのソルダーレジスト層2が充填されていた。また、第二面は厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmのソルダーレジスト層2の円形開口部が形成されていたが、外部接続用接続パッド4上には厚さ3μmのソルダーレジスト層2の残渣が残っていた。 Next, in order to cure the solder resist layer 2 on the first surface and the second surface, the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was. As a result of observation with an optical microscope, on the first surface, the conductor wiring 7 having a thickness of 15 μm is covered with the solder resist layer 2 having a thickness of 30 μm, and the connection pads 3 for connecting an electronic component having a thickness of 15 μm are exposed. The solder resist layer 2 having a thickness of 10.0 μm was filled between the connection pads 3 for connecting electronic components. Further, the second surface was formed with a circular opening of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm on a part of the connection pad 4 for external connection having a thickness of 15 μm. Residue of the solder resist layer 2 having a thickness of 3 μm remained on the top.
 電子部品を実装する際、隣接する電子部品接続用接続パッド3間に十分な厚さのソルダーレジスト層2があり、半田による電気的な短絡を確実に防ぐことができたが、外部電気基板に実装する際、外部接続用接続パッド4上に残ったソルダーレジスト層2の残渣によって、半田バンプ接続において電気的絶縁不良が発生した。 When mounting an electronic component, there was a solder resist layer 2 of sufficient thickness between adjacent connection pads 3 for connecting an electronic component, and an electrical short circuit due to solder could be reliably prevented. When mounting, due to the residue of the solder resist layer 2 remaining on the connection pad 4 for external connection, an electrical insulation failure occurred in the solder bump connection.
 隣接する電子部品接続用接続パッド3間のソルダーレジスト層2の表面粗さを測定したところ、表面粗さRaは0.03μmであった。電子部品接続用接続パッド3間のソルダーレジスト表面が平滑である比較例1で製造された配線基板よりも、実施例1~5で製造された配線基板の方が、アンダーフィルとの密着性が高く、接続信頼性が優れていた。 When the surface roughness of the solder resist layer 2 between the adjacent connection pads 3 for connecting electronic components was measured, the surface roughness Ra was 0.03 μm. The wiring board manufactured in Examples 1 to 5 has better adhesion to the underfill than the wiring board manufactured in Comparative Example 1 in which the solder resist surface between the connection pads 3 for connecting electronic components is smooth. High connection reliability.
 実施例7~11は、図5-1、図5-2および図5-3に示した配線基板の製造方法(2)に関する例である。 Examples 7 to 11 are examples relating to the method (2) for manufacturing the wiring board shown in FIGS. 5-1, 5-2, and 5-3.
(実施例7)
<工程(A)>
 セミアディティブ法を用いて、両表面に導体配線7が形成された回路基板1(面積170mm×200mm、導体厚さ15μm、基板厚さ0.4mm)を作製した。表面(第一面)には電子部品接続用接続パッド3として使用される線幅25μm、間隔50μmの導体配線がある。裏面(第二面)には外部接続用接続パッド4として使用される直径600μmの円形状の導体配線が形成されている。次に、真空ラミネータを用いて、厚さ25μmのソルダーレジストフィルム(太陽インキ製造(株)製、商品名:PFR-800 AUS410)を上記回路基板1の両表面に真空熱圧着させた(ラミネート温度75℃、吸引時間30秒、加圧時間10秒)。これにより、ソルダーレジスト層2が形成された。第一面のソルダーレジスト層2では、絶縁層8表面からの厚さが30μmであり、電子部品接続用接続パッド3上の厚さは15μmであった。第二面のソルダーレジスト層2では、絶縁層8表面からの厚さが38μmであり、外部接続用接続パッド4上の厚さが23μmであった。導体配線の密度がより小さい第一面では、導体配線の密度がより大きい第二面に比べ、ソルダーレジスト層2の厚さが8μm薄くなっていた。
(Example 7)
<Process (A)>
Using a semi-additive method, a circuit board 1 (area 170 mm × 200 mm, conductor thickness 15 μm, board thickness 0.4 mm) having conductor wirings 7 formed on both surfaces was produced. On the surface (first surface), there is a conductor wiring having a line width of 25 μm and an interval of 50 μm used as the connection pad 3 for connecting electronic components. A circular conductor wiring having a diameter of 600 μm used as the external connection pad 4 is formed on the back surface (second surface). Next, using a vacuum laminator, a 25 μm thick solder resist film (manufactured by Taiyo Ink Manufacturing Co., Ltd., trade name: PFR-800 AUS410) was vacuum thermocompression bonded to both surfaces of the circuit board 1 (lamination temperature). 75 ° C., suction time 30 seconds, pressurization time 10 seconds). Thereby, the soldering resist layer 2 was formed. In the solder resist layer 2 on the first surface, the thickness from the surface of the insulating layer 8 was 30 μm, and the thickness on the connection pad 3 for connecting electronic components was 15 μm. In the solder resist layer 2 on the second surface, the thickness from the surface of the insulating layer 8 was 38 μm, and the thickness on the connection pad 4 for external connection was 23 μm. On the first surface where the density of the conductor wiring is smaller, the thickness of the solder resist layer 2 is 8 μm thinner than on the second surface where the density of the conductor wiring is larger.
<工程(C1)>
 第一面のソルダーレジスト層2に対して、複数の電子部品接続用接続パッド3の端部から400μm離れた外周よりも外側の領域に活性光線6が照射されるようなパターンのフォトマスク5を用いて、露光量200mJ/cmで密着露光を行った。
<Process (C1)>
A photomask 5 having a pattern in which actinic rays 6 are irradiated to a region outside the outer periphery 400 μm away from the end portions of the plurality of connection pads 3 for connecting electronic components to the solder resist layer 2 on the first surface. The contact exposure was performed at an exposure amount of 200 mJ / cm 2 .
<工程(C2)>
 第二面のソルダーレジスト層2に対して、外部接続用接続パッド4上に直径500μmの円形開口部領域を設けるべく、円形開口部領域以外に活性光線6が照射されるようなパターンのフォトマスク5を用いて、露光量200mJ/cmで密着露光を行った。
<Process (C2)>
A photomask having a pattern in which actinic rays 6 are irradiated in areas other than the circular opening area in order to provide a circular opening area having a diameter of 500 μm on the external connection pad 4 for the solder resist layer 2 on the second surface. 5 was used for contact exposure at an exposure amount of 200 mJ / cm 2 .
<工程(B1)>
 第一面及び第二面のソルダーレジスト層2上の支持層フィルムを剥離した後、10質量%のメタケイ酸ナトリウム水溶液(液温25℃)を薄膜化処理液として用いて、第一面を上にして薄膜化処理液に回路基板1を25秒間浸漬させてミセル化処理(薄膜化処理)を行った。その後、ミセル除去液(液温25℃)のスプレーによるミセル除去処理、水洗処理(液温25℃)及び乾燥処理を行い、第一面の非露光部のソルダーレジスト層2の厚さが電子部品接続用接続パッド3の表面上5.0μmになるまで、平均10μmのソルダーレジスト層2を薄膜化した。光学顕微鏡で観察したところ、第一面のソルダーレジスト層2の表面に処理ムラはなく、良好な面内均一性が得られた。一方、第二面のソルダーレジスト層2も平均10μm薄膜化されていたが、薄膜化処理液中の気泡が第二面の非露光部のソルダーレジスト層2に付着し、膜厚不均一となっている箇所があった。また、外部接続用接続パッド4には約13μmのソルダーレジスト層2の残渣が残っていた。
<Process (B1)>
After peeling off the support layer film on the solder resist layer 2 on the first side and the second side, the first side is turned up using a 10% by mass sodium metasilicate aqueous solution (liquid temperature 25 ° C.) as a thinning solution. Then, the circuit board 1 was immersed in the thinning treatment solution for 25 seconds to perform micellization treatment (thinning treatment). Then, the micelle removal process by spraying the micelle removal liquid (liquid temperature 25 ° C.), the water washing process (liquid temperature 25 ° C.) and the drying process are performed, and the thickness of the solder resist layer 2 in the non-exposed portion on the first surface is the electronic component. The solder resist layer 2 having an average of 10 μm was thinned to 5.0 μm on the surface of the connection pad 3 for connection. When observed with an optical microscope, the surface of the solder resist layer 2 on the first surface was free from uneven processing, and good in-plane uniformity was obtained. On the other hand, the solder resist layer 2 on the second surface was also thinned by an average of 10 μm, but bubbles in the thinning treatment liquid adhered to the solder resist layer 2 on the non-exposed portion of the second surface, resulting in non-uniform film thickness. There was a place. Further, the residue of the solder resist layer 2 of about 13 μm remained on the connection pad 4 for external connection.
<工程(C4)>
 第一面のソルダーレジスト層2に対して、複数の電子部品接続用接続パッド3の端部から200μm離れた外周よりも外側の領域に、活性光線6が照射されるようなパターンのフォトマスク5を用いて、酸素雰囲気下での非接触露光により、露光量400mJ/cmで露光を行った。
<Process (C4)>
A photomask 5 having a pattern in which actinic rays 6 are irradiated to a region outside the outer periphery that is 200 μm away from the end portions of the plurality of connection pads 3 for connecting electronic components to the solder resist layer 2 on the first surface. Was exposed at an exposure amount of 400 mJ / cm 2 by non-contact exposure in an oxygen atmosphere.
<工程(B2)>
 10質量%のメタケイ酸ナトリウム水溶液(液温25℃)を薄膜化処理液として用いて、第一面を上にして薄膜化処理液に回路基板1を25秒間浸漬させてミセル化処理(薄膜化処理)を行った。その後、ミセル除去液(液温25℃)のスプレーによるミセル除去処理、水洗処理(液温25℃)及び乾燥処理を行い、第一面の非露光部のソルダーレジスト層2の厚さが電子部品接続用接続パッド3の表面下5.0μmになるまで、平均10μmのソルダーレジスト層2を薄膜化した。光学顕微鏡で観察したところ、第一面のソルダーレジスト層2の表面に処理ムラはなく、良好な面内均一性が得られた。工程(C4)における酸素雰囲気下での非接触露光により、第一面に配置された電子部品接続用接続パッド3の端部から200μm離れた外周から400μm離れた外周までの領域のソルダーレジスト層2表面の光重合が抑制され、結果としてソルダーレジスト層2の厚さが0.5μm減少した。一方、第二面のソルダーレジスト層2も平均10μm薄膜化されていたが、薄膜化処理液中の気泡が第二面の非露光部のソルダーレジスト層2に付着し、膜厚不均一となっている箇所があった。また、外部接続用接続パッド4には約3μmのソルダーレジスト層2の残渣が残っていた。
<Process (B2)>
Using 10% by mass of sodium metasilicate aqueous solution (liquid temperature: 25 ° C.) as the thinning treatment solution, the circuit board 1 is immersed in the thinning treatment solution for 25 seconds with the first side facing up, and the micelle treatment (thinning) Treatment). Thereafter, the micelle removal treatment by spraying the micelle removal liquid (liquid temperature 25 ° C.), the water washing treatment (liquid temperature 25 ° C.) and the drying treatment are performed, and the thickness of the solder resist layer 2 of the non-exposed portion on the first surface is the electronic component. The solder resist layer 2 having an average of 10 μm was thinned to 5.0 μm below the surface of the connection pad 3 for connection. When observed with an optical microscope, the surface of the solder resist layer 2 on the first surface was free from uneven processing, and good in-plane uniformity was obtained. Solder resist layer 2 in the region from the outer periphery 200 μm away to the outer periphery 400 μm away from the end of the connection pad 3 for connecting electronic components arranged on the first surface by non-contact exposure in an oxygen atmosphere in step (C4) Surface photopolymerization was suppressed, and as a result, the thickness of the solder resist layer 2 was reduced by 0.5 μm. On the other hand, the solder resist layer 2 on the second surface was also thinned by an average of 10 μm, but bubbles in the thinning treatment liquid adhered to the solder resist layer 2 on the non-exposed portion of the second surface, resulting in non-uniform film thickness. There was a place. Further, the residue of the solder resist layer 2 of about 3 μm remained on the connection pad 4 for external connection.
<工程(C5)>
 第一面のソルダーレジスト層2に対して、工程(B2)において薄膜化された領域部分及びその薄膜化された領域の境界部から200μm外側までの領域に、活性光線6が照射されるようなパターンのフォトマスク5を用いて、酸素雰囲気下での非接触露光により、露光量400mJ/cmで露光を行った。
<Process (C5)>
The actinic ray 6 is irradiated to the solder resist layer 2 on the first surface to the region part thinned in the step (B2) and the region from the boundary part of the thinned region to the outside of 200 μm. Using a photomask 5 having a pattern, exposure was performed at an exposure amount of 400 mJ / cm 2 by non-contact exposure in an oxygen atmosphere.
<工程(D)>
 1質量%の炭酸ナトリウム水溶液(液温度30℃、スプレー圧0.15MPa)を用いて30秒間現像を行い、第二面の非露光部のソルダーレジスト層2を除去した。光学顕微鏡で観察した結果、第一面及び第二面ともに、電子部品接続用接続パッド3及び外部接続用接続パッド4上にソルダーレジスト層2の残渣は見られなかった。また、第一面では、電子部品接続用接続パッド3の表面下5.5μmまで、電子部品接続用接続パッド3間にソルダーレジスト層2が充填されていた。工程(C4)及び(C5)における酸素雰囲気下での非接触露光により、第一面では、工程(C1)における密着露光で活性光線6が照射された領域以外のソルダーレジスト層2表面の光重合が抑制され、結果として、ソルダーレジスト層2の厚さが0.5μm減少していた。
<Process (D)>
Development was performed for 30 seconds using a 1% by mass aqueous sodium carbonate solution (liquid temperature 30 ° C., spray pressure 0.15 MPa), and the solder resist layer 2 in the non-exposed area on the second surface was removed. As a result of observation with an optical microscope, no residue of the solder resist layer 2 was found on the connection pad 3 for connecting electronic parts and the connection pad 4 for external connection on both the first surface and the second surface. On the first surface, the solder resist layer 2 was filled between the connection pads 3 for electronic component connection up to 5.5 μm below the surface of the connection pads 3 for electronic component connection. Photopolymerization of the surface of the solder resist layer 2 other than the region irradiated with the actinic ray 6 in the contact exposure in the step (C1) on the first surface by the non-contact exposure in the oxygen atmosphere in the steps (C4) and (C5). As a result, the thickness of the solder resist layer 2 was reduced by 0.5 μm.
 次に、第一面及び第二面のソルダーレジスト層2を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施して、配線基板を得た。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmと19.5μmのソルダーレジスト層2によって被覆され、その段差に相当する厚さ10.5μmのアンダーフィル堰き止め用ダムが形成されていた。また、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ9.5μmのソルダーレジスト層2が充填されていた。また、第二面では、厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmのソルダーレジスト層2の円形開口部が形成されていて、外部接続用接続パッド4の一部が露出していた。 Next, in order to cure the solder resist layer 2 on the first surface and the second surface, the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was. As a result of observation with an optical microscope, on the first surface, a conductor wiring 7 with a thickness of 15 μm is covered with a solder resist layer 2 with a thickness of 30 μm and 19.5 μm, and an underfill weir with a thickness of 10.5 μm corresponding to the step. A stop dam was formed. In addition, the electronic component connecting connection pads 3 having a thickness of 15 μm were exposed, and the solder resist layer 2 having a thickness of 9.5 μm was filled between the adjacent electronic component connecting connection pads 3. On the second surface, a circular opening of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm is formed on a part of the connection pad 4 for external connection having a thickness of 15 μm. A part of was exposed.
 次に、第一面に配置された複数の電子部品接続用接続パッド3の端部から200μm離れた外周と該端部から400μm離れた外周との間の領域にある厚さ19.5μmのソルダーレジスト層2の表面粗さを測定したところ、表面粗さRaは0.40μmであった。また、隣接する電子部品接続用接続パッド3間のソルダーレジスト層2の表面粗さを測定したところ、表面粗さRaは0.40μmであった。 Next, a solder having a thickness of 19.5 μm in a region between the outer periphery 200 μm away from the ends of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 μm away from the ends When the surface roughness of the resist layer 2 was measured, the surface roughness Ra was 0.40 μm. Moreover, when the surface roughness of the soldering resist layer 2 between the adjacent connection pads 3 for electronic component connection was measured, the surface roughness Ra was 0.40 μm.
(実施例8)
 工程(C1)と工程(C2)の順番を入れ替えた以外は実施例7と同じ方法で、工程(A)~工程(D)までを実施した。光学顕微鏡で観察した結果、第一面及び第二面ともに電子部品接続用接続パッド3及び外部接続用接続パッド4上にソルダーレジスト層2の残渣は見られなかった。また、第一面に配置された電子部品接続用接続パッド3の表面下5.5μmまでソルダーレジスト層2が充填されていた。工程(C4)及び(C5)における酸素雰囲気下での非接触露光により、第一面では、工程(C1)における密着露光で活性光線6が照射された領域以外のソルダーレジスト層2表面の光重合が抑制され、結果として、ソルダーレジスト層2の厚さが0.5μm減少していた。
(Example 8)
Steps (A) to (D) were performed in the same manner as in Example 7 except that the order of the steps (C1) and (C2) was changed. As a result of observation with an optical microscope, no residue of the solder resist layer 2 was found on the connection pads 3 for connecting electronic components and the connection pads 4 for external connection on both the first surface and the second surface. Further, the solder resist layer 2 was filled up to 5.5 μm below the surface of the connection pad 3 for connecting electronic components arranged on the first surface. Photopolymerization of the surface of the solder resist layer 2 other than the region irradiated with the actinic ray 6 in the contact exposure in the step (C1) on the first surface by the non-contact exposure in the oxygen atmosphere in the steps (C4) and (C5). As a result, the thickness of the solder resist layer 2 was reduced by 0.5 μm.
 次に、第一面及び第二面のソルダーレジスト層2を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施して、配線基板を得た。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmと19.5μmのソルダーレジスト層2によって被覆され、その段差に相当する厚さ10.5μmのアンダーフィル堰き止め用ダムが形成されていた。また、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ9.5μmのソルダーレジスト層2が充填されていた。また、第二面では、厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmのソルダーレジスト層2の円形開口部が形成されていて、外部接続用接続パッド4の一部が露出していた。 Next, in order to cure the solder resist layer 2 on the first surface and the second surface, the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was. As a result of observation with an optical microscope, on the first surface, a conductor wiring 7 with a thickness of 15 μm is covered with a solder resist layer 2 with a thickness of 30 μm and 19.5 μm, and an underfill weir with a thickness of 10.5 μm corresponding to the step. A stop dam was formed. In addition, the electronic component connecting connection pads 3 having a thickness of 15 μm were exposed, and the solder resist layer 2 having a thickness of 9.5 μm was filled between the adjacent electronic component connecting connection pads 3. On the second surface, a circular opening of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm is formed on a part of the connection pad 4 for external connection having a thickness of 15 μm. A part of was exposed.
 次に、第一面に配置された複数の電子部品接続用接続パッド3の端部から200μm離れた外周と該端部から400μm離れた外周との間の領域にある厚さ19.5μmのソルダーレジスト層2の表面粗さを測定したところ、表面粗さRaは0.40μmであった。また、隣接する電子部品接続用接続パッド3間のソルダーレジスト層2の表面粗さを測定したところ、表面粗さRaは0.40μmであった。 Next, a solder having a thickness of 19.5 μm in a region between the outer periphery 200 μm away from the ends of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 μm away from the ends When the surface roughness of the resist layer 2 was measured, the surface roughness Ra was 0.40 μm. Moreover, when the surface roughness of the soldering resist layer 2 between the adjacent connection pads 3 for electronic component connection was measured, the surface roughness Ra was 0.40 μm.
(実施例9)
 工程(C4)及び(C5)における露光量を200mJ/cmとした以外は実施例7と同じ方法で、工程(A)~工程(D)までを実施した。光学顕微鏡で観察した結果、第一面及び第二面ともに電子部品接続用接続パッド3及び外部接続用接続パッド4上にソルダーレジスト層2の残渣は見られなかった。また、第一面に配置された電子部品接続用接続パッド3の表面下6.0μmまでソルダーレジスト層2が充填されていた。工程(C4)及び(C5)における酸素雰囲気下での非接触露光により、第一面では、工程(C1)における密着露光で活性光線6が照射された領域以外のソルダーレジスト層2表面の光重合が抑制され、結果として、ソルダーレジスト層2の厚さが1.0μm減少していた。
Example 9
Steps (A) to (D) were carried out in the same manner as in Example 7 except that the exposure dose in steps (C4) and (C5) was 200 mJ / cm 2 . As a result of observation with an optical microscope, no residue of the solder resist layer 2 was found on the connection pads 3 for connecting electronic components and the connection pads 4 for external connection on both the first surface and the second surface. Further, the solder resist layer 2 was filled up to 6.0 μm below the surface of the connection pad 3 for connecting electronic components arranged on the first surface. Photopolymerization of the surface of the solder resist layer 2 other than the region irradiated with the actinic ray 6 in the contact exposure in the step (C1) on the first surface by the non-contact exposure in the oxygen atmosphere in the steps (C4) and (C5). As a result, the thickness of the solder resist layer 2 was reduced by 1.0 μm.
 次に、第一面及び第二面のソルダーレジスト層2を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施して、配線基板を得た。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmと19μmのソルダーレジスト層2によって被覆され、その段差に相当する厚さ11μmのアンダーフィル堰き止め用ダムが形成されていた。また、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ9.0μmのソルダーレジスト層2が充填されていた。また、第二面では、厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmのソルダーレジスト層2の円形開口部が形成されていて、外部接続用接続パッド4の一部が露出していた。 Next, in order to cure the solder resist layer 2 on the first surface and the second surface, the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was. As a result of observation with an optical microscope, on the first surface, a conductor wiring 7 with a thickness of 15 μm is covered with a solder resist layer 2 with a thickness of 30 μm and a thickness of 19 μm. Was formed. Further, the connection pad 3 for connecting an electronic component having a thickness of 15 μm was exposed, and the solder resist layer 2 having a thickness of 9.0 μm was filled between adjacent connection pads 3 for connecting an electronic component. On the second surface, a circular opening of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm is formed on a part of the connection pad 4 for external connection having a thickness of 15 μm. A part of was exposed.
 次に、第一面に配置された複数の電子部品接続用接続パッド3の端部から200μm離れた外周と該端部から400μm離れた外周との間の領域にある厚さ19μmのソルダーレジスト層2の表面粗さを測定したところ、表面粗さRaは0.50μmであった。また、隣接する電子部品接続用接続パッド3間のソルダーレジスト層2の表面粗さを測定したところ、表面粗さRaは0.50μmであった。 Next, a 19 μm thick solder resist layer in a region between the outer periphery 200 μm away from the ends of the plurality of connection pads 3 for connecting electronic components disposed on the first surface and the outer periphery 400 μm away from the ends When the surface roughness 2 was measured, the surface roughness Ra was 0.50 μm. Further, when the surface roughness of the solder resist layer 2 between the adjacent connection pads 3 for connecting electronic components was measured, the surface roughness Ra was 0.50 μm.
(実施例10)
 工程(C4)及び(C5)における露光量を1000mJ/cmとした以外は実施例6と同じ方法で、工程(A)~工程(D)までを実施した。光学顕微鏡で観察した結果、第一面及び第二面ともに電子部品接続用接続パッド3及び外部接続用接続パッド4上にソルダーレジスト層2の残渣は見られなかった。また、第一面に配置された電子部品接続用接続パッド3の表面下5.0μmまでソルダーレジスト層2が充填されており、工程(C4)及び(C5)における酸素の重合阻害による第一面のソルダーレジスト層2の膜減りは確認されなかった。
(Example 10)
Steps (A) to (D) were performed in the same manner as in Example 6 except that the exposure dose in steps (C4) and (C5) was 1000 mJ / cm 2 . As a result of observation with an optical microscope, no residue of the solder resist layer 2 was found on the connection pads 3 for connecting electronic components and the connection pads 4 for external connection on both the first surface and the second surface. Further, the solder resist layer 2 is filled up to 5.0 μm below the surface of the connection pad 3 for connecting electronic components arranged on the first surface, and the first surface due to the inhibition of oxygen polymerization in the steps (C4) and (C5) The film loss of the solder resist layer 2 was not confirmed.
 次に、第一面及び第二面のソルダーレジスト層2を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施して、配線基板を得た。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmと20μmのソルダーレジスト層2によって被覆され、その段差に相当する厚さ10μmのアンダーフィル堰き止め用ダムが形成されていた。また、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ10.0μmのソルダーレジスト層2が充填されていた。また、第二面では、厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmのソルダーレジスト層2の円形開口部が形成されていて、外部接続用接続パッド4の一部が露出していた。 Next, in order to cure the solder resist layer 2 on the first surface and the second surface, the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was. As a result of observation with an optical microscope, on the first surface, a conductor wiring 7 with a thickness of 15 μm is covered with a solder resist layer 2 with a thickness of 30 μm and a thickness of 20 μm. Was formed. Further, the connection pad 3 for connecting an electronic component having a thickness of 15 μm was exposed, and the solder resist layer 2 having a thickness of 10.0 μm was filled between adjacent connection pads 3 for connecting an electronic component. On the second surface, a circular opening of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm is formed on a part of the connection pad 4 for external connection having a thickness of 15 μm. A part of was exposed.
 次に、第一面に配置された複数の電子部品接続用接続パッド3の端部から200μm離れた外周と該端部から400μm離れた外周との間の領域にある厚さ20μmのソルダーレジスト層2の表面粗さを測定したところ、表面粗さRaは0.30μmであった。また、隣接する電子部品接続用接続パッド3間のソルダーレジスト層2の表面粗さを測定したところ、表面粗さRaは0.30μmであった。 Next, a solder resist layer having a thickness of 20 μm in a region between the outer periphery 200 μm away from the ends of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 μm away from the ends When the surface roughness 2 was measured, the surface roughness Ra was 0.30 μm. Further, when the surface roughness of the solder resist layer 2 between the adjacent connection pads 3 for connecting electronic components was measured, the surface roughness Ra was 0.30 μm.
(実施例11)
 工程(C4)及び(C5)において、密着露光方式にて露光を行った以外は、実施例7と同じ方法で、工程(A)~工程(D)までを実施した。光学顕微鏡で観察した結果、第一面及び第二面ともに電子部品接続用接続パッド3及び外部接続用接続パッド4上にソルダーレジスト層2の残渣は見られなかった。また、第一面では、電子部品接続用接続パッド3の表面下5.0μmまで、電子部品接続用接続パッド3間にソルダーレジスト層2が充填されていた。工程(C4)及び(C5)において、密着露光時のエア抜きを十分行うことにより、非酸素雰囲気下で露光を行ったため、ソルダーレジスト層2表面が粗面化せず、結果として、ソルダーレジスト層2の厚さは減少しなかった。
(Example 11)
In the steps (C4) and (C5), the steps (A) to (D) were carried out in the same manner as in Example 7 except that the exposure was performed by the contact exposure method. As a result of observation with an optical microscope, no residue of the solder resist layer 2 was found on the connection pads 3 for connecting electronic components and the connection pads 4 for external connection on both the first surface and the second surface. On the first surface, the solder resist layer 2 was filled between the connection pads 3 for electronic component connection up to 5.0 μm below the surface of the connection pads 3 for electronic component connection. In the steps (C4) and (C5), the surface of the solder resist layer 2 was not roughened because exposure was performed in a non-oxygen atmosphere by sufficiently releasing air during contact exposure. As a result, the solder resist layer was not roughened. The thickness of 2 did not decrease.
 次に、第一面及び第二面のソルダーレジスト層2を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施して、配線基板を得た。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmと20μmのソルダーレジスト層2によって被覆され、その段差に相当する厚さ10μmのアンダーフィル堰き止め用ダムが形成されていた。また、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ10.0μmのソルダーレジスト層2が充填されていた。また、第二面では、厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmのソルダーレジスト層2の円形開口部が形成されていて、外部接続用接続パッド4の一部が露出していた。 Next, in order to cure the solder resist layer 2 on the first surface and the second surface, the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was. As a result of observation with an optical microscope, on the first surface, a conductor wiring 7 with a thickness of 15 μm is covered with a solder resist layer 2 with a thickness of 30 μm and a thickness of 20 μm. Was formed. Further, the connection pad 3 for connecting an electronic component having a thickness of 15 μm was exposed, and the solder resist layer 2 having a thickness of 10.0 μm was filled between adjacent connection pads 3 for connecting an electronic component. On the second surface, a circular opening of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm is formed on a part of the connection pad 4 for external connection having a thickness of 15 μm. A part of was exposed.
 次に、第一面に配置された複数の電子部品接続用接続パッド3の端部から200μm離れた外周と該端部から400μm離れた外周との間の領域にある厚さ20μmのソルダーレジスト層2の表面粗さを測定したところ、表面粗さRaは0.10μmであった。また、隣接する電子部品接続用接続パッド3間のソルダーレジスト層2の表面粗さを測定したところ、表面粗さRaは0.10μmであった。 Next, a solder resist layer having a thickness of 20 μm in a region between the outer periphery 200 μm away from the ends of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 μm away from the ends When the surface roughness 2 was measured, the surface roughness Ra was 0.10 μm. Further, when the surface roughness of the solder resist layer 2 between the adjacent connection pads 3 for connecting electronic components was measured, the surface roughness Ra was 0.10 μm.
 実施例7~11では、隣接する電子部品接続用接続パッド3間に十分な厚さのソルダーレジスト層2があるため、電子部品を実装する際に半田による電気的な短絡が起きるのを確実に防ぐことができた。外部接続用接続パッド4上にソルダーレジスト層2の残渣が存在しないため、外部電気基板に実装する際にも電気的絶縁不良が発生しない信頼性の高い配線基板を作製することができた。実施例7~11を比較すると、電子部品接続用接続パッド3間及び周囲のソルダーレジスト層2の表面が平滑である実施例11で製造された配線基板よりも、実施例7~10で製造された配線基板の方が、アンダーフィルとの密着性が高く、接続信頼性が優れていた。 In Examples 7 to 11, since there is a solder resist layer 2 having a sufficient thickness between adjacent connection pads 3 for connecting electronic components, it is ensured that an electrical short circuit due to solder occurs when the electronic components are mounted. I was able to prevent it. Since there is no residue of the solder resist layer 2 on the connection pad 4 for external connection, a highly reliable wiring board that does not cause an electrical insulation failure when mounted on the external electric board can be produced. Comparing Examples 7 to 11, it is manufactured in Examples 7 to 10 rather than the wiring board manufactured in Example 11 in which the surface of the solder resist layer 2 between and around the connection pads 3 for connecting electronic components is smooth. The printed wiring board had higher adhesion to the underfill and better connection reliability.
(比較例2)
<工程(A)>
 セミアディティブ法を用いて、両表面に導体配線7が形成された回路基板1(面積170mm×200mm、導体厚さ15μm、基板厚さ0.4mm)を作製した。表面(第一面)には電子部品接続用接続パッド3として使用される線幅25μm、間隔50μmの導体配線がある。裏面(第二面)には外部接続用接続パッド4として使用される直径600μmの円形状の導体配線が形成されている。次に、真空ラミネータを用いて、厚さ25μmのソルダーレジストフィルム(太陽インキ製造(株)製、商品名:PFR-800 AUS410)を上記回路基板1の両表面に真空熱圧着させた(ラミネート温度75℃、吸引時間30秒、加圧時間10秒)。これにより、ソルダーレジスト層2が形成された。第一面のソルダーレジスト層2では、絶縁層8表面からの厚さが30μmであり、電子部品接続用接続パッド3上の厚さは15μmであった。第二面のソルダーレジスト層2では、絶縁層8表面からの厚さが38μmであり、外部接続用接続パッド4上の厚さが23μmであった。導体配線の密度がより小さい第一面では、導体配線の密度がより大きい第二面に比べ、ソルダーレジスト層2の厚さが8μm薄くなっていた。
(Comparative Example 2)
<Process (A)>
Using a semi-additive method, a circuit board 1 (area 170 mm × 200 mm, conductor thickness 15 μm, board thickness 0.4 mm) having conductor wirings 7 formed on both surfaces was produced. On the surface (first surface), there is a conductor wiring having a line width of 25 μm and an interval of 50 μm used as the connection pad 3 for connecting electronic components. A circular conductor wiring having a diameter of 600 μm used as the external connection pad 4 is formed on the back surface (second surface). Next, using a vacuum laminator, a 25 μm thick solder resist film (manufactured by Taiyo Ink Manufacturing Co., Ltd., trade name: PFR-800 AUS410) was vacuum thermocompression bonded to both surfaces of the circuit board 1 (lamination temperature). 75 ° C., suction time 30 seconds, pressurization time 10 seconds). Thereby, the soldering resist layer 2 was formed. In the solder resist layer 2 on the first surface, the thickness from the surface of the insulating layer 8 was 30 μm, and the thickness on the connection pad 3 for connecting electronic components was 15 μm. In the solder resist layer 2 on the second surface, the thickness from the surface of the insulating layer 8 was 38 μm, and the thickness on the connection pad 4 for external connection was 23 μm. On the first surface where the density of the conductor wiring is smaller, the thickness of the solder resist layer 2 is 8 μm thinner than on the second surface where the density of the conductor wiring is larger.
<工程(C1)>
 第一面のソルダーレジスト層2に対して、複数の電子部品接続用接続パッド3の端部から200μm離れた外周よりも外側の領域に活性光線6が照射されるようなパターンのフォトマスク5を用いて、露光量200mJ/cmで密着露光を行った。
<Process (C1)>
A photomask 5 having a pattern in which actinic rays 6 are irradiated to a region outside the outer periphery 200 μm away from the end portions of the plurality of connection pads 3 for connecting electronic components to the solder resist layer 2 on the first surface. The contact exposure was performed at an exposure amount of 200 mJ / cm 2 .
<工程(C2)>
 第二面のソルダーレジスト層2に対して、外部接続用接続パッド4上に直径500μmの円形開口部領域を設けるべく、円形開口部領域以外に活性光線6が照射されるようなパターンのフォトマスク5を用いて、露光量200mJ/cmで密着露光を行った。
<Process (C2)>
A photomask having a pattern in which actinic rays 6 are irradiated in areas other than the circular opening area in order to provide a circular opening area having a diameter of 500 μm on the external connection pad 4 for the solder resist layer 2 on the second surface. 5 was used for contact exposure at an exposure amount of 200 mJ / cm 2 .
<工程(B1)>
 第一面及び第二面のソルダーレジスト層2上の支持層フィルムを剥離した後、10質量%のメタケイ酸ナトリウム水溶液(液温25℃)を薄膜化処理液として用いて、第一面を上にして薄膜化処理液に回路基板1を25秒間浸漬させてミセル化処理(薄膜化処理)を行った。その後、ミセル除去液(液温25℃)のスプレーによるミセル除去処理、水洗処理(液温25℃)及び乾燥処理を行い、第一面の非露光部のソルダーレジスト層2の厚さが電子部品接続用接続パッド3の表面上5.0μmになるまで、平均10μmのソルダーレジスト層2を薄膜化した。光学顕微鏡で観察したところ、第一面のソルダーレジスト層2の表面に処理ムラはなく、良好な面内均一性が得られた。一方、第二面のソルダーレジスト層2も平均10μm薄膜化されていたが、薄膜化処理液中の気泡が第二面の非露光部のソルダーレジスト層2に付着し、膜厚不均一となっている箇所があった。また、外部接続用接続パッド4には約13μmのソルダーレジスト層2の残渣が残っていた。
<Process (B1)>
After peeling off the support layer film on the solder resist layer 2 on the first side and the second side, the first side is turned up using a 10% by mass sodium metasilicate aqueous solution (liquid temperature 25 ° C.) as a thinning solution. Then, the circuit board 1 was immersed in the thinning treatment solution for 25 seconds to perform micellization treatment (thinning treatment). Then, the micelle removal process by spraying the micelle removal liquid (liquid temperature 25 ° C.), the water washing process (liquid temperature 25 ° C.) and the drying process are performed, and the thickness of the solder resist layer 2 in the non-exposed portion on the first surface is the electronic component. The solder resist layer 2 having an average of 10 μm was thinned to 5.0 μm on the surface of the connection pad 3 for connection. When observed with an optical microscope, the surface of the solder resist layer 2 on the first surface was free from uneven processing, and good in-plane uniformity was obtained. On the other hand, the solder resist layer 2 on the second surface was also thinned by an average of 10 μm, but bubbles in the thinning treatment liquid adhered to the solder resist layer 2 on the non-exposed portion of the second surface, resulting in non-uniform film thickness. There was a place. Further, the residue of the solder resist layer 2 of about 13 μm remained on the connection pad 4 for external connection.
<工程(C4)>
 第一面のソルダーレジスト層2に対して、複数の電子部品接続用接続パッド3の端部から200μm離れた外周と該端部から400μm離れた外周との間の領域に、活性光線6が照射されるようなパターンのフォトマスク5を用いて、酸素雰囲気下での非接触露光により、露光量400mJ/cmで露光を行った。
<Process (C4)>
The actinic ray 6 irradiates the area between the outer periphery 200 μm away from the ends of the plurality of connection pads 3 for connecting electronic components and the outer periphery 400 μm away from the ends of the solder resist layer 2 on the first surface. Using the photomask 5 having such a pattern, exposure was performed at a dose of 400 mJ / cm 2 by non-contact exposure in an oxygen atmosphere.
<工程(B2)>
 10質量%のメタケイ酸ナトリウム水溶液(液温25℃)を薄膜化処理液として用いて、第一面を上にして薄膜化処理液に回路基板1を25秒間浸漬させてミセル化処理(薄膜化処理)を行った。その後、ミセル除去液(液温25℃)のスプレーによるミセル除去処理、水洗処理(液温25℃)及び乾燥処理を行い、第一面の非露光部のソルダーレジスト層2の厚さが電子部品接続用接続パッド3の表面下5.0μmになるまで、平均10μmのソルダーレジスト層2を薄膜化した。光学顕微鏡で観察したところ、第一面のソルダーレジスト層2の表面に処理ムラはなく、良好な面内均一性が得られた。工程(C4)における酸素雰囲気下での非接触露光により、第一面に配置された電子部品接続用接続パッド3の端部から200μm離れた外周から400μm離れた外周までの領域のソルダーレジスト層2表面の光重合が抑制され、結果としてソルダーレジスト層2の厚さが0.5μm減少した。一方、第二面のソルダーレジスト層2も平均10μm薄膜化されていたが、薄膜化処理液中の気泡が第二面の非露光部のソルダーレジスト層2に付着し、膜厚不均一となっている箇所があった。また、外部接続用接続パッド4には約3μmのソルダーレジスト層2の残渣が残っていた。
<Process (B2)>
Using 10% by mass of sodium metasilicate aqueous solution (liquid temperature: 25 ° C.) as the thinning treatment solution, the circuit board 1 is immersed in the thinning treatment solution for 25 seconds with the first side facing up, and the micelle treatment (thinning) Treatment). Thereafter, the micelle removal treatment by spraying the micelle removal liquid (liquid temperature 25 ° C.), the water washing treatment (liquid temperature 25 ° C.) and the drying treatment are performed, and the thickness of the solder resist layer 2 of the non-exposed portion on the first surface is the electronic component. The solder resist layer 2 having an average of 10 μm was thinned to 5.0 μm below the surface of the connection pad 3 for connection. When observed with an optical microscope, the surface of the solder resist layer 2 on the first surface was free from uneven processing, and good in-plane uniformity was obtained. Solder resist layer 2 in the region from the outer periphery 200 μm away to the outer periphery 400 μm away from the end of the connection pad 3 for connecting electronic components arranged on the first surface by non-contact exposure in an oxygen atmosphere in step (C4) Surface photopolymerization was suppressed, and as a result, the thickness of the solder resist layer 2 was reduced by 0.5 μm. On the other hand, the solder resist layer 2 on the second surface was also thinned by an average of 10 μm, but bubbles in the thinning treatment liquid adhered to the solder resist layer 2 on the non-exposed portion of the second surface, resulting in non-uniform film thickness. There was a place. Further, the residue of the solder resist layer 2 of about 3 μm remained on the connection pad 4 for external connection.
 次に、第一面及び第二面のソルダーレジスト層2を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施して、配線基板を得た。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmと19.5μmのソルダーレジスト層2によって被覆され、その段差に相当する厚さ10.5μmのアンダーフィル堰き止め用ダムが形成されていた。また、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ9.5μmのソルダーレジスト層2が充填されていた。また、第二面は厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmのソルダーレジスト層2の円形開口部が形成されていたが、外部接続用接続パッド4上には3μmのソルダーレジスト層2の残渣が残っていた。 Next, in order to cure the solder resist layer 2 on the first surface and the second surface, the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and then a thermosetting process is performed at 150 ° C. for 60 minutes to obtain a wiring board. It was. As a result of observation with an optical microscope, on the first surface, a conductor wiring 7 with a thickness of 15 μm is covered with a solder resist layer 2 with a thickness of 30 μm and 19.5 μm, and an underfill weir with a thickness of 10.5 μm corresponding to the step. A stop dam was formed. In addition, the electronic component connecting connection pads 3 having a thickness of 15 μm were exposed, and the solder resist layer 2 having a thickness of 9.5 μm was filled between the adjacent electronic component connecting connection pads 3. Further, the second surface has a circular opening of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm formed on a part of the connection pad 4 for external connection having a thickness of 15 μm. Residue of 3 μm solder resist layer 2 remained on the top.
 電子部品を実装する際、隣接する電子部品接続用接続パッド3間に十分な厚さのソルダーレジスト層2があり、半田による電気的な短絡を確実に防ぐことができるが、外部電気基板に実装する際、外部接続用接続パッド4上に残ったソルダーレジスト層2の残渣によって、半田バンプ接続において電気的絶縁不良が発生した。 When mounting electronic components, there is a solder resist layer 2 of sufficient thickness between adjacent connection pads 3 for connecting electronic components, which can prevent electrical short circuit due to soldering, but can be mounted on an external electric board. At this time, due to the residue of the solder resist layer 2 remaining on the connection pads 4 for external connection, an electrical insulation failure occurred in the solder bump connection.
 隣接する電子部品接続用接続パッド3間のソルダーレジスト層2の表面粗さを測定したところ、表面粗さRaは0.03μmであった。電子部品接続用接続パッド3間のソルダーレジスト表面が平滑である比較例2で製造された配線基板よりも、実施例7~11で製造された配線基板の方が、アンダーフィルとの密着性が高く、接続信頼性が優れていた。 When the surface roughness of the solder resist layer 2 between the adjacent connection pads 3 for connecting electronic components was measured, the surface roughness Ra was 0.03 μm. The wiring board manufactured in Examples 7 to 11 has better adhesion to the underfill than the wiring board manufactured in Comparative Example 2 in which the solder resist surface between the connection pads 3 for connecting electronic components is smooth. High connection reliability.
 実施例12~16は、図6-1、図6-2および図6-3に示した配線基板の製造方法(3)に関する例である。 Examples 12 to 16 are examples relating to the manufacturing method (3) of the wiring board shown in FIGS. 6-1, 6-2, and 6-3.
(実施例12)
<工程(A1)>
 セミアディティブ法を用いて、両表面に導体配線7が形成された回路基板1(面積170mm×200mm、導体厚さ15μm、基板厚さ0.4mm)を作製した。表面(第一面)には電子部品接続用接続パッド3として使用される線幅25μm、間隔50μmの導体配線がある。裏面(第二面)には外部接続用接続パッド4として使用される直径600μmの円形状の導体配線が形成されている。次に、真空ラミネータを用いて、厚さ15μmのソルダーレジストフィルム(太陽インキ製造(株)製、商品名:PFR-800 AUS410)を上記回路基板1の表面に、厚さ25μmのソルダーレジストフィルム(太陽インキ製造(株)製、商品名:PFR-800 AUS410)を上記回路基板1の裏面に真空熱圧着させた(ラミネート温度75℃、吸引時間30秒、加圧時間10秒)。これにより、第一ソルダーレジスト層2-1が形成された。第一面の第一ソルダーレジスト層2-1では、絶縁層8表面からの厚さが20μmであり、電子部品接続用接続パッド3上の厚さは5μmであった。第二面の第一ソルダーレジスト層2-1では、絶縁層8表面からの厚さが38μmであり、外部接続用接続パッド4上の厚さが23μmであった。
Example 12
<Process (A1)>
Using a semi-additive method, a circuit board 1 (area 170 mm × 200 mm, conductor thickness 15 μm, board thickness 0.4 mm) having conductor wirings 7 formed on both surfaces was produced. On the surface (first surface), there is a conductor wiring having a line width of 25 μm and an interval of 50 μm used as the connection pad 3 for connecting electronic components. A circular conductor wiring having a diameter of 600 μm used as the external connection pad 4 is formed on the back surface (second surface). Next, using a vacuum laminator, a 15 μm thick solder resist film (manufactured by Taiyo Ink Manufacturing Co., Ltd., trade name: PFR-800 AUS410) is applied to the surface of the circuit board 1 and a 25 μm thick solder resist film ( Taiyo Ink Mfg. Co., Ltd., trade name: PFR-800 AUS410) was vacuum thermocompression bonded to the back surface of the circuit board 1 (lamination temperature 75 ° C., suction time 30 seconds, pressurization time 10 seconds). Thereby, the first solder resist layer 2-1 was formed. In the first solder resist layer 2-1 on the first surface, the thickness from the surface of the insulating layer 8 was 20 μm, and the thickness on the connection pad 3 for connecting electronic components was 5 μm. In the first solder resist layer 2-1 on the second surface, the thickness from the surface of the insulating layer 8 was 38 μm, and the thickness on the connection pad 4 for external connection was 23 μm.
<工程(C1)>
 第一面の第一ソルダーレジスト層2-1に対して、複数の電子部品接続用接続パッド3の端部から200μm離れた外周よりも外側の領域に活性光線6が照射されるようなパターンのフォトマスク5を用いて、露光量200mJ/cmで密着露光を行った。
<Process (C1)>
The first solder resist layer 2-1 on the first surface has a pattern in which actinic rays 6 are irradiated to a region outside the outer periphery that is 200 μm away from the ends of the plurality of connection pads 3 for connecting electronic components. Using the photomask 5, contact exposure was performed with an exposure amount of 200 mJ / cm 2 .
<工程(C2)>
 第二面の第一ソルダーレジスト層2-1に対して、外部接続用接続パッド4上に直径500μmの円形開口部領域を設けるべく、円形開口部領域以外に活性光線6が照射されるようなパターンのフォトマスク5を用いて、露光量200mJ/cmで密着露光を行った。
<Process (C2)>
In order to provide a circular opening area having a diameter of 500 μm on the external connection pad 4 with respect to the first solder resist layer 2-1 on the second surface, the actinic ray 6 is irradiated in a region other than the circular opening area. Using the photomask 5 having a pattern, contact exposure was performed at an exposure amount of 200 mJ / cm 2 .
<工程(B)>
 第一面及び第二面の第一ソルダーレジスト層2-1上の支持層フィルムを剥離した後、10質量%のメタケイ酸ナトリウム水溶液(液温25℃)を薄膜化処理液として用いて、第一面を上にして薄膜化処理液に回路基板1を25秒間浸漬させてミセル化処理(薄膜化処理)を行った。その後、ミセル除去液(液温25℃)のスプレーによるミセル除去処理、水洗処理(液温25℃)及び乾燥処理を行い、第一面の非露光部の第一ソルダーレジスト層2-1の厚さが電子部品接続用接続パッド3の表面下5.0μmになるまで、平均10μmの第一ソルダーレジスト層2-1を薄膜化した。光学顕微鏡で観察したところ、第一面の第一ソルダーレジスト層2-1の表面に処理ムラはなく、良好な面内均一性が得られた。一方、第二面の第一ソルダーレジスト層2-1も平均10μm薄膜化されていたが、薄膜化処理液中の気泡が第二面の非露光部の第一ソルダーレジスト層2-1に付着し、膜厚不均一となっている箇所があった。また、外部接続用接続パッド4には約13μmの第一ソルダーレジスト層2-1の残渣が残っていた。
<Process (B)>
After peeling off the support layer film on the first solder resist layer 2-1 on the first surface and the second surface, a 10% by mass sodium metasilicate aqueous solution (liquid temperature 25 ° C.) was used as the thinning treatment solution. The circuit board 1 was immersed for 25 seconds in a thinning solution with one side facing up to perform micellization (thinning). Thereafter, the micelle removal treatment by spraying the micelle removal liquid (liquid temperature 25 ° C.), the water washing treatment (liquid temperature 25 ° C.) and the drying treatment are performed, and the thickness of the first solder resist layer 2-1 in the non-exposed portion of the first surface The first solder resist layer 2-1 having an average of 10 μm was thinned until the thickness became 5.0 μm below the surface of the connection pad 3 for connecting electronic parts. When observed with an optical microscope, the surface of the first solder resist layer 2-1 on the first surface was not uneven and good in-plane uniformity was obtained. On the other hand, the first solder resist layer 2-1 on the second surface was also thinned by an average of 10 μm, but bubbles in the thinning treatment liquid adhered to the first solder resist layer 2-1 on the non-exposed portion of the second surface. However, there was a portion where the film thickness was non-uniform. Further, the residue of the first solder resist layer 2-1 of about 13 μm remained on the connection pad 4 for external connection.
<工程(C3)>
 第一面の第一ソルダーレジスト層2-1に対して、工程(B)において薄膜化された領域に、活性光線6が照射されるようなパターンのフォトマスク5を用いて、酸素雰囲気下での非接触露光により、露光量400mJ/cmで露光を行った。
<Process (C3)>
Using a photomask 5 having a pattern in which actinic rays 6 are irradiated onto the thinned region in step (B) with respect to the first solder resist layer 2-1 on the first surface, in an oxygen atmosphere. In this non-contact exposure, exposure was performed at an exposure amount of 400 mJ / cm 2 .
<工程(A2)>
 真空ラミネータを用いて、厚さ15μmのソルダーレジストフィルム(太陽インキ製造(株)製、商品名:PFR-800 AUS410)を、工程(C3)まで完了した回路基板1の第一面の第一ソルダーレジスト層2-1上に、真空熱圧着させた(ラミネート温度75℃、吸引時間30秒、加圧時間10秒)。これにより、第一面の第二ソルダーレジスト層2-2が形成された。第一面の第二ソルダーレジスト層2-2では、絶縁層8表面からの厚さが30μmであった。
<Process (A2)>
The first solder on the first surface of the circuit board 1 which has completed the solder resist film (trade name: PFR-800 AUS410, manufactured by Taiyo Ink Manufacturing Co., Ltd.) having a thickness of 15 μm up to the step (C3) using a vacuum laminator. A vacuum thermocompression bonding was performed on the resist layer 2-1 (lamination temperature 75 ° C., suction time 30 seconds, pressurization time 10 seconds). As a result, the second solder resist layer 2-2 on the first surface was formed. In the second solder resist layer 2-2 on the first surface, the thickness from the surface of the insulating layer 8 was 30 μm.
<工程(C6)>
 第一面の第二ソルダーレジスト層2-2に対して、電子部品接続用接続パッド3の端部から400μm離れた外周よりも外側の領域に、活性光線6が照射されるようなパターンのフォトマスク5を用いて、露光量200mJ/cmで密着露光を行った。
<Process (C6)>
A photo of a pattern in which the active light beam 6 is irradiated to a region outside the outer periphery 400 μm away from the end of the connection pad 3 for connecting the electronic component to the second solder resist layer 2-2 on the first surface. Using mask 5, contact exposure was performed at an exposure amount of 200 mJ / cm 2 .
<工程(D1)>
 1質量%の炭酸ナトリウム水溶液(液温度30℃、スプレー圧0.15MPa)を用いて30秒間現像を行い、第一面の非露光部の第二ソルダーレジスト層2-2及び第二面の非露光部の第一ソルダーレジスト層2-1を除去した。これによって、アンダーフィル堰き止め用ダムを形成するとともに、第二ソルダーレジスト層2-2によって覆われていた第一ソルダーレジスト層2-1から露出した状態の電子部品接続用接続パッド3とその周囲の第一ソルダーレジスト層2-1が再び露出した。光学顕微鏡で観察した結果、第一面及び第二面ともに電子部品接続用接続パッド3及び外部接続用接続パッド4上に第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2の残渣は見られなかった。また、第一面に配置された電子部品接続用接続パッド3の表面下5.5μmまで第一ソルダーレジスト層2-1が充填されていた。工程(C3)における酸素雰囲気下での非接触露光により、第一面に配置された電子部品接続用接続パッド3間の第一ソルダーレジスト層2-1表面の光重合が抑制され、結果として、第一面の第一ソルダーレジスト層2-1の厚さが0.5μm減少していた。
<Process (D1)>
Development is performed for 30 seconds using a 1% by mass aqueous sodium carbonate solution (liquid temperature 30 ° C., spray pressure 0.15 MPa), and the second solder resist layer 2-2 in the non-exposed area on the first surface and the non-exposed surface on the second surface The first solder resist layer 2-1 in the exposed area was removed. As a result, an underfill dam is formed, and the electronic component connecting connection pad 3 exposed from the first solder resist layer 2-1 covered with the second solder resist layer 2-2 and its surroundings are formed. The first solder resist layer 2-1 was exposed again. As a result of observation with an optical microscope, residues of the first solder resist layer 2-1 and the second solder resist layer 2-2 on the connection pads 3 for electronic component connection and the connection pads 4 for external connection on both the first surface and the second surface Was not seen. Further, the first solder resist layer 2-1 was filled up to 5.5 μm below the surface of the connection pad 3 for connecting electronic parts arranged on the first surface. By non-contact exposure in an oxygen atmosphere in the step (C3), photopolymerization of the surface of the first solder resist layer 2-1 between the connection pads 3 for connecting electronic components arranged on the first surface is suppressed, and as a result, The thickness of the first solder resist layer 2-1 on the first surface was reduced by 0.5 μm.
 次に、第一面の第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2並びに第二面の第一ソルダーレジスト層2-1を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施して、配線基板を得た。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmと20μmの第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2によって被覆され、その段差に相当する厚さ10μmのアンダーフィル堰き止め用ダムが形成されていた。また、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ9.5μmの第一ソルダーレジスト層2-1が充填されていた。また、第二面では、厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmの第一ソルダーレジスト層2-1の円形開口部が形成されていて、外部接続用接続パッド4の一部が露出していた。 Next, in order to cure the first solder resist layer 2-1 and the second solder resist layer 2-2 on the first surface and the first solder resist layer 2-1 on the second surface, the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 . The substrate was exposed and subsequently subjected to thermosetting at 150 ° C. for 60 minutes to obtain a wiring board. As a result of observation with an optical microscope, on the first surface, the conductor wiring 7 with a thickness of 15 μm is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 with a thickness of 30 μm and 20 μm, and the step is A corresponding underfill dam with a thickness of 10 μm was formed. Further, the electronic component connecting connection pads 3 having a thickness of 15 μm were exposed, and the first solder resist layer 2-1 having a thickness of 9.5 μm was filled between the adjacent electronic component connecting connection pads 3. On the second surface, a circular opening of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm is formed on a part of the connection pad 4 for external connection having a thickness of 15 μm. A part of the connection pad 4 was exposed.
 次に、第一面に配置された複数の電子部品接続用接続パッド3の端部から200μm離れた外周と該端部から400μm離れた外周との間の領域にある厚さ20μmの第一ソルダーレジスト層2-1の表面粗さを測定したところ、表面粗さRaは0.05μmであった。また、隣接する電子部品接続用接続パッド3間の領域の第一ソルダーレジスト層2-1の表面粗さを測定したところ、表面粗さRaは0.40μmであった。 Next, a first solder having a thickness of 20 μm in a region between the outer periphery 200 μm away from the end of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 μm away from the end When the surface roughness of the resist layer 2-1 was measured, the surface roughness Ra was 0.05 μm. Further, when the surface roughness of the first solder resist layer 2-1 in the region between adjacent electronic component connection pads 3 was measured, the surface roughness Ra was 0.40 μm.
(実施例13)
 工程(C1)と工程(C2)の順番を入れ替えた以外は実施例12と同じ方法で、工程(A1)~工程(D1)までを実施した。光学顕微鏡で観察した結果、第一面及び第二面ともに電子部品接続用接続パッド3及び外部接続用接続パッド4上に第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2の残渣は見られなかった。また、第一面に配置された電子部品接続用接続パッド3の表面下5.5μmまで第一ソルダーレジスト層2-1が充填されていた。工程(C3)における酸素雰囲気下での非接触露光により、第一面に配置された電子部品接続用接続パッド3間の第一ソルダーレジスト層2-1表面の光重合が抑制され、結果として、第一ソルダーレジスト層2-1の厚さが0.5μm減少していた。
(Example 13)
The steps (A1) to (D1) were carried out in the same manner as in Example 12 except that the order of the steps (C1) and (C2) was changed. As a result of observation with an optical microscope, residues of the first solder resist layer 2-1 and the second solder resist layer 2-2 on the connection pads 3 for electronic component connection and the connection pads 4 for external connection on both the first surface and the second surface Was not seen. Further, the first solder resist layer 2-1 was filled up to 5.5 μm below the surface of the connection pad 3 for connecting electronic parts arranged on the first surface. By non-contact exposure in an oxygen atmosphere in the step (C3), the photopolymerization of the surface of the first solder resist layer 2-1 between the connection pads 3 for connecting electronic components arranged on the first surface is suppressed, and as a result, The thickness of the first solder resist layer 2-1 was reduced by 0.5 μm.
 次に、第一面の第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2並びに第二面の第一ソルダーレジスト層2-1を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施して、配線基板を得た。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmと20μmの第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2によって被覆され、その段差に相当する厚さ10μmのアンダーフィル堰き止め用ダムが形成されていた。また、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ9.5μmの第一ソルダーレジスト層2-1が充填されていた。また、第二面では、厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmの第一ソルダーレジスト層2-1の円形開口部が形成されていて、外部接続用接続パッド4の一部が露出していた。 Next, in order to cure the first solder resist layer 2-1 and the second solder resist layer 2-2 on the first surface and the first solder resist layer 2-1 on the second surface, the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 . The substrate was exposed and subsequently subjected to thermosetting at 150 ° C. for 60 minutes to obtain a wiring board. As a result of observation with an optical microscope, on the first surface, the conductor wiring 7 with a thickness of 15 μm is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 with a thickness of 30 μm and 20 μm, and the step is A corresponding underfill dam with a thickness of 10 μm was formed. Further, the electronic component connecting connection pads 3 having a thickness of 15 μm were exposed, and the first solder resist layer 2-1 having a thickness of 9.5 μm was filled between the adjacent electronic component connecting connection pads 3. On the second surface, a circular opening of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm is formed on a part of the connection pad 4 for external connection having a thickness of 15 μm. A part of the connection pad 4 was exposed.
 次に、第一面に配置された複数の電子部品接続用接続パッド3の端部から200μm離れた外周と該端部から400μm離れた外周との間の領域にある厚さ20μmの第一ソルダーレジスト層2-1の表面粗さを測定したところ、表面粗さRaは0.05μmであった。また、隣接する電子部品接続用接続パッド3間の領域の第一ソルダーレジスト層2-1の表面粗さを測定したところ、表面粗さRaは0.40μmであった。 Next, a first solder having a thickness of 20 μm in a region between the outer periphery 200 μm away from the end of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 μm away from the end When the surface roughness of the resist layer 2-1 was measured, the surface roughness Ra was 0.05 μm. Further, when the surface roughness of the first solder resist layer 2-1 in the region between adjacent electronic component connection pads 3 was measured, the surface roughness Ra was 0.40 μm.
(実施例14)
 工程(C3)における露光量を200mJ/cmとした以外は実施例12と同じ方法で、工程(A1)~工程(D1)までを実施した。光学顕微鏡で観察した結果、第一面及び第二面ともに電子部品接続用接続パッド3及び外部接続用接続パッド4上に第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2の残渣は見られなかった。また、第一面に配置された電子部品接続用接続パッド3の表面下6.0μmまで第一ソルダーレジスト層2-1が充填されていた。工程(C3)における酸素雰囲気下での非接触露光により、第一面に配置された電子部品接続用接続パッド3間の第一ソルダーレジスト層2-1表面の光重合が抑制され、結果として、第一ソルダーレジスト層2-1の厚さが1.0μm減少していた。
(Example 14)
Steps (A1) to (D1) were performed in the same manner as in Example 12 except that the exposure dose in step (C3) was 200 mJ / cm 2 . As a result of observation with an optical microscope, residues of the first solder resist layer 2-1 and the second solder resist layer 2-2 on the connection pads 3 for electronic component connection and the connection pads 4 for external connection on both the first surface and the second surface Was not seen. Further, the first solder resist layer 2-1 was filled up to 6.0 μm below the surface of the connection pad 3 for connecting electronic components arranged on the first surface. By non-contact exposure in an oxygen atmosphere in the step (C3), the photopolymerization of the surface of the first solder resist layer 2-1 between the connection pads 3 for connecting electronic components arranged on the first surface is suppressed, and as a result, The thickness of the first solder resist layer 2-1 was reduced by 1.0 μm.
 次に、第一面の第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2並びに第二面の第一ソルダーレジスト層2-1を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施して、配線基板を得た。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmと20μmの第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2によって被覆され、その段差に相当する厚さ10μmのアンダーフィル堰き止め用ダムが形成されていた。また、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ9.0μmの第一ソルダーレジスト層2-1が充填されていた。また、第二面では、厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmの第一ソルダーレジスト層2-1の円形開口部が形成されていて、外部接続用接続パッド4の一部が露出していた。 Next, in order to cure the first solder resist layer 2-1 and the second solder resist layer 2-2 on the first surface and the first solder resist layer 2-1 on the second surface, the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 . The substrate was exposed and subsequently subjected to thermosetting at 150 ° C. for 60 minutes to obtain a wiring board. As a result of observation with an optical microscope, on the first surface, the conductor wiring 7 with a thickness of 15 μm is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 with a thickness of 30 μm and 20 μm, and the step is A corresponding underfill dam with a thickness of 10 μm was formed. Further, the connection pad 3 for connecting an electronic component having a thickness of 15 μm was exposed, and the first solder resist layer 2-1 having a thickness of 9.0 μm was filled between adjacent connection pads 3 for connecting an electronic component. On the second surface, a circular opening of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm is formed on a part of the connection pad 4 for external connection having a thickness of 15 μm. A part of the connection pad 4 was exposed.
 次に、第一面に配置された複数の電子部品接続用接続パッド3の端部から200μm離れた外周と該端部から400μm離れた外周との間の領域にある厚さ20μmの第一ソルダーレジスト層2-1の表面粗さを測定したところ、表面粗さRaは0.05μmであった。また、隣接する電子部品接続用接続パッド3間の領域の第一ソルダーレジスト層2-1の表面粗さを測定したところ、表面粗さRaは0.50μmであった。 Next, a first solder having a thickness of 20 μm in a region between the outer periphery 200 μm away from the end of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 μm away from the end When the surface roughness of the resist layer 2-1 was measured, the surface roughness Ra was 0.05 μm. Further, when the surface roughness of the first solder resist layer 2-1 in the region between adjacent electronic component connection pads 3 was measured, the surface roughness Ra was 0.50 μm.
(実施例15)
 工程(C3)における露光量を1000mJ/cmとした以外は実施例12と同じ方法で、工程(A1)~工程(D1)までを実施した。光学顕微鏡で観察した結果、第一面及び第二面ともに電子部品接続用接続パッド3及び外部接続用接続パッド4上に第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2の残渣は見られなかった。また、第一面に配置された電子部品接続用接続パッド3の表面下5.0μmまで第一ソルダーレジスト層2-1が充填されており、工程(C3)における酸素の重合阻害による第一面の第一ソルダーレジスト層2-1の膜減りは確認されなかった。
(Example 15)
Steps (A1) to (D1) were performed in the same manner as in Example 12 except that the exposure dose in step (C3) was 1000 mJ / cm 2 . As a result of observation with an optical microscope, residues of the first solder resist layer 2-1 and the second solder resist layer 2-2 on the connection pads 3 for electronic component connection and the connection pads 4 for external connection on both the first surface and the second surface Was not seen. Also, the first solder resist layer 2-1 is filled up to 5.0 μm below the surface of the connection pad 3 for connecting electronic components arranged on the first surface, and the first surface due to inhibition of oxygen polymerization in the step (C3) No film loss of the first solder resist layer 2-1 was confirmed.
 次に、第一面の第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2並びに第二面の第一ソルダーレジスト層2-1を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施した。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmと20μmの第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2によって被覆され、その段差に相当する厚さ10μmのアンダーフィル堰き止め用ダムが形成されていた。また、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ10.0μmの第一ソルダーレジスト層2-1が充填されていた。また、第二面では、厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmの第一ソルダーレジスト層2-1の円形開口部が形成されていて、外部接続用接続パッド4の一部が露出していた。 Next, in order to cure the first solder resist layer 2-1 and the second solder resist layer 2-2 on the first surface and the first solder resist layer 2-1 on the second surface, the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 . The exposure was followed by a thermosetting treatment at 150 ° C. for 60 minutes. As a result of observation with an optical microscope, on the first surface, the conductor wiring 7 with a thickness of 15 μm is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 with a thickness of 30 μm and 20 μm, and the step is A corresponding underfill dam with a thickness of 10 μm was formed. Further, the connection pad 3 for connecting an electronic component having a thickness of 15 μm was exposed, and the first solder resist layer 2-1 having a thickness of 10.0 μm was filled between adjacent connection pads 3 for connecting an electronic component. On the second surface, a circular opening of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm is formed on a part of the connection pad 4 for external connection having a thickness of 15 μm. A part of the connection pad 4 was exposed.
 次に、第一面に配置された複数の電子部品接続用接続パッド3の端部から200μm離れた外周と該端部から400μm離れた外周との間の領域にある厚さ20μmの第一ソルダーレジスト層2-1の表面粗さを測定したところ、表面粗さRaは0.05μmであった。また、隣接する電子部品接続用接続パッド3間の領域の第一ソルダーレジスト層2-1の表面粗さを測定したところ、表面粗さRaは0.30μmであった。 Next, a first solder having a thickness of 20 μm in a region between the outer periphery 200 μm away from the end of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 μm away from the end When the surface roughness of the resist layer 2-1 was measured, the surface roughness Ra was 0.05 μm. Further, when the surface roughness of the first solder resist layer 2-1 in the region between the adjacent electronic component connection pads 3 was measured, the surface roughness Ra was 0.30 μm.
(実施例16)
 工程(C3)において、密着露光方式にて露光を行った以外は、実施例12と同じ方法で、工程(A1)~工程(D1)までを実施した。光学顕微鏡で観察した結果、第一面及び第二面ともに電子部品接続用接続パッド3及び外部接続用接続パッド4上に第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2の残渣は見られなかった。また、第一面に配置された電子部品接続用接続パッド3の表面下5.0μmまで第一ソルダーレジスト層2-1が充填されていた。工程(C3)において、密着露光時のエア抜きを十分行うことにより、非酸素雰囲気下で露光を行ったため、第一ソルダーレジスト層2-1表面が粗面化せず、結果として、第一ソルダーレジスト層2-1の厚さは減少しなかった。
(Example 16)
Step (A1) to Step (D1) were carried out in the same manner as in Example 12 except that the exposure in the contact exposure method was performed in Step (C3). As a result of observation with an optical microscope, residues of the first solder resist layer 2-1 and the second solder resist layer 2-2 on the connection pads 3 for electronic component connection and the connection pads 4 for external connection on both the first surface and the second surface Was not seen. Further, the first solder resist layer 2-1 was filled up to 5.0 μm below the surface of the connection pad 3 for connecting electronic parts arranged on the first surface. In step (C3), the surface of the first solder resist layer 2-1 was not roughened because the exposure was performed in a non-oxygen atmosphere by sufficiently releasing the air during contact exposure. As a result, the first solder resist layer 2-1 was not roughened. The thickness of the resist layer 2-1 did not decrease.
 次に、第一面の第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2並びに第二面の第一ソルダーレジスト層2-1を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施した。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmと20μmの第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2によって被覆され、その段差に相当する厚さ10μmのアンダーフィル堰き止め用ダムが形成されていた。また、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ10.0μmの第一ソルダーレジスト層2-1が充填されていた。また、第二面では、厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmの第一ソルダーレジスト層2-1の円形開口部が形成されていて、外部接続用接続パッド4の一部が露出していた。 Next, in order to cure the first solder resist layer 2-1 and the second solder resist layer 2-2 on the first surface and the first solder resist layer 2-1 on the second surface, the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 . The exposure was followed by a thermosetting treatment at 150 ° C. for 60 minutes. As a result of observation with an optical microscope, on the first surface, the conductor wiring 7 with a thickness of 15 μm is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 with a thickness of 30 μm and 20 μm, and the step is A corresponding underfill dam with a thickness of 10 μm was formed. Further, the connection pad 3 for connecting an electronic component having a thickness of 15 μm was exposed, and the first solder resist layer 2-1 having a thickness of 10.0 μm was filled between adjacent connection pads 3 for connecting an electronic component. On the second surface, a circular opening of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm is formed on a part of the connection pad 4 for external connection having a thickness of 15 μm. A part of the connection pad 4 was exposed.
 次に、第一面に配置された複数の電子部品接続用接続パッド3の端部から200μm離れた外周と該端部から400μm離れた外周との間の領域にある厚さ20μmの第一ソルダーレジスト層2-1の表面粗さを測定したところ、表面粗さRaは0.05μmであった。また、隣接する電子部品接続用接続パッド3間の第一ソルダーレジスト層2-1の表面粗さを測定したところ、表面粗さRaは0.10μmであった。 Next, a first solder having a thickness of 20 μm in a region between the outer periphery 200 μm away from the end of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 μm away from the end When the surface roughness of the resist layer 2-1 was measured, the surface roughness Ra was 0.05 μm. Further, when the surface roughness of the first solder resist layer 2-1 between the adjacent connection pads 3 for connecting electronic components was measured, the surface roughness Ra was 0.10 μm.
 実施例12~16では、隣接する電子部品接続用接続パッド3間に十分な厚さの第一ソルダーレジスト層2-1があるため、電子部品を実装する際に半田による電気的な短絡が起きるのを確実に防ぐことができた。外部接続用接続パッド4上に第一ソルダーレジスト層2-1の残渣が存在しないため、外部電気基板に実装する際にも電気的絶縁不良が発生しない信頼性の高い配線基板を作製することができた。実施例12~16を比較すると、電子部品接続用接続パッド3間の第一ソルダーレジスト層2-1の表面が平滑である実施例16で製造された配線基板よりも、実施例12~15で製造された配線基板の方が、アンダーフィルとの密着性が高く、接続信頼性が優れていた。 In Examples 12 to 16, since the first solder resist layer 2-1 having a sufficient thickness is provided between the adjacent connection pads 3 for connecting electronic components, an electrical short circuit due to solder occurs when the electronic components are mounted. It was possible to prevent this reliably. Since there is no residue of the first solder resist layer 2-1 on the connection pad 4 for external connection, it is possible to manufacture a highly reliable wiring board that does not cause an electrical insulation failure even when mounted on the external electric board. did it. Comparing the examples 12 to 16, the examples 12 to 15 are more suitable than the wiring board manufactured in the example 16 in which the surface of the first solder resist layer 2-1 between the connection pads 3 for connecting the electronic parts is smooth. The manufactured wiring board had higher adhesion to the underfill and better connection reliability.
 実施例17~21は、図7-1、図7-2および図7-3に示した配線基板の製造方法(4)に関する例である。 Examples 17 to 21 are examples relating to the method (4) of manufacturing the wiring board shown in FIGS. 7-1, 7-2 and 7-3.
(実施例17)
<工程(A1)>
 セミアディティブ法を用いて、両表面に導体配線7が形成された回路基板1(面積170mm×200mm、導体厚さ15μm、基板厚さ0.4mm)を作製した。表面(第一面)には電子部品接続用接続パッド3として使用される線幅25μm、間隔50μmの導体配線がある。裏面(第二面)には外部接続用接続パッド4として使用される直径600μmの円形状の導体配線が形成されている。次に、真空ラミネータを用いて、厚さ15μmのソルダーレジストフィルム(太陽インキ製造(株)製、商品名:PFR-800 AUS410)を上記回路基板1の表面に、厚さ25μmのソルダーレジストフィルム(太陽インキ製造(株)製、商品名:PFR-800 AUS410)を上記回路基板1の裏面に真空熱圧着させた(ラミネート温度75℃、吸引時間30秒、加圧時間10秒)。これにより、第一ソルダーレジスト層2-1が形成された。第一面の第一ソルダーレジスト層2-1では、絶縁層8表面からの厚さが20μmであり、電子部品接続用接続パッド3上の厚さは5μmであった。第二面の第一ソルダーレジスト層2-1では、絶縁層8表面からの厚さが38μmであり、外部接続用接続パッド4上の厚さが23μmであった。
(Example 17)
<Process (A1)>
Using a semi-additive method, a circuit board 1 (area 170 mm × 200 mm, conductor thickness 15 μm, board thickness 0.4 mm) having conductor wirings 7 formed on both surfaces was produced. On the surface (first surface), there is a conductor wiring having a line width of 25 μm and an interval of 50 μm used as the connection pad 3 for connecting electronic components. A circular conductor wiring having a diameter of 600 μm used as the external connection pad 4 is formed on the back surface (second surface). Next, using a vacuum laminator, a 15 μm thick solder resist film (manufactured by Taiyo Ink Manufacturing Co., Ltd., trade name: PFR-800 AUS410) is applied to the surface of the circuit board 1 and a 25 μm thick solder resist film ( Taiyo Ink Mfg. Co., Ltd., trade name: PFR-800 AUS410) was vacuum thermocompression bonded to the back surface of the circuit board 1 (lamination temperature 75 ° C., suction time 30 seconds, pressurization time 10 seconds). Thereby, the first solder resist layer 2-1 was formed. In the first solder resist layer 2-1 on the first surface, the thickness from the surface of the insulating layer 8 was 20 μm, and the thickness on the connection pad 3 for connecting electronic components was 5 μm. In the first solder resist layer 2-1 on the second surface, the thickness from the surface of the insulating layer 8 was 38 μm, and the thickness on the connection pad 4 for external connection was 23 μm.
<工程(C1)>
 第一面の第一ソルダーレジスト層2-1に対して、複数の電子部品接続用接続パッド3の端部から200μm離れた外周よりも外側の領域に活性光線6が照射されるようなパターンのフォトマスク5を用いて、露光量200mJ/cmで密着露光を行った。
<Process (C1)>
The first solder resist layer 2-1 on the first surface has a pattern in which actinic rays 6 are irradiated to a region outside the outer periphery that is 200 μm away from the ends of the plurality of connection pads 3 for connecting electronic components. Using the photomask 5, contact exposure was performed with an exposure amount of 200 mJ / cm 2 .
<工程(C2)>
 第二面の第一ソルダーレジスト層2-1に対して、外部接続用接続パッド4上に直径500μmの円形開口部領域を設けるべく、円形開口部領域以外に活性光線6が照射されるようなパターンのフォトマスク5を用いて、露光量200mJ/cmで密着露光を行った。
<Process (C2)>
In order to provide a circular opening area having a diameter of 500 μm on the external connection pad 4 with respect to the first solder resist layer 2-1 on the second surface, the actinic ray 6 is irradiated in a region other than the circular opening area. Using the photomask 5 having a pattern, contact exposure was performed at an exposure amount of 200 mJ / cm 2 .
<工程(B)>
 第一面及び第二面の第一ソルダーレジスト層2-1上の支持層フィルムを剥離した後、10質量%のメタケイ酸ナトリウム水溶液(液温25℃)を薄膜化処理液として用いて、第一面を上にして薄膜化処理液に回路基板1を25秒間浸漬させてミセル化処理(薄膜化処理)を行った。その後、ミセル除去液(液温25℃)のスプレーによるミセル除去処理、水洗処理(液温25℃)及び乾燥処理を行い、第一面の非露光部の第一ソルダーレジスト層2-1の厚さが電子部品接続用接続パッド3の表面下5.0μmになるまで、平均10μmの第一ソルダーレジスト層2-1を薄膜化した。光学顕微鏡で観察したところ、第一面の第一ソルダーレジスト層2-1の表面に処理ムラはなく、良好な面内均一性が得られた。一方、第二面の第一ソルダーレジスト層2-1も平均10μm薄膜化されていたが、薄膜化処理液中の気泡が第二面の非露光部の第一ソルダーレジスト層2-1に付着し、膜厚不均一となっている箇所があった。また、外部接続用接続パッド4には約13μmの第一ソルダーレジスト層2-1の残渣が残っていた。
<Process (B)>
After peeling off the support layer film on the first solder resist layer 2-1 on the first surface and the second surface, a 10% by mass sodium metasilicate aqueous solution (liquid temperature 25 ° C.) was used as the thinning treatment solution. The circuit board 1 was immersed for 25 seconds in a thinning solution with one side facing up to perform micellization (thinning). Thereafter, the micelle removal treatment by spraying the micelle removal liquid (liquid temperature 25 ° C.), the water washing treatment (liquid temperature 25 ° C.) and the drying treatment are performed, and the thickness of the first solder resist layer 2-1 in the non-exposed portion of the first surface The first solder resist layer 2-1 having an average of 10 μm was thinned until the thickness became 5.0 μm below the surface of the connection pad 3 for connecting electronic parts. When observed with an optical microscope, the surface of the first solder resist layer 2-1 on the first surface was not uneven and good in-plane uniformity was obtained. On the other hand, the first solder resist layer 2-1 on the second surface was also thinned by an average of 10 μm, but bubbles in the thinning treatment liquid adhered to the first solder resist layer 2-1 on the non-exposed portion of the second surface. However, there was a portion where the film thickness was non-uniform. Further, the residue of the first solder resist layer 2-1 of about 13 μm remained on the connection pad 4 for external connection.
<工程(C3)>
 第一面の第一ソルダーレジスト層2-1に対して、工程(B)において薄膜化された領域に、活性光線6が照射されるようなパターンのフォトマスク5を用いて、酸素雰囲気下での非接触露光により、露光量400mJ/cmで露光を行った。
<Process (C3)>
Using a photomask 5 having a pattern in which actinic rays 6 are irradiated onto the thinned region in step (B) with respect to the first solder resist layer 2-1 on the first surface, in an oxygen atmosphere. In this non-contact exposure, exposure was performed at an exposure amount of 400 mJ / cm 2 .
<工程(D)>
 1質量%の炭酸ナトリウム水溶液(液温度30℃、スプレー圧0.15MPa)を用いて30秒間現像を行い、第二面の非露光部の第一ソルダーレジスト層2-1を除去した。
<Process (D)>
Development was performed for 30 seconds using a 1% by mass aqueous sodium carbonate solution (liquid temperature 30 ° C., spray pressure 0.15 MPa) to remove the first solder resist layer 2-1 in the non-exposed area on the second surface.
<工程(A2)>
 真空ラミネータを用いて、厚さ15μmのソルダーレジストフィルム(太陽インキ製造(株)製、商品名:PFR-800 AUS410)を、工程(D)まで完了した回路基板1の第一面の第一ソルダーレジスト層2-1上に、真空熱圧着させた(ラミネート温度75℃、吸引時間30秒、加圧時間10秒)。これにより、第一面の第二ソルダーレジスト層2-2が形成された。第一面の第二ソルダーレジスト層2-2では、絶縁層8表面からの厚さが30μmであった。
<Process (A2)>
The first solder on the first surface of the circuit board 1 that has been processed up to the step (D) by using a vacuum laminator to complete a solder resist film having a thickness of 15 μm (trade name: PFR-800 AUS410, manufactured by Taiyo Ink Manufacturing Co., Ltd.) A vacuum thermocompression bonding was performed on the resist layer 2-1 (lamination temperature 75 ° C., suction time 30 seconds, pressurization time 10 seconds). As a result, the second solder resist layer 2-2 on the first surface was formed. In the second solder resist layer 2-2 on the first surface, the thickness from the surface of the insulating layer 8 was 30 μm.
<工程(C6)>
 第一面の第二ソルダーレジスト層2-2に対して、電子部品接続用接続パッド3の端部から400μm離れた外周よりも外側の領域に、活性光線6が照射されるようなパターンのフォトマスク5を用いて、露光量200mJ/cmで密着露光を行った。
<Process (C6)>
A photo of a pattern in which the active light beam 6 is irradiated to a region outside the outer periphery 400 μm away from the end of the connection pad 3 for connecting the electronic component to the second solder resist layer 2-2 on the first surface. Using mask 5, contact exposure was performed at an exposure amount of 200 mJ / cm 2 .
<工程(D2)>
 1質量%の炭酸ナトリウム水溶液(液温度30℃、スプレー圧0.15MPa)を用いて30秒間現像を行い、第一面の非露光部の第二ソルダーレジスト層2-2を除去した。これによって、アンダーフィル堰き止め用ダムを形成するとともに、第二ソルダーレジスト層2-2によって覆われていた第一ソルダーレジスト層2-1から露出した状態の電子部品接続用接続パッド3とその周囲の第一ソルダーレジスト層2-1が再び露出した。光学顕微鏡で観察した結果、第一面及び第二面ともに電子部品接続用接続パッド3及び外部接続用接続パッド4上に第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2の残渣は見られなかった。また、第一面に配置された電子部品接続用接続パッド3の表面下5.5μmまで第一ソルダーレジスト層2-1が充填されていた。工程(C3)における酸素雰囲気下での非接触露光により、第一面に配置された電子部品接続用接続パッド3間の第一ソルダーレジスト層2-1表面の光重合が抑制され、結果として、第一面の第一ソルダーレジスト層2-1の厚さが0.5μm減少していた。
<Process (D2)>
Development was performed for 30 seconds using a 1% by mass aqueous sodium carbonate solution (liquid temperature 30 ° C., spray pressure 0.15 MPa) to remove the second solder resist layer 2-2 in the non-exposed area on the first surface. As a result, an underfill dam is formed, and the electronic component connecting connection pad 3 exposed from the first solder resist layer 2-1 covered with the second solder resist layer 2-2 and its surroundings are formed. The first solder resist layer 2-1 was exposed again. As a result of observation with an optical microscope, residues of the first solder resist layer 2-1 and the second solder resist layer 2-2 on the connection pads 3 for electronic component connection and the connection pads 4 for external connection on both the first surface and the second surface Was not seen. Further, the first solder resist layer 2-1 was filled up to 5.5 μm below the surface of the connection pad 3 for connecting electronic parts arranged on the first surface. By non-contact exposure in an oxygen atmosphere in the step (C3), photopolymerization of the surface of the first solder resist layer 2-1 between the connection pads 3 for connecting electronic components arranged on the first surface is suppressed, and as a result, The thickness of the first solder resist layer 2-1 on the first surface was reduced by 0.5 μm.
 次に、第一面の第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2並びに第二面の第一ソルダーレジスト層2-1を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施して、配線基板を得た。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmと20μmの第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2によって被覆され、その段差に相当する厚さ10μmのアンダーフィル堰き止め用ダムが形成されていた。また、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ9.5μmの第一ソルダーレジスト層2-1が充填されていた。また、第二面では、厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmの第一ソルダーレジスト層2-1の円形開口部が形成されていて、外部接続用接続パッド4の一部が露出していた。 Next, in order to cure the first solder resist layer 2-1 and the second solder resist layer 2-2 on the first surface and the first solder resist layer 2-1 on the second surface, the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 . The substrate was exposed and subsequently subjected to thermosetting at 150 ° C. for 60 minutes to obtain a wiring board. As a result of observation with an optical microscope, on the first surface, the conductor wiring 7 with a thickness of 15 μm is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 with a thickness of 30 μm and 20 μm, and the step is A corresponding underfill dam with a thickness of 10 μm was formed. Further, the electronic component connecting connection pads 3 having a thickness of 15 μm were exposed, and the first solder resist layer 2-1 having a thickness of 9.5 μm was filled between the adjacent electronic component connecting connection pads 3. On the second surface, a circular opening of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm is formed on a part of the connection pad 4 for external connection having a thickness of 15 μm. A part of the connection pad 4 was exposed.
 次に、第一面に配置された複数の電子部品接続用接続パッド3の端部から200μm離れた外周と該端部から400μm離れた外周との間の領域にある厚さ20μmの第一ソルダーレジスト層2-1の表面粗さを測定したところ、表面粗さRaは0.05μmであった。また、隣接する電子部品接続用接続パッド3間の領域の第一ソルダーレジスト層2-1の表面粗さを測定したところ、表面粗さRaは0.40μmであった。 Next, a first solder having a thickness of 20 μm in a region between the outer periphery 200 μm away from the end of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 μm away from the end When the surface roughness of the resist layer 2-1 was measured, the surface roughness Ra was 0.05 μm. Further, when the surface roughness of the first solder resist layer 2-1 in the region between adjacent electronic component connection pads 3 was measured, the surface roughness Ra was 0.40 μm.
(実施例18)
 工程(C1)と工程(C2)の順番を入れ替えた以外は実施例17と同じ方法で、工程(A1)~工程(D2)までを実施した。光学顕微鏡で観察した結果、第一面及び第二面ともに電子部品接続用接続パッド3及び外部接続用接続パッド4上に第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2の残渣は見られなかった。また、第一面に配置された電子部品接続用接続パッド3の表面下5.5μmまで第一ソルダーレジスト層2-1が充填されていた。工程(C3)における酸素雰囲気下での非接触露光により、第一面に配置された電子部品接続用接続パッド3間の第一ソルダーレジスト層2-1表面の光重合が抑制され、結果として、第一面の第一ソルダーレジスト層2-1の厚さが0.5μm減少していた。
(Example 18)
The steps (A1) to (D2) were performed in the same manner as in Example 17 except that the order of the steps (C1) and (C2) was changed. As a result of observation with an optical microscope, residues of the first solder resist layer 2-1 and the second solder resist layer 2-2 on the connection pads 3 for electronic component connection and the connection pads 4 for external connection on both the first surface and the second surface Was not seen. Further, the first solder resist layer 2-1 was filled up to 5.5 μm below the surface of the connection pad 3 for connecting electronic parts arranged on the first surface. By non-contact exposure in an oxygen atmosphere in the step (C3), photopolymerization of the surface of the first solder resist layer 2-1 between the connection pads 3 for connecting electronic components arranged on the first surface is suppressed, and as a result, The thickness of the first solder resist layer 2-1 on the first surface was reduced by 0.5 μm.
 次に、第一面の第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2並びに第二面の第一ソルダーレジスト層2-1を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施して、配線基板を得た。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmと20μmの第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2によって被覆され、その段差に相当する厚さ10μmのアンダーフィル堰き止め用ダムが形成されていた。また、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ9.5μmの第一ソルダーレジスト層2-1が充填されていた。また、第二面では、厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmの第一ソルダーレジスト層2-1の円形開口部が形成されていて、外部接続用接続パッド4の一部が露出していた。 Next, in order to cure the first solder resist layer 2-1 and the second solder resist layer 2-2 on the first surface and the first solder resist layer 2-1 on the second surface, the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 . The substrate was exposed and subsequently subjected to thermosetting at 150 ° C. for 60 minutes to obtain a wiring board. As a result of observation with an optical microscope, on the first surface, the conductor wiring 7 with a thickness of 15 μm is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 with a thickness of 30 μm and 20 μm, and the step is A corresponding underfill dam with a thickness of 10 μm was formed. Further, the electronic component connecting connection pads 3 having a thickness of 15 μm were exposed, and the first solder resist layer 2-1 having a thickness of 9.5 μm was filled between the adjacent electronic component connecting connection pads 3. On the second surface, a circular opening of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm is formed on a part of the connection pad 4 for external connection having a thickness of 15 μm. A part of the connection pad 4 was exposed.
 次に、第一面に配置された複数の電子部品接続用接続パッド3の端部から200μm離れた外周と該端部から400μm離れた外周との間の領域にある厚さ20μmの第一ソルダーレジスト層2-1の表面粗さを測定したところ、表面粗さRaは0.05μmであった。また、隣接する電子部品接続用接続パッド3間の領域の第一ソルダーレジスト層2-1の表面粗さを測定したところ、表面粗さRaは0.40μmであった。 Next, a first solder having a thickness of 20 μm in a region between the outer periphery 200 μm away from the end of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 μm away from the end When the surface roughness of the resist layer 2-1 was measured, the surface roughness Ra was 0.05 μm. Further, when the surface roughness of the first solder resist layer 2-1 in the region between adjacent electronic component connection pads 3 was measured, the surface roughness Ra was 0.40 μm.
(実施例19)
 工程(C3)における露光量を200mJ/cmとした以外は実施例17と同じ方法で、工程(A1)~工程(D2)までを実施した。光学顕微鏡で観察した結果、第一面及び第二面ともに電子部品接続用接続パッド3及び外部接続用接続パッド4上に第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2の残渣は見られなかった。また、第一面に配置された電子部品接続用接続パッド3の表面下6.0μmまで第一ソルダーレジスト層2-1が充填されていた。工程(C3)における酸素雰囲気下での非接触露光により、第一面に配置された電子部品接続用接続パッド3間の第一ソルダーレジスト層2-1表面の光重合が抑制され、結果として、第一面の第一ソルダーレジスト層2-1の厚さが1.0μm減少していた。
(Example 19)
Steps (A1) to (D2) were carried out in the same manner as in Example 17 except that the exposure amount in step (C3) was 200 mJ / cm 2 . As a result of observation with an optical microscope, residues of the first solder resist layer 2-1 and the second solder resist layer 2-2 on the connection pads 3 for electronic component connection and the connection pads 4 for external connection on both the first surface and the second surface Was not seen. Further, the first solder resist layer 2-1 was filled up to 6.0 μm below the surface of the connection pad 3 for connecting electronic components arranged on the first surface. By non-contact exposure in an oxygen atmosphere in the step (C3), the photopolymerization of the surface of the first solder resist layer 2-1 between the connection pads 3 for connecting electronic components arranged on the first surface is suppressed, and as a result, The thickness of the first solder resist layer 2-1 on the first surface was reduced by 1.0 μm.
 次に、第一面の第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2並びに第二面の第一ソルダーレジスト層2-1を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施して、配線基板を得た。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmと20μmの第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2によって被覆され、その段差に相当する厚さ10μmのアンダーフィル堰き止め用ダムが形成されていた。また、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ9.0μmの第一ソルダーレジスト層2-1が充填されていた。また、第二面では、厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmの第一ソルダーレジスト層2-1の円形開口部が形成されていて、外部接続用接続パッド4の一部が露出していた。 Next, in order to cure the first solder resist layer 2-1 and the second solder resist layer 2-2 on the first surface and the first solder resist layer 2-1 on the second surface, the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 . The substrate was exposed and subsequently subjected to thermosetting at 150 ° C. for 60 minutes to obtain a wiring board. As a result of observation with an optical microscope, on the first surface, the conductor wiring 7 with a thickness of 15 μm is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 with a thickness of 30 μm and 20 μm, and the step is A corresponding underfill dam with a thickness of 10 μm was formed. Further, the connection pad 3 for connecting an electronic component having a thickness of 15 μm was exposed, and the first solder resist layer 2-1 having a thickness of 9.0 μm was filled between adjacent connection pads 3 for connecting an electronic component. On the second surface, a circular opening of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm is formed on a part of the connection pad 4 for external connection having a thickness of 15 μm. A part of the connection pad 4 was exposed.
 次に、第一面に配置された複数の電子部品接続用接続パッド3の端部から200μm離れた外周と該端部から400μm離れた外周との間の領域にある厚さ20μmの第一ソルダーレジスト層2-1の表面粗さを測定したところ、表面粗さRaは0.05μmであった。また、隣接する電子部品接続用接続パッド3間の領域の第一ソルダーレジスト層2-1の表面粗さを測定したところ、表面粗さRaは0.50μmであった。 Next, a first solder having a thickness of 20 μm in a region between the outer periphery 200 μm away from the end of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 μm away from the end When the surface roughness of the resist layer 2-1 was measured, the surface roughness Ra was 0.05 μm. Further, when the surface roughness of the first solder resist layer 2-1 in the region between adjacent electronic component connection pads 3 was measured, the surface roughness Ra was 0.50 μm.
(実施例20)
 工程(C3)における露光量を1000mJ/cmとした以外は実施例17と同じ方法で、工程(A1)~工程(D2)までを実施した。光学顕微鏡で観察した結果、第一面及び第二面ともに電子部品接続用接続パッド3及び外部接続用接続パッド4上に第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2の残渣は見られなかった。また、第一面に配置された電子部品接続用接続パッド3の表面下5.0μmまで第一ソルダーレジスト層2-1が充填されており、工程(C3)における酸素の重合阻害による第一面の第一ソルダーレジスト層2-1の膜減りは確認されなかった。
(Example 20)
Steps (A1) to (D2) were carried out in the same manner as in Example 17 except that the exposure dose in step (C3) was 1000 mJ / cm 2 . As a result of observation with an optical microscope, residues of the first solder resist layer 2-1 and the second solder resist layer 2-2 on the connection pads 3 for electronic component connection and the connection pads 4 for external connection on both the first surface and the second surface Was not seen. Also, the first solder resist layer 2-1 is filled up to 5.0 μm below the surface of the connection pad 3 for connecting electronic components arranged on the first surface, and the first surface due to inhibition of oxygen polymerization in the step (C3) No film loss of the first solder resist layer 2-1 was confirmed.
 次に、第一面の第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2並びに第二面の第一ソルダーレジスト層2-1を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施して、配線基板を得た。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmと20μmの第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2によって被覆され、その段差に相当する厚さ10μmのアンダーフィル堰き止め用ダムが形成されていた。また、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ10.0μmの第一ソルダーレジスト層2-1が充填されていた。また、第二面では、厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmの第一ソルダーレジスト層2-1の円形開口部が形成されていて、外部接続用接続パッド4の一部が露出していた。 Next, in order to cure the first solder resist layer 2-1 and the second solder resist layer 2-2 on the first surface and the first solder resist layer 2-1 on the second surface, the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 . The substrate was exposed and subsequently subjected to thermosetting at 150 ° C. for 60 minutes to obtain a wiring board. As a result of observation with an optical microscope, on the first surface, the conductor wiring 7 with a thickness of 15 μm is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 with a thickness of 30 μm and 20 μm, and the step is A corresponding underfill dam with a thickness of 10 μm was formed. Further, the connection pad 3 for connecting an electronic component having a thickness of 15 μm was exposed, and the first solder resist layer 2-1 having a thickness of 10.0 μm was filled between adjacent connection pads 3 for connecting an electronic component. On the second surface, a circular opening of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm is formed on a part of the connection pad 4 for external connection having a thickness of 15 μm. A part of the connection pad 4 was exposed.
 次に、第一面に配置された複数の電子部品接続用接続パッド3の端部から200μm離れた外周と該端部から400μm離れた外周との間の領域にある厚さ20μmの第一ソルダーレジスト層2-1の表面粗さを測定したところ、表面粗さRaは0.05μmであった。また、隣接する電子部品接続用接続パッド3間の領域の第一ソルダーレジスト層2-1の表面粗さを測定したところ、表面粗さRaは0.30μmであった。 Next, a first solder having a thickness of 20 μm in a region between the outer periphery 200 μm away from the end of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 μm away from the end When the surface roughness of the resist layer 2-1 was measured, the surface roughness Ra was 0.05 μm. Further, when the surface roughness of the first solder resist layer 2-1 in the region between the adjacent electronic component connection pads 3 was measured, the surface roughness Ra was 0.30 μm.
(実施例21)
 工程(C3)において、密着露光方式にて露光を行った以外は、実施例17と同じ方法で、工程(A1)~工程(D2)までを実施した。光学顕微鏡で観察した結果、第一面及び第二面ともに電子部品接続用接続パッド3及び外部接続用接続パッド4上に第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2の残渣は見られなかった。また、第一面に配置された電子部品接続用接続パッド3の表面下5.0μmまで第一ソルダーレジスト層2-1が充填されていた。工程(C3)において、密着露光時のエア抜きを十分行うことにより、非酸素雰囲気下で露光を行ったため、第一ソルダーレジスト層2-1表面が粗面化せず、結果として、第一ソルダーレジスト層2-1の厚さは減少しなかった。
(Example 21)
Step (A1) to Step (D2) were carried out in the same manner as in Example 17 except that the exposure in the contact exposure method was performed in Step (C3). As a result of observation with an optical microscope, residues of the first solder resist layer 2-1 and the second solder resist layer 2-2 on the connection pads 3 for electronic component connection and the connection pads 4 for external connection on both the first surface and the second surface Was not seen. Further, the first solder resist layer 2-1 was filled up to 5.0 μm below the surface of the connection pad 3 for connecting electronic parts arranged on the first surface. In step (C3), the surface of the first solder resist layer 2-1 was not roughened because the exposure was performed in a non-oxygen atmosphere by sufficiently releasing the air during contact exposure. As a result, the first solder resist layer 2-1 was not roughened. The thickness of the resist layer 2-1 did not decrease.
 次に、第一面の第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2並びに第二面の第一ソルダーレジスト層2-1を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施した。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmと20μmの第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2によって被覆され、その段差に相当する厚さ10μmのアンダーフィル堰き止め用ダムが形成されていた。また、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ10.0μmの第一ソルダーレジスト層2-1が充填されていた。また、第二面では、厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmの第一ソルダーレジスト層2-1の円形開口部が形成されていて、外部接続用接続パッド4の一部が露出していた。 Next, in order to cure the first solder resist layer 2-1 and the second solder resist layer 2-2 on the first surface and the first solder resist layer 2-1 on the second surface, the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 . The exposure was followed by a thermosetting treatment at 150 ° C. for 60 minutes. As a result of observation with an optical microscope, on the first surface, the conductor wiring 7 with a thickness of 15 μm is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 with a thickness of 30 μm and 20 μm, and the step is A corresponding underfill dam with a thickness of 10 μm was formed. Further, the connection pad 3 for connecting an electronic component having a thickness of 15 μm was exposed, and the first solder resist layer 2-1 having a thickness of 10.0 μm was filled between adjacent connection pads 3 for connecting an electronic component. On the second surface, a circular opening of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm is formed on a part of the connection pad 4 for external connection having a thickness of 15 μm. A part of the connection pad 4 was exposed.
 次に、第一面に配置された複数の電子部品接続用接続パッド3の端部から200μm離れた外周と該端部から400μm離れた外周との間の領域にある厚さ20μmの第一ソルダーレジスト層2-1の表面粗さを測定したところ、表面粗さRaは0.05μmであった。また、隣接する電子部品接続用接続パッド3間の第一ソルダーレジスト層2-2の表面粗さを測定したところ、表面粗さRaは0.10μmであった。 Next, a first solder having a thickness of 20 μm in a region between the outer periphery 200 μm away from the end of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 μm away from the end When the surface roughness of the resist layer 2-1 was measured, the surface roughness Ra was 0.05 μm. Further, when the surface roughness of the first solder resist layer 2-2 between the adjacent connection pads 3 for connecting electronic components was measured, the surface roughness Ra was 0.10 μm.
 実施例17~21では、隣接する電子部品接続用接続パッド3間に十分な厚さの第一ソルダーレジスト層2-1があるため、電子部品を実装する際に半田による電気的な短絡が起きるのを確実に防ぐことができた。外部接続用接続パッド4上に第一ソルダーレジスト層2-1の残渣が存在しないため、外部電気基板に実装する際にも電気的絶縁不良が発生しない信頼性の高い配線基板を作製することができた。実施例17~21を比較すると、電子部品接続用接続パッド3間の第一ソルダーレジスト層2-1の表面が平滑である実施例21で製造された配線基板よりも、実施例17~20で製造された配線基板の方が、アンダーフィルとの密着性が高く、接続信頼性が優れていた。 In Examples 17 to 21, since the first solder resist layer 2-1 having a sufficient thickness is provided between adjacent connection pads 3 for connecting electronic components, an electrical short circuit due to solder occurs when the electronic components are mounted. It was possible to prevent this reliably. Since there is no residue of the first solder resist layer 2-1 on the connection pad 4 for external connection, it is possible to manufacture a highly reliable wiring board that does not cause an electrical insulation failure even when mounted on the external electric board. did it. Comparing Examples 17 to 21, in Examples 17 to 20, the surface of the first solder resist layer 2-1 between the connection pads 3 for connecting electronic components is smoother than the wiring board manufactured in Example 21. The manufactured wiring board had higher adhesion to the underfill and better connection reliability.
 実施例22~25は、図8-1、図8-2および図8-3に示した配線基板の製造方法(5)に関する例である。 Examples 22 to 25 are examples relating to the manufacturing method (5) of the wiring board shown in FIGS. 8-1, FIG. 8-2, and FIG. 8-3.
(実施例22)
<工程(A1)>
 セミアディティブ法を用いて、両表面に導体配線7が形成された回路基板1(面積170mm×200mm、導体厚さ15μm、基板厚さ0.4mm)を作製した。表面(第一面)には電子部品接続用接続パッド3として使用される線幅25μm、間隔50μmの導体配線がある。裏面(第二面)には外部接続用接続パッド4として使用される直径600μmの円形状の導体配線が形成されている。次に、真空ラミネータを用いて、厚さ15μmのソルダーレジストフィルム(太陽インキ製造(株)製、商品名:PFR-800 AUS410)を上記回路基板1の表面に、厚さ25μmのソルダーレジストフィルム(太陽インキ製造(株)製、商品名:PFR-800 AUS410)を上記回路基板1の裏面に真空熱圧着させた(ラミネート温度75℃、吸引時間30秒、加圧時間10秒)。これにより、第一ソルダーレジスト層2-1が形成された。第一面の第一ソルダーレジスト層2-1では、絶縁層8表面からの厚さが20μmであり、電子部品接続用接続パッド3上の厚さは5μmであった。第二面の第一ソルダーレジスト層2-1では、絶縁層8表面からの厚さが38μmであり、外部接続用接続パッド4上の厚さが23μmであった。
(Example 22)
<Process (A1)>
Using a semi-additive method, a circuit board 1 (area 170 mm × 200 mm, conductor thickness 15 μm, board thickness 0.4 mm) having conductor wirings 7 formed on both surfaces was produced. On the surface (first surface), there is a conductor wiring having a line width of 25 μm and an interval of 50 μm used as the connection pad 3 for connecting electronic components. A circular conductor wiring having a diameter of 600 μm used as the external connection pad 4 is formed on the back surface (second surface). Next, using a vacuum laminator, a 15 μm thick solder resist film (manufactured by Taiyo Ink Manufacturing Co., Ltd., trade name: PFR-800 AUS410) is applied to the surface of the circuit board 1 and a 25 μm thick solder resist film ( Taiyo Ink Mfg. Co., Ltd., trade name: PFR-800 AUS410) was vacuum thermocompression bonded to the back surface of the circuit board 1 (lamination temperature 75 ° C., suction time 30 seconds, pressurization time 10 seconds). Thereby, the first solder resist layer 2-1 was formed. In the first solder resist layer 2-1 on the first surface, the thickness from the surface of the insulating layer 8 was 20 μm, and the thickness on the connection pad 3 for connecting electronic components was 5 μm. In the first solder resist layer 2-1 on the second surface, the thickness from the surface of the insulating layer 8 was 38 μm, and the thickness on the connection pad 4 for external connection was 23 μm.
<工程(C2)>
 第二面の第一ソルダーレジスト層2-1に対して、外部接続用接続パッド4上に直径500μmの円形開口部領域を設けるべく、円形開口部領域以外に活性光線6が照射されるようなパターンのフォトマスク5を用いて、露光量200mJ/cmで密着露光を行った。
<Process (C2)>
In order to provide a circular opening area having a diameter of 500 μm on the external connection pad 4 with respect to the first solder resist layer 2-1 on the second surface, the actinic ray 6 is irradiated in a region other than the circular opening area. Using the photomask 5 having a pattern, contact exposure was performed at an exposure amount of 200 mJ / cm 2 .
<工程(B)>
 第一面及び第二面の第一ソルダーレジスト層2-1上の支持層フィルムを剥離した後、10質量%のメタケイ酸ナトリウム水溶液(液温25℃)を薄膜化処理液として用いて、第一面を上にして薄膜化処理液に回路基板1を25秒間浸漬させてミセル化処理(薄膜化処理)を行った。その後、ミセル除去液(液温25℃)のスプレーによるミセル除去処理、水洗処理(液温25℃)及び乾燥処理を行い、第一面の非露光部の第一ソルダーレジスト層2-1の厚さが電子部品接続用接続パッド3の表面下5.0μmになるまで、平均10μmの第一ソルダーレジスト層2-1を薄膜化した。光学顕微鏡で観察したところ、第一面の第一ソルダーレジスト層2-1の表面に処理ムラはなく、良好な面内均一性が得られた。一方、第二面の第一ソルダーレジスト層2-1も平均10μm薄膜化されていたが、薄膜化処理液中の気泡が第二面の非露光部の第一ソルダーレジスト層2-1に付着し、膜厚不均一となっている箇所があった。また、外部接続用接続パッド4には約13μmの第一ソルダーレジスト層2-1の残渣が残っていた。
<Process (B)>
After peeling off the support layer film on the first solder resist layer 2-1 on the first surface and the second surface, a 10% by mass sodium metasilicate aqueous solution (liquid temperature 25 ° C.) was used as the thinning treatment solution. The circuit board 1 was immersed for 25 seconds in a thinning solution with one side facing up to perform micellization (thinning). Thereafter, the micelle removal treatment by spraying the micelle removal liquid (liquid temperature 25 ° C.), the water washing treatment (liquid temperature 25 ° C.) and the drying treatment are performed, and the thickness of the first solder resist layer 2-1 in the non-exposed portion of the first surface The first solder resist layer 2-1 having an average of 10 μm was thinned until the thickness became 5.0 μm below the surface of the connection pad 3 for connecting electronic parts. When observed with an optical microscope, the surface of the first solder resist layer 2-1 on the first surface was not uneven and good in-plane uniformity was obtained. On the other hand, the first solder resist layer 2-1 on the second surface was also thinned by an average of 10 μm, but bubbles in the thinning treatment liquid adhered to the first solder resist layer 2-1 on the non-exposed portion of the second surface. However, there was a portion where the film thickness was non-uniform. Further, the residue of the first solder resist layer 2-1 of about 13 μm remained on the connection pad 4 for external connection.
<工程(C3)>
 第一面の第一ソルダーレジスト層2-1に対して、工程(B)において薄膜化された領域に、活性光線6が照射されるようなパターンのフォトマスク5を用いて、酸素雰囲気下での非接触露光により、露光量400mJ/cmで露光を行った。
<Process (C3)>
Using a photomask 5 having a pattern in which actinic rays 6 are irradiated onto the thinned region in step (B) with respect to the first solder resist layer 2-1 on the first surface, in an oxygen atmosphere. In this non-contact exposure, exposure was performed at an exposure amount of 400 mJ / cm 2 .
<工程(A2)>
 真空ラミネータを用いて、厚さ20μmのソルダーレジストフィルム(太陽インキ製造(株)製、商品名:PFR-800 AUS410)を、工程(C)まで完了した回路基板1の第一面の第一ソルダーレジスト層2-1上に、真空熱圧着させた(ラミネート温度75℃、吸引時間30秒、加圧時間10秒)。これにより、第一面の第二ソルダーレジスト層2-2が形成された。第一面の第二ソルダーレジスト層2-2では、絶縁層8表面からの厚さが30μmであった。
<Process (A2)>
The first solder on the first surface of the circuit board 1 that has completed the process up to step (C) using a vacuum laminator to complete a 20 μm thick solder resist film (manufactured by Taiyo Ink Manufacturing Co., Ltd., product name: PFR-800 AUS410). A vacuum thermocompression bonding was performed on the resist layer 2-1 (lamination temperature 75 ° C., suction time 30 seconds, pressurization time 10 seconds). As a result, the second solder resist layer 2-2 on the first surface was formed. In the second solder resist layer 2-2 on the first surface, the thickness from the surface of the insulating layer 8 was 30 μm.
<工程(C6)>
 第一面の第二ソルダーレジスト層2-2に対して、電子部品接続用接続パッド3の端部から400μm離れた外周よりも外側の領域に、活性光線6が照射されるようなパターンのフォトマスク5を用いて、露光量200mJ/cmで密着露光を行った。
<Process (C6)>
A photo of a pattern in which the active light beam 6 is irradiated to a region outside the outer periphery 400 μm away from the end of the connection pad 3 for connecting the electronic component to the second solder resist layer 2-2 on the first surface. Using mask 5, contact exposure was performed at an exposure amount of 200 mJ / cm 2 .
<工程(B3)>
 第一面の第二ソルダーレジスト層2-2上の支持層フィルムを剥離した後、10質量%のメタケイ酸ナトリウム水溶液(液温25℃)を薄膜化処理液として用いて、第一面を上にして薄膜化処理液に回路基板1を25秒間浸漬させてミセル化処理(薄膜化処理)を行った。その後、ミセル除去液(液温25℃)のスプレーによるミセル除去処理、水洗処理(液温25℃)及び乾燥処理を行い、第一面の非露光部の第二ソルダーレジスト層2-2の厚さが電子部品接続用接続パッド3の表面上5.0μmになるまで、平均10μmの第二ソルダーレジスト層2-2を薄膜化した。光学顕微鏡で観察したところ、第一面の第二ソルダーレジスト層2-2の表面に処理ムラはなく、良好な面内均一性が得られた。一方、第二面の第一ソルダーレジスト層2-1も平均10μm薄膜化されていたが、薄膜化処理液中の気泡が第二面の非露光部の第一ソルダーレジスト層2-1に付着し、膜厚不均一となっている箇所があった。また、外部接続用接続パッド4には約3μmの第一ソルダーレジスト層2-1の残渣が残っていた。
<Process (B3)>
After peeling off the support layer film on the second solder resist layer 2-2 on the first surface, 10% by mass sodium metasilicate aqueous solution (liquid temperature 25 ° C.) was used as the thinning treatment solution, and the first surface was Then, the circuit board 1 was immersed in the thinning treatment solution for 25 seconds to perform micellization treatment (thinning treatment). Thereafter, the micelle removal treatment by spraying the micelle removal solution (liquid temperature 25 ° C.), the water washing treatment (liquid temperature 25 ° C.) and the drying treatment are performed, and the thickness of the second solder resist layer 2-2 in the non-exposed portion of the first surface The second solder resist layer 2-2 having an average thickness of 10 μm was thinned until the thickness became 5.0 μm on the surface of the connection pad 3 for connecting electronic components. When observed with an optical microscope, the surface of the second solder resist layer 2-2 on the first surface was not uneven and good in-plane uniformity was obtained. On the other hand, the first solder resist layer 2-1 on the second surface was also thinned by an average of 10 μm, but bubbles in the thinning treatment liquid adhered to the first solder resist layer 2-1 on the non-exposed portion of the second surface. However, there was a portion where the film thickness was non-uniform. Further, the residue of the first solder resist layer 2-1 of about 3 μm remained on the connection pad 4 for external connection.
<工程(C7)>
 第一面の第二ソルダーレジスト層2-2に対して、電子部品接続用接続パッド3の端部から200μm離れた外周よりも外側の領域に、活性光線6が照射されるようなパターンのフォトマスク5を用いて、酸素雰囲気下での非接触露光により、露光量400mJ/cmで露光を行った。
<Process (C7)>
A photo of a pattern in which the active light beam 6 is irradiated to a region outside the outer periphery 200 μm away from the end of the connection pad 3 for connecting the electronic component to the second solder resist layer 2-2 on the first surface The mask 5 was used for exposure at an exposure amount of 400 mJ / cm 2 by non-contact exposure in an oxygen atmosphere.
<工程(D1)>
 1質量%の炭酸ナトリウム水溶液(液温度30℃、スプレー圧0.15MPa)を用いて30秒間現像を行い、第一面の非露光部の第二ソルダーレジスト層2-2及び第二面の非露光部の第一ソルダーレジスト層2-1を除去した。これによって、アンダーフィル堰き止め用ダムを形成するとともに、第二ソルダーレジスト層2-2によって覆われていた第一ソルダーレジスト層2-1から露出した状態の電子部品接続用接続パッド3とその周囲の第一ソルダーレジスト層2-1が再び露出した。光学顕微鏡で観察した結果、第一面及び第二面ともに電子部品接続用接続パッド3及び外部接続用接続パッド4上に第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2の残渣は見られなかった。また、第一面に配置された電子部品接続用接続パッド3の表面下5.5μmまで第一ソルダーレジスト層2-1が充填されていた。工程(C3)における酸素雰囲気下での非接触露光により、第一面に配置された電子部品接続用接続パッド3間の第一ソルダーレジスト層2-1表面の光重合が抑制され、結果として、第一面の第一ソルダーレジスト層2-1の厚さが0.5μm減少していた。また、工程(C7)における酸素雰囲気下での非接触露光により、第一面に配置された複数の電子部品接続用接続パッド3の端部から200μm離れた外周と該端部から400μm離れた外周との間の領域にある厚さ20μmの第二ソルダーレジスト層2-2の表面の光重合が抑制され、結果として、厚さ20μmの第二ソルダーレジスト層2-2の表面の厚さが0.5μm減少していた。
<Process (D1)>
Development is performed for 30 seconds using a 1% by mass aqueous sodium carbonate solution (liquid temperature 30 ° C., spray pressure 0.15 MPa), and the second solder resist layer 2-2 in the non-exposed area on the first surface and the non-exposed surface on the second surface The first solder resist layer 2-1 in the exposed area was removed. As a result, an underfill dam is formed, and the electronic component connecting connection pad 3 exposed from the first solder resist layer 2-1 covered with the second solder resist layer 2-2 and its surroundings are formed. The first solder resist layer 2-1 was exposed again. As a result of observation with an optical microscope, residues of the first solder resist layer 2-1 and the second solder resist layer 2-2 on the connection pads 3 for electronic component connection and the connection pads 4 for external connection on both the first surface and the second surface Was not seen. Further, the first solder resist layer 2-1 was filled up to 5.5 μm below the surface of the connection pad 3 for connecting electronic parts arranged on the first surface. By non-contact exposure in an oxygen atmosphere in the step (C3), photopolymerization of the surface of the first solder resist layer 2-1 between the connection pads 3 for connecting electronic components arranged on the first surface is suppressed, and as a result, The thickness of the first solder resist layer 2-1 on the first surface was reduced by 0.5 μm. Further, by non-contact exposure in an oxygen atmosphere in the step (C7), the outer periphery separated from the ends of the plurality of connection pads 3 for connecting electronic components arranged on the first surface by 200 μm and the outer periphery separated from the ends by 400 μm The photopolymerization of the surface of the second solder resist layer 2-2 having a thickness of 20 μm in the region between the second solder resist layer 2-2 is suppressed, and as a result, the thickness of the surface of the second solder resist layer 2-2 having a thickness of 20 μm is reduced to 0. It was reduced by 5 μm.
 次に、第一面の第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2並びに第二面の第一ソルダーレジスト層2-1を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施して、配線基板を得た。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmと19.5μmの第二ソルダーレジスト層2-2によって被覆され、その段差に相当する厚さ10.5μmのアンダーフィル堰き止め用ダムが形成されていた。また、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ9.5μmの第一ソルダーレジスト層2-1が充填されていた。また、第二面では、厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmの第一ソルダーレジスト層2-1の円形開口部が形成されていて、外部接続用接続パッド4の一部が露出していた。 Next, in order to cure the first solder resist layer 2-1 and the second solder resist layer 2-2 on the first surface and the first solder resist layer 2-1 on the second surface, the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 . The substrate was exposed and subsequently subjected to thermosetting at 150 ° C. for 60 minutes to obtain a wiring board. As a result of observation with an optical microscope, on the first surface, the conductor wiring 7 having a thickness of 15 μm is covered with the second solder resist layer 2-2 having a thickness of 30 μm and 19.5 μm, and the thickness corresponding to the step is 10.5 μm. An underfill weir dam was formed. Further, the electronic component connecting connection pads 3 having a thickness of 15 μm were exposed, and the first solder resist layer 2-1 having a thickness of 9.5 μm was filled between the adjacent electronic component connecting connection pads 3. On the second surface, a circular opening of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm is formed on a part of the connection pad 4 for external connection having a thickness of 15 μm. A part of the connection pad 4 was exposed.
 次に、第一面に配置された複数の電子部品接続用接続パッド3の端部から200μm離れた外周と該端部から400μm離れた外周との間の領域にある厚さ19.5μmの第二ソルダーレジスト層2-2の表面粗さを測定したところ、表面粗さRaは0.40μmであった。また、隣接する電子部品接続用接続パッド3間の領域の第一ソルダーレジスト層2-1の表面粗さを測定したところ、表面粗さRaは0.40μmであった。 Next, a 19.5 μm-thick first electrode in a region between the outer periphery 200 μm away from the ends of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 μm away from the ends. When the surface roughness of the two solder resist layer 2-2 was measured, the surface roughness Ra was 0.40 μm. Further, when the surface roughness of the first solder resist layer 2-1 in the region between adjacent electronic component connection pads 3 was measured, the surface roughness Ra was 0.40 μm.
(実施例23)
 工程(C3)及び(C7)における露光量を200mJ/cmとした以外は実施例22と同じ方法で、工程(A1)~工程(D1)までを実施した。光学顕微鏡で観察した結果、第一面及び第二面ともに電子部品接続用接続パッド3及び外部接続用接続パッド4上に第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2の残渣は見られなかった。また、第一面に配置された電子部品接続用接続パッド3の表面下6.0μmまで第一ソルダーレジスト層2-1が充填されていた。工程(C3)における酸素雰囲気下での非接触露光により、第一面に配置された電子部品接続用接続パッド3間の第一ソルダーレジスト層2-1表面の光重合が抑制され、結果として、第一面の第一ソルダーレジスト層2-1の厚さが1.0μm減少していた。また、工程(C7)における酸素雰囲気下での非接触露光により、第一面に配置された複数の電子部品接続用接続パッド3の端部から200μm離れた外周と該端部から400μm離れた外周との間の領域にある厚さ20μmの第二ソルダーレジスト層2-2の表面の光重合が抑制され、結果として、厚さ20μmの第二ソルダーレジスト層2-2の表面の厚さが1.0μm減少していた。
(Example 23)
Steps (A1) to (D1) were performed in the same manner as in Example 22 except that the exposure dose in steps (C3) and (C7) was 200 mJ / cm 2 . As a result of observation with an optical microscope, residues of the first solder resist layer 2-1 and the second solder resist layer 2-2 on the connection pads 3 for electronic component connection and the connection pads 4 for external connection on both the first surface and the second surface Was not seen. Further, the first solder resist layer 2-1 was filled up to 6.0 μm below the surface of the connection pad 3 for connecting electronic components arranged on the first surface. By non-contact exposure in an oxygen atmosphere in the step (C3), the photopolymerization of the surface of the first solder resist layer 2-1 between the connection pads 3 for connecting electronic components arranged on the first surface is suppressed, and as a result, The thickness of the first solder resist layer 2-1 on the first surface was reduced by 1.0 μm. Further, by non-contact exposure in an oxygen atmosphere in the step (C7), the outer periphery separated from the ends of the plurality of connection pads 3 for connecting electronic components arranged on the first surface by 200 μm and the outer periphery separated from the ends by 400 μm The photopolymerization of the surface of the second solder resist layer 2-2 having a thickness of 20 μm in the region between the first and second layers is suppressed. As a result, the thickness of the surface of the second solder resist layer 2-2 having a thickness of 20 μm is reduced to 1. It was reduced by 0.0 μm.
 次に、第一面のソルダーレジスト層2-1及び2-2、第二面の第一ソルダーレジスト層2-1を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施して、配線基板を得た。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmと19μmの第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2によって被覆され、その段差に相当する厚さ11μmのアンダーフィル堰き止め用ダムが形成されていた。また、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ9.0μmの第一ソルダーレジスト層2-1が充填されていた。また、第二面では、厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmの第一ソルダーレジスト層2-1の円形開口部が形成されていて、外部接続用接続パッド4の一部が露出していた。 Next, in order to cure the solder resist layers 2-1 and 2-2 on the first surface and the first solder resist layer 2-1 on the second surface, the entire surface is exposed with an exposure amount of 1000 mJ / cm 2 , and subsequently 150 A wiring board was obtained by performing a thermosetting treatment at 60 ° C. for 60 minutes. As a result of observation with an optical microscope, on the first surface, the conductor wiring 7 having a thickness of 15 μm is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 having a thickness of 30 μm and 19 μm, and the step is A corresponding underfill weir dam with a thickness of 11 μm was formed. Further, the connection pad 3 for connecting an electronic component having a thickness of 15 μm was exposed, and the first solder resist layer 2-1 having a thickness of 9.0 μm was filled between adjacent connection pads 3 for connecting an electronic component. On the second surface, a circular opening of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm is formed on a part of the connection pad 4 for external connection having a thickness of 15 μm. A part of the connection pad 4 was exposed.
 次に、第一面に配置された複数の電子部品接続用接続パッド3の端部から200μm離れた外周と該端部から400μm離れた外周との間の領域にある厚さ19μmの第二ソルダーレジスト層2-2の表面粗さを測定したところ、表面粗さRaは0.50μmであった。また、隣接する電子部品接続用接続パッド3間の領域の第一ソルダーレジスト層2-1の表面粗さを測定したところ、表面粗さRaは0.50μmであった。 Next, a second solder having a thickness of 19 μm in a region between the outer periphery 200 μm away from the ends of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 μm away from the ends When the surface roughness of the resist layer 2-2 was measured, the surface roughness Ra was 0.50 μm. Further, when the surface roughness of the first solder resist layer 2-1 in the region between adjacent electronic component connection pads 3 was measured, the surface roughness Ra was 0.50 μm.
(実施例24)
 工程(C3)及び(C7)における露光量を1000mJ/cmとした以外は実施例22と同じ方法で、工程(A1)~工程(D1)までを実施した。光学顕微鏡で観察した結果、第一面及び第二面ともに電子部品接続用接続パッド3及び外部接続用接続パッド4上に第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2の残渣は見られなかった。また、第一面に配置された電子部品接続用接続パッド3の表面下5.0μmまで第一ソルダーレジスト層2-1が充填されており、工程(C3)及び(C7)における酸素の重合阻害による第一面の第一ソルダーレジスト層2-1及び第一面の第二ソルダーレジスト層2-2の膜減りは確認されなかった。
(Example 24)
Steps (A1) to (D1) were performed in the same manner as in Example 22 except that the exposure dose in steps (C3) and (C7) was 1000 mJ / cm 2 . As a result of observation with an optical microscope, residues of the first solder resist layer 2-1 and the second solder resist layer 2-2 on the connection pads 3 for electronic component connection and the connection pads 4 for external connection on both the first surface and the second surface Was not seen. Further, the first solder resist layer 2-1 is filled up to 5.0 μm below the surface of the connection pad 3 for connecting the electronic parts arranged on the first surface, and oxygen polymerization inhibition in the steps (C3) and (C7) No film loss of the first solder resist layer 2-1 on the first surface and the second solder resist layer 2-2 on the first surface due to was confirmed.
 次に、第一面の第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2並びに第二面の第一ソルダーレジスト層2-1を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施して、配線基板を得た。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmと20μmの第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2によって被覆され、その段差に相当する厚さ10μmのアンダーフィル堰き止め用ダムが形成されていた。また、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ10.0μmの第一ソルダーレジスト層2-1が充填されていた。また、第二面では、厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmの第一ソルダーレジスト層2-1の円形開口部が形成されていて、外部接続用接続パッド4の一部が露出していた。 Next, in order to cure the first solder resist layer 2-1 and the second solder resist layer 2-2 on the first surface and the first solder resist layer 2-1 on the second surface, the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 . The substrate was exposed and subsequently subjected to thermosetting at 150 ° C. for 60 minutes to obtain a wiring board. As a result of observation with an optical microscope, on the first surface, the conductor wiring 7 with a thickness of 15 μm is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 with a thickness of 30 μm and 20 μm, and the step is A corresponding underfill dam with a thickness of 10 μm was formed. Further, the connection pad 3 for connecting an electronic component having a thickness of 15 μm was exposed, and the first solder resist layer 2-1 having a thickness of 10.0 μm was filled between adjacent connection pads 3 for connecting an electronic component. On the second surface, a circular opening of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm is formed on a part of the connection pad 4 for external connection having a thickness of 15 μm. A part of the connection pad 4 was exposed.
 次に、第一面に配置された複数の電子部品接続用接続パッド3の端部から200μm離れた外周と該端部から400μm離れた外周との間の領域にある厚さ20μmの第二ソルダーレジスト層2-2の表面粗さを測定したところ、表面粗さRaは0.30μmであった。また、隣接する電子部品接続用接続パッド3間の領域の第一ソルダーレジスト層2-1の表面粗さを測定したところ、表面粗さRaは0.30μmであった。 Next, a second solder having a thickness of 20 μm in a region between the outer periphery 200 μm away from the end of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 μm away from the end When the surface roughness of the resist layer 2-2 was measured, the surface roughness Ra was 0.30 μm. Further, when the surface roughness of the first solder resist layer 2-1 in the region between the adjacent electronic component connection pads 3 was measured, the surface roughness Ra was 0.30 μm.
(実施例25)
 工程(C3)及び(C7)において、密着露光方式にて露光を行った以外は、実施例22と同じ方法で、工程(A1)~工程(D1)までを実施した。光学顕微鏡で観察した結果、第一面及び第二面ともに電子部品接続用接続パッド3及び外部接続用接続パッド4上に第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2の残渣は見られなかった。また、第一面に配置された電子部品接続用接続パッド3の表面下5.0μmまで第一ソルダーレジスト層2-1が充填されていた。工程(C3)及び(C7)において、密着露光時のエア抜きを十分行うことにより、非酸素雰囲気下で露光を行ったため、ソルダーレジスト層2表面が粗面化せず、結果として、第一面の第一ソルダーレジスト層2-1及び第一面の第二ソルダーレジスト層2-2の厚さは減少しなかった。
(Example 25)
In steps (C3) and (C7), steps (A1) to (D1) were performed in the same manner as in Example 22 except that the exposure was performed by the contact exposure method. As a result of observation with an optical microscope, residues of the first solder resist layer 2-1 and the second solder resist layer 2-2 on the connection pads 3 for electronic component connection and the connection pads 4 for external connection on both the first surface and the second surface Was not seen. Further, the first solder resist layer 2-1 was filled up to 5.0 μm below the surface of the connection pad 3 for connecting electronic parts arranged on the first surface. In the steps (C3) and (C7), the surface of the solder resist layer 2 was not roughened because the exposure was performed in a non-oxygen atmosphere by sufficiently releasing the air during contact exposure. The thicknesses of the first solder resist layer 2-1 and the second solder resist layer 2-2 on the first surface did not decrease.
 次に、第一面の第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2並びに第二面の第一ソルダーレジスト層2-1を硬化させるため、露光量1000mJ/cmで全面露光し、続いて、150℃で60分間熱硬化処理を施した。光学顕微鏡で観察した結果、第一面では、厚さ15μmの導体配線7が厚さ30μmと20μmの第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2によって被覆され、その段差に相当する厚さ10μmのアンダーフィル堰き止め用ダムが形成されていた。また、厚さ15μmの電子部品接続用接続パッド3が露出しており、隣接する電子部品接続用接続パッド3間に厚さ10μmの第一ソルダーレジスト層2-1が充填されていた。また、第二面では、厚さ15μmの外部接続用接続パッド4上の一部に、厚さ38μm、直径500μmの第一ソルダーレジスト層2-1の円形開口部が形成されていて、外部接続用接続パッド4の一部が露出していた。 Next, in order to cure the first solder resist layer 2-1 and the second solder resist layer 2-2 on the first surface and the first solder resist layer 2-1 on the second surface, the entire surface is exposed at an exposure amount of 1000 mJ / cm 2 . The exposure was followed by a thermosetting treatment at 150 ° C. for 60 minutes. As a result of observation with an optical microscope, on the first surface, the conductor wiring 7 with a thickness of 15 μm is covered with the first solder resist layer 2-1 and the second solder resist layer 2-2 with a thickness of 30 μm and 20 μm, and the step is A corresponding underfill dam with a thickness of 10 μm was formed. Further, the connection pad 3 for connecting an electronic component having a thickness of 15 μm was exposed, and the first solder resist layer 2-1 having a thickness of 10 μm was filled between the connection pads 3 for connecting an electronic component adjacent to each other. On the second surface, a circular opening of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm is formed on a part of the connection pad 4 for external connection having a thickness of 15 μm. A part of the connection pad 4 was exposed.
 次に、第一面に配置された複数の電子部品接続用接続パッド3の端部から200μm離れた外周と該端部から400μm離れた外周との間の領域にある厚さ20μmの第二ソルダーレジスト層2-2の表面粗さを測定したところ、表面粗さRaは0.10μmであった。また、隣接する電子部品接続用接続パッド3間の第一ソルダーレジスト層2-1の表面粗さを測定したところ、表面粗さRaは0.10μmであった。 Next, a second solder having a thickness of 20 μm in a region between the outer periphery 200 μm away from the end of the plurality of connection pads 3 for connecting electronic components arranged on the first surface and the outer periphery 400 μm away from the end When the surface roughness of the resist layer 2-2 was measured, the surface roughness Ra was 0.10 μm. Further, when the surface roughness of the first solder resist layer 2-1 between the adjacent connection pads 3 for connecting electronic components was measured, the surface roughness Ra was 0.10 μm.
 実施例22~25では、隣接する電子部品接続用接続パッド3間に十分な厚さの第一ソルダーレジスト層2-1があるため、電子部品を実装する際に半田による電気的な短絡が起きるのを確実に防ぐことができた。外部接続用接続パッド4上に第一ソルダーレジスト層2-1の残渣が存在しないため、外部電気基板に実装する際にも電気的絶縁不良が発生しない信頼性の高い配線基板を作製することができた。実施例22~25を比較すると、電子部品接続用接続パッド3間の第一ソルダーレジスト層2-1及び電子部品接続用接続パッド3周囲の第二ソルダーレジスト層2-2の表面が平滑である実施例25で製造された配線基板よりも、実施例22~24で製造された配線基板の方が、アンダーフィルとの密着性が高く、接続信頼性が優れていた。 In Examples 22 to 25, since the first solder resist layer 2-1 having a sufficient thickness is provided between the adjacent connection pads 3 for connecting electronic components, an electrical short circuit due to solder occurs when the electronic components are mounted. It was possible to prevent this reliably. Since there is no residue of the first solder resist layer 2-1 on the connection pad 4 for external connection, it is possible to manufacture a highly reliable wiring board that does not cause an electrical insulation failure even when mounted on the external electric board. did it. Comparing Examples 22 to 25, the surfaces of the first solder resist layer 2-1 between the electronic component connecting connection pads 3 and the second solder resist layer 2-2 around the electronic component connecting connection pads 3 are smooth. Compared to the wiring board manufactured in Example 25, the wiring boards manufactured in Examples 22 to 24 had higher adhesion to the underfill and better connection reliability.
 上記に説明したように、実施例1~6によって製造された配線基板は、第一面の電子部品接続用接続パッド3の一部がソルダーレジスト層2から露出されている。この配線基板を使用してフリップチップ接続を行った場合、電子部品接続用接続パッド3が高密度に配置された配線基板においても、隣接する電子部品接続用接続パッド3間に十分な厚さのソルダーレジスト層2があるため、電子部品を実装する際に半田による電気的な短絡が起きるのを確実に防ぐことができる。また、絶縁層8と電子部品接続用接続パッド3の接着強度及び電子部品接続用接続パッド3と半田との接着強度が大きくなり、高い接続信頼性が得られる。さらに、工程(C3)における露光が酸素雰囲気下での非接触露光方式によって行われている場合、電子部品接続用接続パッド3周囲のソルダーレジスト層2の表面が十分粗面化しているため、アンダーフィルとの密着性が良く、高い接続信頼性が得られる。また、第二面の外部接続用接続パッド4の表面上にもソルダーレジスト層2の残渣がないため、外部基板に実装する際、半田接続における電気的絶縁不良の発生がない高い接続信頼性が得られる。 As described above, in the wiring boards manufactured according to Examples 1 to 6, a part of the connection pads 3 for connecting electronic components on the first surface is exposed from the solder resist layer 2. When flip-chip connection is performed using this wiring board, even in a wiring board in which the electronic component connecting connection pads 3 are arranged at a high density, a sufficient thickness is provided between the adjacent electronic component connecting connection pads 3. Since the solder resist layer 2 is provided, it is possible to reliably prevent an electrical short circuit due to solder when the electronic component is mounted. Further, the adhesive strength between the insulating layer 8 and the connection pad 3 for connecting electronic parts and the adhesive strength between the connection pad 3 for connecting electronic parts and solder are increased, and high connection reliability is obtained. Furthermore, when the exposure in the step (C3) is performed by a non-contact exposure method in an oxygen atmosphere, the surface of the solder resist layer 2 around the connection pad 3 for connecting electronic parts is sufficiently roughened, so Good adhesion to the fill and high connection reliability. Moreover, since there is no residue of the solder resist layer 2 on the surface of the external connection pad 4 on the second surface, there is no electrical insulation failure in solder connection when mounting on an external substrate, and high connection reliability is achieved. can get.
 上記に説明したように、実施例7~26によって製造された配線基板は、電子部品接続用接続パッド3の一部がソルダーレジスト層2(第一ソルダーレジスト層2-1)から露出され、さらに、二段構造のソルダーレジスト層2(第一ソルダーレジスト層2-1及び第二ソルダーレジスト層2-2)によって形成されたアンダーフィル堰き止め用ダムを有する。この配線基板を使用してフリップチップ接続を行った場合、電子部品と配線基板との間に充填するアンダーフィルが周囲に溢れて、電気的接続信頼性に悪影響を及ぼすことを防止することができる。また、電子部品接続用接続パッド3が高密度に配置された配線基板においても、隣接する電子部品接続用接続パッド3間に十分な厚さのソルダーレジスト層2(第一ソルダーレジスト層2-1)があるため、電子部品を実装する際に半田による電気的な短絡が起きるのを確実に防ぐことができる。絶縁層8と電子部品接続用接続パッド3の接着強度及び電子部品接続用接続パッド3と半田との接着強度が大きくなり、高い接続信頼性が得られる。さらに、配線基板の製造方法(2)の工程(C4)及び(C5)、配線基板の製造方法(3)、(4)、(5)の工程(C3)、配線基板の製造方法(5)の工程(C7)における露光が酸素雰囲気下での非接触露光方式によって行われている場合には、電子部品接続用接続パッド3間や周囲のソルダーレジスト層2(第一ソルダーレジスト層2-1、第二ソルダーレジスト層2-2)表面が十分粗面化しているため、アンダーフィルとの密着性が良く、高い接続信頼性が得られる。また、第二面の外部接続用接続パッド4の表面上にも第一ソルダーレジスト層2-1の残渣がないため、外部基板に実装する際、半田接続における電気的絶縁不良の発生がない高い接続信頼性が得られる。 As described above, in the wiring boards manufactured according to Examples 7 to 26, part of the connection pads 3 for connecting electronic components is exposed from the solder resist layer 2 (first solder resist layer 2-1). And an underfill dam for preventing underfill formed by the two-stage solder resist layer 2 (the first solder resist layer 2-1 and the second solder resist layer 2-2). When flip-chip connection is performed using this wiring board, it is possible to prevent an underfill filling between the electronic component and the wiring board from overflowing around and adversely affecting electrical connection reliability. . Further, even in a wiring board in which the connection pads 3 for connecting electronic components are arranged at high density, a solder resist layer 2 (first solder resist layer 2-1) having a sufficient thickness between the adjacent connection pads 3 for connecting electronic components. Therefore, it is possible to reliably prevent an electrical short circuit due to solder when mounting an electronic component. The adhesive strength between the insulating layer 8 and the connection pad 3 for connecting electronic parts and the adhesive strength between the connection pad 3 for connecting electronic parts and solder are increased, and high connection reliability is obtained. Further, the steps (C4) and (C5) of the method (2) for manufacturing the wiring substrate, the methods (3), (4), (5) for manufacturing the wiring substrate (C3), and the method (5) for manufacturing the wiring substrate. When the exposure in the step (C7) is performed by a non-contact exposure method in an oxygen atmosphere, the solder resist layer 2 (first solder resist layer 2-1) between or around the connection pads 3 for connecting electronic components is used. Second solder resist layer 2-2) Since the surface is sufficiently roughened, adhesion to the underfill is good and high connection reliability is obtained. Further, since there is no residue of the first solder resist layer 2-1 on the surface of the external connection pad 4 on the second surface, there is no occurrence of electrical insulation failure in solder connection when mounted on the external substrate. Connection reliability can be obtained.
 本発明の配線基板の製造方法は、例えば、半導体チップや他のプリント配線板等の電子部品を接続するための複数の接続パッドを有する配線基板を製造する用途に適用できる。 The method for manufacturing a wiring board according to the present invention can be applied, for example, to an application for manufacturing a wiring board having a plurality of connection pads for connecting electronic components such as semiconductor chips and other printed wiring boards.
1 回路基板
2 ソルダーレジスト層
2-1 第一ソルダーレジスト層
2-2 第二ソルダーレジスト層
3 電子部品接続用接続パッド、第一面の接続パッド
4 外部接続用接続パッド、第二面の接続パッド
5 フォトマスク
6 活性光線
7 導体配線
8 絶縁層
1 Circuit Board 2 Solder Resist Layer 2-1 First Solder Resist Layer 2-2 Second Solder Resist Layer 3 Electronic Component Connection Pad, First Side Connection Pad 4 External Connection Connection Pad, Second Side Connection Pad 5 Photomask 6 Actinic ray 7 Conductor wiring 8 Insulating layer

Claims (16)

  1.  絶縁層と、絶縁層の表面に形成された接続パッドとを両表面に有する回路基板を有し、回路基板の両表面にソルダーレジスト層を有し、ソルダーレジスト層から接続パッドの一部が露出している配線基板の製造方法において、
    (A)絶縁層と、絶縁層の表面に形成された接続パッドとを両表面に有する回路基板の両表面に、厚さの異なるソルダーレジスト層が形成される工程、
    (C1)第二面のソルダーレジスト層よりも厚さが薄い第一面のソルダーレジスト層に対して、後工程である工程(B)において薄膜化される領域以外の部分が露光される工程、
    (C2)第二面のソルダーレジスト層に対して、後工程である工程(D)において現像される領域以外の部分が露光される工程、
    (B)第一面において、薄膜化処理液によって、接続パッドの厚さ以下になるまで、非露光部のソルダーレジスト層が薄膜化されて、接続パッドの一部を露出する工程、
    (C3)第一面のソルダーレジスト層に対して、工程(B)において薄膜化された領域部分が露光される工程、
    (D)第二面の非露光部のソルダーレジスト層が、現像液によって除去される工程、
    を含むことを特徴とする配線基板の製造方法。
    A circuit board having an insulating layer and a connection pad formed on the surface of the insulating layer on both surfaces, a solder resist layer on both surfaces of the circuit board, and a part of the connection pad exposed from the solder resist layer In the manufacturing method of the wiring board which is doing,
    (A) a step in which solder resist layers having different thicknesses are formed on both surfaces of a circuit board having an insulating layer and a connection pad formed on the surface of the insulating layer on both surfaces;
    (C1) A step in which a portion other than the region to be thinned in the step (B) which is a subsequent step is exposed to the solder resist layer on the first surface which is thinner than the solder resist layer on the second surface,
    (C2) A step of exposing a portion other than the region to be developed in step (D), which is a subsequent step, to the solder resist layer on the second surface,
    (B) On the first surface, the solder resist layer of the non-exposed part is thinned until the thickness of the connection pad becomes equal to or less than the thickness of the connection pad by the thinning treatment solution, and a part of the connection pad is exposed.
    (C3) The step of exposing the area portion thinned in step (B) to the solder resist layer on the first surface,
    (D) the step of removing the solder resist layer of the non-exposed portion of the second surface with a developer;
    A method for manufacturing a wiring board, comprising:
  2.  絶縁層と、絶縁層の表面に形成された接続パッドとを両表面に有する回路基板を有し、回路基板の両表面にソルダーレジスト層を有し、ソルダーレジスト層から接続パッドの一部が露出している配線基板の製造方法において、
    (A)絶縁層と、絶縁層の表面に形成された接続パッドとを両表面に有する回路基板の両表面に、厚さの異なるソルダーレジスト層が形成される工程、
    (C1)第二面のソルダーレジスト層よりも厚さが薄い第一面のソルダーレジスト層に対して、後工程である工程(B1)において薄膜化される領域以外の部分が露光される工程、
    (C2)第二面のソルダーレジスト層に対して、後工程である工程(D)において現像される領域以外の部分が露光される工程、
    (B1)第一面において、薄膜化処理液によって、接続パッドが露出しない範囲で、非露光部のソルダーレジスト層が薄膜化される工程、
    (C4)第一面のソルダーレジスト層に対して、後工程である工程(B2)において薄膜化される領域以外の部分が露光される工程、
    (B2)第一面において、薄膜化処理液によって、接続パッドの厚さ以下になるまで、非露光部のソルダーレジスト層が薄膜化されて、接続パッドの一部を露出する工程、
    (C5)第一面のソルダーレジスト層に対して、工程(B2)において薄膜化された領域部分が露光される工程、
    (D)第二面の非露光部のソルダーレジスト層が、現像液によって除去される工程、
    を含むことを特徴とする配線基板の製造方法。
    A circuit board having an insulating layer and a connection pad formed on the surface of the insulating layer on both surfaces, a solder resist layer on both surfaces of the circuit board, and a part of the connection pad exposed from the solder resist layer In the manufacturing method of the wiring board which is doing,
    (A) a step in which solder resist layers having different thicknesses are formed on both surfaces of a circuit board having an insulating layer and a connection pad formed on the surface of the insulating layer on both surfaces;
    (C1) A step of exposing a portion other than the region to be thinned in the step (B1), which is a subsequent step, to the solder resist layer on the first surface that is thinner than the solder resist layer on the second surface,
    (C2) A step of exposing a portion other than the region to be developed in step (D), which is a subsequent step, to the solder resist layer on the second surface,
    (B1) In the first surface, the step in which the solder resist layer of the non-exposed part is thinned by the thinning treatment liquid in a range where the connection pad is not exposed,
    (C4) A step of exposing a portion other than the region to be thinned in the step (B2), which is a subsequent step, to the solder resist layer on the first surface,
    (B2) On the first surface, the solder resist layer of the non-exposed portion is thinned until the thickness of the connection pad becomes equal to or less than the thickness of the connection pad by the thinning treatment solution, and a part of the connection pad is exposed.
    (C5) The step of exposing the thinned region in step (B2) to the solder resist layer on the first surface,
    (D) the step of removing the solder resist layer of the non-exposed portion of the second surface with a developer;
    A method for manufacturing a wiring board, comprising:
  3.  絶縁層と、絶縁層の表面に形成された接続パッドとを両表面に有する回路基板を有し、回路基板の両表面にソルダーレジスト層を有し、ソルダーレジスト層から接続パッドの一部が露出している配線基板の製造方法において、
    (A1)絶縁層と、絶縁層の表面に形成された接続パッドとを両表面に有する回路基板の両表面に、厚さの異なる第一ソルダーレジスト層が形成される工程、
    (C1)第二面の第一ソルダーレジスト層よりも厚さが薄い第一面の第一ソルダーレジスト層に対して、後工程である工程(B)において薄膜化される領域以外の部分が露光される工程、
    (C2)第二面の第一ソルダーレジスト層に対して、後工程である工程(D1)において現像される領域以外の部分が露光される工程、
    (B)第一面において、薄膜化処理液によって、接続パッドの厚さ以下になるまで、非露光部の第一ソルダーレジスト層が薄膜化されて、接続パッドの一部を露出する工程、
    (C3)第一面の第一ソルダーレジスト層に対して、工程(B)において薄膜化された領域部分が露光される工程、
    (A2)(C3)工程まで完了した回路基板の第一面の第一ソルダーレジスト層上に、第二ソルダーレジスト層が形成される工程、
    (C6)第一面の第二ソルダーレジスト層に対して、後工程である工程(D1)において現像される領域以外の部分が露光される工程、
    (D1)第一面の非露光部の第二ソルダーレジスト層及び第二面の非露光部の第一ソルダーレジスト層が、現像液によって除去される工程、
    を含むことを特徴とする配線基板の製造方法。
    A circuit board having an insulating layer and a connection pad formed on the surface of the insulating layer on both surfaces, a solder resist layer on both surfaces of the circuit board, and a part of the connection pad exposed from the solder resist layer In the manufacturing method of the wiring board which is doing,
    (A1) a step in which first solder resist layers having different thicknesses are formed on both surfaces of a circuit board having an insulating layer and connection pads formed on the surfaces of the insulating layer on both surfaces;
    (C1) The first solder resist layer on the first surface, which is thinner than the first solder resist layer on the second surface, is exposed to a portion other than the region to be thinned in the subsequent step (B). Process
    (C2) A step of exposing a portion other than the region to be developed in step (D1), which is a subsequent step, to the first solder resist layer on the second surface,
    (B) On the first surface, the first solder resist layer of the non-exposed part is thinned until the thickness of the connection pad is equal to or less than the thickness of the connection pad by the thinning treatment liquid, and a part of the connection pad is exposed;
    (C3) The step of exposing the region portion thinned in step (B) to the first solder resist layer on the first surface,
    (A2) A step of forming a second solder resist layer on the first solder resist layer on the first surface of the circuit board completed up to the step (C3),
    (C6) A step in which a portion other than a region to be developed in the step (D1) which is a subsequent step is exposed to the second solder resist layer on the first surface;
    (D1) a step of removing the second solder resist layer of the non-exposed portion of the first surface and the first solder resist layer of the non-exposed portion of the second surface with a developer;
    A method for manufacturing a wiring board, comprising:
  4.  絶縁層と、絶縁層の表面に形成された接続パッドとを両表面に有する回路基板を有し、回路基板の両表面にソルダーレジスト層を有し、ソルダーレジスト層から接続パッドの一部が露出している配線基板の製造方法において、
    (A1)絶縁層と、絶縁層の表面に形成された接続パッドとを両表面に有する回路基板の両表面に、厚さの異なる第一ソルダーレジスト層が形成される工程、
    (C1)第二面の第一ソルダーレジスト層よりも厚さが薄い第一面の第一ソルダーレジスト層に対して、後工程である工程(B)において薄膜化される領域以外の部分が露光される工程、
    (C2)第二面の第一ソルダーレジスト層に対して、後工程である工程(D)において現像される領域以外の部分が露光される工程、
    (B)第一面において、薄膜化処理液によって、接続パッドの厚さ以下になるまで、非露光部の第一ソルダーレジスト層が薄膜化されて、接続パッドの一部を露出する工程、
    (C3)第一面の第一ソルダーレジスト層に対して、工程(B)において薄膜化された領域部分が露光される工程、
    (D)第二面の非露光部の第一ソルダーレジスト層が、現像液によって除去される工程、
    (A2)(D)工程まで完了した回路基板の第一面の第一ソルダーレジスト層上に、第二ソルダーレジスト層が形成される工程、
    (C6)第一面の第二ソルダーレジスト層に対して、後工程である工程(D2)において現像される領域以外の部分が露光される工程、
    (D2)第一面の非露光部の第二ソルダーレジスト層が、現像液によって除去される工程、
    を含むことを特徴とする配線基板の製造方法。
    A circuit board having an insulating layer and a connection pad formed on the surface of the insulating layer on both surfaces, a solder resist layer on both surfaces of the circuit board, and a part of the connection pad exposed from the solder resist layer In the manufacturing method of the wiring board which is doing,
    (A1) a step in which first solder resist layers having different thicknesses are formed on both surfaces of a circuit board having an insulating layer and connection pads formed on the surfaces of the insulating layer on both surfaces;
    (C1) The first solder resist layer on the first surface, which is thinner than the first solder resist layer on the second surface, is exposed to a portion other than the region to be thinned in the subsequent step (B). Process
    (C2) A step of exposing a portion other than a region to be developed in step (D), which is a subsequent step, to the first solder resist layer on the second surface;
    (B) On the first surface, the first solder resist layer of the non-exposed part is thinned until the thickness of the connection pad is equal to or less than the thickness of the connection pad by the thinning treatment liquid, and a part of the connection pad is exposed;
    (C3) The step of exposing the region portion thinned in step (B) to the first solder resist layer on the first surface,
    (D) the step of removing the first solder resist layer of the non-exposed portion of the second surface with a developer;
    (A2) A step in which a second solder resist layer is formed on the first solder resist layer on the first surface of the circuit board completed up to step (D),
    (C6) A step in which a portion other than the region to be developed in the step (D2) which is a subsequent step is exposed to the second solder resist layer on the first surface,
    (D2) a step of removing the second solder resist layer of the non-exposed portion of the first surface with a developer;
    A method for manufacturing a wiring board, comprising:
  5.  絶縁層と、絶縁層の表面に形成された接続パッドとを両表面に有する回路基板を有し、回路基板の両表面にソルダーレジスト層を有し、ソルダーレジスト層から接続パッドの一部が露出している配線基板の製造方法において、
    (A1)絶縁層と、絶縁層の表面に形成された接続パッドとを両表面に有する回路基板の両表面に、厚さの異なる第一ソルダーレジスト層が形成される工程、
    (C2)第二面の第一ソルダーレジスト層に対して、後工程である工程(D1)において現像される領域以外の部分が露光される工程、
    (B)第一面において、薄膜化処理液によって、接続パッドの厚さ以下になるまで、非露光部の第一ソルダーレジスト層が薄膜化されて、接続パッドの一部を露出する工程、
    (C3)第一面の第一ソルダーレジスト層に対して、工程(B)において薄膜化された領域部分が露光される工程、
    (A2)(C3)工程まで完了した回路基板の第一面の第一ソルダーレジスト層上に、第二ソルダーレジスト層が形成される工程、
    (C6)第一面の第二ソルダーレジスト層に対して、後工程である工程(B3)において薄膜化される領域以外の部分が露光される工程、
    (B3)第一面において、薄膜化処理液によって、接続パッドが露出しない範囲で、非露光部の第二ソルダーレジスト層が薄膜化される工程、
    (C7)第一面の第二ソルダーレジスト層に対して、後工程である工程(D1)において現像される領域以外の部分が露光される工程、
    (D1)第一面の非露光部の第二ソルダーレジスト層及び第二面の非露光部の第一ソルダーレジスト層が、現像液によって除去される工程、
    を含むことを特徴とする配線基板の製造方法。
    A circuit board having an insulating layer and a connection pad formed on the surface of the insulating layer on both surfaces, a solder resist layer on both surfaces of the circuit board, and a part of the connection pad exposed from the solder resist layer In the manufacturing method of the wiring board which is doing,
    (A1) a step in which first solder resist layers having different thicknesses are formed on both surfaces of a circuit board having an insulating layer and connection pads formed on the surfaces of the insulating layer on both surfaces;
    (C2) A step of exposing a portion other than the region to be developed in step (D1), which is a subsequent step, to the first solder resist layer on the second surface,
    (B) On the first surface, the first solder resist layer of the non-exposed part is thinned until the thickness of the connection pad is equal to or less than the thickness of the connection pad by the thinning treatment liquid, and a part of the connection pad is exposed;
    (C3) The step of exposing the region portion thinned in step (B) to the first solder resist layer on the first surface,
    (A2) A step of forming a second solder resist layer on the first solder resist layer on the first surface of the circuit board completed up to the step (C3),
    (C6) A step of exposing a portion other than the region to be thinned in the subsequent step (B3) to the second solder resist layer on the first surface;
    (B3) On the first surface, the second solder resist layer of the non-exposed part is thinned by the thinning treatment liquid in a range where the connection pad is not exposed,
    (C7) A step in which a portion other than the region to be developed in the step (D1) which is a subsequent step is exposed to the second solder resist layer on the first surface;
    (D1) a step of removing the second solder resist layer of the non-exposed portion of the first surface and the first solder resist layer of the non-exposed portion of the second surface with a developer;
    A method for manufacturing a wiring board, comprising:
  6.  工程(C1)の前に工程(C2)を行う請求項1~4のいずれかに記載の配線基板の製造方法。 The method for manufacturing a wiring board according to any one of claims 1 to 4, wherein the step (C2) is performed before the step (C1).
  7.  工程(C1)と工程(C2)を同時に行う請求項1~4のいずれかに記載の配線基板の製造方法。 The method for manufacturing a wiring board according to claim 1, wherein the step (C1) and the step (C2) are performed simultaneously.
  8.  工程(C3)における露光が、酸素雰囲気下での非接触露光方式によって行われる請求項1、3、4のいずれかに記載の配線基板の製造方法。 5. The method of manufacturing a wiring board according to claim 1, wherein the exposure in the step (C3) is performed by a non-contact exposure method in an oxygen atmosphere.
  9.  工程(C3)及び工程(C7)における露光が、酸素雰囲気下での非接触露光方式によって行われる請求項5記載の配線基板の製造方法。 The method for manufacturing a wiring board according to claim 5, wherein the exposure in the step (C3) and the step (C7) is performed by a non-contact exposure method in an oxygen atmosphere.
  10.  工程(C4)及び工程(C5)における露光が、酸素雰囲気下での非接触露光方式によって行われる請求項2に記載の配線基板の製造方法。 The method for manufacturing a wiring board according to claim 2, wherein the exposure in the step (C4) and the step (C5) is performed by a non-contact exposure method in an oxygen atmosphere.
  11.  工程(C3)における露光量が、工程(C1)における露光量の1倍以上5倍以下である請求項1、3、4、8のいずれかに記載の配線基板の製造方法。 The method for manufacturing a wiring board according to any one of claims 1, 3, 4, and 8, wherein an exposure amount in the step (C3) is 1 to 5 times the exposure amount in the step (C1).
  12.  工程(C3)及び工程(C7)における露光量が、工程(C6)における露光量の1倍以上5倍以下である請求項5又は9記載の配線基板の製造方法。 The method for manufacturing a wiring board according to claim 5 or 9, wherein the exposure amount in the step (C3) and the step (C7) is 1 to 5 times the exposure amount in the step (C6).
  13.  工程(C4)及び工程(C5)における露光量が、工程(C1)における露光量の1倍以上5倍以下である請求項2又は10に記載の配線基板の製造方法。 The method for manufacturing a wiring board according to claim 2 or 10, wherein the exposure amount in the step (C4) and the step (C5) is 1 to 5 times the exposure amount in the step (C1).
  14.  工程(B)におけるソルダーレジスト層の薄膜化処理が、薄膜化処理面を上にして行われる請求項1、3、4、8、11のいずれかに記載の配線基板の製造方法。 The method for manufacturing a wiring board according to any one of claims 1, 3, 4, 8, and 11, wherein the thinning process of the solder resist layer in the step (B) is performed with the thinning process surface facing up.
  15.  工程(B)及び工程(B3)におけるソルダーレジスト層の薄膜化処理が、薄膜化処理面を上にして行われる請求項5、9、12のいずれかに記載の配線基板の製造方法。 The method for manufacturing a wiring board according to any one of claims 5, 9, and 12, wherein the thinning process of the solder resist layer in the step (B) and the step (B3) is performed with the thinning process surface facing upward.
  16.  工程(B1)及び工程(B2)におけるソルダーレジスト層の薄膜化処理が、薄膜化処理面を上にして行われる請求項2、10、13のいずれかに記載の配線基板の製造方法。 14. The method for manufacturing a wiring board according to claim 2, wherein the thinning process of the solder resist layer in the step (B1) and the step (B2) is performed with the thinning process surface facing up.
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