TW201509256A - Process for manufacturing wiring substrate - Google Patents

Process for manufacturing wiring substrate Download PDF

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Publication number
TW201509256A
TW201509256A TW103117893A TW103117893A TW201509256A TW 201509256 A TW201509256 A TW 201509256A TW 103117893 A TW103117893 A TW 103117893A TW 103117893 A TW103117893 A TW 103117893A TW 201509256 A TW201509256 A TW 201509256A
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Taiwan
Prior art keywords
solder resist
resist layer
thickness
exposed
wiring board
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TW103117893A
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Chinese (zh)
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TWI625996B (en
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Yuji Toyoda
Norihiko Gokan
Noriyuki Kawai
Kunihiro Nakagawa
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Mitsubishi Paper Mills Ltd
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Publication of TWI625996B publication Critical patent/TWI625996B/en

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/288Removal of non-metallic coatings, e.g. for repairing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845Stepped hole, via, edge, bump or conductor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01Tools for processing; Objects used during processing
    • H05K2203/0104Tools for processing; Objects used during processing for patterning or coating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05Patterning and lithography; Masks; Details of resist
    • H05K2203/0502Patterning and lithography

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Ceramic Engineering (AREA)

Abstract

The present invention is a manufacturing method for a wiring board, which is characterized in including steps for: (A) forming solder mask layers of different thickness on both surfaces of a circuit board; (C1) for a solder mask layer of a first surface which is of thinner thickness than a solder mask layer of a second surface, exposing portions other than areas to be thinned in step (B), which is a later step; (C2) for the solder mask layer of the second surface, exposing portions other than areas to be developed in step (D), which is a later step; (B) by way of a thin-film processing solution, thinning the solder mask layer of the first surface of the non-exposed portions until reaching thicknesses that are less than or equal to connection pads; (C3) for the solder mask layer of the first surface, exposing the area-portions that have been thinned in step (B); and (D) removing, by way of a developer solution, the solder mask layers of the non-exposed portions of the second surface.

Description

配線基板的製造方法 Wiring substrate manufacturing method

本發明係關於配線基板的製造方法,尤其是,與具有用以連結半導體晶片及其他印刷線路板等電子構件之複數連結墊之配線基板的製造方法相關。 The present invention relates to a method of manufacturing a wiring board, and more particularly to a method of manufacturing a wiring board having a plurality of connection pads for connecting electronic components such as semiconductor wafers and other printed wiring boards.

各種電氣機器內部之配線基板,於其中一側表面或兩表面,有具備絕緣層、及形成於絕緣層表面之導體配線的電路基板。此外,於配線基板的電路基板表面,為了使焊劑不會附著於無需焊接之導體配線,而在未焊接之部分全面形成防焊層。該防焊層,發揮防止導體配線之氧化、電氣絕緣及阻隔外部環境之機能。 A wiring board inside each of the electric devices has a circuit board having an insulating layer and conductor wiring formed on the surface of the insulating layer on one or both surfaces thereof. Further, on the surface of the circuit board of the wiring board, in order to prevent the solder from adhering to the conductor wiring which is not required to be soldered, a solder resist layer is formed over the unwelded portion. The solder resist layer functions to prevent oxidation, electrical insulation, and external environment of the conductor wiring.

此外,於配線基板上配載半導體晶片等電子構件時,於配線基板的表面,形成有用以連結半導體晶片、及其他印刷線路板等電子構件之多數連結墊。連結墊,係以使電路基板表面之導體配線的整體或一部分從防焊層露出之方式來製作。近年來,該連結墊持續朝高密度化發展,所配置之連結墊的彼此間距愈來愈狹窄,例如, 也有50μm以下之窄間距。 Further, when an electronic component such as a semiconductor wafer is mounted on the wiring substrate, a plurality of connection pads for connecting electronic components such as a semiconductor wafer and other printed wiring boards are formed on the surface of the wiring substrate. The connection pad is formed such that the entire or a part of the conductor wiring on the surface of the circuit board is exposed from the solder resist layer. In recent years, the connection pads have continued to be densified, and the spacing of the connected pads is becoming narrower and narrower, for example, There is also a narrow pitch of 50 μm or less.

於高密度配置之連結墊配載電子構件的方法,有利用覆晶連結的方法。覆晶連結,係指使配設於配線基板上之電子構件連結用連結墊的一部分對應於電子構件之電極端子的配置並露出,並使該電子構件連結用連結墊之露出部與電子構件之電極端子相對,再介由焊劑凸塊進行電氣連結。 A method of attaching an electronic component to a connection pad of a high-density arrangement has a method of using a flip chip connection. The flip-chip connection means that a part of the connection pad for the electronic component to be placed on the wiring board is exposed in accordance with the arrangement of the electrode terminals of the electronic component, and the exposed portion of the connection pad for the electronic component is connected to the electrode of the electronic component. The terminals are opposite and are electrically connected by solder bumps.

連結墊之構造上,有除去部分防焊層來使連結墊表面之整體或一部分露出的SMD(Solder Mask Defined)構造、及除去部分防焊層來使連結墊完全露出的NSMD(Non Solder Mask Defined)構造。 The structure of the connection pad includes an SMD (Solder Mask Defined) structure in which a part of the solder resist layer is removed to expose the entire or a part of the surface of the connection pad, and an NSMD (Non Solder Mask Defined) in which a part of the solder resist layer is removed to completely expose the connection pad. )structure.

第1圖A係具有SMD構造之配線基板一例的概略剖面圖。在絕緣層8表面配設有導體配線7及導體配線之部分連結墊3的電路基板1表面,形成有防焊層2。連結墊3,其周邊附近為防焊層2所覆蓋。所以,有不易因為機械衝擊而發生連結墊3剝落及從連結墊3之延伸配線之頸部斷線的優點。相反地,因為電子構件之電極端子與對應其之連結墊3的電氣連結獲得確實固定,必須於形成在連結墊3露出面之接合部確保必要的焊劑量,因而導致連結墊3的大型化,故難以對應電子構件之小型化及高性能化所伴隨之連結墊3的高密度化要求。 Fig. 1A is a schematic cross-sectional view showing an example of a wiring board having an SMD structure. The surface of the circuit board 1 on which the conductor wiring 7 and the part of the conductor wiring are connected to the pad 3 is disposed on the surface of the insulating layer 8, and the solder resist layer 2 is formed. The connection pad 3 is covered by the solder resist layer 2 in the vicinity of the periphery. Therefore, there is an advantage that it is difficult to cause the connection pad 3 to peel off and the neck of the extension wire of the connection pad 3 to be broken due to mechanical impact. On the contrary, since the electrical connection between the electrode terminal of the electronic component and the connection pad 3 corresponding thereto is surely fixed, it is necessary to secure a necessary amount of soldering at the joint portion formed on the exposed surface of the connection pad 3, thereby causing an increase in the size of the connection pad 3. Therefore, it is difficult to meet the demand for higher density of the connection pad 3 in accordance with the miniaturization and high performance of the electronic component.

第1圖B係具有NSMD構造之配線基板一例的概略剖面圖。在絕緣層8表面配設有導體配線7及導體配線之部分連結墊3的電路基板1表面,形成有防焊層 2。防焊層2之同一開口內,配置有複數連結墊3,該等連結墊3從防焊層2露出。NSMD構造時,連結墊3之周邊附近的防焊層2被完全除去,而使連結墊3的側面完全露出。所以,相較於SMD構造,即使較小的連結墊3,也可確保連結墊3與焊劑的接著強度。相反地,連結墊3的側面完全露出,可能降低連結墊3與絕緣層8之間的接著強度。此外,以窄間距配置之連結墊3時,在後製程的無電解鎳/金電鍍有時於連結墊3間會發生短路,或者,在連結墊3上配設焊劑凸塊的話,有時熔融之焊劑流至相鄰之連結墊3,而使連結墊3間發生短路。 Fig. 1B is a schematic cross-sectional view showing an example of a wiring board having an NSMD structure. A surface of the circuit board 1 on which the conductor wiring 7 and the portion of the conductor wiring are connected to the pad 3 are disposed on the surface of the insulating layer 8, and a solder resist layer is formed. 2. In the same opening of the solder resist layer 2, a plurality of connection pads 3 are disposed, and the connection pads 3 are exposed from the solder resist layer 2. In the NSMD structure, the solder resist layer 2 in the vicinity of the periphery of the connection pad 3 is completely removed, and the side surface of the connection pad 3 is completely exposed. Therefore, compared with the SMD structure, even if the connection pad 3 is small, the bonding strength of the bonding pad 3 and the flux can be ensured. Conversely, the side surface of the bonding pad 3 is completely exposed, which may lower the bonding strength between the bonding pad 3 and the insulating layer 8. Further, when the connection pads 3 are arranged at a narrow pitch, the electroless nickel/gold plating in the post-process may be short-circuited between the connection pads 3, or may be melted if the solder bumps are provided on the connection pads 3. The flux flows to the adjacent connection pads 3, causing a short circuit between the connection pads 3.

為了解決連結墊與絕緣層間的接著強度問題,有人提出以下之方法,藉由照射雷射光使配設於電路基板表面之防焊層的一部分形成深度0~15μm程度的開口部,來製造具有連結墊部分側面從防焊層露出之構造之印刷線路板的方法(例如,參照專利文獻1)。藉由採用以專利文獻1所記載之方法得到的印刷線路板,相較於使存在於防焊層下部之連結墊完全露出的印刷線路板,可能會提高連結墊與絕緣層間的接著強度。 In order to solve the problem of the adhesion strength between the connection pad and the insulating layer, a method of manufacturing a connection by forming a portion of the solder resist layer disposed on the surface of the circuit board to a depth of about 0 to 15 μm by irradiating the laser light is provided. A method of printing a wiring board having a structure in which the side of the pad portion is exposed from the solder resist layer (for example, refer to Patent Document 1). By using the printed wiring board obtained by the method described in Patent Document 1, the bonding strength between the connection pad and the insulating layer may be improved as compared with the printed wiring board in which the connection pads existing in the lower portion of the solder resist layer are completely exposed.

此外,為了解決窄間距配置之連結墊3的短路問題,有人提出製造於相鄰連結墊3間充填防焊層2之配線基板的方法(例如,參照專利文獻2)。依據專利文獻2之方法的話,可以形成如第2圖所示之於連結墊3間充填著防焊層2,且充填之防焊層2的厚度為連結墊3之厚度以下的NSMD構造。具體而言,於電路基板1上形成 防焊層2,對防焊層2之厚度薄膜化至連結墊3之厚度以下為止的區域以外之部分進行曝光後,利用鹼性水溶液薄膜化處理液,實施使其成為連結墊3之厚度以下為止之非曝光部之防焊層2的薄膜化。藉此,形成具有包含連結墊3之厚度以下的部分及超過連結墊3之厚度的部分之多段構造的防焊層2,進而製造出做為連結墊3之部分導體配線露出的配線基板。 In addition, a method of manufacturing a wiring board in which the solder resist layer 2 is filled between adjacent connection pads 3 has been proposed in order to solve the problem of short-circuiting of the connection pads 3 in a narrow pitch (see, for example, Patent Document 2). According to the method of Patent Document 2, it is possible to form the NSMD structure in which the solder resist layer 2 is filled between the connection pads 3 as shown in FIG. 2, and the thickness of the solder resist layer 2 to be filled is equal to or less than the thickness of the connection pad 3. Specifically, formed on the circuit substrate 1 In the solder resist layer 2, after the thickness of the solder resist layer 2 is thinned to a portion other than the region below the thickness of the connection pad 3, the solution is thinned by the alkaline aqueous solution to be equal to or less than the thickness of the connection pad 3. The thin film of the solder resist layer 2 in the non-exposed portion. Thereby, the solder resist layer 2 having a multi-stage structure including a portion having a thickness equal to or less than the thickness of the connection pad 3 and a portion exceeding the thickness of the connection pad 3 is formed, and a wiring board in which a part of the conductor wiring of the connection pad 3 is exposed is manufactured.

通常,配載著電子構件之配線基板時,於背面以高密度形成有多數之外部連結用連結墊。外部連結用連結墊,也可藉由使電路基板背面之部分導體配線從防焊層露出來製作。使該外部連結用連結墊之露出部與主機板等之外部電氣基板的導體配線相對,介由焊劑凸塊來進行電氣連結。 In general, when a wiring board of an electronic component is mounted, a large number of external connection connecting pads are formed at a high density on the back surface. The external connection connecting pad can also be produced by exposing a part of the conductor wiring on the back surface of the circuit board from the solder resist layer. The exposed portion of the external connection connecting pad is opposed to the conductor wiring of the external electrical board such as the motherboard, and is electrically connected via the solder bump.

於電路基板兩面形成防焊層時,連結墊上之防焊層厚度,隨著包含連結墊在內之其周圍的導體配線密度而變化。例如,導體配線密度較小時,充填於導體配線間之間隙的防焊層量較多,呈現連結墊上之防焊層厚度較薄的傾向。另一方面,導體配線密度較大時,充填於導體配線間之間隙的防焊層量較少,呈現連結墊上之防焊層厚度較厚的傾向。 When the solder resist layer is formed on both surfaces of the circuit board, the thickness of the solder resist layer on the connection pad changes with the density of the conductor wiring around the connection pad. For example, when the conductor wiring density is small, the amount of the solder resist layer filled in the gap between the conductor wirings is large, and the thickness of the solder resist layer on the connection pad tends to be thin. On the other hand, when the conductor wiring density is large, the amount of the solder resist layer filled in the gap between the conductor wirings is small, and the thickness of the solder resist layer on the connection pad tends to be thick.

以覆晶連結來配載電子構件之配線基板時,有時包含背面之外部連結用連結墊在內之其周圍的導體配線密度大於包含表面之電子構件連結用連結墊在內之其周圍的導體配線密度。所以,有時背面之外部連結用連結墊 上的防焊層厚度比表面之電子構件連結用連結墊上的防焊層厚度更厚。在利用薄膜化處理液實施防焊層薄膜化來使連結墊露出的方法時,對兩面同時實施薄膜化時,有時會發生以下之問題。 When the wiring board of the electronic component is mounted by the flip chip connection, the conductor wiring density around the external connection connection pad including the back surface may be larger than the conductor around the electronic component connection connection pad including the surface. Wiring density. Therefore, sometimes the external connection connecting pad on the back side The thickness of the solder resist layer on the surface is thicker than the thickness of the solder resist layer on the connection pad for electronic component connection on the surface. When a method of thinning the solder resist layer by using a thin film processing liquid to expose the bonding pad, when the both surfaces are simultaneously thinned, the following problems may occur.

首先,以使表面之防焊層2成為電子構件連結用連結墊3之厚度以下為止的薄膜化做為基準時,背面之防焊層2也同時被實施與表面同量之薄膜化,然而,因為背面之防焊層2比表面之防焊層2更厚,背面之外部連結用連結墊4上殘留著防焊層2之殘渣,該殘渣有時會導致電氣絕緣不良的問題(第3圖)。 First, when the surface solder resist layer 2 is made thinner than the thickness of the electronic component connecting connecting pad 3, the solder resist layer 2 on the back surface is simultaneously thinned in the same amount as the surface. Since the solder resist layer 2 on the back surface is thicker than the solder resist layer 2 on the surface, the residue of the solder resist layer 2 remains on the connection pad 4 for external connection on the back surface, which may cause a problem of poor electrical insulation (Fig. 3) ).

相反地,以使背面之防焊層2成為外部連結用連結墊4之厚度以下為止的薄膜化做為基準時,表面之防焊層2也同時被實施與背面同量之薄膜化,然而,因為背面之防焊層2比表面之防焊層2更厚,充填於表面之電子構件連結用連結墊3間的防焊層2厚度比期望厚度更薄,有時會發生相鄰之電子構件連結用連結墊3間的短路問題。 On the other hand, when the solder resist layer 2 on the back surface is made thinner than the thickness of the outer connecting connecting pad 4, the solder resist layer 2 on the surface is simultaneously thinned by the same amount as the back surface. Since the solder resist layer 2 on the back surface is thicker than the solder resist layer 2 on the surface, the thickness of the solder resist layer 2 between the bonding pads 3 for connecting electronic components on the surface is thinner than the desired thickness, and adjacent electronic components sometimes occur. A short circuit problem between the connection pads 3 for connection.

但是,於電路基板上實施電子構件之覆晶連結的印刷線路板時,為了確保電子構件與電路基板之連結信賴性,以填膠(密封樹脂)充填電子構件與電路基板之空隙來進行補強。為了確保補強效果,必須對電子構件與電路基板之空隙進行充分量之填膠的充填。然而,使用專利文獻1所得到之印刷線路板來實施覆晶連結時,為了確保補強效果而實施充分填膠之充填時,填膠從電子構件與 電路基板之空隙溢至周圍,有時會對電氣作動產生不良影響。所以,為了防止填膠溢至周圍,有人提出具有堤壩構造的印刷線路板(例如,參照專利文獻3~5)。 However, when a printed wiring board in which the electronic component is flip-chip bonded is mounted on a circuit board, in order to secure the connection reliability between the electronic component and the circuit board, the gap between the electronic component and the circuit board is filled with a filler (sealing resin) to reinforce. In order to ensure the reinforcing effect, it is necessary to fill a sufficient amount of the gap between the electronic component and the circuit board. However, when the flip chip connection is performed using the printed wiring board obtained in Patent Document 1, when the filling of the sufficient filling is performed to secure the reinforcing effect, the filling is performed from the electronic component and The gap of the circuit board overflows to the surroundings, which may adversely affect electrical operation. Therefore, in order to prevent the glue from overflowing to the surroundings, a printed wiring board having a bank structure has been proposed (for example, refer to Patent Documents 3 to 5).

專利文獻3提出之方法,係在具有導體電路之電路基板上形成防焊層後,實施部分曝光,其後,對未曝光部實施顯影處理,形成使部分連結墊上部從防焊層露出的開口部,其次,實施第2次部分曝光,其後,以除膠渣處理來實施第2次部分曝光之未曝光部的薄膜化,進而形成堤壩形狀的方法。利用此方法之防焊層的開口部,因為係SMD構造,難以確實固定電子構件之電極端子與對應於其之連結墊的電氣連結,有時連結墊與焊球之電氣連結會不充分。此外,利用此方法之堤壩構造的形成,因為係利用除膠渣處理來實施,有時,防焊層會粗面化而導致防焊層強度降低,進而無法充分確保印刷線路板之信賴性。 According to the method proposed in Patent Document 3, after the solder resist layer is formed on the circuit board having the conductor circuit, partial exposure is performed, and then the unexposed portion is subjected to development processing to form an opening for exposing the upper portion of the portion of the connection pad from the solder resist layer. In the second step, a second partial exposure is performed, and thereafter, a method of forming a bank shape by performing a second partial exposure of the unexposed portion by the desmear treatment is performed. The opening of the solder resist layer by this method is difficult to securely fix the electrical connection between the electrode terminal of the electronic component and the connection pad corresponding thereto due to the SMD structure, and the electrical connection between the connection pad and the solder ball may be insufficient. Further, since the formation of the dam structure by this method is performed by the desmear treatment, the solder resist layer may be roughened to lower the strength of the solder resist layer, and the reliability of the printed wiring board may not be sufficiently ensured.

專利文獻4所提出之方法,係在具有導體電路之電路基板上形成防焊層後,實施部分曝光,其後,對未曝光部實施顯影處理,來形成使連結墊完全從防焊層之露出的開口部,其次,形成第2次防焊後,實施未曝光部遠大於第1次部分曝光區域之第2次部分曝光,其後,以未曝光部之顯影來形成堤壩形狀的方法。利用此方法之防焊層的開口部,係NSMD構造,連結墊之周邊附近的防焊層被完全除去,連結墊之側面完全露出,可能導致連結墊與絕緣層間的接著強度降低。 According to the method proposed in Patent Document 4, after the solder resist layer is formed on the circuit board having the conductor circuit, partial exposure is performed, and then the unexposed portion is subjected to development processing to form the connection pad completely exposed from the solder resist layer. In the opening, secondly, after the second solder mask is formed, the unexposed portion is much larger than the second partial exposure of the first partial exposure region, and thereafter, the bank shape is formed by development of the unexposed portion. The opening of the solder resist layer by this method is an NSMD structure, and the solder resist layer in the vicinity of the vicinity of the connection pad is completely removed, and the side surface of the connection pad is completely exposed, which may cause a decrease in the bonding strength between the connection pad and the insulating layer.

專利文獻5提出之方法,係在具有導體電路之電路基板上形成防焊層後,實施部分曝光製程,其後,實施未曝光部之防焊層的薄膜化,而於防焊層形成開口部及堤壩形狀的方法。利用此方法之防焊層的開口部,係SMD構造,因為連結墊之周邊附近為防焊層所覆蓋,難以使電子構件之電極端子與對應其之連結墊的電氣連結獲得確實固定,有時會有連結墊與焊球之電氣連結不充分的情形。 According to the method proposed in Patent Document 5, after a solder resist layer is formed on a circuit board having a conductor circuit, a partial exposure process is performed, and thereafter, a solder resist layer of the unexposed portion is thinned, and an opening portion is formed in the solder resist layer. And the method of the shape of the dam. The opening of the solder resist layer by this method is an SMD structure, and since the vicinity of the vicinity of the connection pad is covered by the solder resist layer, it is difficult to secure the electrical connection between the electrode terminal of the electronic component and the connection pad corresponding thereto, and sometimes There is a case where the electrical connection between the connection pad and the solder ball is insufficient.

[專利文獻] [Patent Literature]

[專利文獻1]日本特許3346263號公報 [Patent Document 1] Japanese Patent No. 3346263

[專利文獻2]國際公開第2012/043201號小冊子 [Patent Document 2] International Publication No. 2012/043201

[專利文獻3]日本特開2012-238668號公報 [Patent Document 3] Japanese Laid-Open Patent Publication No. 2012-238668

[專利文獻4]日本特開平05-226505號公報 [Patent Document 4] Japanese Laid-Open Patent Publication No. 05-226505

[專利文獻5]日本特開2011-77191號公報 [Patent Document 5] Japanese Patent Laid-Open Publication No. 2011-77191

本發明之課題,係在提供一種於兩表面具有絕緣層、及形成於絕緣層表面之連結墊的電路基板,且電路基板之兩表面具有防焊層,使連結墊之一部分從防焊層露出之配線基板的製造方法,在配線基板的兩表面,從防焊層露出之連結墊間不會發生電氣短路,且露出之連結墊上不殘留防焊層之殘渣的配線基板的製造方法。此外,本發明之其他課題,係在提供一種印刷線路板的製造方法, 可以得到連結墊與絕緣層及連結墊與焊劑之接著強度高,無填膠流出所致之電性作動不良,防焊層強度高的印刷線路板。 An object of the present invention is to provide a circuit board having an insulating layer on both surfaces and a bonding pad formed on the surface of the insulating layer, and both surfaces of the circuit substrate have a solder resist layer to expose a portion of the bonding pad from the solder resist layer In the method of manufacturing a wiring board, a method of manufacturing a wiring board in which no residue of the solder resist layer remains on the exposed connection pads without causing an electrical short between the connection pads exposed from the solder resist layer on both surfaces of the wiring board. Further, another object of the present invention is to provide a method of manufacturing a printed wiring board. It is possible to obtain a printed wiring board having high bonding strength between the bonding pad and the insulating layer and the bonding pad and the solder, and having no electrical breakdown due to the outflow of the adhesive, and having high strength of the solder resist layer.

本發明者們,為了解決上述課題,經過審慎檢討的結果,發現以下述發明可以解決上述課題。 The inventors of the present invention have found that the above problems can be solved by the following inventions in order to solve the above problems.

(1)之配線基板的製造方法,係具有於兩表面具有絕緣層、及形成於絕緣層表面之連結墊的電路基板,於電路基板之兩表面,具有防焊層,使連結墊之一部分從防焊層露出之配線基板的製造方法,其特徵為,含有:於兩表面具有絕緣層、及形成於絕緣層表面之連結墊之電路基板的兩表面,形成厚度不同之防焊層的製程(A);對厚度薄於第二面之防焊層的第一面之防焊層,實施於後製程之製程(B)被薄膜化區域以外部分之曝光的製程(C1);對第二面之防焊層,實施於後製程之製程(D)被顯影之區域以外部分之曝光的製程(C2);於第一面,以薄膜化處理液實施使非曝光部之防焊層成為連結墊之厚度以下為止的薄膜化,來使連結墊之一部分露出的製程(B);對第一面之防焊層,實施於製程(B)被薄膜化之區域部分之曝光的製程(C3);以及以顯影液除去第二面之非曝光部之防焊層的製程 (D)。 (1) A method of manufacturing a wiring board, comprising: a circuit board having an insulating layer on both surfaces and a connection pad formed on a surface of the insulating layer; and having a solder resist layer on both surfaces of the circuit board to partially form a connection pad A method of manufacturing a wiring board in which a solder resist layer is exposed, comprising: a process of forming a solder resist layer having different thicknesses on both surfaces of an electric circuit having an insulating layer and a connection pad formed on a surface of the insulating layer; A); a solder resist layer having a thickness smaller than the first surface of the solder resist layer of the second surface, a process (C1) of performing a post-process (B) exposure process on a portion other than the thinned region; The solder resist layer is subjected to a process (C2) of exposing a portion other than the developed region in the process of the post-process (D); on the first surface, the solder resist layer of the non-exposed portion is used as a bonding pad by the thin film processing liquid a process (B) for exposing one portion of the connection pad to a thickness of the thickness of the connection pad, and a process (C3) for exposing the portion of the process area (B) to the thinned portion of the process (B); And removing the non-exposed portion of the second side with a developer Welding process layer (D).

(2)之配線基板的製造方法,係具有於兩表面具有絕緣層、及形成於絕緣層表面之連結墊的電路基板,於電路基板之兩表面,具有防焊層,使連結墊之一部分從防焊層露出之配線基板的製造方法,其特徵為,含有:於兩表面具有絕緣層、及形成於絕緣層表面之連結墊之電路基板的兩表面,形成厚度不同之防焊層的製程(A);對厚度薄於第二面之防焊層的第一面之防焊層,實施後製程之製程(B1)被薄膜化區域以外部分之曝光的製程(C1);對第二面之防焊層,實施於後製程之製程(D)被顯影之區域以外部分之曝光的製程(C2);對第一面,在連結墊未露出之範圍,以薄膜化處理液,實施非曝光部之防焊層之薄膜化的製程(B1);於第一面之防焊層,實施於後製程之製程(B2)被薄膜化區域以外部分之曝光的製程(C4);於第一面,以薄膜化處理液實施使非曝光部之防焊層成為連結墊之厚度以下為止的薄膜化,來使連結墊之一部分露出的製程(B2);對第一面之防焊層,實施於製程(B2)被薄膜化之區域部分之曝光的製程(C5);以及以顯影液除去第二面之非曝光部之防焊層的製程 (D)。 (2) A method of manufacturing a wiring board, comprising: a circuit board having an insulating layer on both surfaces and a connection pad formed on a surface of the insulating layer; and having a solder resist layer on both surfaces of the circuit board, and a part of the connection pad is A method of manufacturing a wiring board in which a solder resist layer is exposed, comprising: a process of forming a solder resist layer having different thicknesses on both surfaces of an electric circuit having an insulating layer and a connection pad formed on a surface of the insulating layer; A); for the solder resist layer having a thickness thinner than the first surface of the solder mask of the second surface, a process (C1) of performing a post-process (B1) exposure process on a portion other than the thinned region; The solder resist layer is subjected to a process (C2) for exposing a portion other than the developed region in the process of the post-process (D2); and the non-exposed portion is formed by thinning the solution on the first surface in a range where the bonding pad is not exposed; a process for thinning the solder resist layer (B1); a solder resist layer on the first side, a process (C4) for performing a post-process (B2) exposure process on a portion other than the thinned region; on the first side, The film formation treatment liquid is used to make the solder resist layer of the non-exposure portion The process of thinning the thickness of the bonding pad to expose one of the bonding pads (B2); and the process of exposing the soldering layer of the first surface to the portion of the process (B2) which is thinned (C5) And a process of removing the solder resist layer of the non-exposed portion of the second surface by the developer (D).

(3)之配線基板的製造方法,係具有於兩表面具有絕緣層、及形成於絕緣層表面之連結墊的電路基板,於電路基板之兩表面,具有防焊層,使連結墊之一部分從防焊層露出之配線基板的製造方法,其特徵為,含有:於兩表面具有絕緣層、及形成於絕緣層表面之連結墊之電路基板的兩表面,形成厚度不同之第一防焊層的製程(A1);對厚度薄於第二面之第一防焊層的第一面之第一防焊層,實施於後製程之製程(B)被薄膜化區域以外部分之曝光的製程(C1);對第二面之第一防焊層,實施於後製程之製程(D1)被顯影區域以外部分之曝光的製程(C2);於第一面,以薄膜化處理液實施使非曝光部之第一防焊層成為連結墊之厚度以下為止的薄膜化,來使連結墊之一部分露出的製程(B);對第一面之第一防焊層,實施於製程(B)被薄膜化區域部分之曝光的製程(C3);於完成至(C3)製程為止之電路基板之第一面的第一防焊層上,形成第二防焊層之製程(A2);對第一面之第二防焊層,實施於後製程之製程(D1)被顯影區域以外部分之曝光的製程(C6);以及以顯影液除去第一面之非曝光部之第二防焊層及第二 面之非曝光部之第一防焊層的製程(D1)。 (3) A method of manufacturing a wiring board, comprising: a circuit board having an insulating layer on both surfaces and a connection pad formed on a surface of the insulating layer; and having a solder resist layer on both surfaces of the circuit board to partially form a connection pad A method of manufacturing a wiring board in which a solder resist layer is exposed, comprising: forming an insulating layer on both surfaces and a surface of a circuit board formed on a connection pad on a surface of the insulating layer, and forming a first solder resist layer having a thickness different from each other Process (A1); the first solder resist layer having a thickness smaller than the first surface of the first solder resist layer of the second surface is subjected to a process of post-process (B) exposure of a portion other than the thinned region (C1) The first solder resist layer on the second surface is subjected to a process (C2) of exposing a portion of the process (D1) to the portion other than the developed region in the post-process; on the first surface, the non-exposed portion is implemented as a thin film processing solution The first solder resist layer is formed into a film having a thickness equal to or less than the thickness of the bonding pad, and a part (b) of the bonding pad is exposed; and the first solder resist layer on the first surface is formed into a thin film in the process (B). Process for exposure of the regional part (C3); after completion to (C3) a second solder resist layer process (A2) is formed on the first solder resist layer on the first surface of the circuit substrate; and the second solder resist layer on the first surface is developed in the post process (D1) a process for exposing a portion outside the region (C6); and a second solder resist layer and a second portion of the non-exposed portion of the first side removed by the developer The process of the first solder mask of the non-exposed portion of the surface (D1).

(4)之配線基板的製造方法,係具有於兩表面具有絕緣層、及形成於絕緣層表面之連結墊的電路基板,於電路基板之兩表面,具有防焊層,使連結墊之一部分從防焊層露出之配線基板的製造方法,其特徵為,含有:於兩表面具有絕緣層、及形成於絕緣層表面之連結墊之電路基板的兩表面,形成厚度不同之第一防焊層的製程(A1);對厚度薄於第二面之第一防焊層的第一面之第一防焊層,實施於後製程之製程(B)被薄膜化區域以外部分之曝光的製程(C1);對第二面之第一防焊層,實施於後製程之製程(D)被顯影之區域以外部分之曝光的製程(C2);於第一面,以薄膜化處理液實施使非曝光部之第一防焊層成為連結墊之厚度以下為止的薄膜化,來使連結墊之一部分露出的製程(B);對第一面之第一防焊層,實施於製程(B)被薄膜化區域部分之曝光的製程(C3);以顯影液除去第二面之非曝光部之第一防焊層的製程(D);於完成至(D)製程為止之電路基板之第一面的第一防焊層上,形成第二防焊層之製程(A2);對第一面之第二防焊層,實施於後製程之製程(D2) 被顯影區域以外部分之曝光的製程(C6);以及以顯影液除去第一面之非曝光部之第二防焊層的製程(D2)。 (4) A method of manufacturing a wiring board, comprising: a circuit board having an insulating layer on both surfaces and a connection pad formed on a surface of the insulating layer; and having a solder resist layer on both surfaces of the circuit board, and a part of the connection pad is A method of manufacturing a wiring board in which a solder resist layer is exposed, comprising: forming an insulating layer on both surfaces and a surface of a circuit board formed on a connection pad on a surface of the insulating layer, and forming a first solder resist layer having a thickness different from each other Process (A1); the first solder resist layer having a thickness smaller than the first surface of the first solder resist layer of the second surface is subjected to a process of post-process (B) exposure of a portion other than the thinned region (C1) The first solder resist layer on the second side is subjected to a process (C2) for exposing a portion of the process other than the developed region in the post-process (D); on the first side, the film is treated with a thin film to make the non-exposure The first solder resist layer of the portion is formed by thinning the thickness of the bonding pad or less to expose one of the bonding pads (B); and the first solder resist layer of the first surface is applied to the film (B) by the film Process for exposure of the region (C3); removal with developer a process (D) of the first solder resist layer of the non-exposed portion of the second surface; a process of forming the second solder resist layer on the first solder resist layer of the first surface of the circuit substrate until the (D) process is completed (A2); for the second solder mask on the first side, implemented in the post-process (D2) a process for exposing a portion other than the developed region (C6); and a process for removing the second solder resist layer of the non-exposed portion of the first face by the developer (D2).

(5)之配線基板的製造方法,係具有於兩表面具有絕緣層、及形成於絕緣層表面之連結墊的電路基板,於電路基板之兩表面,具有防焊層,使連結墊之一部分從防焊層露出之配線基板的製造方法,其特徵為,含有:於兩表面具有絕緣層、及形成於絕緣層表面之連結墊之電路基板的兩表面,形成厚度不同之第一防焊層的製程(A1);對第二面之第一防焊層,實施於後製程之製程(D1)被顯影區域以外部分之曝光的製程(C2);於第一面,以薄膜化處理液實施使非曝光部之第一防焊層成為連結墊之厚度以下為止的薄膜化,來使連結墊之一部分露出的製程(B);對第一面之第一防焊層,實施於製程(B)被薄膜化區域部分之曝光的製程(C3);於完成至(C3)製程為止之電路基板之第一面的第一防焊層上,形成第二防焊層之製程(A2);對第一面之第二防焊層,實施於後製程之製程(B3)被薄膜化區域以外部分之曝光的製程(C6);於第一面,在連結墊未露出之範圍,以薄膜化處理液實施非曝光部之第二防焊層之薄膜化的製程(B3); 對第一面之第二防焊層,實施於後製程之製程(D1)被顯影區域以外部分之曝光的製程(C7);以及以顯影液除去第一面之非曝光部之第二防焊層及第二面之非曝光部之第一防焊層的製程(D1)。 (5) A method of manufacturing a wiring board, comprising: a circuit board having an insulating layer on both surfaces and a connection pad formed on a surface of the insulating layer; and having a solder resist layer on both surfaces of the circuit board, and a part of the connection pad is A method of manufacturing a wiring board in which a solder resist layer is exposed, comprising: forming an insulating layer on both surfaces and a surface of a circuit board formed on a connection pad on a surface of the insulating layer, and forming a first solder resist layer having a thickness different from each other Process (A1); the first solder resist layer on the second side is subjected to a process (C2) of exposing a portion of the process (D1) to the portion other than the developed region in the post-process; on the first side, the film is treated with a thin film processing solution The first solder resist layer of the non-exposed portion is formed by thinning the thickness of the bonding pad or less to expose one of the bonding pads (B); and the first solder resist layer of the first surface is formed in the process (B) a process for exposing a portion of the thinned region (C3); a process for forming a second solder resist layer on the first solder resist layer on the first side of the circuit substrate until the (C3) process is completed (A2); The second solder mask on one side is implemented in the post-process (B3) a process for exposing a portion other than the thinned region (C6); a process for forming a thin film of the second solder resist layer in the non-exposed portion by the thin film processing liquid on the first surface in a range where the bonding pad is not exposed (B3) ; a second solder resist layer on the first surface, a process (C7) of exposing a portion of the process (D1) to the portion other than the developed region, and a second solder resist for removing the non-exposed portion of the first face by the developer The process (D1) of the first solder resist layer of the non-exposed portion of the layer and the second surface.

.(6)之配線基板的製造方法,係在製程(C1)之前,實施製程(C2)之上述(1)~(4)項之其中任一項所記載之配線基板的製造方法。 . (6) A method of manufacturing a wiring board according to any one of the above-mentioned items (1) to (4) of the process (C2) before the process (C1).

.(7)配線基板的製造方法,係同時實施製程(C1)及製程(C2)之上述(1)~(4)項之其中任一項所記載之配線基板的製造方法。 . (7) A method of manufacturing a wiring board according to any one of the above-mentioned items (1) to (4) of the process (C1) and the process (C2).

(8)之配線基板的製造方法,係以氧環境下之非接觸曝光方式來實施製程(C3)之曝光之上述(1)、(3)、(4)項之其中任一項所記載之配線基板的製造方法。 (8) A method of manufacturing a wiring board, which is described in any one of the above items (1), (3), and (4) by performing a process (C3) exposure by a non-contact exposure method in an oxygen atmosphere. A method of manufacturing a wiring board.

(9)之配線基板的製造方法,係以氧環境下之非接觸曝光方式來實施製程(C3)及製程(C7)之曝光之上述(5)所記載之配線基板的製造方法。 (9) A method of manufacturing a wiring board according to the above (5), which is a method of performing the process (C3) and the process (C7) by a non-contact exposure method in an oxygen atmosphere.

(10)之配線基板的製造方法,係以氧環境下之非接觸曝光方式來實施製程(C4)及製程(C5)之曝光之上述(2)所記載之配線基板的製造方法。 (10) A method of manufacturing a wiring board according to the above (2), which is a method of performing the process (C4) and the process (C5) by a non-contact exposure method in an oxygen atmosphere.

(11)之配線基板的製造方法,係製程(C3)之曝光量為製程(C1)之曝光量之1倍以上、5倍以下之上述(1)、(3)、(4)、(8)項之其中任一項所記載之配線基板的製造方法。 (11) The method of manufacturing the wiring board according to the above (1), (3), (4), (8) in which the exposure amount of the process (C3) is one time or more and five times or less the exposure amount of the process (C1). The method of manufacturing a wiring board according to any one of the items.

(12)之配線基板的製造方法,係製程(C3)及製程(C7)之曝光量為製程(C6)之曝光量之1倍以上、5倍以下之上述(5)或(9)所記載之配線基板的製造方法。 (12) The method of manufacturing the wiring board, wherein the exposure amount of the process (C3) and the process (C7) is 1 time or more and 5 times or less of the exposure amount of the process (C6), and the above (5) or (9) is described. A method of manufacturing a wiring board.

(13)之配線基板的製造方法,係製程(C4)及製程(C5)之曝光量為製程(C1)之曝光量之1倍以上、5倍以下之上述(2)或(10)所記載之配線基板的製造方法。 (13) The method of manufacturing the wiring board, wherein the exposure amount of the process (C4) and the process (C5) is 1 time or more and 5 times or less of the exposure amount of the process (C1), and the above (2) or (10) is described. A method of manufacturing a wiring board.

(14)之配線基板的製造方法,係製程(B)之防焊層的薄膜化處理以薄膜化處理面朝上來實施之上述(1)、(3)、(4)、(8)、(11)項之其中任一項所記載之配線基板的製造方法。 (14) The method for producing a wiring board, wherein the thinning treatment of the solder resist layer of the process (B) is performed by the thinning treatment surface (1), (3), (4), (8), A method of manufacturing a wiring board according to any one of the items 1 to 4.

(15)之配線基板的製造方法,係製程(B)及製程(B3)之防焊層的薄膜化處理以薄膜化處理面朝上來實施之上述(5)、(9)、(12)項之其中任一項所記載之配線基板的製造方法。 (15) The method for producing a wiring board, wherein the thinning treatment of the solder resist layer of the process (B) and the process (B3) is carried out with the thinned surface facing up (5), (9), and (12) A method of manufacturing a wiring board according to any one of the preceding claims.

(16)之配線基板的製造方法,係製程(B1)及製程(B2)之防焊層的薄膜化處理以薄膜化處理面朝上來實施之上述(2)、(10)、(13)項之其中任一項所記載之配線基板的製造方法。 (16) The method for producing a wiring board, wherein the thinning treatment of the solder resist layer of the process (B1) and the process (B2) is carried out with the thinned surface facing up (2), (10), and (13) A method of manufacturing a wiring board according to any one of the preceding claims.

依據本發明,可以提供一種配線基板的製造方法,係具有於兩表面具有絕緣層、及形成於絕緣層表面之連結墊的電路基板,於電路基板之兩表面,具有防焊層,使連結墊之一部分從防焊層露出之配線基板的製造方法,在配線基板的兩表面,從防焊層露出之連結墊間不會 發生電氣短路,此外,防焊層之殘渣不會殘留於露出之連結墊上。此外,依據本發明,可以提供一種印刷線路板之製造方法,可以得到連結墊與絕緣層及連結墊與焊劑之高接著強度,無填膠流出所導致的電氣作動不良,且防焊層強度高的印刷線路板。 According to the present invention, there is provided a method of manufacturing a wiring board, comprising: a circuit board having an insulating layer on both surfaces and a connection pad formed on a surface of the insulating layer; and having a solder resist layer on both surfaces of the circuit board to connect the pad A part of the method of manufacturing the wiring board exposed from the solder resist layer does not form between the bonding pads exposed from the solder resist layer on both surfaces of the wiring board. An electrical short circuit occurs, and the residue of the solder resist layer does not remain on the exposed bonding pads. In addition, according to the present invention, it is possible to provide a method for manufacturing a printed wiring board, which can obtain high bonding strength between the bonding pad and the insulating layer and the bonding pad and the flux, and the electrical operation failure caused by the outflow of the glue is not required, and the solder resist layer has high strength. Printed circuit board.

1‧‧‧電路基板 1‧‧‧ circuit substrate

2‧‧‧防焊層 2‧‧‧ solder mask

2-1‧‧‧第一防焊層 2-1‧‧‧First solder mask

2-2‧‧‧第二防焊層 2-2‧‧‧Second solder mask

3‧‧‧電子構件連結用連結墊、第一面之連結墊 3‧‧‧Connecting pads for electronic components and connecting pads for the first side

4‧‧‧外部連結用連結墊、第二面之連結墊 4‧‧‧Connecting mat for external connection and connecting mat for second side

5‧‧‧光罩 5‧‧‧Photomask

6‧‧‧活性光線 6‧‧‧Active light

7‧‧‧導體配線 7‧‧‧Conductor wiring

8‧‧‧絕緣層 8‧‧‧Insulation

第1圖係配線基板一例之概略剖面圖。 Fig. 1 is a schematic cross-sectional view showing an example of a wiring board.

第2圖係配線基板一例之概略剖面圖。 Fig. 2 is a schematic cross-sectional view showing an example of a wiring board.

第3圖係配線基板一例之概略剖面圖。 Fig. 3 is a schematic cross-sectional view showing an example of a wiring board.

第4圖係本發明之配線基板的製造方法一例之剖面製程圖。 Fig. 4 is a cross-sectional process view showing an example of a method of manufacturing a wiring board of the present invention.

第5圖係本發明之配線基板的製造方法一例之剖面製程圖。 Fig. 5 is a cross-sectional process view showing an example of a method of manufacturing a wiring board of the present invention.

第6圖係本發明之配線基板的製造方法一例之剖面製程圖。 Fig. 6 is a cross-sectional process view showing an example of a method of manufacturing a wiring board of the present invention.

第7圖係本發明之配線基板的製造方法一例之剖面製程圖。 Fig. 7 is a cross-sectional process view showing an example of a method of manufacturing a wiring board of the present invention.

第8圖係本發明之配線基板的製造方法一例之剖面製程圖。 Fig. 8 is a cross-sectional process view showing an example of a method of manufacturing a wiring board of the present invention.

第9圖係本發明所製造之配線基板一例的概略剖面圖。 Fig. 9 is a schematic cross-sectional view showing an example of a wiring board manufactured by the present invention.

第10圖係本發明所製造之配線基板一例的概略剖面 圖。 Fig. 10 is a schematic cross-sectional view showing an example of a wiring board manufactured by the present invention. Figure.

第11圖係本發明所製造之配線基板一例的概略剖面圖。 Fig. 11 is a schematic cross-sectional view showing an example of a wiring board manufactured by the present invention.

第12圖係本發明所製造之配線基板一例的概略剖面圖。 Fig. 12 is a schematic cross-sectional view showing an example of a wiring board manufactured by the present invention.

第13圖係多層電路基板一例之概略剖面圖。 Fig. 13 is a schematic cross-sectional view showing an example of a multilayer circuit substrate.

以下,針對本發明之配線基板的製造方法進行詳細說明。 Hereinafter, a method of manufacturing the wiring board of the present invention will be described in detail.

第4-1圖及第4-2圖係配線基板的製造方法(1)一例之剖面製程圖。準備兩表面具有絕緣層8、及形成於絕緣層8表面之導體配線7的電路基板。導體配線7之一部分係連結墊3及4。製程(A)時,於電路基板1之兩表面,以覆蓋全面之方式形成著防焊層2。第一面及第二面之防焊層2的形成上,可以兩表面同時實施,也可以逐面實施,然而,必須對應形成之防焊層厚度,設定不會過度熱硬化之加熱條件。兩表面之防焊層2的厚度不同,厚度較薄之一方為「第一面」,厚度較厚之一方為「第二面」。在兩表面,以相同條件形成防焊層2時,防焊層2之厚度,隨著包含各面之連結墊3及4在內的導體配線7密度而產生變化。第4-1圖時,下側之第二面之導體配線7密度大於上側之第一面,故第二面之導體配線7上的防焊層2厚度也大於第一面之導體配線7上的防焊層 2厚度。而且,配載電子構件之配線基板時,有時包含背面之外部連結用連結墊4在內之周圍導體配線7的密度大於包含表面之電子構件連結用連結墊3在內之周圍導體配線7密度,故表面為第一面,背面則為第二面。 FIGS. 4-1 and 4-2 are diagrams showing a method of manufacturing a wiring board (1). A circuit board having an insulating layer 8 on both surfaces and a conductor wiring 7 formed on the surface of the insulating layer 8 is prepared. One of the conductor wires 7 is connected to the pads 3 and 4. In the process (A), the solder resist layer 2 is formed on both surfaces of the circuit board 1 so as to cover the entire surface. The formation of the solder resist layer 2 on the first surface and the second surface may be performed simultaneously on both surfaces, or may be performed on a surface-by-side basis. However, it is necessary to set a heating condition that does not excessively harden the thickness of the solder resist layer to be formed. The thickness of the solder resist layer 2 on both surfaces is different, and one of the thinner sides is the "first side", and the one of the thicker ones is the "second side". When the solder resist layer 2 is formed under the same conditions on both surfaces, the thickness of the solder resist layer 2 changes in accordance with the density of the conductor wiring 7 including the connection pads 3 and 4 of the respective surfaces. In the case of FIG. 4-1, the density of the conductor wiring 7 on the second side of the lower side is larger than the first surface of the upper side, so that the thickness of the solder resist layer 2 on the conductor wiring 7 on the second side is also larger than that on the conductor wiring 7 of the first surface. Solder mask 2 thickness. In addition, when the wiring board of the electronic component is mounted, the density of the surrounding conductor wiring 7 including the external connection connecting pad 4 on the back surface may be larger than the density of the surrounding conductor wiring 7 including the electronic component connecting connecting pad 3 including the surface. Therefore, the surface is the first side and the back side is the second side.

製程(C1)時,對第一面之防焊層2,實施於後製程之製程(B)被薄膜化區域以外部分之曝光。製程(C2)時,對第二面之防焊層2,實施於後製程之製程(D)被顯影之區域以外部分的曝光。在防焊層2之經過曝光的部分,防焊劑產生光聚合,而對薄膜化製程及顯影製程具有耐性。 In the process (C1), the solder resist layer 2 on the first side is exposed to a portion other than the thinned region in the process (B) of the post-process. In the process (C2), the solder resist layer 2 on the second side is exposed to a portion other than the region where the process of the post-process (D) is developed. In the exposed portion of the solder resist layer 2, the solder resist generates photopolymerization, and is resistant to the thin film formation process and the development process.

製程(B)時,於第一面,以薄膜化處理液實施使非曝光部之防焊層2成為連結墊3之厚度以下為止的薄膜化,來使連結墊3之一部分露出。配載電子構件之配線基板時,於該製程(B),將露出之連結墊3當做電子構件連結用連結墊3來使用。製程(B)時,也同時實施第二面之非曝光部之防焊層2的薄膜化,然而,因為第二面之連結墊4上的防焊層2比第一面之連結墊3上的防焊層2更厚,防焊層2之殘渣殘留於連結墊4上。 In the case of the process (B), the film formation treatment liquid is used to form a thin film of the non-exposed portion of the solder resist layer 2 to a thickness equal to or less than the thickness of the connection pad 3, and a part of the connection pad 3 is exposed. When the wiring board of the electronic component is loaded, the exposed connection pad 3 is used as the connection pad 3 for electronic component connection in the process (B). In the process (B), the thin film formation of the solder resist layer 2 of the non-exposed portion of the second surface is simultaneously performed, however, since the solder resist layer 2 on the bonding pad 4 of the second surface is on the bonding pad 3 of the first surface. The solder resist layer 2 is thicker, and the residue of the solder resist layer 2 remains on the bonding pad 4.

製程(C3)時,對第一面之防焊層2,實施在製程(B)被薄膜化之區域部分的曝光。防焊層2之經過曝光的部分,防焊劑產生光聚合,而對顯影製程具有耐性。 In the process (C3), the solder resist layer 2 on the first side is exposed to a portion of the region where the process (B) is thinned. The exposed portion of the solder resist layer 2, the solder resist generates photopolymerization, and is resistant to the development process.

製程(D)時,於第二面,以顯影液除去非曝光部之防焊層2,來使連結墊4之一部分露出。藉由製程 (D),殘留於連結墊4上之防焊層2殘渣被除去。配載電子構件之配線基板時,將於該製程(D)露出之連結墊4當做外部連結用連結墊4來使用。在第一面之防焊層2,於製程(B)被薄膜化之區域部分,在製程(D)之前所實施的製程(C3)被曝光,對顯影製程具有耐性,而未被顯影液除去。 In the process (D), on the second surface, the solder resist layer 2 of the non-exposed portion is removed by a developing solution to expose a part of the bonding pad 4. By process (D), the residue of the solder resist layer 2 remaining on the connection pad 4 is removed. When the wiring board of the electronic component is placed, the connection pad 4 exposed in the process (D) is used as the external connection connection pad 4. In the solder mask layer 2 on the first side, in the portion where the process (B) is thinned, the process (C3) performed before the process (D) is exposed to be resistant to the development process without being removed by the developer. .

配線基板的製造方法(1)時,可以將製程(C1)之曝光區域變化成任意形狀,藉由曝光區域之變更,例如,可以製作如第9圖所示之剖面形狀的配線基板。第9之a圖時,於第一面之連結墊3間形成有防焊層2之凸部。第9之b圖時,於第一面,交互並列著為從防焊層2露出之連結墊3及防焊層2所覆蓋的導體配線7。 In the method (1) of manufacturing the wiring board, the exposure region of the process (C1) can be changed to an arbitrary shape, and by changing the exposure region, for example, a wiring board having a cross-sectional shape as shown in FIG. 9 can be produced. In the case of the ninth a diagram, the convex portion of the solder resist layer 2 is formed between the connection pads 3 on the first surface. In the case of the ninth b, the conductor wiring 7 covered by the connection pad 3 and the solder resist layer 2 exposed from the solder resist layer 2 is alternately arranged on the first surface.

第5-1圖、第5-2圖及第5-3圖,係配線基板的製造方法(2)一例之剖面製程圖。配線基板的製造方法(1)的不同,係於第一面,分別追加一次防焊層2之曝光製程及薄膜化製程。藉由覆晶連結將電子構件配載於配線基板時,因為電子構件與配線基板之熱膨漲係數差而承受到熱衝擊時,應力集中於連結部,而使連結部發生變形或被破壞。為了防止應力集中於連結部並提高連結信賴性,一般,以被稱為填膠之樹脂組成物來密封電子構件與配線基板之間。依據配線基板的製造方法(2),可以形成具有以堰塞充填於電子構件與配線基板之間之填膠為目的之堤壩構造之二段構造的防焊層。 FIGS. 5-1, 5-2, and 5-3 are cross-sectional process diagrams of an example of a method (2) of manufacturing a wiring board. In the method (1) for manufacturing the wiring board, the exposure process and the thinning process of the solder resist layer 2 are added once on the first surface. When the electronic component is placed on the wiring board by the flip chip connection, the thermal stress is applied to the connection portion due to the difference in thermal expansion coefficient between the electronic component and the wiring substrate, and the connection portion is deformed or broken. In order to prevent stress from being concentrated on the joint portion and improve the connection reliability, generally, a resin composition called a filler is used to seal the gap between the electronic component and the wiring board. According to the method (2) for manufacturing a wiring board, it is possible to form a solder resist layer having a two-stage structure of a bank structure for filling a gel between the electronic component and the wiring board.

製程(A)時,於電路基板1之兩表面,以覆 蓋全面之方式來形成防焊層2。製程(C1)時,對第一面之防焊層2,實施於後製程之製程(B1)被薄膜化區域以外部分之曝光。製程(C2)時,對第二面之防焊層2,實施於後製程之製程(D)被顯影之區域以外部分的曝光。 In the process (A), on both surfaces of the circuit substrate 1, The cover is formed in a comprehensive manner to form the solder resist layer 2. In the process (C1), the solder resist layer 2 on the first side is exposed to a portion of the post-process (B1) which is exposed outside the thinned region. In the process (C2), the solder resist layer 2 on the second side is exposed to a portion other than the region where the process of the post-process (D) is developed.

製程(B1)時,於第一面,在連結墊3未露出之範圍,以薄膜化處理液實施非曝光部之防焊層2的薄膜化。製程(B1)時,也同時對第二面之非曝光部的防焊層2實施薄膜化。 In the process (B1), the solder resist layer 2 of the non-exposed portion is thinned by the thin film processing liquid on the first surface in a range where the bonding pad 3 is not exposed. In the process (B1), the solder resist layer 2 of the non-exposed portion of the second surface is also thinned.

製程(C4)時,對第一面之防焊層2,實施於後製程之製程(B2)被薄膜化之區域以外部分的曝光。 In the process (C4), the solder resist layer 2 on the first side is exposed to a portion other than the thinned region of the process (B2) of the post-process.

製程(B2)時,於第一面,以薄膜化處理液實施使非曝光部之防焊層2成為連結墊3之厚度以下為止的薄膜化,來使連結墊3之一部分露出。配載電子構件之配線基板時,於該製程(B2),將露出之連結墊3當做電子構件連結用連結墊3來使用。製程(B2)時,也同時實施第二面之非曝光部之防焊層2的薄膜化,因為第二面之連結墊4上的防焊層2比第一面之連結墊3上的防焊層2更厚,防焊層2之殘渣殘留於連結墊4上。 In the process (B2), the film formation treatment liquid is used to form a thin film of the non-exposed portion of the solder resist layer 2 to a thickness equal to or less than the thickness of the connection pad 3 on the first surface, and a part of the connection pad 3 is exposed. When the wiring board of the electronic component is loaded, the exposed connection pad 3 is used as the connection pad 3 for electronic component connection in the process (B2). In the process (B2), the thinning of the solder resist layer 2 of the non-exposed portion of the second surface is also performed simultaneously, because the solder resist layer 2 on the bonding pad 4 of the second surface is more resistant than the bonding pad 3 of the first surface. The solder layer 2 is thicker, and the residue of the solder resist layer 2 remains on the connection pad 4.

製程(C5)時,對第一面之防焊層2,實施在製程(B2)被薄膜化之區域部分的曝光。 In the process (C5), the solder resist layer 2 on the first surface is exposed to a portion of the region where the process (B2) is thinned.

製程(D)時,於第二面,以顯影液除去非曝光部之防焊層2,來使連結墊4之一部分露出。藉由製程(D),殘留於連結墊4上之防焊層2殘渣被除去。配載電子構件之配線基板時,將於該製程(D)露出之連結墊 4當做外部連結用連結墊4來使用。 In the process (D), on the second surface, the solder resist layer 2 of the non-exposed portion is removed by a developing solution to expose a part of the bonding pad 4. By the process (D), the residue of the solder resist layer 2 remaining on the bonding pad 4 is removed. When the wiring board of the electronic component is loaded, the bonding pad which will be exposed in the process (D) 4 It is used as the external connection connection pad 4.

配線基板的製造方法(2)時,可以將製程(C4)之曝光區域變化成任意形狀,藉由曝光區域之變更,例如,可以製作第10圖所示之剖面形狀的配線基板。第10之c圖時,於第一面之連結墊3間形成有防焊層2之凸部。第10圖之d時,於第一面,交互並列著從防焊層2露出之連結墊3及被防焊層2覆蓋之導體配線7。 In the method (2) of manufacturing the wiring board, the exposure region of the process (C4) can be changed to an arbitrary shape, and by changing the exposure region, for example, a wiring board having a cross-sectional shape as shown in FIG. 10 can be produced. In the case of the 10th c, the convex portion of the solder resist layer 2 is formed between the connection pads 3 on the first surface. In the case of d in FIG. 10, on the first surface, the connection pads 3 exposed from the solder resist layer 2 and the conductor wirings 7 covered by the solder resist layer 2 are alternately arranged.

第6-1圖、第6-2圖及第6-3圖,係配線基板的製造方法(3)一例之剖面製程圖。與配線基板的製造方法(2)不同之點,係第一面之防焊層由第一防焊層2-1及第二防焊層2-2所構成。配線基板的製造方法(3)時,係進行使第一面之非曝光部的第一防焊層2-1之厚度成為連結墊3之厚度以下為止的薄膜化後,於第一防焊層2-1之表面上形成第二防焊層2-2,進行曝光後,進行非曝光部之第二防焊層2-2的顯影處理。藉此,與使用配線基板的製造方法(2)時相同,可以形成具有以堰塞充填於電子構件與配線基板之間之填膠為目的之堤壩構造之二段構造的防焊層。 Fig. 6-1, Fig. 6-2, and Fig. 6-3 are cross-sectional process diagrams of an example of a method (3) of manufacturing a wiring board. Unlike the manufacturing method (2) of the wiring board, the solder resist layer on the first surface is composed of the first solder resist layer 2-1 and the second solder resist layer 2-2. In the method (3) of manufacturing the wiring board, the thickness of the first solder resist layer 2-1 of the non-exposed portion of the first surface is reduced to a thickness equal to or less than the thickness of the connection pad 3, and then the first solder resist layer is formed. The second solder resist layer 2-2 is formed on the surface of 2-1, and after exposure, development processing of the second solder resist layer 2-2 of the non-exposed portion is performed. As a result, in the same manner as in the case of the manufacturing method (2) using the wiring board, it is possible to form a solder resist layer having a two-stage structure of a bank structure for filling the plug between the electronic component and the wiring board.

製程(A1)時,於電路基板1之第一面與第二面,形成有厚度不同之第一防焊層2-1。第一面與第二面之第一防焊層2-1的形成,可以兩表面同時也可逐片實施,但必須對應所形成之防焊層的厚度,來設定不會過度熱硬化之加熱條件。 In the process (A1), the first solder resist layer 2-1 having a different thickness is formed on the first surface and the second surface of the circuit board 1. The formation of the first solder mask layer 2-1 on the first surface and the second surface may be performed on both surfaces at the same time or in one piece, but the heat of the solder resist layer formed may be set corresponding to the thickness of the solder resist layer formed. condition.

製程(C1)時,對厚度比第二面之第一防焊層2-1更薄之第一面的第一防焊層2-1,實施於後製程之製程(B)被薄膜化區域以外部分之曝光。製程(C2)時,對第二面之第一防焊層2-1,實施於後製程之製程(D1)被顯影之區域以外部分的曝光。 In the process (C1), the first solder resist layer 2-1 having a first surface thinner than the first solder resist layer 2-1 of the second surface is subjected to a post-process (B) thinned region. Exposure to the outside part. In the process (C2), the first solder resist layer 2-1 on the second surface is exposed to a portion other than the region where the process (D1) of the post-process is developed.

製程(B)時,於第一面,以薄膜化處理液實施使非曝光部之第一防焊層2-1成為連結墊3之厚度以下為止的薄膜化,來使連結墊3之一部分露出。製程(B)時,第二面之非曝光部的第一防焊層2-1也同時被薄膜化。然而,因為第二面之連結墊4上之第一防焊層2-1比第一面之連結墊3上之第一防焊層2-1更厚,於連結墊4上,殘留著第一防焊層2-1之殘渣。 In the case of the process (B), the first solder resist layer 2-1 of the non-exposed portion is formed into a film thickness equal to or less than the thickness of the connection pad 3 on the first surface, and a part of the connection pad 3 is exposed. . In the process (B), the first solder resist layer 2-1 of the non-exposed portion of the second surface is also thinned at the same time. However, since the first solder resist layer 2-1 on the bonding pad 4 of the second surface is thicker than the first solder resist layer 2-1 on the bonding pad 3 of the first surface, the bonding pad 4 remains on the bonding pad 4 A residue of the solder resist layer 2-1.

製程(C3)時,對第一面之第一防焊層2-1,實施於製程(B)被薄膜化之區域部分的曝光。 In the process (C3), the first solder resist layer 2-1 on the first surface is exposed to a portion of the region where the process (B) is thinned.

製程(A2)時,於完成至製程(C3)為止之電路基板之第一面的第一防焊層2-1,形成第二防焊層2-2。此時,調整第一面之第二防焊層2-2的相關加熱條件,來使第二面之第一防焊層2-1的非曝光部不會發生過度熱硬化。 In the process (A2), the second solder resist layer 2-2 is formed on the first solder resist layer 2-1 on the first surface of the circuit board until the process (C3). At this time, the relevant heating conditions of the second solder resist layer 2-2 of the first surface are adjusted so that the non-exposed portion of the first solder resist layer 2-1 of the second surface is not excessively thermally hardened.

製程(C6)時,對第一面之第二防焊層2-2,實施於後製程之製程(D1)被顯影區域以外部分之曝光。 In the process (C6), the second solder resist layer 2-2 on the first surface is subjected to a post-process (D1) exposure to a portion other than the developing region.

製程(D1)時,以顯影液除去第一面之非曝光部的第二防焊層2-2及第二面之非曝光部的第一防焊層2-1,來使連結墊3及4之一部分露出。以製程(D1), 除去殘留於連結墊4上之第一防焊層2-1的殘渣。配載電子構件之配線基板時,於該製程(D1)露出之連結墊3被當做電子構件連結用連結墊3來使用,連結墊4則被當做外部連結用連結墊4來使用。 In the process (D1), the second solder resist layer 2-2 of the non-exposed portion of the first surface and the first solder resist layer 2-1 of the non-exposed portion of the second surface are removed by the developer to bond the pad 3 and One of the 4 parts is exposed. With process (D1), The residue of the first solder resist layer 2-1 remaining on the bonding pad 4 is removed. When the wiring board of the electronic component is mounted, the connection pad 3 exposed in the process (D1) is used as the connection pad 3 for electronic component connection, and the connection pad 4 is used as the connection pad 4 for external connection.

第7-1圖、第7-2圖及第7-3圖,係配線基板的製造方法(4)一例之剖面製程圖。與配線基板的製造方法(3)不同之點,係在形成第一面之第二防焊層2-2前,以顯影液除去第二面之第一防焊層2-1。首先,在以顯影液除去第二面之非曝光部的第一防焊層2-1來形成第一面之第二防焊層2-2時,無需實施同時對第二面之非曝光部的第一防焊層2-1進行加熱來避免過度熱硬化之加熱條件調整。配線基板的製造方法(4)時,與使用配線基板的製造方法(2)及(3)時相同,可以形成具有以堰塞充填於電子構件與配線基板之間之填膠為目的之堤壩構造之二段構造的防焊層。 Fig. 7-1, Fig. 7-2, and Fig. 7-3 are cross-sectional process diagrams of an example of a method (4) of manufacturing a wiring board. Unlike the manufacturing method (3) of the wiring board, the first solder resist layer 2-1 of the second surface is removed by the developer before the second solder resist layer 2-2 of the first surface is formed. First, when the first solder resist layer 2-2 of the first surface is formed by removing the first solder resist layer 2-1 of the non-exposed portion of the second surface by the developer, it is not necessary to perform the non-exposed portion of the second surface at the same time. The first solder resist layer 2-1 is heated to avoid adjustment of heating conditions for excessive thermal hardening. In the manufacturing method (4) of the wiring board, as in the case of using the manufacturing methods (2) and (3) of the wiring board, it is possible to form a bank structure having a purpose of filling the gap between the electronic component and the wiring board with a plug. The solder mask of the second section.

製程(A1)時,於電路基板1之第一面與第二面,形成有厚度不同之第一防焊層2-1。製程(C1),對厚度比第二面之第一防焊層2-1更薄之第一面之第一防焊層2-1,實施於後製程之製程(B)被薄膜化區域以外部分之曝光。製程(C2)時,對第二面之第一防焊層2-1,實施於後製程之製程(D)被顯影之區域以外部分的曝光。 In the process (A1), the first solder resist layer 2-1 having a different thickness is formed on the first surface and the second surface of the circuit board 1. In the process (C1), the first solder resist layer 2-1 having a first surface thinner than the first solder resist layer 2-1 of the second surface is disposed outside the thinned region in the process (B) of the post-process Partial exposure. In the process (C2), the first solder resist layer 2-1 on the second surface is exposed to a portion other than the region where the process of the post-process (D) is developed.

製程(B)時,於第一面,以薄膜化處理液實施使非曝光部之第一防焊層2-1成為連結墊3之厚度以下 為止之薄膜化,來使連結墊3之一部分露出。製程(B)時,第二面之非曝光部的第一防焊層2-1也同時被薄膜化。然而,因為第二面之連結墊4上的第一防焊層2-1比第一面之連結墊3上的第一防焊層2-1更厚,連結墊4上殘留著第一防焊層2-1之殘渣。 In the process (B), the first solder resist layer 2-1 of the non-exposed portion is made to have a thickness equal to or less than the thickness of the connection pad 3 on the first surface. As soon as it is thinned, a part of the connection pad 3 is exposed. In the process (B), the first solder resist layer 2-1 of the non-exposed portion of the second surface is also thinned at the same time. However, since the first solder resist layer 2-1 on the bonding pad 4 of the second surface is thicker than the first solder resist layer 2-1 on the bonding pad 3 of the first surface, the first anti-resistance remains on the bonding pad 4. The residue of the solder layer 2-1.

製程(C3)時,對第一面之第一防焊層2-1,實施於製程(B)被薄膜化之區域部分的曝光。 In the process (C3), the first solder resist layer 2-1 on the first surface is exposed to a portion of the region where the process (B) is thinned.

製程(D)時,以顯影液除去第二面之非曝光部的第一防焊層2-1,來使連結墊4之一部分露出。藉由製程(D),殘留於連結墊4上之第一防焊層2-1的殘渣被除去。配載電子構件之配線基板時,將於該製程(D)露出之連結墊4當做外部連結用連結墊4來使用。 In the process (D), the first solder resist layer 2-1 of the non-exposed portion of the second surface is removed by a developing solution to expose a part of the bonding pad 4. By the process (D), the residue of the first solder resist layer 2-1 remaining on the bonding pad 4 is removed. When the wiring board of the electronic component is placed, the connection pad 4 exposed in the process (D) is used as the external connection connection pad 4.

製程(A2)時,於完成至製程(D)為止之電路基板之第一面的第一防焊層2-1上,形成第二防焊層2-2。 In the process (A2), the second solder resist layer 2-2 is formed on the first solder resist layer 2-1 on the first surface of the circuit board until the process (D) is completed.

製程(C6)時,對第一面之第二防焊層2-2,實施於後製程之製程(D2)被顯影區域以外部分之曝光。 In the process (C6), the second solder resist layer 2-2 on the first surface is subjected to a post-process (D2) exposure to a portion other than the developed region.

製程(D2)時,以顯影液除去第一面之非曝光部的第二防焊層2-2,來使連結墊3之一部分露出。配載電子構件之配線基板時,將於製程(D2)被露出之連結墊3當做電子構件連結用連結墊3來使用。 In the process (D2), the second solder resist layer 2-2 of the non-exposed portion of the first surface is removed by a developing solution to expose a part of the bonding pad 3. When the wiring board of the electronic component is mounted, the connection pad 3 which exposes the process (D2) is used as the connection pad 3 for electronic component connection.

配線基板的製造方法(3)及(4)時,可以將製程(C1)之曝光區域變化成任意形狀,藉由曝光區域之變更,例如,可以製作第11圖所示之剖面形狀的配線 基板。第11之e圖時,於第一面之連結墊3之間,形成有第一防焊層2-1之凸部。第11之f圖時,交互並列著從第一防焊層2-1露出之連結墊3及為第一防焊層2-1所覆蓋之導體配線7。 In the method (3) and (4) of manufacturing the wiring board, the exposure region of the process (C1) can be changed to an arbitrary shape, and by changing the exposure region, for example, the wiring of the cross-sectional shape shown in Fig. 11 can be produced. Substrate. In the eleventh figure, the convex portion of the first solder resist layer 2-1 is formed between the connection pads 3 on the first surface. In the case of Fig. 11 f, the connection pads 3 exposed from the first solder resist layer 2-1 and the conductor wirings 7 covered by the first solder resist layer 2-1 are alternately arranged.

第8-1圖、第8-2圖及第8-3圖,係配線基板的製造方法(5)一例之剖面製程圖。配線基板的製造方法(5)時,係於第一面,在對第一防焊層2-1實施曝光前,實施使第一防焊層2-1之厚度成為連結墊3之厚度以下為止之薄膜化處理。其後,於第一防焊層2-1之表面上形成第二防焊層2-2並曝光後,實施非曝光部之第二防焊層2-2的薄膜化處理,其後,再度執行曝光,執行殘餘之非曝光部之第二防焊層2-2的顯影處理。配線基板的製造方法(5)時,與使用配線基板的製造方法(2)~(4)時相同,可以形成具有以堰塞充填於電子構件與配線基板之間之填膠為目的之堤壩構造之二段構造的防焊層。 Figs. 8-1, 8-2, and 8-3 are cross-sectional process diagrams of an example of a method (5) of manufacturing a wiring board. In the method (5) of manufacturing the wiring board, the thickness of the first solder resist layer 2-1 is set to be equal to or less than the thickness of the connection pad 3 before the first solder resist layer 2-1 is exposed on the first surface. Thin film treatment. Thereafter, after the second solder resist layer 2-2 is formed on the surface of the first solder resist layer 2-1 and exposed, the second solder resist layer 2-2 of the non-exposed portion is subjected to thinning treatment, and thereafter, again Exposure is performed, and development processing of the second solder resist layer 2-2 of the remaining non-exposed portion is performed. In the manufacturing method (5) of the wiring board, as in the case of using the manufacturing methods (2) to (4) of the wiring board, it is possible to form a bank structure having a purpose of filling the gap between the electronic component and the wiring board with a plug. The solder mask of the second section.

製程(A1)時,於電路基板1之第一面與第二面,形成有厚度不同之第一防焊層2-1。製程(C2)時,對第二面之第一防焊層2-1,實施於後製程之製程(D1)被顯影區域以外部分之曝光。 In the process (A1), the first solder resist layer 2-1 having a different thickness is formed on the first surface and the second surface of the circuit board 1. In the process (C2), the first solder resist layer 2-1 on the second surface is subjected to a post-process (D1) exposure to a portion other than the developed region.

製程(B)時,於第一面,以薄膜化處理液實施使非曝光部之第一防焊層2-1成為連結墊3之厚度以下為止之薄膜化,來使所有的連結墊3之一部分露出。製程(B)時,第二面之非曝光部的第一防焊層2-1也同時被薄膜化。然而,因為第二面之連結墊4上的第一防焊層2- 1比第一面之連結墊3上的第一防焊層2-1更厚,連結墊4上殘留著第一防焊層2-1之殘渣。 In the case of the process (B), the first solder resist layer 2-1 of the non-exposed portion is formed into a thin film at a thickness equal to or less than the thickness of the bonding pad 3 on the first surface, so that all the bonding pads 3 are formed. Part of it is exposed. In the process (B), the first solder resist layer 2-1 of the non-exposed portion of the second surface is also thinned at the same time. However, because the first solder resist layer 2 on the bonding pad 4 of the second side 1 is thicker than the first solder resist layer 2-1 on the connection pad 3 of the first surface, and the residue of the first solder resist layer 2-1 remains on the connection pad 4.

製程(C3)時,對第一面之第一防焊層2-1,實施於製程(B)被薄膜化之區域部分的曝光。 In the process (C3), the first solder resist layer 2-1 on the first surface is exposed to a portion of the region where the process (B) is thinned.

製程(A2)時,於完成至製程(C3)為止之電路基板之第一面的第一防焊層2-1上,形成第二防焊層2-2。 In the process (A2), the second solder resist layer 2-2 is formed on the first solder resist layer 2-1 on the first surface of the circuit board until the process (C3) is completed.

製程(C6)時,對第一面之第二防焊層2-2,實施於後製程之製程(B3)被薄膜化區域以外部分之曝光。 In the process (C6), the second solder resist layer 2-2 on the first surface is exposed to a portion of the post-process (B3) which is exposed outside the thinned region.

製程(B3)時,於第一面,在連結墊3未露出之範圍,以薄膜化處理液實施非曝光部之第二防焊層2-2的薄膜化。製程(B3)時,第二面之非曝光部的第一防焊層2-1也同時被薄膜化。然而,有時連結墊4上殘留著第一防焊層2-1之殘渣。 In the process (B3), on the first surface, in the range where the connection pad 3 is not exposed, the second solder resist layer 2-2 of the non-exposed portion is thinned by the thin film processing liquid. In the process (B3), the first solder resist layer 2-1 of the non-exposed portion of the second surface is also thinned at the same time. However, the residue of the first solder resist layer 2-1 may remain on the bonding pad 4.

製程(C7)時,對第一面之第二防焊層2-2,實施於後製程之製程(D1)被顯影區域以外部分之曝光。 In the process (C7), the second solder resist layer 2-2 on the first surface is subjected to a post-process (D1) exposure to a portion other than the developed region.

製程(D1)時,以顯影液除去第一面之非曝光部的第二防焊層2-2及第二面之非曝光部的第一防焊層2-1,使連結墊3之一部分再度露出,同時,使連結墊4之一部分露出。藉由製程(D1),殘留於連結墊4上之第一防焊層2-1的殘渣被除去。配載電子構件之配線基板時,將該製程(D1)所露出之連結墊3當做電子構件連結用連結墊3來使用,將連結墊4當做外部連結用連結墊4 來使用。 In the process (D1), the second solder resist layer 2-2 of the non-exposed portion of the first surface and the first solder resist layer 2-1 of the non-exposed portion of the second surface are removed by a developing solution to make a part of the bonding pad 3 It is exposed again, and at the same time, a part of the connection pad 4 is exposed. By the process (D1), the residue of the first solder resist layer 2-1 remaining on the bonding pad 4 is removed. When the wiring board of the electronic component is mounted, the connection pad 3 exposed by the process (D1) is used as the connection pad 3 for electronic component connection, and the connection pad 4 is used as the connection pad 4 for external connection. To use.

配線基板的製造方法(5)時,可以將製程(C7)之曝光區域變化成任意形狀,藉由曝光區域之變更,例如,可以製作第12圖所示之剖面形狀的配線基板。第12之g圖時,於第一面之連結墊3間,形成有第二防焊層2-2之凸部。第12之h圖時,交互並列著從第一防焊層2-1露出之連結墊3、及為第一防焊層2-1及第二防焊層2-2所覆蓋之導體配線7。 In the manufacturing method (5) of the wiring board, the exposure region of the process (C7) can be changed to an arbitrary shape, and by changing the exposure region, for example, a wiring board having a cross-sectional shape as shown in Fig. 12 can be produced. In the case of the 12th g, the convex portion of the second solder resist layer 2-2 is formed between the connection pads 3 on the first surface. In the case of the 12th h, the connection pads 3 exposed from the first solder resist layer 2-1 and the conductor wiring 7 covered by the first solder resist layer 2-1 and the second solder resist layer 2-2 are alternately arranged. .

本發明之電路基板1,具有絕緣層8、及形成於絕緣層8表面之連結墊3、4。於絕緣層8表面,形成有導體配線7,連結墊3、4係導體配線7之一部分。本發明之配線基板,於電路基板1之兩表面具有防焊層2,連結墊3、4之一部分從防焊層2露出。配載電子構件之配線基板時,於表面具有電子構件連結用連結墊3,於背面具有外部連結用連結墊4。表面之電子構件連結用連結墊3用以接合電子構件,背面之外部連結用連結墊4則用以接合外部電氣基板之導體配線。 The circuit board 1 of the present invention has an insulating layer 8 and connection pads 3 and 4 formed on the surface of the insulating layer 8. On the surface of the insulating layer 8, a conductor wiring 7 is formed, and one of the pads 3 and 4 is connected to the conductor wiring 7. In the wiring board of the present invention, the solder resist layer 2 is provided on both surfaces of the circuit board 1, and one of the connection pads 3, 4 is exposed from the solder resist layer 2. When the wiring board of the electronic component is mounted, the electronic component connection connection pad 3 is provided on the surface, and the external connection connection pad 4 is provided in the back surface. The electronic component connecting connection pad 3 on the surface is used to bond the electronic component, and the external connection connecting pad 4 on the back surface is used to bond the conductor wiring of the external electrical substrate.

本發明之電路基板,例如,係於配設著導體配線之絕緣基板,交互疊層增建用絕緣層及導體配線來製作。第13A、B圖,係於配設著導體配線之絕緣基板交互疊層著增建用絕緣層及導體配線所製作之電路基板一例的概略剖面圖。第4~8圖係本發明之配線基板的製造方法一例的剖面製程圖,在依據本發明所製造之配線基板一例之概略剖面圖的第9~12圖中,記載著具有一層之絕緣層 8且具有形成於絕緣層8之兩表面之導體配線7的電路基板1,然而,使用於本發明之配線基板的製造方法之電路基板1,如第13A、B圖所示,係於配設有導體配線之絕緣基板交互疊層著增建用絕緣層及導體配線來製作,包含於兩表面具有絕緣層8、及形成於絕緣層8表面之導體配線7的電路基板1在內。絕緣基板,例如,由使玻璃布含浸有雙馬來醯亞胺-三氮雜苯樹脂或環氧樹脂等之熱硬化性樹脂的電氣絕緣材料等所構成之樹脂製基板。增建用絕緣層,例如,與絕緣基板相同之使玻璃布含浸有熱硬化性樹脂之電氣絕緣材料、或使氧化矽等無機填料分散於環氧樹脂等熱硬化性樹脂之電氣絕緣材料等。導體配線,例如,係以消去法、半加法、加法等來形成。消去法時,例如,於絕緣層上形成銅層後,形成抗蝕層,實施曝光、顯影、蝕刻、去除光阻,來形成導體配線。半加法時,於絕緣層表面,以無電解銅電鍍來配設電解銅電鍍用之基底金屬層。其次,形成具有對應導體配線之開口的電鍍抗蝕層,而於因電解銅電鍍而露出之基底金屬層的表面,形成電解銅電鍍層。其後,剝離電鍍抗蝕層,以閃蝕除去露出之基底金屬層,即可形成導體配線。 The circuit board of the present invention is produced, for example, by an insulating substrate on which conductor wirings are disposed, and an insulating layer for conductor lamination and conductor wiring. 13A and FIG. B are schematic cross-sectional views showing an example of a circuit board produced by laminating an insulating layer and a conductor wiring in an insulating substrate in which conductor wirings are arranged. 4 to 8 are cross-sectional process diagrams showing an example of a method of manufacturing a wiring board of the present invention, and FIGS. 9 to 12 of a schematic cross-sectional view of an example of a wiring board manufactured according to the present invention, showing an insulating layer having one layer. 8 and the circuit board 1 having the conductor wirings 7 formed on the both surfaces of the insulating layer 8, but the circuit board 1 used in the method of manufacturing the wiring board of the present invention is arranged as shown in Figs. 13A and B The insulating substrate having the conductor wiring is formed by alternately laminating the insulating layer for insulation and the conductor wiring, and is included in the circuit board 1 having the insulating layer 8 and the conductor wiring 7 formed on the surface of the insulating layer 8 on both surfaces. The insulating substrate is, for example, a resin substrate made of an electrical insulating material or the like which is made of a thermosetting resin such as a bismaleimide-triazole resin or an epoxy resin. The insulating layer for the build-up is, for example, an electrical insulating material in which a glass cloth is impregnated with a thermosetting resin, or an inorganic insulating material such as cerium oxide is dispersed in an electrical insulating material such as a thermosetting resin such as an epoxy resin. The conductor wiring is formed, for example, by elimination, semi-addition, addition, or the like. In the erasing method, for example, after a copper layer is formed on the insulating layer, a resist layer is formed, and exposure, development, etching, and photoresist removal are performed to form a conductor wiring. In the case of the semi-addition, an underlying metal layer for electrolytic copper plating is disposed on the surface of the insulating layer by electroless copper plating. Next, an electroplated resist layer having an opening corresponding to the conductor wiring is formed, and an electrolytic copper plating layer is formed on the surface of the underlying metal layer exposed by electrolytic copper plating. Thereafter, the plating resist is peeled off, and the exposed underlying metal layer is removed by flash etching to form a conductor wiring.

配載電子構件之配線基板時,配線基板表面之連結墊,係用以連結電子構件之連結用墊。電子構件,介由該連結墊與焊劑凸塊來電氣連結,被覆晶組裝於配線基板。為了提高防焊層之黏著性,也可進行連結墊表面之粗面化處理、或耦合劑處理。配線基板背面之連結墊,係 以外部連結為目的的連結用墊。介由焊劑凸塊,將該連結墊與主機板等外部電氣基板之導體配線進行電氣連結,來覆晶組裝於主機板。 When the wiring board of the electronic component is mounted, the connection pad on the surface of the wiring board is used to connect the connection pads of the electronic component. The electronic component is electrically connected to the solder bump via the connection pad, and the coated crystal is assembled on the wiring substrate. In order to improve the adhesion of the solder resist layer, roughening treatment or coupling agent treatment may be performed on the surface of the bonding pad. The connection pad on the back of the wiring board A connection pad for external connection. The connection pad is electrically connected to the conductor wiring of the external electrical board such as the motherboard via the solder bump, and is flip-chip mounted on the motherboard.

本發明之防焊劑,可以使用鹼性顯影型防焊劑。此外,1液性、2液性的任一液狀防焊劑皆可,也可以為乾膜光阻。防焊劑,例如,含有鹼溶性樹脂、單官能壓克力單體、多官能壓克力單體、光起始劑、環氧樹脂、無機填料等。 As the solder resist of the present invention, an alkaline development type solder resist can be used. Further, either a liquid-based or two-liquid liquid solder resist may be used, or a dry film photoresist may be used. The solder resist includes, for example, an alkali-soluble resin, a monofunctional acrylic monomer, a polyfunctional acrylic monomer, a photoinitiator, an epoxy resin, an inorganic filler, and the like.

鹼溶性樹脂,例如,具有光硬化性及熱硬化性之兩方特性的鹼溶性樹脂,例如,對附加有丙烯酸之酚醛型環氧樹脂而環氧壓克力化樹脂的2級羥基附加酸酐的樹脂。多官能壓克力單體,例如,三羥甲基丙烷三丙烯酸酯(Trimethylol Propane Triacrylate)、二新戊四醇聚丙烯酸酯(Di-pentaerythritol Polyacrylate)、季戊四醇三丙烯酸酯(Pentaerythritol Triacrylate)等。光起始劑,例如,2-甲基-1-(4-甲基苯硫基)-2-瑪啉基正丙醇-1-酮(2-Methyl-1-(4-Methylthiophenyl)-2-Morpholinopropan-1-one)等。環氧樹脂,當做硬化劑來使用。以使其與鹼溶性樹脂之羧酸產生反應來進行架橋,謀求提高耐熱性及耐藥性之特性,然而,因為羧酸與環氧基在常溫也會產生反應,保存安定性差,鹼性顯影型防焊劑,一般都採用在使用前進行混合之2液性形態。無機填料,例如,滑石、矽石、硫酸鋇、氧化鈦、氧化鋅等。 The alkali-soluble resin is, for example, an alkali-soluble resin having both photocurability and thermosetting properties, for example, a secondary hydroxy group-added acid anhydride of an epoxy acryl resin and an epoxy acryl resin. Resin. A polyfunctional acrylic monomer, for example, Trimethylol Propane Triacrylate, Di-pentaerythritol Polyacrylate, Pentaerythritol Triacrylate, or the like. Photoinitiator, for example, 2-methyl-1-(4-methylphenylthio)-2- morphine-n-propyl-1-one (2-Methyl-1-(4-Methylthiophenyl)-2 -Morpholinopropan-1-one) and so on. Epoxy resin, used as a hardener. By bridging with a carboxylic acid of an alkali-soluble resin, bridging is carried out, and the characteristics of heat resistance and chemical resistance are improved. However, since a carboxylic acid and an epoxy group react at normal temperature, storage stability is poor, and alkali development is performed. Type solder resists are generally in a two-liquid form that is mixed prior to use. Inorganic fillers, for example, talc, vermiculite, barium sulfate, titanium oxide, zinc oxide, and the like.

防焊層,在電路基板之兩表面,係以覆蓋全 面之方式來形成。防焊層之形成上,例如,液狀防焊劑的話,可以使用網版印刷法、輥塗法、噴霧法、浸漬法、幕塗法、棒塗法、氣刀法、熱熔法、凹版塗佈法、毛刷塗佈法、套版印刷法。此外,膜狀防焊劑的話,使用疊合法及真空疊合法。 The solder resist layer is covered on both surfaces of the circuit board The way to form. For the formation of the solder resist layer, for example, a liquid solder resist, a screen printing method, a roll coating method, a spray method, a dipping method, a curtain coating method, a bar coating method, an air knife method, a hot melt method, and a gravure coating method can be used. Cloth method, brush coating method, and plate printing method. In addition, in the case of a film-like solder resist, a stacking method and a vacuum stacking method are used.

以配線基板的製造方法(1)及(2)之製程(A)所形成的防焊層2、及以配線基板的製造方法(3)~(5)之製程(A1)所形成的第一防焊層2-1,在電路基板之兩表面的厚度不同,厚度較薄之一方為「第一面」,厚度較厚之一方為「第二面」。於電路基板之兩表面形成防焊層時,一般係對兩表面設定相同條件。其係因為防焊劑具有熱硬化性。液狀防焊劑時,因為在塗佈後必須實施以去溶劑為目的的加熱乾燥,各表面之塗佈量不同的話,就必須依各表面變更乾燥條件,然而,其時,又必須設定不會過度熱硬化之條件。此外,乾膜光阻時,因為疊合時必須加熱,各表面若使用厚度不同之乾膜光阻的話,就必須依各表面變更疊合時的加熱條件,然而,其時,又必須設定不會過度熱硬化之條件。如上所示,不改變各表面之防焊層厚度、加熱乾燥條件等,而採用兩表面之防焊層種類、厚度、加熱乾燥條件等相同之條件,可以使作業製程較為簡單而較佳。 The solder resist layer 2 formed by the manufacturing method (1) and (2) of the wiring board, and the first method (A1) of the wiring board manufacturing method (3) to (5) The solder resist layer 2-1 has a thickness different from each other on both surfaces of the circuit board, and one of the thinner portions is the "first surface", and the thicker one is the "second surface". When a solder resist layer is formed on both surfaces of a circuit board, the same conditions are generally set for both surfaces. This is because the solder resist has thermosetting properties. In the case of a liquid solder resist, since it is necessary to perform heat drying for the purpose of solvent removal after coating, if the coating amount of each surface is different, it is necessary to change the drying conditions depending on each surface. However, it is necessary to set the drying conditions. Conditions for excessive heat hardening. In addition, in the case of dry film photoresist, since it is necessary to heat during lamination, if dry film photoresists having different thicknesses are used for each surface, it is necessary to change the heating conditions at the time of lamination according to each surface. However, at this time, it is necessary to set Conditions that will be excessively hardened. As described above, the thickness of the solder resist layer on each surface, the heating and drying conditions, and the like are not changed, and the same conditions as those of the solder resist layer on both surfaces, the thickness, and the heating and drying conditions can be used to make the work process simpler and more preferable.

於電路基板之兩表面,以相同條件形成防焊層時,防焊層之厚度,隨著包含各面之連結墊在內之周圍的導體配線密度而變化。例如,於配載電子構件之配線基 板,背面之外部連結用連結墊配列成區域陣列型時,相較於表面之包含電子構件連結用連結墊在內之周圍的導體配線密度,背面之包含外部連結用連結墊在內之周圍的導體配線密度較大。結果,背面之外部連結用連結墊上的防焊層厚度,比表面之電子構件連結用連結墊上的防焊層厚度更厚。此時,表面為第一面,背面為第二面。 When the solder resist layer is formed under the same conditions on both surfaces of the circuit board, the thickness of the solder resist layer varies depending on the density of the conductor wiring around the connection pads of the respective surfaces. For example, a wiring base for loading electronic components When the outer surface of the panel is connected to the area array by the connection pad, the density of the conductor wiring around the surface including the connection pad for the electronic component connection is included in the periphery of the back surface including the external connection connection pad. The conductor wiring density is large. As a result, the thickness of the solder resist layer on the connection pads for external connection on the back surface is thicker than the thickness of the solder resist layer on the connection pads for electronic component connection on the surface. At this time, the surface is the first side and the back side is the second side.

本發明之防焊層被薄膜化的製程,係包含:以薄膜化處理液進行非曝光部之防焊層成份之膠束化的膠束化處理(薄膜化處理)、及以膠束除去液除去膠束之膠束除去處理在內的製程。此外,也可以包含:以水洗來清洗未除去之膠束、殘存薄膜化處理液、及膠束除去液的水洗處理、及除去水洗水之乾燥處理在內。 The process for thinning the solder resist layer of the present invention comprises a micellization treatment (thinning treatment) of micelleizing the solder resist layer of the non-exposed portion by a thin film processing liquid, and a micelle removing liquid The process of removing the micelles of the micelles is removed. Further, the method may include: washing the unremoved micelles with water, washing the remaining thin film processing liquid, and the micelle removing liquid, and drying the water washing water.

薄膜化處理(膠束化處理),係指以薄膜化處理液實施非曝光部之防焊層成份的膠束化,來使該膠束不溶於薄膜化處理液的處理。 The film formation treatment (myiselation treatment) refers to a treatment in which the micelle of the solder resist layer of the non-exposed portion is subjected to micellization by the thin film treatment liquid to make the micelle insoluble in the thin film treatment liquid.

本發明之薄膜化處理液,可以使用鹼性水溶液。可以做為薄膜化處理液使用之鹼性水溶液,例如,鹼金屬矽酸鹽(Alkali Metal Silicate)、鹼金屬氫氧化物(Alkali Metal Hydroxide)、鹼金屬磷酸鹽(Alkali Metal Phosphate)、鹼金屬碳酸鹽(Alkali Metal Carbonate)、銨磷酸鹽、銨碳酸鹽等之無機鹼性化合物的水溶液;單乙醇胺、二乙醇胺、三乙醇胺、甲胺、二甲胺、乙胺、二乙胺、三乙胺、環己胺、四甲基氫氧化銨(Tetramethylammonium Hydroxide、TMAH)、四乙基氫 氧化銨、三甲基-2-羥乙基氫氧化氨(膽鹼、Choline)等之有機鹼性化合物的水溶液。鹼金屬,例如,鋰、鈉、鉀等。上述無機鹼性化合物及有機鹼性化合物,可以單獨使用,也可以複數組合來使用。也可以使用無機鹼性化合物與有機鹼性化合物之組合。 As the film forming treatment liquid of the present invention, an alkaline aqueous solution can be used. It can be used as an alkaline aqueous solution for use as a thin film treatment liquid, for example, Alkali Metal Silicate, Alkali Metal Hydroxide, Alkali Metal Phosphate, alkali metal carbonate An aqueous solution of an inorganic basic compound such as a salt (Alkali Metal Carbonate), an ammonium phosphate or an ammonium carbonate; monoethanolamine, diethanolamine, triethanolamine, methylamine, dimethylamine, ethylamine, diethylamine, triethylamine, Cyclohexylamine, Tetramethylammonium Hydroxide, TMAH, Tetraethyl Hydrogen An aqueous solution of an organic basic compound such as ammonium oxide or trimethyl-2-hydroxyethylammonium hydroxide (choline, Choline). An alkali metal such as lithium, sodium, potassium or the like. The inorganic basic compound and the organic basic compound may be used singly or in combination of plural kinds. Combinations of inorganic basic compounds with organic basic compounds can also be used.

此外,為了使防焊層表面更均一地薄膜化,也可以於薄膜化處理液添加硫酸鹽、亞硫酸鹽。硫酸鹽或亞硫酸鹽,例如,鋰、鈉或鉀等之鹼金屬硫酸鹽或亞硫酸鹽、鎂、鈣等之鹼土類金屬硫酸鹽或亞硫酸鹽。 Further, in order to make the surface of the solder resist layer more uniform, it is also possible to add a sulfate or a sulfite to the thin film processing liquid. Sulfate or sulfite, for example, an alkali metal sulfate or a sulfite of magnesium, sodium or potassium, or an alkaline earth metal sulfate or sulfite of magnesium or calcium.

薄膜化處理液,於該等中,又以含有從鹼金屬碳酸鹽、鹼金屬磷酸鹽、鹼金屬氫氧化物、鹼金屬矽酸鹽所選取之無機鹼性化合物、及從TMAH(四甲基氫氧化銨)、膽鹼所選取之有機鹼性化合物當中之任1種,且該無機鹼性化合物及有機鹼性化合物之含有量為3~25質量%的薄膜化處理液,因為可以使表面更均一地薄膜化而更適合使用。未滿3質量%時,有時薄膜化處理容易發生不均。此外,超過25質量%的話,有時容易發生無機鹼性化合物析出,而使液之時效安定性、作業性變差。鹼性化合物之含有量為5~20質量%更佳,7~15質量%最好。薄膜化處理液之pH,以10以上為佳。此外,也可以適度添加界面活性劑、消泡劑、溶劑等。 a thin film treatment liquid in which an inorganic basic compound selected from alkali metal carbonates, alkali metal phosphates, alkali metal hydroxides, alkali metal silicates, and TMAH (tetramethyl group) are further contained. Any one of the organic basic compounds selected from the group consisting of ammonium hydroxide and choline, and the content of the inorganic basic compound and the organic basic compound is 3 to 25% by mass of the thin film treatment liquid because the surface can be made It is more uniform and thinner and more suitable for use. When it is less than 3% by mass, the film formation treatment may be uneven. In addition, when it exceeds 25% by mass, precipitation of an inorganic basic compound may occur easily, and the aging stability and workability of the liquid may be deteriorated. The content of the basic compound is preferably 5 to 20% by mass, more preferably 7 to 15% by mass. The pH of the film-forming treatment liquid is preferably 10 or more. Further, a surfactant, an antifoaming agent, a solvent, or the like may be added as appropriate.

防焊層之薄膜化時,不溶於防焊層中所含有之薄膜化處理液之無機填料的存在不能忽視。無機填料之尺寸隨著其種類而不同,具有從被稱為奈米填料之超微米 級至較大之數十微米為止之某種程度的粒度分布,以30~70質量%之含有量存在於層中。薄膜化,在鹼性化合物浸透至防焊層後,於膠束除去過程進行防焊層成份之膠束化,然而,因為不溶性無機填料的存在,鹼性化合物之浸透獲得抑制,而使薄膜化速度變慢。 When the solder resist layer is thinned, the presence of the inorganic filler which is insoluble in the thin film processing liquid contained in the solder resist layer cannot be ignored. The size of the inorganic filler varies with its type and has a supermicron called nanofiller. A certain particle size distribution up to a few tens of micrometers is present in the layer in an amount of 30 to 70% by mass. Thin film formation, after the alkaline compound is impregnated into the solder resist layer, the micelle of the solder resist layer is subjected to the micelle removal process. However, due to the presence of the insoluble inorganic filler, the impregnation of the basic compound is suppressed, and the thin film is formed. The speed is slower.

針對此種無機填料所導致之鹼性化合物的浸透阻礙,只要使薄膜化處理液之pH成為12.5以上即可,13.0以上更佳。薄膜化處理液之pH愈高,則鹼性化合物浸透時之防焊層的膨潤愈大,而不易受到無機填料所導致之浸透阻礙的影響。 The impregnation of the basic compound by the inorganic filler is not particularly limited as long as the pH of the thin film treatment liquid is 12.5 or more, and more preferably 13.0 or more. The higher the pH of the film-forming treatment liquid, the larger the swelling of the solder resist layer when the alkaline compound is impregnated, and the less susceptible to the impregnation of the inorganic filler.

於本發明,以薄膜化使第一面之連結墊的一部分露出時,該露出之連結墊,可以當做電子構件連結用連結墊來使用。通常,連結墊表面被粗面化,利用其錨定效果來提高連結墊與防焊層之黏著性,而可維持長時間之高絕緣信賴性。傳統之防焊圖案形成上,除去防焊層來使連結墊表面露出時,一般係將分散能力優良之低濃度碳酸鈉水溶液當做顯影液來使用,於連結墊表面幾乎不會發生防焊層之殘渣。然而,使用低濃度之碳酸鈉水溶液來實施防焊層之薄膜化的話,無法得到面內均一之薄膜化,而發生面內不均。 In the present invention, when a part of the connection pads of the first surface is exposed by thinning, the exposed connection pads can be used as the connection pads for electronic component connection. Usually, the surface of the connection pad is roughened, and the anchoring effect is used to improve the adhesion between the connection pad and the solder resist layer, and the high insulation reliability for a long period of time can be maintained. In the conventional solder resist pattern formation, when the solder resist layer is removed to expose the surface of the bonding pad, a low-concentration sodium carbonate aqueous solution having excellent dispersing ability is generally used as a developing solution, and a solder resist layer hardly occurs on the surface of the bonding pad. Residue. However, when the film of the solder resist layer is formed by using a low-concentration sodium carbonate aqueous solution, the in-plane uniform film formation cannot be obtained, and the in-plane unevenness occurs.

薄膜化處理液之溫度,以15~35℃為佳,最好為20~30℃。溫度太低的話,有時鹼性化合物對防焊層之浸透速度變慢,進行期望厚度之薄膜化需要較長的時間。另一方面,溫度太高的話,因為膠束除去過程與防焊 層成份之膠束化同時進行,有時容易於面內發生膜厚不均,而應避免。 The temperature of the thin film treatment liquid is preferably 15 to 35 ° C, preferably 20 to 30 ° C. When the temperature is too low, the penetration speed of the alkaline compound to the solder resist layer may be slow, and it takes a long time to form a thin film of a desired thickness. On the other hand, if the temperature is too high, because of the micelle removal process and soldering prevention The micelleization of the layer components is carried out at the same time, and sometimes the film thickness unevenness is likely to occur in the plane, and should be avoided.

在利用薄膜化處理液之薄膜化處理時,可以採用浸漬處理、漿攪拌處理、噴霧處理、塗刷、刮削等方法,然而,以浸漬處理為佳。浸漬處理以外之處理方法,薄膜化處理液中容易發生氣泡,發生之氣泡在薄膜化中附著於防焊層表面,有時會有膜厚不均一的情形。使用噴霧處理等時,以不會發生氣泡之方式來儘量縮小噴霧壓為佳。 In the thin film formation treatment by the thin film treatment liquid, a method such as immersion treatment, slurry agitation treatment, spray treatment, painting, and scraping may be employed. However, the immersion treatment is preferred. In the treatment method other than the immersion treatment, bubbles are likely to be generated in the thin film-forming treatment liquid, and the generated bubbles adhere to the surface of the solder resist layer during film formation, and the film thickness may be uneven. When using a spray treatment or the like, it is preferred to minimize the spray pressure so that bubbles do not occur.

在以薄膜化處理液實施薄膜化處理後,實施除去不溶於薄膜化處理液之防焊層成份之膠束的膠束除去處理時,以膠束除去液之噴霧來一舉溶解除去膠束。 After the film formation treatment is carried out by the film formation treatment liquid, and the micelle removal treatment for removing the micelles of the solder resist component which is insoluble in the film formation treatment liquid is carried out, the micelles are dissolved and removed by the spray of the micelle removal liquid.

膠束除去液,可以使用自來水、工業用水、純水等。此外,將含有從鹼金屬碳酸鹽、鹼金屬磷酸鹽、鹼金屬矽酸鹽所選取之無機鹼性化合物當中之任1種之pH5~10的水溶液當做膠束除去液來使用,容易使不溶於薄膜化處理液之防焊層成份再分散。膠束除去液之Ph為未滿5時,防焊層成份可能聚集而成為不溶性之泥渣,並附著於薄膜化之防焊層表面。另一方面,膠束除去液之pH超過10時,同時促進防焊層成份之膠束化與膠束除去過程,面內容易發生膜厚不均。此外,膠束除去液,可以使硫酸、磷酸、鹽酸等來調整pH。 As the micelle removing liquid, tap water, industrial water, pure water or the like can be used. Further, an aqueous solution containing pH 5 to 10 of any one of an inorganic basic compound selected from an alkali metal carbonate, an alkali metal phosphate or an alkali metal citrate is used as a micelle removing liquid, and is easily dissolved. The solder resist component of the filming treatment liquid is redispersed. When the Ph of the micelle removing liquid is less than 5, the solder resist layer may aggregate to become insoluble sludge and adhere to the surface of the thinned solder resist layer. On the other hand, when the pH of the micelle removing liquid exceeds 10, the micelleization of the solder resist layer and the micelle removal process are promoted, and the film thickness unevenness is likely to occur in the surface. Further, the micelle removing liquid can adjust the pH by sulfuric acid, phosphoric acid, hydrochloric acid or the like.

針對膠束除去處理之噴霧條件來進行說明。噴霧條件(溫度、時間、噴霧壓),係配合薄膜化處理之 防焊層的溶解速度來進行適度調整。具體而言,處理溫度以10~50℃為佳,22~50℃更佳。水溶液之溫度為未滿10℃時,有時會發生防焊層成份的溶解不良,而容易使防焊層之殘渣殘留於粗面化之連結墊表面。另一方面,超過50℃的話,可能發生水溶液的蒸發或連續運轉之溫度管理的問題,而使裝置設計上受到限制,應避免。此外,噴霧壓以0.01~0.5MPa為佳,0.1~0.3MPa更佳。膠束除去液之供給流量,以防焊層每1cm2為0.030~1.0L/min為佳,0.050~1.0L/min更佳,最好為0.10~1.0L/min。供給流量在該範圍內的話,不溶解成份不會殘留於薄膜化後之防焊層表面,而可以在面內大致均一地除去膠束。防焊層每1cm2的供給流量為未滿0.030L/min時,有時防焊層之不溶解成份會殘留。另一方面,供給流量超過1.0L/min的話,供給所需要的泵等構件較為龐大,有時還要大規模的裝置。此外,超過1.0L/min之供給量時,防焊層成份之溶解除去效果沒有改變。 The spray conditions for the micelle removal treatment will be described. The spray conditions (temperature, time, and spray pressure) were appropriately adjusted in accordance with the dissolution rate of the solder resist layer of the film formation treatment. Specifically, the treatment temperature is preferably 10 to 50 ° C, and more preferably 22 to 50 ° C. When the temperature of the aqueous solution is less than 10 ° C, the solder resist component may be poorly dissolved, and the residue of the solder resist layer may be easily left on the surface of the roughened joint pad. On the other hand, if it exceeds 50 ° C, the problem of temperature management of evaporation or continuous operation of the aqueous solution may occur, and the design of the apparatus is limited and should be avoided. Further, the spray pressure is preferably 0.01 to 0.5 MPa, more preferably 0.1 to 0.3 MPa. The supply flow rate of the micelle removing liquid is preferably 0.030 to 1.0 L/min per 1 cm 2 of the solder resist layer, more preferably 0.050 to 1.0 L/min, and most preferably 0.10 to 1.0 L/min. When the supply flow rate is within this range, the insoluble component does not remain on the surface of the solder resist layer after the film formation, and the micelle can be removed substantially uniformly in the plane. When the supply flow rate per 1 cm 2 of the solder resist layer is less than 0.030 L/min, the insoluble component of the solder resist layer may remain. On the other hand, when the supply flow rate exceeds 1.0 L/min, components such as pumps required for supply are large, and large-scale devices are sometimes required. Further, when the supply amount exceeds 1.0 L/min, the effect of dissolving and removing the solder resist layer is not changed.

第一面所露出之連結墊3周圍之防焊層2與第一防焊層2-1的厚度、以及做為填膠堰塞用堤壩之一部分之防焊層2、第一防焊層2-1與第二防焊層2-2的厚度,由配線基板的製造方法(1)與(2)之製程(A)、及配線基板的製造方法(3)~(5)之製程(A1)與(A2)之形成於第一面的防焊層2、第一防焊層2-1與第二防焊層2-2之厚度、及配線基板的製造方法(1)、(3)~(5)之製程(B)、配線基板的製造方法(2)之 製程(B1)與(B2)、配線基板的製造方法(5)之製程(B3)之第一面非曝光部之防焊層2、第一防焊層2-1與第二防焊層2-2的薄膜化量所決定。此外,本發明時,可以在0.01~500μm之範圍內,適度自由地實施薄膜化量調整。被薄膜化至連結墊之厚度以下為止之防焊層2、至從第一防焊層2-1表面所露出之連結墊3表面為止的高度,其後,可以對應必要之焊劑量來進行適度調整。此外,做為填膠堰塞用堤壩之一部分的防焊層2、第一防焊層2-1、及第二防焊層2-2之厚度,可以對應電子構件之大小、電子構件之連結端子的大小、以及充填於電子構件與配線基板之間的填膠量來進行適度調整。 The thickness of the solder resist layer 2 and the first solder resist layer 2-1 around the bonding pad 3 exposed on the first surface, and the solder resist layer 2 as the part of the dam for filling the plug, the first solder resist layer 2 -1 and the thickness of the second solder resist layer 2-2, the manufacturing method of the wiring board (1) and (2), and the manufacturing method of the wiring board (3) to (5) (A1) The thickness of the solder resist layer 2 formed on the first surface of (A2), the thickness of the first solder resist layer 2-1 and the second solder resist layer 2-2, and the method of manufacturing the wiring board (1), (3) Process (B) of ~(5), manufacturing method of wiring board (2) The solder mask 2, the first solder resist layer 2-1 and the second solder resist layer 2 of the non-exposed portion of the first surface of the process (B1) and (B2), the process (5) of the method for manufacturing the wiring substrate (B3) The amount of filming of -2 is determined. Further, in the case of the present invention, the filming amount can be appropriately adjusted in a range of 0.01 to 500 μm. The height of the solder resist layer 2 which is thinned to the thickness of the connection pad to the surface of the connection pad 3 exposed from the surface of the first solder resist layer 2-1, and thereafter, can be appropriately adjusted in accordance with the necessary solder amount. Adjustment. In addition, the thickness of the solder resist layer 2, the first solder resist layer 2-1, and the second solder resist layer 2-2, which is part of the dam for filling the plug, may correspond to the size of the electronic component and the connection of the electronic component. The size of the terminal and the amount of glue filled between the electronic component and the wiring substrate are appropriately adjusted.

配線基板的製造方法(6),在配線基板的製造方法(1)~(4)之製程(C1)前,實施製程(C2)。此外,配線基板的製造方法(7),係同時實施配線基板的製造方法(1)~(4)的製程(C1)及製程(C2)。如上所示,配線基板的製造方法(1)~(4)時,可以更替製程(C1)與製程(C2)之順序,也可以同時實施製程(C1)及製程(C2)。 In the method (6) of manufacturing the wiring board, the process (C2) is performed before the process (C1) of the method (1) to (4) of the method of manufacturing the wiring board. Further, in the method (7) of manufacturing the wiring board, the process (C1) and the process (C2) of the manufacturing methods (1) to (4) of the wiring board are simultaneously performed. As described above, in the manufacturing method (1) to (4) of the wiring board, the order of the process (C1) and the process (C2) may be replaced, or the process (C1) and the process (C2) may be simultaneously performed.

配線基板的製造方法(1)之製程(C1)時,係對第一面之防焊層2,選擇性地實施後製程之製程(B)所薄膜化之區域以外部分的曝光。配線基板的製造方法(2)之製程(C1)時,係對第一面之防焊層2,選擇性地實施後製程之製程(B1)所薄膜化之區域以外部分的曝光。配線基板的製造方法(3)及(4)之製程(C1) 時,係對第一面之第一防焊層2-1,選擇性地實施後製程之製程(B)所薄膜化之區域以外部分的曝光。配線基板的製造方法(2)之製程(C4)時,係對第一面之防焊層2,選擇性地實施後製程之製程(B2)所薄膜化之區域以外部分的曝光。配線基板的製造方法(3)之製程(C6)及配線基板的製造方法(5)之製程(C7)時,係對第一面之第二防焊層2-2,選擇性地實施後製程之製程(D1)所顯影之區域以外部分的曝光。配線基板的製造方法(4)之製程(C6)時,係對第一面之第二防焊層2-2,選擇性地實施後製程之製程(D2)所顯影之區域以外部分的曝光。配線基板的製造方法(5)之製程(C6)時,係對第一面之第二防焊層2-2,實施於後製程之製程(B3)被薄膜化區域以外部分之曝光。被曝光之防焊劑,產生光聚合,防焊層2、第一防焊層2-1、及第二防焊層2-2產生硬化。在第4-1圖~第8-3圖中,係介由光罩5進行活性光線6之曝光,然而,也可以直接描繪方式來實施。曝光方式,例如,可以為以氙燈、高壓水銀燈、低壓水銀燈、超高壓水銀燈、UV螢光燈做為光源之反射影像曝光方式、及採用光罩之接觸曝光方式、近接方式、投射方式及雷射掃描曝光方式等。第一面之「被薄膜化區域」,例如,係連結墊上或包含連結墊之間在內之連結墊的周圍區域。更具體而言,係以配載電子構件為目的之安裝區域及其周圍。 In the process (C1) of the method of manufacturing the wiring board (1), the solder resist layer 2 on the first surface is selectively exposed to a portion other than the region thinned by the process (B) of the post-process. In the process (C1) of the method for manufacturing the wiring board (2), the solder resist layer 2 on the first surface is selectively exposed to a portion other than the region thinned by the process (B1) of the post-process. Manufacturing method (3) and (4) of wiring board (C1) In the case of the first solder resist layer 2-1 on the first side, the exposure of the portion other than the thinned region of the process (B) of the post-process is selectively performed. In the process (C4) of the method for manufacturing the wiring board (2), the solder resist layer 2 on the first surface is selectively exposed to a portion other than the region thinned by the process (B2) of the post-process. In the process (C6) of the method for manufacturing the wiring substrate (3) and the process (C7) for the method of manufacturing the wiring substrate (5), the second solder resist layer 2-2 on the first surface is selectively subjected to a post process. The exposure of the portion outside the area developed by the process (D1). In the process (C6) of the method (4) of manufacturing the wiring board, the second solder resist layer 2-2 on the first surface is selectively exposed to a portion other than the region developed by the process (D2) of the post-process. In the process (C6) of the method (5) for manufacturing the wiring board, the second solder resist layer 2-2 on the first surface is exposed to a portion other than the thinned region in the post-process (B3) process. The exposed solder resist generates photopolymerization, and the solder resist layer 2, the first solder resist layer 2-1, and the second solder resist layer 2-2 are hardened. In the drawings 4-1 to 8-3, the exposure of the active light 6 is performed by the mask 5, but it can also be carried out by direct drawing. The exposure mode may be, for example, a reflection image exposure method using a xenon lamp, a high pressure mercury lamp, a low pressure mercury lamp, an ultra high pressure mercury lamp, a UV fluorescent lamp as a light source, and a contact exposure method using a reticle, a proximity method, a projection method, and a laser. Scan exposure method, etc. The "thinned region" on the first side is, for example, a peripheral region of the connection pad on the connection pad or including the connection pads. More specifically, it is a mounting area for the purpose of loading an electronic component and its surroundings.

配線基板的製造方法(1)與(2)之製程 (C2)時,係對第二面之防焊層2,選擇性地實施後製程之製程(D)所顯影之區域以外部分的曝光。配線基板的製造方法(4)之製程(C2)時,係對第二面之第一防焊層2-1,選擇性地實施後製程之製程(D)所顯影之區域以外部分的曝光。配線基板的製造方法(3)與(5)之製程(C2)時,係對第二面之第一防焊層2-1,選擇性地實施後製程之製程(D1)所顯影之區域以外部分的曝光。被曝光之防焊劑,產生光聚合,防焊層2及第一防焊層2-1產生硬化。曝光方式,可以使用與上述配線基板的製造方法(1)之製程(C1)等相同的方式。第二面之「被顯影區域」,例如,係連結墊上或包含連結墊之間在內之連結墊的周圍區域。更具體而言,係以安裝外部電氣基板之導體配線為目的而使配置成區域陣列(Area array)型之連結墊的一部分露出之圓形開口部區域。 Manufacturing method of wiring board (1) and (2) In the case of (C2), the solder resist layer 2 on the second surface is selectively exposed to a portion other than the region developed by the process (D) of the post-process. In the process (C2) of the method (4) of manufacturing the wiring board, the first solder resist layer 2-1 on the second surface is selectively exposed to a portion other than the region developed by the process (D) of the post-process. In the manufacturing method (3) of the wiring board and the process (C2) of (5), the first solder resist layer 2-1 on the second surface is selectively subjected to the process of developing the post-process (D1). Part of the exposure. The exposed solder resist generates photopolymerization, and the solder resist layer 2 and the first solder resist layer 2-1 are hardened. The exposure method can be the same as the process (C1) of the above-described method (1) of manufacturing the wiring board. The "developed region" of the second surface is, for example, a peripheral region of the connection pad on the connection pad or including the connection pads. More specifically, for the purpose of mounting the conductor wiring of the external electric board, a circular opening portion region in which a part of the connection pad of the area array type is exposed is exposed.

配線基板的製造方法(1)之製程(C3)時,係對第一面之防焊層2,實施於製程(B)被薄膜化之區域部分的曝光。配線基板的製造方法(3)~(5)之製程(C3)時,係對第一面之第一防焊層2-1,實施於製程(B)被薄膜化之區域部分的曝光。配線基板的製造方法(2)之製程(C5)時,係對第一面之防焊層2,實施於製程(B2)被薄膜化之區域部分的曝光。曝光方式,可以使用與上述配線基板的製造方法(1)之製程(C1)等相同的方式。配線基板的製造方法(1)、(3)~(5)之製程(C3)及配線基板的製造方法(2)之製程(C5) 後,因為有非曝光部之防焊層2、第一防焊層2-1、第二防焊層2-2被顯影除去之製程(配線基板的製造方法(1)、(2)及(4)之製程(D)、配線基板的製造方法(3)及(5)之製程(D1)、以及配線基板的製造方法(4)之製程(D2)),而必須實施形成最終防焊層之區域的曝光,來使防焊劑產生光聚合。配線基板的製造方法(1)、(3)、(4)之製程(C3)之曝光部分,至少包含於製程(B)被薄膜化之區域在內,以包含製程(C1)所曝光之部分及製程(B)所薄膜化之區域的境界部在內為佳。此外,配線基板的製造方法(2)之製程(C5)的曝光部分,至少包含於製程(B2)被薄膜化之區域在內,以包含製程(C4)所曝光之部分及製程(B2)所薄膜化之區域的境界部在內為佳。 In the process (C3) of the method (1) of manufacturing the wiring board, the solder resist layer 2 on the first surface is exposed to a portion of the region where the process (B) is thinned. In the manufacturing method (3) to (5) of the wiring board (C3), the first solder resist layer 2-1 on the first surface is exposed to a portion of the region where the process (B) is thinned. In the process (C5) of the method (2) of manufacturing the wiring board, the solder resist layer 2 on the first surface is exposed to a portion of the region where the process (B2) is thinned. The exposure method can be the same as the process (C1) of the above-described method (1) of manufacturing the wiring board. Process for manufacturing wiring board (1), process (3) to (5) (C3), and process for manufacturing wiring board (2) (C5) After that, the solder resist layer 2 of the non-exposed portion, the first solder resist layer 2-1, and the second solder resist layer 2-2 are developed and removed (the manufacturing method (1), (2), and (of the wiring board) 4) Process (D), manufacturing method (3) of wiring board, process (D1) of (5), and process (D2) of manufacturing method (4) of wiring board, and it is necessary to implement formation of final soldering layer Exposure of the area to cause photopolymerization of the solder resist. The exposed portion of the manufacturing method (1), (3), and (4) of the wiring substrate is included in at least the portion of the process (B) which is thinned, and includes the portion exposed by the process (C1). And the boundary between the thinned areas of the process (B) is better. Further, the exposed portion of the process (C5) of the method for manufacturing the wiring substrate (2) is included at least in the region where the process (B2) is thinned, and includes the portion exposed by the process (C4) and the process (B2). The realm of the thinned area is better.

配線基板的製造方法(1)~(4)之製程(C1)、配線基板的製造方法(1)、(3)~(5)之製程(C3)、配線基板的製造方法(1)~(5)之製程(C2)、配線基板的製造方法(2)之製程(C4)及(C5)、配線基板的製造方法(3)~(5)之製程(C6)、以及配線基板的製造方法(5)之製程(C7)的曝光量,可以對應防焊劑之感光度來適度決定。具體而言,配線基板的製造方法(1)、(3)~(5)之製程(B)、配線基板的製造方法(2)之製程(B1)與(B2)、以及配線基板的製造方法(5)之製程(B3)時,所使用之薄膜化處理液,或者,配線基板的製造方法 (1)、(2)、(4)之製程(D)、配線基板的製造方法(3)及(5)之製程(D1)、以及配線基板的製造方法(4)之製程(D2)時,只要對所使用之顯影液,防焊劑不會溶解或膨潤之程度,使防焊劑產生光聚合並硬化即可,通常為100~600mJ/cm2Method for manufacturing wiring board (1) to (4) (C1), method for manufacturing wiring board (1), (3) to (5), (C3), wiring board manufacturing method (1)~( 5) Process (C2), Process for Manufacturing a Wiring Substrate (2) Process (C4) and (C5), Process for Manufacturing a Wiring Substrate (3) to (5) Process (C6), and Method of Manufacturing a Wiring Substrate (5) The exposure amount of the process (C7) can be appropriately determined according to the sensitivity of the solder resist. Specifically, the manufacturing method (1) of the wiring board, the process (B) of (3) to (5), the process (B1) and (B2) of the manufacturing method (2) of the wiring board, and the manufacturing method of the wiring board (5) Process (B3), thin film processing liquid used, or manufacturing method of wiring board (1), (2), (4) process (D), wiring board manufacturing method (3) In the process (D1) of (5) and the process (D2) of the method of manufacturing the wiring board (4), the solder resist is photopolymerized as long as the solder resist is not dissolved or swollen to the developer used. And it can be hardened, usually 100~600mJ/cm 2 .

配線基板的製造方法(1)、(3)、(4)之製程(C3)、配線基板的製造方法(2)之製程(C4)與(C5)、配線基板的製造方法(5)之製程(C3)與製程(C7)的曝光,以在氧環境下之非接觸曝光方式來實施為佳。非接觸曝光方式,例如,於光罩與配線基板之間配設間隙而以非接觸方式來實施曝光之近接方式、投射方式、以及未使用光罩之直接描繪方式。在防焊層2、第一防焊層2-1、以及第二防焊層2-2上沒有支撐層膜的狀態下,實施氧環境下之非接觸曝光,各防焊層之表層附近(從防焊層表面之深度0~0.5μm程度)的光聚合,在氧的影響下受到妨礙而成為未硬化部分,只有離開表層之部位才會硬化。所以,藉由配線基板的製造方法(1)之製程(D)、配線基板的製造方法(2)之製程(B2)與(D)、配線基板的製造方法(3)之製程(D1)、配線基板的製造方法(4)之製程(D)與(D2)、配線基板的製造方法(5)之製程(D1),除去表層附近之未硬化部分,而使防焊層2、第一防焊層2-1、以及第二防焊層2-2的表面被粗面化。位於配線基板表面之電子構件連結用連結墊周圍的防焊層表面被粗面化時,相較於平滑時, 填膠之黏著性更為強固,結果,可以防止熱衝擊所導致之應力集中於電子構件與配線基板的連結部,而進一步提高連結信賴性。藉由氧環境下之非接觸方式曝光來實施防焊層2、第一防焊層2-1、以及第二防焊層2-2之表面的粗面化,可以提高填膠之黏著性,而得到高連結信賴性。提高填膠之黏著性上,防焊層之表面粗細度Ra以0.30μm以上、0.50μm以下為佳。表面粗細度Ra超過0.50μm的話,防焊強度降低,有時無法得到絕緣信賴性。表面粗細度Ra為算術平均表面粗細度。 Process for manufacturing wiring board (1), (3), (4), (C3), wiring board manufacturing method (2), (C4) and (C5), and wiring board manufacturing method (5) The exposure of (C3) and process (C7) is preferably carried out in a non-contact exposure mode in an oxygen atmosphere. The non-contact exposure method is, for example, a proximity method in which a gap is disposed between the photomask and the wiring substrate, and a direct contact method in which the exposure is performed in a non-contact manner, a projection method, and a direct drawing method in which the photomask is not used. In the state in which the support layer film is not provided on the solder resist layer 2, the first solder resist layer 2-1, and the second solder resist layer 2-2, non-contact exposure in an oxygen atmosphere is performed, and the vicinity of the surface layer of each solder resist layer is Photopolymerization from the surface of the solder resist layer to a depth of 0 to 0.5 μm is hindered by the influence of oxygen and becomes an uncured portion, and only the portion which leaves the surface layer is hardened. Therefore, the process (D) of the method (1) of manufacturing the wiring board, the processes (B2) and (D) of the method (2) of manufacturing the wiring board, the process (D1) of the method (3) of manufacturing the wiring board, Process (D) and (D2) of the manufacturing method (4) of the wiring board, and the process (D1) of the manufacturing method (5) of the wiring board, the uncured portion near the surface layer is removed, and the solder resist layer 2 is prevented. The surfaces of the solder layer 2-1 and the second solder resist layer 2-2 are roughened. When the surface of the solder resist layer around the connection pad for electronic component connection on the surface of the wiring board is roughened, when compared with smoothing, The adhesiveness of the glue is stronger, and as a result, the stress caused by the thermal shock can be prevented from being concentrated on the joint portion between the electronic component and the wiring board, and the connection reliability can be further improved. The surface of the solder resist layer 2, the first solder resist layer 2-1, and the second solder resist layer 2-2 is roughened by non-contact exposure in an oxygen atmosphere, thereby improving the adhesion of the filler. And get high link reliability. In order to improve the adhesion of the filler, the surface roughness Ra of the solder resist layer is preferably 0.30 μm or more and 0.50 μm or less. When the surface roughness Ra exceeds 0.50 μm, the solder resist strength is lowered, and insulation reliability may not be obtained. The surface roughness Ra is an arithmetic mean surface thickness.

配線基板的製造方法(1)、(3)、(4)之製程(C3)、及配線基板的製造方法(2)之製程(C4)與(C5)的曝光量,以製程(C1)之曝光量的1倍以上、5倍以下為佳,最好為1.5倍以上、3倍以下。同樣的,配線基板的製造方法(5)之製程(C3)與製程(C7)的曝光量,以製程(C6)之曝光量的1倍以上、5倍以下為佳,最好為1.5倍以上、3倍以下。氧環境下之非接觸曝光時,藉由提供比防焊劑不會被溶解或膨潤之程度而可硬化之必要曝光量更多的曝光量,可以將防焊層表面之氧所導致之聚合妨礙抑制於最小。曝光量愈多,對聚合妨礙之抑制有其效果,然而,另一方面,曝光量太多的話,不但防焊劑之解析度惡化,曝光時間也會過長,故應避免。 The exposure amount of the manufacturing method (1), (3), (4) of the wiring substrate (C3), and the manufacturing process (C4) and (C5) of the manufacturing method of the wiring substrate, by the process (C1) The exposure amount is preferably 1 time or more and 5 times or less, and more preferably 1.5 times or more and 3 times or less. Similarly, the exposure amount of the process (C3) and the process (C7) of the method (5) for manufacturing the wiring substrate is preferably 1 time or more and 5 times or less, more preferably 1.5 times or more, of the exposure amount of the process (C6). , 3 times or less. In the non-contact exposure in an oxygen environment, by providing an exposure amount which is more than necessary for the solder resist to be dissolved or swollen, the polymerization caused by oxygen on the surface of the solder resist layer can be inhibited from being inhibited. At the smallest. The larger the amount of exposure, the more effective the suppression of polymerization hindrance. However, if the amount of exposure is too large, the resolution of the solder resist is deteriorated and the exposure time is too long, so it should be avoided.

配線基板的製造方法(1)、(3)~(5)之製程(B)、及配線基板的製造方法(2)之製程(B2) 時,於第一面,以薄膜化處理液實施使非曝光部之防焊層2、及第一防焊層2-1成為連結墊3之厚度以下為止的薄膜化,來使連結墊3之一部分露出。配線基板的製造方法(2)之製程(B1)、及配線基板的製造方法(5)之製程(B3)時,於第一面,在連結墊3未露出之範圍,以薄膜化處理液實施非曝光部之防焊層2、第二防焊層2-2的薄膜化。使用膜狀防焊劑來配設支撐層膜時,剝離支撐層膜後再執行薄膜化。 Process for manufacturing wiring board (1), process (B) of (3) to (5), and process for manufacturing wiring board (2) (B2) At the time of the first surface, the solder resist layer 2 and the first solder resist layer 2-1 of the non-exposed portion are formed into a film thickness equal to or less than the thickness of the connection pad 3, and the bonding pad 3 is formed. Part of it is exposed. In the process (B1) of the method for manufacturing the wiring board (2) and the process (B3) of the method (5) for manufacturing the wiring board, the film is formed on the first surface in a range in which the connection pad 3 is not exposed. Thinning of the solder resist layer 2 and the second solder resist layer 2-2 in the non-exposed portion. When the support layer film is disposed using a film-like solder resist, the support layer film is peeled off and then thinned.

配線基板的製造方法(1)、(3)~(5)之製程(B)、及配線基板的製造方法(2)之製程(B2)時,以薄膜化後之防焊層2、及第一防焊層2-1的厚度成為與第一面所露出之連結墊3的厚度相同、或更薄為止來實施薄膜化。薄膜化後之防焊層2、及第一防焊層2-1的厚度太薄的話,露出之連結墊3之間的電氣絕緣不足,有時會發生無電解鎳/金電鍍之短路,或者,有時連結墊3之間會發生焊劑所導致的短路。所以、薄膜化後之防焊層2、及第一防焊層2-1的厚度,以連結墊3之厚度的3分之1以上為佳,3分之2以上更佳。 In the manufacturing method (1) of the wiring board, the process (B) of (3) to (5), and the process (B2) of the manufacturing method (2) of the wiring board, the solder resist layer 2 and the thinned film are formed. The thickness of the solder resist layer 2-1 is thinned as long as the thickness of the connection pad 3 exposed on the first surface is the same or thinner. If the thickness of the solder resist layer 2 and the first solder resist layer 2-1 after being thinned is too thin, the electrical insulation between the exposed connection pads 3 is insufficient, and a short circuit of electroless nickel/gold plating may occur, or Sometimes, a short circuit caused by flux occurs between the bonding pads 3. Therefore, the thickness of the solder resist layer 2 and the first solder resist layer 2-1 after the film formation is preferably one-third or more of the thickness of the bonding pad 3, and more preferably two-thirds or more.

配線基板的製造方法(1)之製程(B)、及配線基板的製造方法(2)之製程(B1)與(B2)時,第一面之非曝光部的防焊層2被薄膜化,第二面之非曝光部的防焊層2也同時被薄膜化。在配線基板的製造方法(3)~(5)之製程(B)時,第一面之非曝光部的第一防焊層2-1被薄膜化,第二面之非曝光部的第一防焊層2- 1也同時被薄膜化。配線基板的製造方法(5)之製程(B3)時,第一面之非曝光部的第二防焊層2-2被薄膜化,第二面之非曝光部的第一防焊層2-1也同時被薄膜化。第二面之薄膜化量,因為第二面之非曝光部之防焊層2、及第一防焊層2-1的熱硬化狀態而有所不同,然而,於兩表面,以相同加熱條件來形成防焊層2、及第一防焊層2-1時,通常,第一面與第二面之非曝光部的防焊層2、及第一防焊層2-1,會同時被同量薄膜化。 In the process (B) of the method of manufacturing the wiring board (1) and the processes (B1) and (B2) of the method (2) of manufacturing the wiring board, the solder resist layer 2 of the non-exposed portion of the first surface is thinned. The solder resist layer 2 of the non-exposed portion of the second surface is also thinned at the same time. In the manufacturing process (3) to (5) of the wiring board, the first solder resist layer 2-1 of the non-exposed portion of the first surface is thinned, and the first portion of the non-exposed portion of the second surface is formed. Solder mask 2 1 is also thinned at the same time. In the process (B3) of the method (5) of manufacturing the wiring board, the second solder resist layer 2-2 of the non-exposed portion of the first surface is thinned, and the first solder resist layer 2 of the non-exposed portion of the second surface is formed. 1 is also thinned at the same time. The amount of film formation of the second surface differs depending on the solder resist layer 2 of the non-exposed portion of the second surface and the heat-hardened state of the first solder resist layer 2-1, however, the same heating conditions are applied to both surfaces. When the solder resist layer 2 and the first solder resist layer 2-1 are formed, generally, the solder resist layer 2 of the non-exposed portion of the first surface and the second surface and the first solder resist layer 2-1 are simultaneously The same amount of filming.

配線基板的製造方法(1)、(3)~(5)之製程(B)、配線基板的製造方法(2)之製程(B1)與(B2)、以及配線基板的製造方法(5)之製程(B3)時,薄膜化處理,以第一面朝上來實施為佳。薄膜化處理之處理方式,為了使薄膜化處理液中不易發生氣泡,浸漬處理係有效的方法。萬一,薄膜化處理液中發生氣泡時,氣泡在薄膜化處理液中浮上而附著於下面(第二面)之防焊層2、及第一防焊層2-1的表面。該氣泡的附著,有時會使第二面之薄膜化後的膜厚不均一。然而,在後製程之配線基板的製造方法(1)、(2)、(4)之製程(D)、配線基板的製造方法(3)及(5)之製程(D1)、以及配線基板的製造方法(4)之製程(D2)時,因為第二面之非曝光部的防焊層2、及第一防焊層2-1被顯影除去,最終不會出現膜厚不均的問題。 Process for manufacturing wiring board (1), process (B) of (3) to (5), process (B1) and (B2) of method for manufacturing wiring board (2), and method for manufacturing wiring board (5) In the process (B3), it is preferable to carry out the film forming treatment with the first side facing up. The treatment method of the film formation treatment is an effective method for immersion treatment in order to prevent bubbles from occurring in the film formation treatment liquid. In the case where air bubbles are generated in the thin film processing liquid, the air bubbles float in the thin film processing liquid and adhere to the surface of the lower (second surface) solder resist layer 2 and the first solder resist layer 2-1. The adhesion of the bubbles may result in a non-uniform film thickness after the second surface is thinned. However, the manufacturing method (1), (2), and (4) of the wiring substrate in the post-process, the manufacturing method (3) of the wiring board, and the process (D1) of the wiring substrate (D1), and the wiring substrate In the process (D2) of the manufacturing method (4), since the solder resist layer 2 of the non-exposed portion of the second surface and the first solder resist layer 2-1 are developed and removed, there is no problem that film thickness unevenness eventually occurs.

配線基板的製造方法(1)及(2)之製程(D)時,以顯影來除去第二面之非曝光部的防焊層2。 配線基板的製造方法(4)之製程(D)時,以顯影來除去第二面之非曝光部的第一防焊層2-1。配線基板的製造方法(3)及(5)之製程(D1)時,以顯影來除去第一面之非曝光部的第二防焊層2-2、及第二面之非曝光部的第一防焊層2-1。配線基板的製造方法(4)之製程(D2)時,以顯影來除去第一面之非曝光部的第二防焊層2-2。顯影方法,採用符合使用之防焊劑的顯影液,對電路基板之兩表面進行噴霧,除去各防焊層之不需要部分。顯影液,係使用稀薄之鹼性水溶液,一般而言,係使用0.3~3質量%之碳酸鈉水溶液或碳酸鉀水溶液。 In the manufacturing method (1) of the wiring board and the process (D) of (2), the solder resist layer 2 of the non-exposed part of the second surface is removed by development. In the process (D) of the method (4) of manufacturing the wiring board, the first solder resist layer 2-1 of the non-exposed portion of the second surface is removed by development. In the manufacturing method (3) and (5) of the wiring board (D1), the second solder resist layer 2-2 of the non-exposed portion of the first surface and the non-exposed portion of the second surface are removed by development. A solder mask layer 2-1. In the process (D2) of the manufacturing method (4) of the wiring board, the second solder resist layer 2-2 of the non-exposed portion of the first surface is removed by development. In the developing method, the surface of the circuit board is sprayed with a developer conforming to the solder resist to be used, and unnecessary portions of the solder resist layers are removed. The developer is a thin alkaline aqueous solution, and generally, a 0.3 to 3% by mass aqueous sodium carbonate solution or an aqueous potassium carbonate solution is used.

[實施例] [Examples]

以下,利用實施例來針對本發明進行更詳細的說明,然而,本發明並未受限於該實施例。 Hereinafter, the present invention will be described in more detail by way of examples, however, the invention is not limited thereto.

實施例1~6,係第4-1圖及第4-2圖所示之配線基板的製造方法(1)的相關例。 Examples 1 to 6 are related examples of the method (1) for manufacturing the wiring board shown in Figs. 4-1 and 4-2.

(實施例1) (Example 1) <製程(A)> <Process (A)>

利用半加法,製作於兩表面形成有導體配線7之電路基板1(面積170mm×200mm、導體厚度15μm、基板厚度0.4mm)。於表面(第一面)側,有當做電子構件連結用連結墊3來使用之線寬25μm、間隔50μm的導體配線。於背面(第二面)側,形成有當做外部連結用連結墊4來 使用之直徑600μm之圓形狀導體配線。其次,使用真空層合機,將厚度25μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱:PFR-800 AUS410)真空熱壓接合(疊合溫度75℃、吸引時間30秒、加壓時間10秒)於上述電路基板1之兩表面。藉此,形成防焊層2。第一面之防焊層2時,從絕緣層8表面之厚度為30μm,電子構件連結用連結墊3上之厚度為15μm。第二面之防焊層2時,從絕緣層8表面之厚度為38μm,外部連結用連結墊4上之厚度為23μm。導體配線密度較小之第一面,相較於導體配線密度較大之第二面,防焊層2之厚度為較薄之8μm。 The circuit board 1 (having an area of 170 mm × 200 mm, a conductor thickness of 15 μm, and a substrate thickness of 0.4 mm) on which conductor wirings 7 were formed on both surfaces was produced by a half addition method. On the surface (first surface) side, there is a conductor wiring having a line width of 25 μm and a spacing of 50 μm which is used as the connection pad 3 for electronic component connection. On the back side (second side) side, a connection pad 4 as an external connection is formed. A circular conductor wire having a diameter of 600 μm was used. Next, a 25 mm-thick solder mask (manufactured by TAIYO INK MFG. CO., LTD., trade name: PFR-800 AUS410) was vacuum-compressed using a vacuum laminator (lamination temperature: 75 ° C, suction time: 30 seconds). The pressurization time is 10 seconds) on both surfaces of the circuit board 1 described above. Thereby, the solder resist layer 2 is formed. In the solder resist layer 2 of the first surface, the thickness from the surface of the insulating layer 8 was 30 μm, and the thickness of the connection pad 3 for electronic component connection was 15 μm. In the solder resist layer 2 of the second surface, the thickness from the surface of the insulating layer 8 was 38 μm, and the thickness of the external connection connecting pad 4 was 23 μm. On the first side where the conductor wiring density is small, the thickness of the solder resist layer 2 is 8 μm thinner than the second surface having a larger conductor wiring density.

<製程(C1)> <Process (C1)>

對第一面之防焊層2,使用對比距離複數電子構件連結用連結墊3之端部為200μm之外周更為外側的區域照射活性光線6之圖案的光罩5,以曝光量200mJ/cm2實施接觸曝光。 For the solder resist layer 2 of the first surface, the photomask 5 of the pattern of the active light rays 6 is irradiated with a region in which the end portion of the connection pad 3 of the plurality of electronic component connection is 200 μm and the outer side is irradiated with an exposure amount of 200 mJ/cm. 2 Implementation of contact exposure.

<製程(C2)> <Process (C2)>

對第二面之防焊層2,於外部連結用連結墊4上配設直徑500μm之圓形開口部區域,利用對圓形開口部區域以外照射活性光線6之圖案的光罩5,以曝光量200mJ/cm2實施接觸曝光。 In the solder resist layer 2 on the second surface, a circular opening portion having a diameter of 500 μm is disposed on the external connection connecting pad 4, and the mask 5 that irradiates the pattern of the active light 6 to the outside of the circular opening portion is exposed. Contact exposure was carried out at a quantity of 200 mJ/cm 2 .

<製程(B)> <Process (B)>

剝離第一面及第二面之防焊層2上的支撐層膜後,使用10質量%之偏矽酸鈉水溶液(液溫25℃)當做薄膜化處理液,使第一面朝上,將電路基板1浸漬於薄膜化處理液50秒鐘,實施膠束化處理(薄膜化處理)。其後,實施利用膠束除去液(液溫25℃)之噴霧的膠束除去處理、水洗處理(液溫25℃)、及乾燥處理,使第一面之非曝光部之防焊層2的厚度成為電子構件連結用連結墊3之表面下5.0μm為止,實施平均20μm之防焊層2的薄膜化。以光學顯微鏡進行觀察,第一面之防焊層2表面沒有處理不均,而得到良好的面內均一性。另一方面,於第二面,平均20μm之防焊層2也被薄膜化,薄膜化處理液中之氣泡附著於第二面之非曝光部的防焊層2,出現膜厚不均一的部位。此外,於外部連結用連結墊4上,殘留有約3μm之防焊層2的殘渣。 After peeling off the support layer film on the first surface and the second surface of the solder resist layer 2, using a 10% by mass aqueous sodium metasilicate solution (liquid temperature: 25 ° C) as a thin film treatment liquid, with the first side facing up, The circuit board 1 was immersed in the thin film processing liquid for 50 seconds, and subjected to micellization treatment (thinning treatment). Thereafter, a micelle removal treatment, a water washing treatment (liquid temperature: 25 ° C), and a drying treatment using a spray of a micelle removal liquid (liquid temperature: 25 ° C) were carried out to obtain a solder resist layer 2 of the non-exposed portion of the first surface. When the thickness is 5.0 μm below the surface of the connection pad 3 for electronic component connection, the solder resist layer 2 having an average thickness of 20 μm is formed into a thin film. Observation by an optical microscope revealed that the surface of the solder resist layer 2 on the first side was not unevenly treated, and good in-plane uniformity was obtained. On the other hand, on the second surface, the solder resist layer 2 having an average of 20 μm is also thinned, and the bubbles in the thin film processing liquid adhere to the solder resist layer 2 of the non-exposed portion of the second surface, and a portion having uneven film thickness appears. . Further, on the external connection connecting pad 4, a residue of the solder resist layer 2 of about 3 μm remains.

<製程(C3)> <Process (C3)>

對第一面之防焊層2,利用使活性光線6照射製程(B)所薄膜化之區域部分及從該薄膜化之區域境界部的200μm外側為止之區域之圖案的光罩5,以曝光量400mJ/cm2之氧環境下的非接觸曝光來實施曝光。 For the solder mask layer 2 on the first surface, the photomask 5 which irradiates the active light ray 6 to the region of the region which is thinned by the process (B) and the region from the outer side of the boundary portion of the thinned region of 200 μm is exposed. Exposure was carried out by non-contact exposure in an oxygen atmosphere of 400 mJ/cm 2 .

<製程(D)> <Process (D)>

利用1質量%之碳酸鈉水溶液(液溫度30℃、噴霧 壓0.15MPa)實施30秒鐘之顯影,除去第二面之非曝光部的防焊層2。以光學顯微鏡進行觀察,結果,在第一面及第二面,於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現防焊層2之殘渣。此外,在第一面,至電子構件連結用連結墊3之表面下5.5μm為止,防焊層2充填於電子構件連結用連結墊3之間。藉由製程(C3)之氧環境下的非接觸曝光,電子構件連結用連結墊3之間之防焊層2表面的光聚合獲得抑制,結果,防焊層2的厚度減少0.5μm。 Use 1% by mass aqueous sodium carbonate solution (liquid temperature 30 ° C, spray The development was carried out for 30 seconds under a pressure of 0.15 MPa), and the solder resist layer 2 of the non-exposed portion of the second surface was removed. As a result of observing with an optical microscope, the residue of the solder resist layer 2 was not found on the first and second surfaces of the electronic component connecting connecting pad 3 and the external connecting connecting pad 4. In the first surface, the solder resist layer 2 is filled between the electronic component connecting connecting pads 3 until the surface of the electronic component connecting connecting pad 3 is 5.5 μm lower. By the non-contact exposure in the oxygen atmosphere of the process (C3), photopolymerization of the surface of the solder resist layer 2 between the connection pads 3 for electronic component connection is suppressed, and as a result, the thickness of the solder resist layer 2 is reduced by 0.5 μm.

其次,為了使第一面及第二面之防焊層2硬化,以曝光量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理,而得到配線基板。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm之防焊層2所覆蓋,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度9.5μm之防焊層2。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之防焊層2的圓形開口部,而使外部連結用連結墊4之一部分露出。 Next, in order to cure the solder resist layer 2 of the first surface and the second surface, total exposure was performed at an exposure amount of 1000 mJ/cm 2 , and then heat hardening treatment was performed at 150 ° C for 60 minutes to obtain a wiring substrate. As a result of observation with an optical microscope, the conductor wiring 7 having a thickness of 15 μm is covered by the solder resist layer 2 having a thickness of 30 μm on the first surface, and the connecting pad 3 for connecting the electronic component having a thickness of 15 μm is exposed, and the connecting member for connecting adjacent electronic components is connected. Between the pads 3, a solder resist layer 2 having a thickness of 9.5 μm is filled. Further, on the second surface, a part of the external connection connecting pad 4 having a thickness of 15 μm is formed with a circular opening portion of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm, and a part of the external connection connecting pad 4 is exposed. .

其次,測定相鄰電子構件連結用連結墊3之間之防焊層2的表面粗細度。使用超深度形狀測定顯微鏡(KEYENCE CORPORATION製、商品編號「VK-8500」)測定表面粗細度時,表面粗細度Ra為0.40μm。 Next, the surface roughness of the solder resist layer 2 between the adjacent electronic component connecting pads 3 is measured. When the surface thickness was measured using an ultra-depth shape measuring microscope (manufactured by KEYENCE CORPORATION, product number "VK-8500"), the surface roughness Ra was 0.40 μm.

利用超深度形狀測定顯微鏡(KEYENCE CORPORATION製、商品編號「VK-8500」)之算術平均表面粗細度Ra,係採用以JIS B0601-1994表面粗細度-定義為基準的計算式。而且,測定區域為900μm2,基準長度為40μm。 The arithmetic mean surface roughness Ra of the ultra-depth shape measuring microscope (manufactured by KEYENCE CORPORATION, product number "VK-8500") was calculated using the JIS B0601-1994 surface thickness-definition. Further, the measurement area was 900 μm 2 and the reference length was 40 μm.

(實施例2) (Example 2)

除了更替製程(C1)與製程(C2)之順序以外,以與實施例1相同之方法,實施製程(A)~製程(D)。以光學顯微鏡進行觀察,結果,在第一面及第二面,於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現防焊層2之殘渣。此外,在第一面,至電子構件連結用連結墊3之表面下5.5μm為止,防焊層2充填於電子構件連結用連結墊3之間。藉由製程(C3)之氧環境下的非接觸曝光,電子構件連結用連結墊3之間之防焊層2表面的光聚合獲得抑制,結果,防焊層2的厚度減少0.5μm。 The process (A) to the process (D) were carried out in the same manner as in Example 1 except that the order of the process (C1) and the process (C2) was replaced. As a result of observing with an optical microscope, the residue of the solder resist layer 2 was not found on the first and second surfaces of the electronic component connecting connecting pad 3 and the external connecting connecting pad 4. In the first surface, the solder resist layer 2 is filled between the electronic component connecting connecting pads 3 until the surface of the electronic component connecting connecting pad 3 is 5.5 μm lower. By the non-contact exposure in the oxygen atmosphere of the process (C3), photopolymerization of the surface of the solder resist layer 2 between the connection pads 3 for electronic component connection is suppressed, and as a result, the thickness of the solder resist layer 2 is reduced by 0.5 μm.

其次,為了使第一面及第二面之防焊層2硬化,以曝光量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理,而得到配線基板。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm之防焊層2所覆蓋,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度9.5μm之防焊層2。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之防焊層的圓形開口部,而使外 部連結用連結墊4之一部分露出。 Next, in order to cure the solder resist layer 2 of the first surface and the second surface, total exposure was performed at an exposure amount of 1000 mJ/cm 2 , and then heat hardening treatment was performed at 150 ° C for 60 minutes to obtain a wiring substrate. As a result of observation with an optical microscope, the conductor wiring 7 having a thickness of 15 μm is covered by the solder resist layer 2 having a thickness of 30 μm on the first surface, and the connecting pad 3 for connecting the electronic component having a thickness of 15 μm is exposed, and the connecting member for connecting adjacent electronic components is connected. Between the pads 3, a solder resist layer 2 having a thickness of 9.5 μm is filled. In the second surface, a part of the external connection connecting pad 4 having a thickness of 15 μm is formed with a circular opening having a thickness of 38 μm and a diameter of 500 μm, and a part of the external connection connecting pad 4 is exposed.

其次,測定相鄰電子構件連結用連結墊3之間之防焊層2的表面粗細度,表面粗細度Ra為0.40μm。 Next, the surface roughness of the solder resist layer 2 between the adjacent electronic component connecting pads 3 was measured, and the surface roughness Ra was 0.40 μm.

(實施例3) (Example 3)

除了製程(C3)之曝光量為200mJ/cm2以外,以與實施例1相同之方法,實施製程(A)~製程(D)。以光學顯微鏡進行觀察,結果,在第一面及第二面,於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現防焊層2之殘渣。在第一面,至電子構件連結用連結墊3之表面下6.0μm為止,防焊層2充填於電子構件連結用連結墊3之間。藉由製程(C3)之氧環境下的非接觸曝光,電子構件連結用連結墊3之間之防焊層2表面的光聚合獲得抑制,結果,防焊層2的厚度減少1.0μm。 The process (A) to the process (D) were carried out in the same manner as in Example 1 except that the exposure amount of the process (C3) was 200 mJ/cm 2 . As a result of observing with an optical microscope, the residue of the solder resist layer 2 was not found on the first and second surfaces of the electronic component connecting connecting pad 3 and the external connecting connecting pad 4. On the first surface, the solder resist layer 2 is filled between the electronic component connecting connecting pads 3 until the surface of the electronic component connecting connecting pad 3 is 6.0 μm below the surface. By the non-contact exposure in the oxygen atmosphere of the process (C3), photopolymerization of the surface of the solder resist layer 2 between the connection pads 3 for electronic component connection is suppressed, and as a result, the thickness of the solder resist layer 2 is reduced by 1.0 μm.

其次,為了使第一面及第二面之防焊層2硬化,以曝光量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理,而得到配線基板。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm之防焊層2所覆蓋,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度9.0μm之防焊層2。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之防焊層2的圓形開口部,而使外部連結用連結墊4之一部分露出。 Next, in order to cure the solder resist layer 2 of the first surface and the second surface, total exposure was performed at an exposure amount of 1000 mJ/cm 2 , and then heat hardening treatment was performed at 150 ° C for 60 minutes to obtain a wiring substrate. As a result of observation with an optical microscope, the conductor wiring 7 having a thickness of 15 μm is covered by the solder resist layer 2 having a thickness of 30 μm on the first surface, and the connecting pad 3 for connecting the electronic component having a thickness of 15 μm is exposed, and the connecting member for connecting adjacent electronic components is connected. Between the pads 3, a solder resist layer 2 having a thickness of 9.0 μm is filled. Further, on the second surface, a part of the external connection connecting pad 4 having a thickness of 15 μm is formed with a circular opening portion of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm, and a part of the external connection connecting pad 4 is exposed. .

其次,測定相鄰電子構件連結用連結墊3之間之防焊層2的表面粗細度,表面粗細度Ra為0.50μm。 Next, the surface roughness of the solder resist layer 2 between the adjacent electronic component connecting pads 3 was measured, and the surface roughness Ra was 0.50 μm.

(實施例4) (Example 4)

除了製程(C3)之曝光量為1000mJ/cm2以外,以與實施例1相同之方法,實施製程(A)~製程(D)。以光學顯微鏡進行觀察,結果,在第一面及第二面,於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現防焊層2之殘渣。此外,在第一面,至電子構件連結用連結墊3之表面下5.0μm為止,防焊層2充填於電子構件連結用連結墊3之間。未確認到製程(C3)之氧聚合妨礙所導致之第一面防焊層2的膜減。 The process (A) to the process (D) were carried out in the same manner as in Example 1 except that the exposure amount of the process (C3) was 1000 mJ/cm 2 . As a result of observing with an optical microscope, the residue of the solder resist layer 2 was not found on the first and second surfaces of the electronic component connecting connecting pad 3 and the external connecting connecting pad 4. In the first surface, the solder resist layer 2 is filled between the electronic component connecting connecting pads 3 until 5.0 μm below the surface of the electronic component connecting connecting pad 3 . It was not confirmed that the oxygen polymerization of the process (C3) hindered the film reduction of the first surface solder resist layer 2.

其次,為了使第一面及第二面之防焊層2硬化,以曝光量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理,而得到配線基板。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm之防焊層2所覆蓋,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度10.0μm之防焊層2。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之防焊層2的圓形開口部,而使外部連結用連結墊4之一部分露出。 Next, in order to cure the solder resist layer 2 of the first surface and the second surface, total exposure was performed at an exposure amount of 1000 mJ/cm 2 , and then heat hardening treatment was performed at 150 ° C for 60 minutes to obtain a wiring substrate. As a result of observation with an optical microscope, the conductor wiring 7 having a thickness of 15 μm is covered by the solder resist layer 2 having a thickness of 30 μm on the first surface, and the connecting pad 3 for connecting the electronic component having a thickness of 15 μm is exposed, and the connecting member for connecting adjacent electronic components is connected. Between the pads 3, a solder resist layer 2 having a thickness of 10.0 μm is filled. Further, on the second surface, a part of the external connection connecting pad 4 having a thickness of 15 μm is formed with a circular opening portion of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm, and a part of the external connection connecting pad 4 is exposed. .

其次,測定相鄰電子構件連結用連結墊3之間之防焊層2的表面粗細度,表面粗細度Ra為0.30μm。 Next, the surface roughness of the solder resist layer 2 between the adjacent electronic component connecting pads 3 was measured, and the surface roughness Ra was 0.30 μm.

(實施例5) (Example 5)

除了在氧環境下,利用直接描繪裝置(商品名稱:LI-8500、Dainippon Screen Mfg.Co.,Ltd.製)以曝光量400mJ/cm2實施製程(C3)之曝光以外,以與實施例1相同之方法,實施製程(A)~製程(D)。以光學顯微鏡進行觀察,結果,在第一面及第二面,於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現防焊層2之殘渣。此外,在第一面,至電子構件連結用連結墊3之表面下5.5μm為止,防焊層2充填於電子構件連結用連結墊3之間。藉由製程(C3)之氧環境下的非接觸曝光,電子構件連結用連結墊3之間之防焊層2表面的光聚合獲得抑制,結果,防焊層2的厚度減少0.5μm。 Except for the exposure of the process (C3) at an exposure amount of 400 mJ/cm 2 by using a direct drawing device (trade name: LI-8500, manufactured by Dainippon Screen Mfg. Co., Ltd.) in an oxygen atmosphere, and Example 1 In the same way, the process (A) ~ process (D) is implemented. As a result of observing with an optical microscope, the residue of the solder resist layer 2 was not found on the first and second surfaces of the electronic component connecting connecting pad 3 and the external connecting connecting pad 4. In the first surface, the solder resist layer 2 is filled between the electronic component connecting connecting pads 3 until the surface of the electronic component connecting connecting pad 3 is 5.5 μm lower. By the non-contact exposure in the oxygen atmosphere of the process (C3), photopolymerization of the surface of the solder resist layer 2 between the connection pads 3 for electronic component connection is suppressed, and as a result, the thickness of the solder resist layer 2 is reduced by 0.5 μm.

其次,為了使第一面及第二面之防焊層2硬化,以曝光量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理,而得到配線基板。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm之防焊層2所覆蓋,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度9.5μm之防焊層2。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之防焊層的圓形開口部,而使外部連結用連結墊4之一部分露出。 Next, in order to cure the solder resist layer 2 of the first surface and the second surface, total exposure was performed at an exposure amount of 1000 mJ/cm 2 , and then heat hardening treatment was performed at 150 ° C for 60 minutes to obtain a wiring substrate. As a result of observation with an optical microscope, the conductor wiring 7 having a thickness of 15 μm is covered by the solder resist layer 2 having a thickness of 30 μm on the first surface, and the connecting pad 3 for connecting the electronic component having a thickness of 15 μm is exposed, and the connecting member for connecting adjacent electronic components is connected. Between the pads 3, a solder resist layer 2 having a thickness of 9.5 μm is filled. In the second surface, a part of the external connection connecting pad 4 having a thickness of 15 μm is formed with a circular opening having a thickness of 38 μm and a diameter of 500 μm, and a part of the external connection connecting pad 4 is exposed.

其次,測定相鄰電子構件連結用連結墊3之 間之防焊層2的表面粗細度,表面粗細度Ra為0.40μm。 Next, the connection pad 3 for connecting adjacent electronic components is measured. The surface roughness of the solder resist layer 2 between the two was 0.50 μm.

(實施例6) (Example 6)

製程(C3)時,除了以接觸曝光方式來實施曝光以外,以與實施例1相同之方法,實施製程(A)~製程(D)。以光學顯微鏡進行觀察,結果,在第一面及第二面,於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現防焊層2之殘渣。此外,在第一面,至電子構件連結用連結墊3之表面下5.0μm為止,防焊層2充填於電子構件連結用連結墊3之間。製程(C3)時,藉由充份執行接觸曝光時之排氣,而在非氧環境下實施曝光,故防焊層2表面未粗面化,結果,防焊層2的厚度未減少。 In the process (C3), the processes (A) to (D) were carried out in the same manner as in Example 1 except that the exposure was performed by a contact exposure method. As a result of observing with an optical microscope, the residue of the solder resist layer 2 was not found on the first and second surfaces of the electronic component connecting connecting pad 3 and the external connecting connecting pad 4. In the first surface, the solder resist layer 2 is filled between the electronic component connecting connecting pads 3 until 5.0 μm below the surface of the electronic component connecting connecting pad 3 . In the process (C3), since the exposure is performed in a non-oxygen atmosphere by sufficiently performing the exhaust gas during the contact exposure, the surface of the solder resist layer 2 is not roughened, and as a result, the thickness of the solder resist layer 2 is not reduced.

其次,為了使第一面及第二面之防焊層2硬化,以曝光量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理,而得到配線基板。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm之防焊層2所覆蓋,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度10μm之防焊層2。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之防焊層2的圓形開口部,導體墊4露出。 Next, in order to cure the solder resist layer 2 of the first surface and the second surface, total exposure was performed at an exposure amount of 1000 mJ/cm 2 , and then heat hardening treatment was performed at 150 ° C for 60 minutes to obtain a wiring substrate. As a result of observation with an optical microscope, the conductor wiring 7 having a thickness of 15 μm is covered by the solder resist layer 2 having a thickness of 30 μm on the first surface, and the connecting pad 3 for connecting the electronic component having a thickness of 15 μm is exposed, and the connecting member for connecting adjacent electronic components is connected. Between the pads 3, a solder resist layer 2 having a thickness of 10 μm is filled. Further, on the second surface, a part of the external connection connecting pad 4 having a thickness of 15 μm was formed with a circular opening portion having a solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm, and the conductor pad 4 was exposed.

其次,測定相鄰電子構件連結用連結墊3之間之防焊層2的表面粗細度,表面粗細度Ra為0.10μm。 Next, the surface roughness of the solder resist layer 2 between the adjacent electronic component connecting pads 3 was measured, and the surface roughness Ra was 0.10 μm.

實施例1~6時,因為相鄰電子構件連結用連結墊3之間有足夠厚度之防焊層2,可以確實防止安裝電子構件時之焊劑所導致的電氣短路。此外,因為防焊層2之殘渣不存在於外部連結用連結墊4上,安裝於外部電氣基板時,也可製作不會發生電氣絕緣不良之信賴性高的配線基板。比較實施例1~6的話,相較於電子構件連結用連結墊3之間之防焊層2表面平滑的實施例6所製造的配線基板,實施例1~5所製造的配線基板,填膠之黏著性高,連結信賴性優良。 In the first to sixth embodiments, since the solder resist layer 2 having a sufficient thickness between the adjacent electronic component connecting pads 3 is provided, it is possible to surely prevent an electrical short circuit caused by the solder when the electronic component is mounted. In addition, since the residue of the solder resist layer 2 is not present on the external connection connecting pad 4, when it is mounted on an external electric board, it is possible to manufacture a wiring board having high reliability without causing electrical insulation failure. In the case of the wiring boards manufactured in the sixth embodiment in which the surface of the solder resist layer 2 between the electronic component connecting pads 3 is smooth, the wiring boards manufactured in the first to fifth embodiments are filled with glue. It has high adhesion and excellent connection reliability.

(比較例1) (Comparative Example 1) <製程(A)> <Process (A)>

利用半加法,製作於兩表面形成有導體配線7之電路基板1(面積170mm×200mm、導體厚度15μm、基板厚度0.4mm)。於表面(第一面),有當做電子構件連結用連結墊3來使用之線寬25μm、間隔50μm的導體配線。於背面(第二面),形成有當做外部連結用連結墊4來使用之直徑600μm之圓形狀導體配線。其次,使用真空層合機,將厚度25μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱:PFR-800 AUS410)真空熱壓接合(疊合溫度75℃、吸引時間30秒、加壓時間10秒)於上述電路基板1之兩表面。藉此,形成防焊層2。第一面之防焊層2時,從絕緣層8表面之厚度為30μm,電子構件連結用連結墊3上之厚度為15μm。第二面之防焊層2時,從 絕緣層8表面之厚度為38μm,外部連結用連結墊4上之厚度為23μm。導體配線密度較小之第一面,相較於導體配線密度較大之第二面,防焊層2之厚度為較薄之8μm。 The circuit board 1 (having an area of 170 mm × 200 mm, a conductor thickness of 15 μm, and a substrate thickness of 0.4 mm) on which conductor wirings 7 were formed on both surfaces was produced by a half addition method. On the surface (first surface), there is a conductor wiring having a line width of 25 μm and a spacing of 50 μm which is used as the connection pad 3 for electronic component connection. On the back surface (second surface), a circular conductor wiring having a diameter of 600 μm used as the external connection connecting mat 4 was formed. Next, a 25 mm-thick solder mask (manufactured by TAIYO INK MFG. CO., LTD., trade name: PFR-800 AUS410) was vacuum-compressed using a vacuum laminator (lamination temperature: 75 ° C, suction time: 30 seconds). The pressurization time is 10 seconds) on both surfaces of the circuit board 1 described above. Thereby, the solder resist layer 2 is formed. In the solder resist layer 2 of the first surface, the thickness from the surface of the insulating layer 8 was 30 μm, and the thickness of the connection pad 3 for electronic component connection was 15 μm. The second side of the solder mask 2, from The thickness of the surface of the insulating layer 8 was 38 μm, and the thickness of the external connection connecting pad 4 was 23 μm. On the first side where the conductor wiring density is small, the thickness of the solder resist layer 2 is 8 μm thinner than the second surface having a larger conductor wiring density.

<製程(C1)> <Process (C1)>

對第一面之防焊層2,使用對比距離複數電子構件連結用連結墊3之端部為200μm之外周更為外側的區域照射活性光線6之圖案的光罩5,以曝光量200mJ/cm2實施接觸曝光。 For the solder resist layer 2 of the first surface, the photomask 5 of the pattern of the active light rays 6 is irradiated with a region in which the end portion of the connection pad 3 of the plurality of electronic component connection is 200 μm and the outer side is irradiated with an exposure amount of 200 mJ/cm. 2 Implementation of contact exposure.

<製程(C2)> <Process (C2)>

對第二面之防焊層2,於外部連結用連結墊4上配設直徑500μm之圓形開口部區域,利用對圓形開口部區域以外照射活性光線6之圖案的光罩5,以曝光量200mJ/cm2實施接觸曝光。 In the solder resist layer 2 on the second surface, a circular opening portion having a diameter of 500 μm is disposed on the external connection connecting pad 4, and the mask 5 that irradiates the pattern of the active light 6 to the outside of the circular opening portion is exposed. Contact exposure was carried out at a quantity of 200 mJ/cm 2 .

<製程(B)> <Process (B)>

剝離第一面及第二面之防焊層2上的支撐層膜後,使用10質量%之偏矽酸鈉水溶液(液溫25℃)當做薄膜化處理液,使第一面朝上,將電路基板1浸漬於薄膜化處理液50秒鐘,實施膠束化處理(薄膜化處理)。其後,實施利用膠束除去液(液溫25℃)之噴霧的膠束除去處理、水洗處理(液溫25℃)、及乾燥處理,使第一面之非曝光部之防焊層2的厚度成為電子構件連結用連結墊3 之表面下5.0μm為止,實施平均20μm之防焊層2的薄膜化。以光學顯微鏡進行觀察,第一面之防焊層2表面沒有處理不均,而得到良好的面內均一性。另一方面,第二面之防焊層2也被實施平均20μm之薄膜化,薄膜化處理液中之氣泡附著於第二面之非曝光部的防焊層2,出現膜厚不均一的部位。此外,於外部連結用連結墊4上,殘留有約3μm之防焊層2的殘渣。 After peeling off the support layer film on the first surface and the second surface of the solder resist layer 2, using a 10% by mass aqueous sodium metasilicate solution (liquid temperature: 25 ° C) as a thin film treatment liquid, with the first side facing up, The circuit board 1 was immersed in the thin film processing liquid for 50 seconds, and subjected to micellization treatment (thinning treatment). Thereafter, a micelle removal treatment, a water washing treatment (liquid temperature: 25 ° C), and a drying treatment using a spray of a micelle removal liquid (liquid temperature: 25 ° C) were carried out to obtain a solder resist layer 2 of the non-exposed portion of the first surface. The thickness becomes the connection pad 3 for electronic component connection Thin film formation of the solder resist layer 2 of an average of 20 μm was performed up to 5.0 μm below the surface. Observation by an optical microscope revealed that the surface of the solder resist layer 2 on the first side was not unevenly treated, and good in-plane uniformity was obtained. On the other hand, the solder mask 2 of the second surface is also thinned by an average of 20 μm, and the bubbles in the thin film-forming liquid adhere to the solder resist layer 2 of the non-exposed portion of the second surface, and the film thickness is uneven. . Further, on the external connection connecting pad 4, a residue of the solder resist layer 2 of about 3 μm remains.

其次,為了使第一面及第二面之防焊層2硬化,以曝光量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理,而得到配線基板。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm之防焊層2所覆蓋,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度10.0μm之防焊層2。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之防焊層2的圓形開口部,然而,於外部連結用連結墊4上殘留著厚度3μm之防焊層2的殘渣。 Next, in order to cure the solder resist layer 2 of the first surface and the second surface, total exposure was performed at an exposure amount of 1000 mJ/cm 2 , and then heat hardening treatment was performed at 150 ° C for 60 minutes to obtain a wiring substrate. As a result of observation with an optical microscope, the conductor wiring 7 having a thickness of 15 μm is covered by the solder resist layer 2 having a thickness of 30 μm on the first surface, and the connecting pad 3 for connecting the electronic component having a thickness of 15 μm is exposed, and the connecting member for connecting adjacent electronic components is connected. Between the pads 3, a solder resist layer 2 having a thickness of 10.0 μm is filled. Further, on the second surface, a circular opening portion having a solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm is formed in a part of the external connection connecting pad 4 having a thickness of 15 μm, but remains on the external connection connecting pad 4 The residue of the solder resist layer 2 having a thickness of 3 μm was used.

安裝電子構件時,於相鄰電子構件連結用連結墊3之間有足夠厚度之防焊層2,可確實防止焊劑所導致的電氣短路,然而,安裝於外部電氣基板時,殘留於外部連結用連結墊4上之防焊層2的殘渣,導致焊劑凸塊連結發生電氣絕緣不良。 When the electronic component is mounted, the solder resist layer 2 having a sufficient thickness is provided between the adjacent electronic component connecting connecting pads 3, and the electrical short circuit caused by the solder can be surely prevented. However, when it is mounted on the external electrical substrate, it remains in the external connection. The residue of the solder resist layer 2 on the bonding pad 4 causes electrical insulation failure of the solder bump connection.

測定相鄰電子構件連結用連結墊3之間之防 焊層2的表面粗細度時,表面粗細度Ra為0.03μm。相較於電子構件連結用連結墊3之間之防焊表面平滑的比較例1所製造的配線基板,實施例1~5所製造的配線基板,填膠之黏著性高,連結信賴性優良。 Determining the resistance between the connecting pads 3 for connecting adjacent electronic components When the surface of the solder layer 2 has a thickness, the surface roughness Ra is 0.03 μm. The wiring board manufactured in the first to fifth embodiments of the wiring board manufactured in the first to fifth embodiments has a high adhesiveness and excellent connection reliability, as compared with the wiring board manufactured by the comparative example 1 in which the solder resist surface between the electronic component connection connecting pads 3 is smooth.

實施例7~11,係第5-1圖、第5-2圖及第5-3圖所示之配線基板的製造方法(2)的相關例。 Examples 7 to 11 are related examples of the method (2) for manufacturing the wiring board shown in Figs. 5-1, 5-2, and 5-3.

(實施例7) (Example 7) <製程(A)> <Process (A)>

利用半加法,製作於兩表面形成有導體配線7之電路基板1(面積170mm×200mm、導體厚度15μm、基板厚度0.4mm)。於表面(第一面),有當做電子構件連結用連結墊3來使用之線寬25μm、間隔50μm的導體配線。於背面(第二面),形成有當做外部連結用連結墊4來使用之直徑600μm之圓形狀導體配線。其次,使用真空層合機,將厚度25μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱:PFR-800 AUS410)真空熱壓接合(疊合溫度75℃、吸引時間30秒、加壓時間10秒)於上述電路基板1之兩表面。藉此,形成防焊層2。第一面之防焊層2時,從絕緣層8表面之厚度為30μm,電子構件連結用連結墊3上之厚度為15μm。第二面之防焊層2時,從絕緣層8表面之厚度為38μm,外部連結用連結墊4上之厚度為23μm。導體配線密度較小之第一面,相較於導體配線密度較大之第二面,防焊層2之厚度為較薄之8μm。 The circuit board 1 (having an area of 170 mm × 200 mm, a conductor thickness of 15 μm, and a substrate thickness of 0.4 mm) on which conductor wirings 7 were formed on both surfaces was produced by a half addition method. On the surface (first surface), there is a conductor wiring having a line width of 25 μm and a spacing of 50 μm which is used as the connection pad 3 for electronic component connection. On the back surface (second surface), a circular conductor wiring having a diameter of 600 μm used as the external connection connecting mat 4 was formed. Next, a 25 mm-thick solder mask (manufactured by TAIYO INK MFG. CO., LTD., trade name: PFR-800 AUS410) was vacuum-compressed using a vacuum laminator (lamination temperature: 75 ° C, suction time: 30 seconds). The pressurization time is 10 seconds) on both surfaces of the circuit board 1 described above. Thereby, the solder resist layer 2 is formed. In the solder resist layer 2 of the first surface, the thickness from the surface of the insulating layer 8 was 30 μm, and the thickness of the connection pad 3 for electronic component connection was 15 μm. In the solder resist layer 2 of the second surface, the thickness from the surface of the insulating layer 8 was 38 μm, and the thickness of the external connection connecting pad 4 was 23 μm. On the first side where the conductor wiring density is small, the thickness of the solder resist layer 2 is 8 μm thinner than the second surface having a larger conductor wiring density.

<製程(C1)> <Process (C1)>

對第一面之防焊層2,使用對比距離複數電子構件連結用連結墊3之端部為400μm之外周更為外側的區域照射活性光線6之圖案的光罩5,以曝光量200mJ/cm2實施接觸曝光。 For the solder mask layer 2 of the first surface, the mask 5 of the pattern of the active light rays 6 is irradiated with a region in which the end portion of the connection pad 3 of the plurality of electronic component connection is 400 μm and the outer side is irradiated with an exposure amount of 200 mJ/cm. 2 Implementation of contact exposure.

<製程(C2)> <Process (C2)>

對第二面之防焊層2,於外部連結用連結墊4上配設直徑500μm之圓形開口部區域,利用對圓形開口部區域以外照射活性光線6之圖案的光罩5,以曝光量200mJ/cm2實施接觸曝光。 In the solder resist layer 2 on the second surface, a circular opening portion having a diameter of 500 μm is disposed on the external connection connecting pad 4, and the mask 5 that irradiates the pattern of the active light 6 to the outside of the circular opening portion is exposed. Contact exposure was carried out at a quantity of 200 mJ/cm 2 .

<製程(B1)> <Process (B1)>

剝離第一面及第二面之防焊層2上的支撐層膜後,使用10質量%之偏矽酸鈉水溶液(液溫25℃)當做薄膜化處理液,使第一面朝上,將電路基板1浸漬於薄膜化處理液25秒鐘,實施膠束化處理(薄膜化處理)。其後,實施利用膠束除去液(液溫25℃)之噴霧的膠束除去處理、水洗處理(液溫25℃)、及乾燥處理,至第一面之非曝光部的防焊層2的厚度成為電子構件連結用連結墊3之表面上5.0μm為止,實施平均10μm之防焊層2的薄膜化。以光學顯微鏡進行觀察,第一面之防焊層2表面沒有處理不均,而得到良好的面內均一性。另一方面,第二面 之防焊層2也被實施平均10μm之薄膜化,然而,薄膜化處理液中之氣泡附著於第二面之非曝光部的防焊層2,出現膜厚不均一的部位。此外,於外部連結用連結墊4上,殘留有約13μm之防焊層2的殘渣。 After peeling off the support layer film on the first surface and the second surface of the solder resist layer 2, using a 10% by mass aqueous sodium metasilicate solution (liquid temperature: 25 ° C) as a thin film treatment liquid, with the first side facing up, The circuit board 1 was immersed in the thin film processing liquid for 25 seconds, and subjected to micellization treatment (thinning treatment). Thereafter, a micelle removal treatment, a water washing treatment (liquid temperature: 25° C.), and a drying treatment using a spray of a micelle removal liquid (liquid temperature: 25° C.) are performed to the solder resist layer 2 of the non-exposed portion of the first surface. When the thickness is 5.0 μm on the surface of the connection pad 3 for electronic component connection, thinning of the solder resist layer 2 of an average of 10 μm is performed. Observation by an optical microscope revealed that the surface of the solder resist layer 2 on the first side was not unevenly treated, and good in-plane uniformity was obtained. On the other hand, the second side The solder resist layer 2 is also thinned by an average of 10 μm. However, the bubbles in the thin film-forming treatment liquid adhere to the solder resist layer 2 of the non-exposed portion of the second surface, and a portion having a non-uniform film thickness appears. Further, on the external connection connecting pad 4, a residue of the solder resist layer 2 of about 13 μm remains.

<製程(C4)> <Process (C4)>

對第一面之防焊層2,使用對比距離複數電子構件連結用連結墊3之端部為200μm之外周更為外側的區域照射活性光線6之圖案的光罩5,利用氧環境下之非接觸曝光,以曝光量400mJ/cm2實施曝光。 The mask 5 of the first surface of the solder resist layer 2 is irradiated with a pattern of the active light rays 6 in a region where the end portion of the connection pad 3 for the electronic component connection is 200 μm and the outer side of the connection pad 3 is used. Exposure was carried out, and exposure was performed at an exposure amount of 400 mJ/cm 2 .

<製程(B2)> <Process (B2)>

使用10質量%之偏矽酸鈉水溶液(液溫25℃)當做薄膜化處理液,使第一面朝上,將電路基板1浸漬於薄膜化處理液25秒鐘,實施膠束化處理(薄膜化處理)。其後,實施利用膠束除去液(液溫25℃)之噴霧的膠束除去處理、水洗處理(液溫25℃)、及乾燥處理,使第一面之非曝光部之防焊層2的厚度成為電子構件連結用連結墊3之表面下5.0μm為止,實施平均10μm之防焊層2的薄膜化。以光學顯微鏡進行觀察,第一面之防焊層2表面沒有處理不均,而得到良好的面內均一性。藉由製程(C4)之氧環境下的非接觸曝光,從距離配置於第一面之電子構件連結用連結墊3端部200μm的外周至距離400μm之外周為止之區域之防焊層2表面的光聚合獲得抑 制,結果,防焊層2的厚度減少0.5μm。另一方面,第二面之防焊層2也被實施平均10μm之薄膜化,然而,薄膜化處理液中之氣泡附著於第二面之非曝光部的防焊層2,出現膜厚不均一的部位。此外,於外部連結用連結墊4上,殘留有約3μm之防焊層2的殘渣。 Using a 10% by mass aqueous solution of sodium metasilicate (liquid temperature: 25 ° C) as a thin film treatment liquid, the first substrate was faced upward, and the circuit board 1 was immersed in the thin film treatment liquid for 25 seconds to carry out micellization treatment (film Treatment). Thereafter, a micelle removal treatment, a water washing treatment (liquid temperature: 25 ° C), and a drying treatment using a spray of a micelle removal liquid (liquid temperature: 25 ° C) were carried out to obtain a solder resist layer 2 of the non-exposed portion of the first surface. When the thickness is 5.0 μm below the surface of the connection pad 3 for electronic component connection, the thickness of the solder resist layer 2 having an average of 10 μm is formed. Observation by an optical microscope revealed that the surface of the solder resist layer 2 on the first side was not unevenly treated, and good in-plane uniformity was obtained. By the non-contact exposure in the oxygen atmosphere of the process (C4), the surface of the solder resist layer 2 is located from the outer periphery of the end portion of the connecting portion 3 of the electronic component connecting pad 3 disposed on the first surface to the outer periphery of the distance of 400 μm. Photopolymerization As a result, the thickness of the solder resist layer 2 was reduced by 0.5 μm. On the other hand, the solder resist layer 2 of the second surface is also thinned by an average of 10 μm. However, the bubbles in the thin film processing liquid adhere to the solder resist layer 2 of the non-exposed portion of the second surface, and the film thickness is uneven. The part. Further, on the external connection connecting pad 4, a residue of the solder resist layer 2 of about 3 μm remains.

<製程(C5)> <Process (C5)>

對第一面之防焊層2,使用對製程(B2)被薄膜化之區域部分及從該薄膜化區域之境界部至200μm外側為止之區域照射活性光線6之圖案的光罩5,利用氧環境下之非接觸曝光,以曝光量400mJ/cm2實施曝光。 For the solder mask 2 of the first surface, a mask 5 that irradiates the region of the region where the process (B2) is thinned and the region from the boundary portion of the thinned region to the outer side of the thinned region of 200 μm is irradiated with oxygen. The non-contact exposure in the environment was carried out at an exposure amount of 400 mJ/cm 2 .

<製程(D)> <Process (D)>

使用1質量%之碳酸鈉水溶液(液溫度30℃、噴霧壓0.15MPa)實施30秒鐘顯影,除去第二面之非曝光部的防焊層2。以光學顯微鏡進行觀察,結果,在第一面及第二面,於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現防焊層2之殘渣。此外,在第一面,至電子構件連結用連結墊3之表面下5.5μm為止,防焊層2充填於電子構件連結用連結墊3之間。藉由製程(C4)及(C5)之氧環境下的非接觸曝光,在第一面,製程(C1)之接觸曝光所照射活性光線6之區域以外之防焊層2表面的光聚合獲得抑制,結果,防焊層2的厚度減少0.5μm。 Development was carried out for 30 seconds using a 1% by mass aqueous sodium carbonate solution (liquid temperature: 30 ° C, spray pressure: 0.15 MPa) to remove the solder resist layer 2 of the non-exposed portion on the second surface. As a result of observing with an optical microscope, the residue of the solder resist layer 2 was not found on the first and second surfaces of the electronic component connecting connecting pad 3 and the external connecting connecting pad 4. In the first surface, the solder resist layer 2 is filled between the electronic component connecting connecting pads 3 until the surface of the electronic component connecting connecting pad 3 is 5.5 μm lower. By the non-contact exposure in the oxygen environment of the processes (C4) and (C5), the photopolymerization of the surface of the solder resist layer 2 outside the region irradiated with the active light 6 by the contact exposure of the process (C1) is suppressed on the first side. As a result, the thickness of the solder resist layer 2 was reduced by 0.5 μm.

其次,為了使第一面及第二面之防焊層2硬化,以曝光量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理,而得到配線基板。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm及19.5μm之防焊層2所覆蓋,形成相當於該段差之厚度10.5μm的填膠堰塞用堤壩。此外,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度9.5μm之防焊層2。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之防焊層2的圓形開口部,而使外部連結用連結墊4之一部分露出。 Next, in order to cure the solder resist layer 2 of the first surface and the second surface, total exposure was performed at an exposure amount of 1000 mJ/cm 2 , and then heat hardening treatment was performed at 150 ° C for 60 minutes to obtain a wiring substrate. As a result of observation with an optical microscope, the conductor wiring 7 having a thickness of 15 μm was covered with the solder resist layer 2 having a thickness of 30 μm and 19.5 μm on the first surface, and a dam for filling the plug which had a thickness of 10.5 μm corresponding to the step was formed. In addition, the electronic component connecting connecting pads 3 having a thickness of 15 μm are exposed, and a solder resist layer 2 having a thickness of 9.5 μm is filled between the adjacent electronic component connecting connecting pads 3. Further, on the second surface, a part of the external connection connecting pad 4 having a thickness of 15 μm is formed with a circular opening portion of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm, and a part of the external connection connecting pad 4 is exposed. .

其次,測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度19.5μm之防焊層2的表面粗細度,表面粗細度Ra為0.40μm。此外,測定相鄰電子構件連結用連結墊3之間之防焊層2的表面粗細度,表面粗細度Ra為0.40μm。 Then, the surface roughness of the solder resist layer 2 having a thickness of 19.5 μm which is an outer circumference of the end portion of the plurality of electronic component connection connecting pads 3 disposed on the first surface and a thickness of 19.5 μm from the outer periphery of the end portion of 400 μm is measured. The surface roughness Ra was 0.40 μm. Further, the surface roughness of the solder resist layer 2 between the adjacent electronic component connecting pads 3 was measured, and the surface roughness Ra was 0.40 μm.

(實施例8) (Example 8)

除了更替製程(C1)與製程(C2)之順序以外,以與實施例7相同之方法,實施製程(A)~製程(D)。以光學顯微鏡進行觀察,結果,在第一面及第二面,於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現防焊層2之殘渣。此外,至配置於第一面之電子構件連結 用連結墊3之表面下5.5μm為止,充填著防焊層2。藉由製程(C4)及(C5)之氧環境下的非接觸曝光,在第一面,製程(C1)之接觸曝光所照射活性光線6之區域以外之防焊層2表面的光聚合獲得抑制,結果,防焊層2的厚度減少0.5μm。 The process (A) to the process (D) were carried out in the same manner as in Example 7, except that the order of the process (C1) and the process (C2) were replaced. As a result of observing with an optical microscope, the residue of the solder resist layer 2 was not found on the first and second surfaces of the electronic component connecting connecting pad 3 and the external connecting connecting pad 4. In addition, to the electronic component connected to the first side The solder resist layer 2 is filled up to 5.5 μm below the surface of the connection pad 3. By the non-contact exposure in the oxygen environment of the processes (C4) and (C5), the photopolymerization of the surface of the solder resist layer 2 outside the region irradiated with the active light 6 by the contact exposure of the process (C1) is suppressed on the first side. As a result, the thickness of the solder resist layer 2 was reduced by 0.5 μm.

其次,為了使第一面及第二面之防焊層2硬化,以曝光量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理,而得到配線基板。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm及19.5μm之防焊層2所覆蓋,形成相當於該段差之厚度10.5μm的填膠堰塞用堤壩。此外,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度9.5μm之防焊層2。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之防焊層2的圓形開口部,而使外部連結用連結墊4之一部分露出。 Next, in order to cure the solder resist layer 2 of the first surface and the second surface, total exposure was performed at an exposure amount of 1000 mJ/cm 2 , and then heat hardening treatment was performed at 150 ° C for 60 minutes to obtain a wiring substrate. As a result of observation with an optical microscope, the conductor wiring 7 having a thickness of 15 μm was covered with the solder resist layer 2 having a thickness of 30 μm and 19.5 μm on the first surface, and a dam for filling the plug which had a thickness of 10.5 μm corresponding to the step was formed. In addition, the electronic component connecting connecting pads 3 having a thickness of 15 μm are exposed, and a solder resist layer 2 having a thickness of 9.5 μm is filled between the adjacent electronic component connecting connecting pads 3. Further, on the second surface, a part of the external connection connecting pad 4 having a thickness of 15 μm is formed with a circular opening portion of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm, and a part of the external connection connecting pad 4 is exposed. .

其次,測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度19.5μm之防焊層2的表面粗細度,表面粗細度Ra為0.40μm。此外,測定相鄰電子構件連結用連結墊3之間之防焊層2的表面粗細度,表面粗細度Ra為0.40μm。 Then, the surface roughness of the solder resist layer 2 having a thickness of 19.5 μm which is an outer circumference of the end portion of the plurality of electronic component connection connecting pads 3 disposed on the first surface and a thickness of 19.5 μm from the outer periphery of the end portion of 400 μm is measured. The surface roughness Ra was 0.40 μm. Further, the surface roughness of the solder resist layer 2 between the adjacent electronic component connecting pads 3 was measured, and the surface roughness Ra was 0.40 μm.

(實施例9) (Example 9)

除了製程(C4)及(C5)之曝光量為200mJ/cm2以外,以與實施例7相同之方法,實施製程(A)~製程(D)。以光學顯微鏡進行觀察,結果,在第一面及第二面,於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現防焊層2之殘渣。此外,至配置於第一面之電子構件連結用連結墊3之表面下6.0μm為止,充填著防焊層2。藉由製程(C4)及(C5)之氧環境下的非接觸曝光,在第一面,製程(C1)之接觸曝光所照射活性光線6之區域以外之防焊層2表面的光聚合獲得抑制,結果,防焊層2的厚度減少1.0μm。 The process (A) to the process (D) were carried out in the same manner as in Example 7 except that the exposure amounts of the processes (C4) and (C5) were 200 mJ/cm 2 . As a result of observing with an optical microscope, the residue of the solder resist layer 2 was not found on the first and second surfaces of the electronic component connecting connecting pad 3 and the external connecting connecting pad 4. In addition, the solder resist layer 2 is filled up to 6.0 μm below the surface of the connection pad 3 for electronic component connection disposed on the first surface. By the non-contact exposure in the oxygen environment of the processes (C4) and (C5), the photopolymerization of the surface of the solder resist layer 2 outside the region irradiated with the active light 6 by the contact exposure of the process (C1) is suppressed on the first side. As a result, the thickness of the solder resist layer 2 was reduced by 1.0 μm.

其次,為了使第一面及第二面之防焊層2硬化,以曝光量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理,而得到配線基板。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm及19μm之防焊層2所覆蓋,形成相當於該段差之厚度11μm的填膠堰塞用堤壩。此外,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度9.0μm之防焊層2。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之防焊層2的圓形開口部,而使外部連結用連結墊4之一部分露出。 Next, in order to cure the solder resist layer 2 of the first surface and the second surface, total exposure was performed at an exposure amount of 1000 mJ/cm 2 , and then heat hardening treatment was performed at 150 ° C for 60 minutes to obtain a wiring substrate. As a result of observation with an optical microscope, the conductor wiring 7 having a thickness of 15 μm was covered with the solder resist layer 2 having a thickness of 30 μm and 19 μm on the first surface, and a dam for filling the plug having a thickness of 11 μm corresponding to the step was formed. In addition, the electronic component connecting connecting pads 3 having a thickness of 15 μm are exposed, and a solder resist layer 2 having a thickness of 9.0 μm is filled between the adjacent electronic component connecting connecting pads 3. Further, on the second surface, a part of the external connection connecting pad 4 having a thickness of 15 μm is formed with a circular opening portion of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm, and a part of the external connection connecting pad 4 is exposed. .

其次,測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度19μm之防焊層2的表面 粗細度,表面粗細度Ra為0.50μm。此外,測定相鄰電子構件連結用連結墊3之間之防焊層2的表面粗細度,表面粗細度Ra為0.50μm。 Then, the outer surface of the end portion of the plurality of electronic component connection connecting pads 3 disposed on the first surface and the surface of the solder resist layer 2 having a thickness of 19 μm from the outer portion of the end portion of 400 μm are measured. The thickness and the surface roughness Ra were 0.50 μm. Further, the surface roughness of the solder resist layer 2 between the adjacent electronic component connecting pads 3 was measured, and the surface roughness Ra was 0.50 μm.

(實施例10) (Embodiment 10)

除了製程(C4)及(C5)之曝光量為1000mJ/cm2以外,以與實施例6相同之方法,實施製程(A)~製程(D)。以光學顯微鏡進行觀察,結果,在第一面及第二面,於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現防焊層2之殘渣。此外,至配置於第一面之電子構件連結用連結墊3之表面下5.0μm為止,充填著防焊層2,未確認到製程(C4)及(C5)之氧之聚合妨礙所導致之第一面之防焊層2的膜減。 The process (A) to the process (D) were carried out in the same manner as in Example 6, except that the exposure amounts of the processes (C4) and (C5) were 1000 mJ/cm 2 . As a result of observing with an optical microscope, the residue of the solder resist layer 2 was not found on the first and second surfaces of the electronic component connecting connecting pad 3 and the external connecting connecting pad 4. In addition, the solder resist layer 2 was filled up to 5.0 μm below the surface of the connection pad 3 for electronic component connection disposed on the first surface, and the first cause of the polymerization inhibition of oxygen in the processes (C4) and (C5) was not confirmed. The film of the solder resist layer 2 is reduced.

其次,為了使第一面及第二面之防焊層2硬化,以曝光量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理,而得到配線基板。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm及20μm之防焊層2所覆蓋,形成相當於該段差之厚度10μm的填膠堰塞用堤壩。此外,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度10.0μm之防焊層2。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之防焊層2的圓形開口部,而使外部連結用連結墊4之一部分露出。 Next, in order to cure the solder resist layer 2 of the first surface and the second surface, total exposure was performed at an exposure amount of 1000 mJ/cm 2 , and then heat hardening treatment was performed at 150 ° C for 60 minutes to obtain a wiring substrate. As a result of observation with an optical microscope, the conductor wiring 7 having a thickness of 15 μm was covered with the solder resist layer 2 having a thickness of 30 μm and 20 μm on the first surface, and a dam for filling the plug having a thickness of 10 μm corresponding to the step was formed. In addition, the electronic component connecting connecting pads 3 having a thickness of 15 μm are exposed, and a solder resist layer 2 having a thickness of 10.0 μm is filled between the adjacent electronic component connecting connecting pads 3. Further, on the second surface, a part of the external connection connecting pad 4 having a thickness of 15 μm is formed with a circular opening portion of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm, and a part of the external connection connecting pad 4 is exposed. .

其次,測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之防焊層2的表面粗細度,表面粗細度Ra為0.30μm。此外,測定相鄰電子構件連結用連結墊3之間之防焊層2的表面粗細度,表面粗細度Ra為0.30μm。 Then, the surface roughness of the solder resist layer 2 having a thickness of 20 μm from the outer circumference of the end portion of the plurality of electronic component connection connecting pads 3 disposed on the first surface and the thickness of the region between the outer portions of the end portion of 400 μm and the outer circumference is measured. The surface roughness Ra was 0.30 μm. Further, the surface roughness of the solder resist layer 2 between the adjacent electronic component connection connecting pads 3 was measured, and the surface roughness Ra was 0.30 μm.

(實施例11) (Example 11)

製程(C4)及(C5)時,除了以接觸曝光方式實施曝光以外,以與實施例7相同之方法,實施製程(A)~製程(D)。以光學顯微鏡進行觀察,結果,在第一面及第二面,於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現防焊層2之殘渣。此外,在第一面,至電子構件連結用連結墊3之表面下5.0μm為止,防焊層2充填於電子構件連結用連結墊3之間。製程(C4)及(C5)時,藉由充份執行接觸曝光時之排氣,而在非氧環境下實施曝光,故防焊層2表面未粗面化,結果,防焊層2的厚度未減少。 In the processes (C4) and (C5), the processes (A) to (D) were carried out in the same manner as in Example 7 except that exposure was performed by contact exposure. As a result of observing with an optical microscope, the residue of the solder resist layer 2 was not found on the first and second surfaces of the electronic component connecting connecting pad 3 and the external connecting connecting pad 4. In the first surface, the solder resist layer 2 is filled between the electronic component connecting connecting pads 3 until 5.0 μm below the surface of the electronic component connecting connecting pad 3 . In the processes (C4) and (C5), the exposure is performed in a non-oxygen environment by sufficiently performing the exhaust gas during the contact exposure, so that the surface of the solder resist layer 2 is not roughened, and as a result, the thickness of the solder resist layer 2 is obtained. Not reduced.

其次,為了使第一面及第二面之防焊層2硬化,以曝光量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理,而得到配線基板。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm及20μm之防焊層2所覆蓋,形成相當於該段差之厚度10μm的填膠堰塞用堤壩。此外,厚度 15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度10.0μm之防焊層2。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之防焊層2的圓形開口部,而使外部連結用連結墊4之一部分露出。 Next, in order to cure the solder resist layer 2 of the first surface and the second surface, total exposure was performed at an exposure amount of 1000 mJ/cm 2 , and then heat hardening treatment was performed at 150 ° C for 60 minutes to obtain a wiring substrate. As a result of observation with an optical microscope, the conductor wiring 7 having a thickness of 15 μm was covered with the solder resist layer 2 having a thickness of 30 μm and 20 μm on the first surface, and a dam for filling the plug having a thickness of 10 μm corresponding to the step was formed. In addition, the electronic component connecting connecting pads 3 having a thickness of 15 μm are exposed, and a solder resist layer 2 having a thickness of 10.0 μm is filled between the adjacent electronic component connecting connecting pads 3. Further, on the second surface, a part of the external connection connecting pad 4 having a thickness of 15 μm is formed with a circular opening portion of the solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm, and a part of the external connection connecting pad 4 is exposed. .

其次,測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之防焊層2的表面粗細度,表面粗細度Ra為0.10μm。此外,測定相鄰電子構件連結用連結墊3之間之防焊層2的表面粗細度,表面粗細度Ra為0.10μm。 Then, the surface roughness of the solder resist layer 2 having a thickness of 20 μm from the outer circumference of the end portion of the plurality of electronic component connection connecting pads 3 disposed on the first surface and the thickness of the region between the outer portions of the end portion of 400 μm and the outer circumference is measured. The surface roughness Ra was 0.10 μm. Further, the surface roughness of the solder resist layer 2 between the adjacent electronic component connecting pads 3 was measured, and the surface roughness Ra was 0.10 μm.

實施例7~11時,因為相鄰電子構件連結用連結墊3之間有足夠厚度之防焊層2,可以確實防止安裝電子構件時之焊劑所導致的電氣短路。因為防焊層2之殘渣不存在於外部連結用連結墊4上,安裝於外部電氣基板時,也可製作不會發生電氣絕緣不良之信賴性高的配線基板。比較實施例7~11的話,相較於電子構件連結用連結墊3之間及周圍之防焊層2表面平滑的實施例11所製造的配線基板,實施例7~10所製造的配線基板,填膠之黏著性高,連結信賴性優良。 In the seventh to eleventh embodiments, since the solder resist layer 2 having a sufficient thickness between the adjacent electronic component connecting pads 3 is provided, it is possible to surely prevent an electrical short circuit caused by the solder when the electronic component is mounted. Since the residue of the solder resist layer 2 does not exist on the external connection connecting pad 4, when it is mounted on an external electric board, it is possible to manufacture a wiring board having high reliability without causing electrical insulation failure. In the case of the wiring boards manufactured in the eleventh embodiment, the wiring boards manufactured in the seventh to tenth embodiments are smoother than the wiring boards manufactured in the eleventh embodiment in which the surface of the solder resist layer 2 between the electronic component connecting pads 3 and the periphery is smooth. The adhesive has high adhesion and excellent connection reliability.

(比較例2) (Comparative Example 2) <製程(A)> <Process (A)>

利用半加法,製作於兩表面形成有導體配線7之電路 基板1(面積170mm×200mm、導體厚度15μm、基板厚度0.4mm)。於表面(第一面),有當做電子構件連結用連結墊3來使用之線寬25μm、間隔50μm的導體配線。於背面(第二面),形成有當做外部連結用連結墊4來使用之直徑600μm之圓形狀導體配線。其次,使用真空層合機,將厚度25μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱:PFR-800 AUS410)真空熱壓接合(疊合溫度75℃、吸引時間30秒、加壓時間10秒)於上述電路基板1之兩表面。藉此,形成防焊層2。第一面之防焊層2時,從絕緣層8表面之厚度為30μm,電子構件連結用連結墊3上之厚度為15μm。第二面之防焊層2時,從絕緣層8表面之厚度為38μm,外部連結用連結墊4上之厚度為23μm。導體配線密度較小之第一面,相較於導體配線密度較大之第二面,防焊層2之厚度為較薄之8μm。 A circuit in which conductor wirings 7 are formed on both surfaces by a half addition method Substrate 1 (area 170 mm × 200 mm, conductor thickness 15 μm, substrate thickness 0.4 mm). On the surface (first surface), there is a conductor wiring having a line width of 25 μm and a spacing of 50 μm which is used as the connection pad 3 for electronic component connection. On the back surface (second surface), a circular conductor wiring having a diameter of 600 μm used as the external connection connecting mat 4 was formed. Next, a 25 mm-thick solder mask (manufactured by TAIYO INK MFG. CO., LTD., trade name: PFR-800 AUS410) was vacuum-compressed using a vacuum laminator (lamination temperature: 75 ° C, suction time: 30 seconds). The pressurization time is 10 seconds) on both surfaces of the circuit board 1 described above. Thereby, the solder resist layer 2 is formed. In the solder resist layer 2 of the first surface, the thickness from the surface of the insulating layer 8 was 30 μm, and the thickness of the connection pad 3 for electronic component connection was 15 μm. In the solder resist layer 2 of the second surface, the thickness from the surface of the insulating layer 8 was 38 μm, and the thickness of the external connection connecting pad 4 was 23 μm. On the first side where the conductor wiring density is small, the thickness of the solder resist layer 2 is 8 μm thinner than the second surface having a larger conductor wiring density.

<製程(C1)> <Process (C1)>

對第一面之防焊層2,使用對比距離複數電子構件連結用連結墊3之端部為200μm之外周更為外側的區域照射活性光線6之圖案的光罩5,以曝光量200mJ/cm2實施接觸曝光。 For the solder resist layer 2 of the first surface, the photomask 5 of the pattern of the active light rays 6 is irradiated with a region in which the end portion of the connection pad 3 of the plurality of electronic component connection is 200 μm and the outer side is irradiated with an exposure amount of 200 mJ/cm. 2 Implementation of contact exposure.

<製程(C2)> <Process (C2)>

對第二面之防焊層2,於外部連結用連結墊4上配設直徑500μm之圓形開口部區域,利用對圓形開口部區域 以外照射活性光線6之圖案的光罩5,以曝光量200mJ/cm2實施接觸曝光。 In the solder resist layer 2 on the second surface, a circular opening portion having a diameter of 500 μm is disposed on the external connection connecting pad 4, and the mask 5 that irradiates the pattern of the active light 6 to the outside of the circular opening portion is exposed. Contact exposure was carried out at a quantity of 200 mJ/cm 2 .

<製程(B1)> <Process (B1)>

剝離第一面及第二面之防焊層2上的支撐層膜後,使用10質量%之偏矽酸鈉水溶液(液溫25℃)當做薄膜化處理液,使第一面朝上,將電路基板1浸漬於薄膜化處理液25秒鐘,實施膠束化處理(薄膜化處理)。其後,實施利用膠束除去液(液溫25℃)之噴霧的膠束除去處理、水洗處理(液溫25℃)、及乾燥處理,至第一面之非曝光部的防焊層2的厚度成為電子構件連結用連結墊3之表面上5.0μm為止,實施平均10μm之防焊層2的薄膜化。以光學顯微鏡進行觀察,第一面之防焊層2表面沒有處理不均,而得到良好的面內均一性。另一方面,第二面之防焊層2也被實施平均10μm之薄膜化,然而,薄膜化處理液中之氣泡附著於第二面之非曝光部的防焊層2,出現膜厚不均一的部位。此外,於外部連結用連結墊4上,殘留有約13μm之防焊層2的殘渣。 After peeling off the support layer film on the first surface and the second surface of the solder resist layer 2, using a 10% by mass aqueous sodium metasilicate solution (liquid temperature: 25 ° C) as a thin film treatment liquid, with the first side facing up, The circuit board 1 was immersed in the thin film processing liquid for 25 seconds, and subjected to micellization treatment (thinning treatment). Thereafter, a micelle removal treatment, a water washing treatment (liquid temperature: 25° C.), and a drying treatment using a spray of a micelle removal liquid (liquid temperature: 25° C.) are performed to the solder resist layer 2 of the non-exposed portion of the first surface. When the thickness is 5.0 μm on the surface of the connection pad 3 for electronic component connection, thinning of the solder resist layer 2 of an average of 10 μm is performed. Observation by an optical microscope revealed that the surface of the solder resist layer 2 on the first side was not unevenly treated, and good in-plane uniformity was obtained. On the other hand, the solder resist layer 2 of the second surface is also thinned by an average of 10 μm. However, the bubbles in the thin film processing liquid adhere to the solder resist layer 2 of the non-exposed portion of the second surface, and the film thickness is uneven. The part. Further, on the external connection connecting pad 4, a residue of the solder resist layer 2 of about 13 μm remains.

<製程(C4)> <Process (C4)>

對第一面之防焊層2,使用對距離複數電子構件連結用連結墊3之端部為200μm的外周、及距離該端部400μm之外周之間之區域照射活性光線6之圖案的光罩5,利用氧環境下之非接觸曝光,以曝光量400mJ/cm2實 施曝光。 For the solder mask layer 2 of the first surface, a mask that irradiates the pattern of the active light rays 6 to the outer circumference of the end portion of the connection pad 3 for connecting the plurality of electronic components and the region between the outer circumferences of the end portion of 400 μm is used. 5. Exposure was carried out at an exposure amount of 400 mJ/cm 2 by non-contact exposure in an oxygen atmosphere.

<製程(B2)> <Process (B2)>

使用10質量%之偏矽酸鈉水溶液(液溫25℃)當做薄膜化處理液,使第一面朝上,將電路基板1浸漬於薄膜化處理液25秒鐘,實施膠束化處理(薄膜化處理)。其後,實施利用膠束除去液(液溫25℃)之噴霧的膠束除去處理、水洗處理(液溫25℃)、及乾燥處理,使第一面之非曝光部之防焊層2的厚度成為電子構件連結用連結墊3之表面下5.0μm為止,實施平均10μm之防焊層2的薄膜化。以光學顯微鏡進行觀察,第一面之防焊層2表面沒有處理不均,而得到良好的面內均一性。藉由製程(C4)之氧環境下的非接觸曝光,從距離配置於第一面之電子構件連結用連結墊3之端部200μm的外周至距離400μm之外周為止之區域之防焊層2表面的光聚合獲得抑制,結果,防焊層2的厚度減少0.5μm。另一方面,第二面之防焊層2也被實施平均10μm之薄膜化,然而,薄膜化處理液中之氣泡附著於第二面之非曝光部的防焊層2,出現膜厚不均一的部位。此外,於外部連結用連結墊4上,殘留有約3μm之防焊層2的殘渣。 Using a 10% by mass aqueous solution of sodium metasilicate (liquid temperature: 25 ° C) as a thin film treatment liquid, the first substrate was faced upward, and the circuit board 1 was immersed in the thin film treatment liquid for 25 seconds to carry out micellization treatment (film Treatment). Thereafter, a micelle removal treatment, a water washing treatment (liquid temperature: 25 ° C), and a drying treatment using a spray of a micelle removal liquid (liquid temperature: 25 ° C) were carried out to obtain a solder resist layer 2 of the non-exposed portion of the first surface. When the thickness is 5.0 μm below the surface of the connection pad 3 for electronic component connection, the thickness of the solder resist layer 2 having an average of 10 μm is formed. Observation by an optical microscope revealed that the surface of the solder resist layer 2 on the first side was not unevenly treated, and good in-plane uniformity was obtained. By the non-contact exposure in the oxygen atmosphere of the process (C4), the surface of the solder resist 2 from the outer periphery of the end portion of the connecting portion 3 of the electronic component connecting connection pad 3 disposed on the first surface to the outer periphery of the distance of 400 μm The photopolymerization was suppressed, and as a result, the thickness of the solder resist layer 2 was reduced by 0.5 μm. On the other hand, the solder resist layer 2 of the second surface is also thinned by an average of 10 μm. However, the bubbles in the thin film processing liquid adhere to the solder resist layer 2 of the non-exposed portion of the second surface, and the film thickness is uneven. The part. Further, on the external connection connecting pad 4, a residue of the solder resist layer 2 of about 3 μm remains.

其次,為了使第一面及第二面之防焊層2硬化,以曝光量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理,而得到配線基板。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線 7為厚度30μm及19.5μm之防焊層2所覆蓋,形成相當於該段差之厚度10.5μm的填膠堰塞用堤壩。此外,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度9.5μm之防焊層2。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之防焊層2的圓形開口部,然而,於外部連結用連結墊4上,殘留有3μm之防焊層2的殘渣。 Next, in order to cure the solder resist layer 2 of the first surface and the second surface, total exposure was performed at an exposure amount of 1000 mJ/cm 2 , and then heat hardening treatment was performed at 150 ° C for 60 minutes to obtain a wiring substrate. As a result of observation with an optical microscope, the conductor wiring 7 having a thickness of 15 μm was covered with the solder resist layer 2 having a thickness of 30 μm and 19.5 μm on the first surface, and a dam for filling the plug which had a thickness of 10.5 μm corresponding to the step was formed. In addition, the electronic component connecting connecting pads 3 having a thickness of 15 μm are exposed, and a solder resist layer 2 having a thickness of 9.5 μm is filled between the adjacent electronic component connecting connecting pads 3. Further, on the second surface, a circular opening portion having a solder resist layer 2 having a thickness of 38 μm and a diameter of 500 μm is formed in a part of the external connection connecting pad 4 having a thickness of 15 μm. However, on the external connection connecting pad 4, Residue of the 3 μm solder resist layer 2 remained.

安裝電子構件時,於相鄰電子構件連結用連結墊3之間有足夠厚度之防焊層2,可確實防止焊劑所導致的電氣短路,然而,安裝於外部電氣基板時,殘留於外部連結用連結墊4上之防焊層2的殘渣,導致焊劑凸塊連結發生電氣絕緣不良。 When the electronic component is mounted, the solder resist layer 2 having a sufficient thickness is provided between the adjacent electronic component connecting connecting pads 3, and the electrical short circuit caused by the solder can be surely prevented. However, when it is mounted on the external electrical substrate, it remains in the external connection. The residue of the solder resist layer 2 on the bonding pad 4 causes electrical insulation failure of the solder bump connection.

測定相鄰電子構件連結用連結墊3之間之防焊層2的表面粗細度,表面粗細度Ra為0.03μm。相較於電子構件連結用連結墊3之間之防焊表面平滑的比較例2所製造的配線基板,實施例7~11所製造的配線基板,填膠之黏著性高,連結信賴性優良。 The surface roughness of the solder resist layer 2 between the adjacent electronic component connecting pads 3 was measured, and the surface roughness Ra was 0.03 μm. The wiring board manufactured in the comparative example 2 which is smooth compared with the soldering surface of the connection pad 3 of the electronic component connection is the wiring board manufactured by the Example 7-11, and the adhesiveness of the filler is high, and the connection reliability is excellent.

實施例12~16,係第6-1圖、第6-2圖及第6-3圖所示之配線基板的製造方法(3)的相關例。 Examples 12 to 16 are related examples of the method (3) for manufacturing the wiring board shown in Figs. 6-1, 6-2, and 6-3.

(實施例12) (Embodiment 12) <製程(A1)> <Process (A1)>

利用半加法,製作於兩表面形成有導體配線7之電路 基板1(面積170mm×200mm、導體厚度15μm、基板厚度0.4mm)。於表面(第一面),有當做電子構件連結用連結墊3來使用之線寬25μm、間隔50μm的導體配線。於背面(第二面),形成有當做外部連結用連結墊4來使用之直徑600μm之圓形狀導體配線。其次,使用真空層合機,將厚度15μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱:PFR-800 AUS410)真空熱壓接合於上述電路基板1之表面,並將厚度25μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱:PFR-800 AUS410)真空熱壓接合於上述電路基板1之背面(疊合溫度75℃、吸引時間30秒、加壓時間10秒)。藉此,形成第一防焊層2-1。第一面之第一防焊層2-1時,從絕緣層8表面之厚度為20μm,電子構件連結用連結墊3上之厚度為5μm。第二面之第一防焊層2-1時,從絕緣層8表面之厚度為38μm,外部連結用連結墊4上之厚度為23μm。 A circuit in which conductor wirings 7 are formed on both surfaces by a half addition method Substrate 1 (area 170 mm × 200 mm, conductor thickness 15 μm, substrate thickness 0.4 mm). On the surface (first surface), there is a conductor wiring having a line width of 25 μm and a spacing of 50 μm which is used as the connection pad 3 for electronic component connection. On the back surface (second surface), a circular conductor wiring having a diameter of 600 μm used as the external connection connecting mat 4 was formed. Next, a 15 mm-thick solder mask (manufactured by TAIYO INK MFG. CO., LTD., trade name: PFR-800 AUS410) was vacuum-compression bonded to the surface of the above-mentioned circuit board 1 using a vacuum laminator. A 25 μm solder mask (manufactured by TAIYO INK MFG. CO., LTD., trade name: PFR-800 AUS410) was vacuum-compression bonded to the back surface of the above-mentioned circuit board 1 (overlap temperature: 75 ° C, suction time: 30 seconds, pressurization) Time 10 seconds). Thereby, the first solder resist layer 2-1 is formed. In the first solder resist layer 2-1 of the first surface, the thickness from the surface of the insulating layer 8 is 20 μm, and the thickness of the connecting pad 3 for electronic component connection is 5 μm. In the first solder resist layer 2-1 on the second surface, the thickness from the surface of the insulating layer 8 was 38 μm, and the thickness of the external connection connecting pad 4 was 23 μm.

<製程(C1)> <Process (C1)>

對第一面之第一防焊層2-1,使用對比距離複數電子構件連結用連結墊3之端部為200μm之外周更為外側的區域照射活性光線6之圖案的光罩5,以曝光量200mJ/cm2實施接觸曝光。 For the first solder resist layer 2-1 of the first surface, the mask 5 of the pattern of the active light rays 6 is irradiated with a region in which the end portion of the connection pad 3 for the electronic component connection is 200 μm and the outer side of the connection pad 3 is exposed. Contact exposure was carried out at a quantity of 200 mJ/cm 2 .

<製程(C2)> <Process (C2)>

對第二面之第一防焊層2-1,於外部連結用連結墊4 上配設直徑500μm之圓形開口部區域,利用對圓形開口部區域以外照射活性光線6之圖案的光罩5,以曝光量200mJ/cm2實施接觸曝光。 In the first solder resist layer 2-1 on the second surface, a circular opening portion having a diameter of 500 μm is disposed on the external connection connecting pad 4, and a mask that illuminates the pattern of the active light 6 outside the circular opening portion is used. 5. Contact exposure was performed at an exposure amount of 200 mJ/cm 2 .

<製程(B)> <Process (B)>

剝離第一面及第二面之第一防焊層2-1上的支撐層膜後,使用10質量%之偏矽酸鈉水溶液(液溫25℃)當做薄膜化處理液,使第一面朝上,將電路基板1浸漬於薄膜化處理液25秒鐘,實施膠束化處理(薄膜化處理)。其後,實施利用膠束除去液(液溫25℃)之噴霧的膠束除去處理、水洗處理(液溫25℃)、及乾燥處理,至第一面之非曝光部的第一防焊層2-1之厚度成為電子構件連結用連結墊3之表面下5.0μm為止,實施平均10μm之第一防焊層2-1的薄膜化。以光學顯微鏡進行觀察,第一面之第一防焊層2-1表面沒有處理不均,而得到良好的面內均一性。另一方面,第二面之第一防焊層2-1也被實施平均10μm之薄膜化,然而,薄膜化處理液中之氣泡附著於第二面之非曝光部的第一防焊層2-1,出現膜厚不均一的部位。此外,於外部連結用連結墊4上,殘留有約13μm之第一防焊層2-1的殘渣。 After peeling off the support layer film on the first solder mask layer 2-1 on the first surface and the second surface, a 10% by mass aqueous sodium metasilicate solution (liquid temperature 25 ° C) is used as a thin film treatment liquid to make the first surface The circuit board 1 was immersed in the thin film processing liquid for 25 seconds, and subjected to micellization treatment (thinning treatment). Thereafter, a micelle removal treatment, a water washing treatment (liquid temperature: 25° C.), and a drying treatment using a spray of a micelle removal liquid (liquid temperature: 25° C.) are performed to the first solder resist layer of the non-exposed portion of the first surface. When the thickness of 2-1 is 5.0 μm below the surface of the connection pad 3 for electronic component connection, the first solder resist layer 2-1 having an average thickness of 10 μm is formed into a thin film. Observed by an optical microscope, the surface of the first solder resist layer 2-1 on the first side was not treated unevenly, and good in-plane uniformity was obtained. On the other hand, the first solder resist layer 2-1 of the second surface is also thinned by an average of 10 μm, however, the bubbles in the thin film processing liquid adhere to the first solder resist layer 2 of the non-exposed portion of the second surface. -1, where the film thickness is uneven. Further, on the external connection connecting pad 4, the residue of the first solder resist layer 2-1 of about 13 μm remains.

<製程(C3)> <Process (C3)>

對第一面之第一防焊層2-1,使用對於製程(B)被薄膜化區域照射活性光線6之圖案的光罩5,利用氧環境 下之非接觸曝光,以曝光量400mJ/cm2實施曝光。 For the first solder resist layer 2-1 of the first surface, a mask 5 for irradiating the pattern of the active light rays 6 to the thinned region of the process (B) is used, and the non-contact exposure under an oxygen atmosphere is used for an exposure amount of 400 mJ/cm. 2 implementation of exposure.

<製程(A2)> <Process (A2)>

使用真空層合機,將厚度15μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱:PFR-800 AUS410)真空熱壓接合於完成至製程(C3)為止之電路基板1之第一面之第一防焊層2-1上(疊合溫度75℃、吸引時間30秒、加壓時間10秒)。藉此,形成第一面之第二防焊層2-2。第一面之第二防焊層2-2時,從絕緣層8表面之厚度為30μm。 A solder mask (available from TAIYO INK MFG. CO., LTD., trade name: PFR-800 AUS410) having a thickness of 15 μm was vacuum-compression bonded to the circuit substrate 1 until completion of the process (C3) using a vacuum laminator. The first solder mask layer 2-1 on the first side (the superimposed temperature is 75 ° C, the suction time is 30 seconds, and the pressurization time is 10 seconds). Thereby, the second solder resist layer 2-2 of the first surface is formed. In the second solder resist layer 2-2 of the first surface, the thickness from the surface of the insulating layer 8 is 30 μm.

<製程(C6)> <Process (C6)>

對第一面之第二防焊層2-2,使用對比距離電子構件連結用連結墊3之端部400μm之外周更為外側的區域照射活性光線6之圖案的光罩5,以曝光量200mJ/cm2實施接觸曝光。 For the second solder resist layer 2-2 of the first surface, the mask 5 of the pattern of the active light rays 6 is irradiated with a region on the outer side of the outer peripheral portion of the connecting pad 3 of the electronic component connecting connecting pad 3, which is 400 μm, to the exposure amount of 200 mJ. /cm 2 performs contact exposure.

<製程(D1)> <Process (D1)>

使用1質量%之碳酸鈉水溶液(液溫度30℃、噴霧壓0.15MPa)實施30秒鐘顯影,除去第一面之非曝光部的第二防焊層2-2及第二面之非曝光部的第一防焊層2-1。藉此,形成填膠堰塞用堤壩,而且,再度使從被第二防焊層2-2所覆蓋之第一防焊層2-1露出之狀態的電子構件連結用連結墊3及其周圍之第一防焊層2-1露出。以光 學顯微鏡進行觀察,結果,在第一面及第二面,於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外,至配置於第一面之電子構件連結用連結墊3之表面下5.5μm為止,充填著第一防焊層2-1。藉由製程(C3)之氧環境下的非接觸曝光,配置於第一面之電子構件連結用連結墊3之間之第一防焊層2-1表面的光聚合獲得抑制,結果,第一面之第一防焊層2-1的厚度減少0.5μm。 Development was carried out for 30 seconds using a 1% by mass aqueous sodium carbonate solution (liquid temperature: 30° C., spray pressure: 0.15 MPa) to remove the second solder resist layer 2-2 of the non-exposed portion of the first surface and the non-exposed portion of the second surface. The first solder mask layer 2-1. In this way, the entangled plug dam is formed, and the electronic component connecting connecting pad 3 in a state in which the first solder resist layer 2-1 covered by the second solder resist layer 2-2 is exposed again and its surroundings is formed. The first solder resist layer 2-1 is exposed. Light When the microscope was observed, the first solder resist layer 2-1 and the second solder resist layer 2 were not found on the first and second surfaces of the electronic component connecting connecting pad 3 and the external connecting connecting pad 4. -2 residue. In addition, the first solder resist layer 2-1 is filled up to 5.5 μm below the surface of the connection pad 3 for electronic component connection disposed on the first surface. The photopolymerization of the surface of the first solder resist layer 2-1 disposed between the electronic component connection connecting pads 3 on the first surface is suppressed by the non-contact exposure in the oxygen atmosphere of the process (C3), and as a result, the first The thickness of the first solder resist layer 2-1 is reduced by 0.5 μm.

其次,為了使第一面之第一防焊層2-1、第二防焊層2-2、以及第二面之第一防焊層2-1硬化,以曝光量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理,而得到配線基板。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm及20μm之第一防焊層2-1及第二防焊層2-2所覆蓋,形成相當於該段差之厚度10μm的填膠堰塞用堤壩。此外,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度9.5μm之第一防焊層2-1。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之第一防焊層2-1的圓形開口部,而使外部連結用連結墊4之一部分露出。 Next, in order to harden the first solder resist layer 2-1, the second solder resist layer 2-2, and the first solder resist layer 2-1 of the second surface, the exposure amount is 1000 mJ/cm 2 . After exposure, heat-hardening treatment was performed at 150 ° C for 60 minutes to obtain a wiring board. As a result of observation with an optical microscope, as a result, on the first surface, the conductor wiring 7 having a thickness of 15 μm is covered by the first solder resist layer 2-1 and the second solder resist layer 2-2 having a thickness of 30 μm and 20 μm, forming a step corresponding to the step. The dam is filled with a plug of 10 μm in thickness. In addition, the electronic component connecting connecting pads 3 having a thickness of 15 μm are exposed, and a first solder resist layer 2-1 having a thickness of 9.5 μm is filled between the adjacent electronic component connecting connecting pads 3. Further, on the second surface, a part of the external connection connecting pad 4 having a thickness of 15 μm is formed with a circular opening portion of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm, and the external connection connecting pad is formed. One of the 4 parts is exposed.

其次,測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之第一防焊層2-1 的表面粗細度,表面粗細度Ra為0.05μm。此外,測定相鄰電子構件連結用連結墊3間之區域之第一防焊層2-1的表面粗細度,表面粗細度Ra為0.40μm。 Then, the first solder resist layer 2-1 having a thickness of 20 μm from the outer circumference of the end portion of the plurality of electronic component connection connecting pads 3 disposed on the first surface and the region between the outer portions of the end portion of 400 μm and the outer circumference of the end portion is measured. The surface roughness and the surface roughness Ra were 0.05 μm. Further, the surface roughness of the first solder resist layer 2-1 in the region between the adjacent electronic component connecting pads 3 was measured, and the surface roughness Ra was 0.40 μm.

(實施例13) (Example 13)

除了更替製程(C1)與製程(C2)之順序以外,以與實施例12相同之方法,實施製程(A1)~製程(D1)。以光學顯微鏡進行觀察,結果,在第一面及第二面,於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外,至配置於第一面之電子構件連結用連結墊3之表面下5.5μm為止,充填著第一防焊層2-1。藉由製程(C3)之氧環境下的非接觸曝光,配置於第一面之電子構件連結用連結墊3之間之第一防焊層2-1表面的光聚合獲得抑制,結果,第一防焊層2-1的厚減少0.5μm。 The process (A1) to the process (D1) were carried out in the same manner as in Example 12 except for the order of the process (C1) and the process (C2). As a result of observing with an optical microscope, the first solder resist layer 2-1 and the second solder resist layer were not found on the first and second surfaces of the electronic component connecting connecting pad 3 and the external connecting connecting pad 4. 2-2 residue. In addition, the first solder resist layer 2-1 is filled up to 5.5 μm below the surface of the connection pad 3 for electronic component connection disposed on the first surface. The photopolymerization of the surface of the first solder resist layer 2-1 disposed between the electronic component connection connecting pads 3 on the first surface is suppressed by the non-contact exposure in the oxygen atmosphere of the process (C3), and as a result, the first The thickness of the solder resist layer 2-1 is reduced by 0.5 μm.

其次,為了使第一面之第一防焊層2-1、第二防焊層2-2、以及第二面之第一防焊層2-1硬化,以曝光量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理,而得到配線基板。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm及20μm之第一防焊層2-1及第二防焊層2-2所覆蓋,形成相當於該段差之厚度10μm的填膠堰塞用堤壩。此外,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度9.5μm之第 一防焊層2-1。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之第一防焊層2-1的圓形開口部,而使外部連結用連結墊4之一部分露出。 Next, in order to harden the first solder resist layer 2-1, the second solder resist layer 2-2, and the first solder resist layer 2-1 of the second surface, the exposure amount is 1000 mJ/cm 2 . After exposure, heat-hardening treatment was performed at 150 ° C for 60 minutes to obtain a wiring board. As a result of observation with an optical microscope, as a result, on the first surface, the conductor wiring 7 having a thickness of 15 μm is covered by the first solder resist layer 2-1 and the second solder resist layer 2-2 having a thickness of 30 μm and 20 μm, forming a step corresponding to the step. The dam is filled with a plug of 10 μm in thickness. In addition, the electronic component connecting connecting pads 3 having a thickness of 15 μm are exposed, and a first solder resist layer 2-1 having a thickness of 9.5 μm is filled between the adjacent electronic component connecting connecting pads 3. Further, on the second surface, a part of the external connection connecting pad 4 having a thickness of 15 μm is formed with a circular opening portion of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm, and the external connection connecting pad is formed. One of the 4 parts is exposed.

其次,測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之第一防焊層2-1的表面粗細度,表面粗細度Ra為0.05μm。此外,測定相鄰電子構件連結用連結墊3間之區域之第一防焊層2-1的表面粗細度,表面粗細度Ra為0.40μm。 Then, the outer surface of the outer surface of the plurality of electronic component connection connecting pads 3 disposed on the first surface, and the first solder resist layer 2-1 having a thickness of 20 μm from the outer peripheral portion of the end portion of 400 μm are measured. The surface roughness and the surface roughness Ra were 0.05 μm. Further, the surface roughness of the first solder resist layer 2-1 in the region between the adjacent electronic component connecting pads 3 was measured, and the surface roughness Ra was 0.40 μm.

(實施例14) (Example 14)

除了製程(C3)之曝光量為200mJ/cm2以外,以與實施例12相同之方法,實施製程(A1)~製程(D1)。以光學顯微鏡進行觀察,結果,在第一面及第二面,於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外,至配置於第一面之電子構件連結用連結墊3之表面下6.0μm為止,充填著第一防焊層2-1。藉由製程(C3)之氧環境下的非接觸曝光,配置於第一面之電子構件連結用連結墊3之間之第一防焊層2-1表面的光聚合獲得抑制,結果,第一防焊層2-1的厚度減少1.0μm。 The process (A1) to the process (D1) were carried out in the same manner as in Example 12 except that the exposure amount of the process (C3) was 200 mJ/cm 2 . As a result of observing with an optical microscope, the first solder resist layer 2-1 and the second solder resist layer were not found on the first and second surfaces of the electronic component connecting connecting pad 3 and the external connecting connecting pad 4. 2-2 residue. In addition, the first solder resist layer 2-1 is filled up to 6.0 μm below the surface of the connection pad 3 for electronic component connection disposed on the first surface. The photopolymerization of the surface of the first solder resist layer 2-1 disposed between the electronic component connection connecting pads 3 on the first surface is suppressed by the non-contact exposure in the oxygen atmosphere of the process (C3), and as a result, the first The thickness of the solder resist layer 2-1 was reduced by 1.0 μm.

其次,為了使第一面之第一防焊層2-1、第二防焊層2-2、以及第二面之第一防焊層2-1硬化,以曝光 量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理,而得到配線基板。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm及20μm之第一防焊層2-1及第二防焊層2-2所覆蓋,形成相當於該段差之厚度10μm的填膠堰塞用堤壩。此外,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度9.0μm之第一防焊層2-1。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之第一防焊層2-1的圓形開口部,而使外部連結用連結墊4之一部分露出。 Next, in order to harden the first solder resist layer 2-1, the second solder resist layer 2-2, and the first solder resist layer 2-1 of the second surface, the exposure amount is 1000 mJ/cm 2 . After exposure, heat-hardening treatment was performed at 150 ° C for 60 minutes to obtain a wiring board. As a result of observation with an optical microscope, as a result, on the first surface, the conductor wiring 7 having a thickness of 15 μm is covered by the first solder resist layer 2-1 and the second solder resist layer 2-2 having a thickness of 30 μm and 20 μm, forming a step corresponding to the step. The dam is filled with a plug of 10 μm in thickness. In addition, the electronic component connecting connecting pads 3 having a thickness of 15 μm are exposed, and the first solder resist layer 2-1 having a thickness of 9.0 μm is filled between the adjacent electronic component connecting connecting pads 3. Further, on the second surface, a part of the external connection connecting pad 4 having a thickness of 15 μm is formed with a circular opening portion of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm, and the external connection connecting pad is formed. One of the 4 parts is exposed.

其次,測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之第一防焊層2-1的表面粗細度,表面粗細度Ra為0.05μm。此外,測定相鄰電子構件連結用連結墊3間之區域之第一防焊層2-1的表面粗細度,表面粗細度Ra為0.50μm。 Then, the outer surface of the outer surface of the plurality of electronic component connection connecting pads 3 disposed on the first surface, and the first solder resist layer 2-1 having a thickness of 20 μm from the outer peripheral portion of the end portion of 400 μm are measured. The surface roughness and the surface roughness Ra were 0.05 μm. Further, the surface roughness of the first solder resist layer 2-1 in the region between the adjacent electronic component connecting pads 3 was measured, and the surface roughness Ra was 0.50 μm.

(實施例15) (Example 15)

除了製程(C3)之曝光量為1000mJ/cm2以外,以與實施例12相同之方法,實施製程(A1)~製程(D1)。以光學顯微鏡進行觀察,結果,在第一面及第二面,於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外,至配置 於第一面之電子構件連結用連結墊3之表面下5.0μm為止,充填著第一防焊層2-1,未確認到製程(C3)之氧之聚合妨礙所導致之第一面之第一防焊層2-1的膜減。 The process (A1) to the process (D1) were carried out in the same manner as in Example 12 except that the exposure amount of the process (C3) was 1000 mJ/cm 2 . As a result of observing with an optical microscope, the first solder resist layer 2-1 and the second solder resist layer were not found on the first and second surfaces of the electronic component connecting connecting pad 3 and the external connecting connecting pad 4. 2-2 residue. In addition, the first solder resist layer 2-1 was filled up to 5.0 μm below the surface of the connection pad 3 for electronic component connection disposed on the first surface, and the first cause of the polymerization inhibition of oxygen in the process (C3) was not confirmed. The film of the first solder resist layer 2-1 is reduced.

其次,為了使第一面之第一防焊層2-1、第二防焊層2-2、以及第二面之第一防焊層2-1硬化,以曝光量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm及20μm之第一防焊層2-1及第二防焊層2-2所覆蓋,形成相當於該段差之厚度10μm的填膠堰塞用堤壩。此外,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度10.0μm之第一防焊層2-1。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之第一防焊層2-1的圓形開口部,而使外部連結用連結墊4之一部分露出。 Next, in order to harden the first solder resist layer 2-1, the second solder resist layer 2-2, and the first solder resist layer 2-1 of the second surface, the exposure amount is 1000 mJ/cm 2 . Exposure, followed by heat hardening treatment at 150 ° C for 60 minutes. As a result of observation with an optical microscope, as a result, on the first surface, the conductor wiring 7 having a thickness of 15 μm is covered by the first solder resist layer 2-1 and the second solder resist layer 2-2 having a thickness of 30 μm and 20 μm, forming a step corresponding to the step. The dam is filled with a plug of 10 μm in thickness. In addition, the electronic component connecting connecting pads 3 having a thickness of 15 μm are exposed, and a first solder resist layer 2-1 having a thickness of 10.0 μm is filled between the adjacent electronic component connecting connecting pads 3. Further, on the second surface, a part of the external connection connecting pad 4 having a thickness of 15 μm is formed with a circular opening portion of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm, and the external connection connecting pad is formed. One of the 4 parts is exposed.

其次,測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之第一防焊層2-1的表面粗細度,表面粗細度Ra為0.05μm。此外,測定相鄰電子構件連結用連結墊3間之區域之第一防焊層2-1的表面粗細度,表面粗細度Ra為0.30μm。 Then, the outer surface of the outer surface of the plurality of electronic component connection connecting pads 3 disposed on the first surface, and the first solder resist layer 2-1 having a thickness of 20 μm from the outer peripheral portion of the end portion of 400 μm are measured. The surface roughness and the surface roughness Ra were 0.05 μm. Further, the surface roughness of the first solder resist layer 2-1 in the region between the adjacent electronic component connecting pads 3 was measured, and the surface roughness Ra was 0.30 μm.

(實施例16) (Embodiment 16)

製程(C3)時,除了以接觸曝光方式實施曝光以外,以與實施例12相同之方法,實施製程(A1)~製程(D1)。以光學顯微鏡進行觀察,結果,在第一面及第二面,於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外,至配置於第一面之電子構件連結用連結墊3之表面下5.0μm為止,充填著第一防焊層2-1。製程(C3)時,藉由充份執行接觸曝光時之排氣,而在非氧環境下實施曝光,故第一防焊層2-1表面未粗面化,結果,第一防焊層2-1的厚度未減少。 In the process (C3), the process (A1) to the process (D1) were carried out in the same manner as in Example 12 except that exposure was performed by contact exposure. As a result of observing with an optical microscope, the first solder resist layer 2-1 and the second solder resist layer were not found on the first and second surfaces of the electronic component connecting connecting pad 3 and the external connecting connecting pad 4. 2-2 residue. In addition, the first solder resist layer 2-1 is filled up to 5.0 μm below the surface of the connection pad 3 for electronic component connection disposed on the first surface. In the process (C3), the exposure is performed in a non-oxygen environment by sufficiently performing the exhaust gas during the contact exposure, so that the surface of the first solder resist layer 2-1 is not roughened, and as a result, the first solder resist layer 2 is obtained. The thickness of -1 is not reduced.

其次,為了使第一面之第一防焊層2-1、第二防焊層2-2、以及第二面之第一防焊層2-1硬化,以曝光量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm及20μm之第一防焊層2-1及第二防焊層2-2所覆蓋,形成相當於該段差之厚度10μm的填膠堰塞用堤壩。此外,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度10.0μm之第一防焊層2-1。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之第一防焊層2-1的圓形開口部,而使外部連結用連結墊4之一部分露出。 Next, in order to harden the first solder resist layer 2-1, the second solder resist layer 2-2, and the first solder resist layer 2-1 of the second surface, the exposure amount is 1000 mJ/cm 2 . Exposure, followed by heat hardening treatment at 150 ° C for 60 minutes. As a result of observation with an optical microscope, as a result, on the first surface, the conductor wiring 7 having a thickness of 15 μm is covered by the first solder resist layer 2-1 and the second solder resist layer 2-2 having a thickness of 30 μm and 20 μm, forming a step corresponding to the step. The dam is filled with a plug of 10 μm in thickness. In addition, the electronic component connecting connecting pads 3 having a thickness of 15 μm are exposed, and a first solder resist layer 2-1 having a thickness of 10.0 μm is filled between the adjacent electronic component connecting connecting pads 3. Further, on the second surface, a part of the external connection connecting pad 4 having a thickness of 15 μm is formed with a circular opening portion of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm, and the external connection connecting pad is formed. One of the 4 parts is exposed.

其次,測定距離配置於第一面之複數電子構 件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之第一防焊層2-1的表面粗細度,表面粗細度Ra為0.05μm。此外,測定相鄰電子構件連結用連結墊3之間之第一防焊層2-1的表面粗細度,表面粗細度Ra為0.10μm。 Secondly, measuring the complex electronic structure of the first surface The outer thickness of the end portion of the connection bonding pad 3 and the surface roughness of the first solder resist layer 2-1 having a thickness of 20 μm from the outer portion of the end portion of 400 μm, the surface roughness Ra was 0.05 μm. Further, the surface roughness of the first solder resist layer 2-1 between the adjacent electronic component connecting pads 3 was measured, and the surface roughness Ra was 0.10 μm.

實施例12~16時,因為相鄰電子構件連結用連結墊3之間有足夠厚度之第一防焊層2-1,可以確實防止安裝電子構件時之焊劑所導致的電氣短路。因為第一防焊層2-1之殘渣不存在於外部連結用連結墊4上,安裝於外部電氣基板時,也可製作不會發生電氣絕緣不良之信賴性高的配線基板。比較實施例12~16的話,相較於電子構件連結用連結墊3之間之第一防焊層2-1之表面平滑的實施例16所製造的配線基板,實施例12~15所製造的配線基板,填膠之黏著性高,連結信賴性優良。 In the examples 12 to 16, the first solder resist layer 2-1 having a sufficient thickness between the adjacent electronic component connecting pads 3 can surely prevent an electrical short circuit caused by the solder when the electronic component is mounted. When the residue of the first solder resist layer 2-1 is not present on the external connection connecting pad 4, when it is mounted on an external electric board, it is possible to manufacture a wiring board having high reliability without causing electrical insulation failure. In Comparative Examples 12 to 16, the wiring boards manufactured in Example 16 which were smoother than the surface of the first solder resist layer 2-1 between the electronic component connection connecting pads 3 were produced in Examples 12 to 15. The wiring board has high adhesion to the glue and excellent connection reliability.

實施例17~21,係第7-1圖、第7-2圖及第7-3圖所示之配線基板的製造方法(4)的相關例。 Examples 17 to 21 are related examples of the method (4) for manufacturing the wiring board shown in Figs. 7-1, 7-2, and 7-3.

(實施例17) (Example 17) <製程(A1)> <Process (A1)>

利用半加法,製作於兩表面形成有導體配線7之電路基板1(面積170mm×200mm、導體厚度15μm、基板厚度0.4mm)。於表面(第一面),有當做電子構件連結用連結墊3來使用之線寬25μm、間隔50μm的導體配線。於背面(第二面),形成有當做外部連結用連結墊4來使用 之直徑600μm之圓形狀導體配線。其次,使用真空層合機,將厚度15μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱:PFR-800 AUS410)真空熱壓接合於上述電路基板1之表面,並將厚度25μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱:PFR-800 AUS410)真空熱壓接合於上述電路基板1之背面(疊合溫度75℃、吸引時間30秒、加壓時間10秒)。藉此,形成第一防焊層2-1。第一面之第一防焊層2-1時,從絕緣層8表面之厚度為20μm,電子構件連結用連結墊3上之厚度為5μm。第二面之第一防焊層2-1時,從絕緣層8表面之厚度為38μm,外部連結用連結墊4上之厚度為23μm。 The circuit board 1 (having an area of 170 mm × 200 mm, a conductor thickness of 15 μm, and a substrate thickness of 0.4 mm) on which conductor wirings 7 were formed on both surfaces was produced by a half addition method. On the surface (first surface), there is a conductor wiring having a line width of 25 μm and a spacing of 50 μm which is used as the connection pad 3 for electronic component connection. On the back side (second side), it is formed as a connection pad 4 for external connection. A circular conductor wire having a diameter of 600 μm. Next, a 15 mm-thick solder mask (manufactured by TAIYO INK MFG. CO., LTD., trade name: PFR-800 AUS410) was vacuum-compression bonded to the surface of the above-mentioned circuit board 1 using a vacuum laminator. A 25 μm solder mask (manufactured by TAIYO INK MFG. CO., LTD., trade name: PFR-800 AUS410) was vacuum-compression bonded to the back surface of the above-mentioned circuit board 1 (overlap temperature: 75 ° C, suction time: 30 seconds, pressurization) Time 10 seconds). Thereby, the first solder resist layer 2-1 is formed. In the first solder resist layer 2-1 of the first surface, the thickness from the surface of the insulating layer 8 is 20 μm, and the thickness of the connecting pad 3 for electronic component connection is 5 μm. In the first solder resist layer 2-1 on the second surface, the thickness from the surface of the insulating layer 8 was 38 μm, and the thickness of the external connection connecting pad 4 was 23 μm.

<製程(C1)> <Process (C1)>

對第一面之第一防焊層2-1,使用對比距離複數電子構件連結用連結墊3之端部為200μm之外周更為外側的區域照射活性光線6之圖案的光罩5,以曝光量200mJ/cm2實施接觸曝光。 For the first solder resist layer 2-1 of the first surface, the mask 5 of the pattern of the active light rays 6 is irradiated with a region in which the end portion of the connection pad 3 for the electronic component connection is 200 μm and the outer side of the connection pad 3 is exposed. Contact exposure was carried out at a quantity of 200 mJ/cm 2 .

<製程(C2)> <Process (C2)>

對第二面之第一防焊層2-1,於外部連結用連結墊4上配設直徑500μm之圓形開口部區域,利用對圓形開口部區域以外照射活性光線6之圖案的光罩5,以曝光量200mJ/cm2實施接觸曝光。 In the first solder resist layer 2-1 on the second surface, a circular opening portion having a diameter of 500 μm is disposed on the external connection connecting pad 4, and a mask that irradiates the pattern of the active light 6 to the outside of the circular opening portion is used. 5. Contact exposure was performed at an exposure amount of 200 mJ/cm 2 .

<製程(B)> <Process (B)>

剝離第一面及第二面之第一防焊層2-1上的支撐層膜後,使用10質量%之偏矽酸鈉水溶液(液溫25℃)當做薄膜化處理液,使第一面朝上,將電路基板1浸漬於薄膜化處理液25秒鐘,實施膠束化處理(薄膜化處理)。其後,實施利用膠束除去液(液溫25℃)之噴霧的膠束除去處理、水洗處理(液溫25℃)、及乾燥處理,至第一面之非曝光部的第一防焊層2-1之厚度成為電子構件連結用連結墊3之表面下5.0μm為止,實施平均10μm之第一防焊層2-1的薄膜化。以光學顯微鏡進行觀察,第一面之第一防焊層2-1表面沒有處理不均,而得到良好的面內均一性。另一方面,第二面之第一防焊層2-1也被實施平均10μm之薄膜化,然而,薄膜化處理液中之氣泡附著於第二面之非曝光部的第一防焊層2-1,出現膜厚不均一的部位。此外,於外部連結用連結墊4上,殘留有約13μm之第一防焊層2-1的殘渣。 After peeling off the support layer film on the first solder mask layer 2-1 on the first surface and the second surface, a 10% by mass aqueous sodium metasilicate solution (liquid temperature 25 ° C) is used as a thin film treatment liquid to make the first surface The circuit board 1 was immersed in the thin film processing liquid for 25 seconds, and subjected to micellization treatment (thinning treatment). Thereafter, a micelle removal treatment, a water washing treatment (liquid temperature: 25° C.), and a drying treatment using a spray of a micelle removal liquid (liquid temperature: 25° C.) are performed to the first solder resist layer of the non-exposed portion of the first surface. When the thickness of 2-1 is 5.0 μm below the surface of the connection pad 3 for electronic component connection, the first solder resist layer 2-1 having an average thickness of 10 μm is formed into a thin film. Observed by an optical microscope, the surface of the first solder resist layer 2-1 on the first side was not treated unevenly, and good in-plane uniformity was obtained. On the other hand, the first solder resist layer 2-1 of the second surface is also thinned by an average of 10 μm, however, the bubbles in the thin film processing liquid adhere to the first solder resist layer 2 of the non-exposed portion of the second surface. -1, where the film thickness is uneven. Further, on the external connection connecting pad 4, the residue of the first solder resist layer 2-1 of about 13 μm remains.

<製程(C3)> <Process (C3)>

對第一面之第一防焊層2-1,使用對於製程(B)被薄膜化區域照射活性光線6之圖案的光罩5,利用氧環境下之非接觸曝光,以曝光量400mJ/cm2實施曝光。 For the first solder resist layer 2-1 of the first surface, a mask 5 for irradiating the pattern of the active light rays 6 to the thinned region of the process (B) is used, and the non-contact exposure under an oxygen atmosphere is used for an exposure amount of 400 mJ/cm. 2 implementation of exposure.

<製程(D)> <Process (D)>

使用1質量%之碳酸鈉水溶液(液溫度30℃、噴霧 壓0.15MPa)實施30秒鐘顯影,除去第二面之非曝光部的第一防焊層2-1。 Use 1% by mass aqueous sodium carbonate solution (liquid temperature 30 ° C, spray The development was carried out for 30 seconds at a pressure of 0.15 MPa), and the first solder resist layer 2-1 of the non-exposed portion of the second surface was removed.

<製程(A2)> <Process (A2)>

使用真空層合機,將厚度15μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱:PFR-800 AUS410)真空熱壓接合於完成至製程(D)為止之電路基板1之第一面之第一防焊層2-1上(疊合溫度75℃、吸引時間30秒、加壓時間10秒)。藉此,形成第一面之第二防焊層2-2。第一面之第二防焊層2-2時,從絕緣層8表面之厚度為30μm。 A solder mask (available from TAIYO INK MFG. CO., LTD., trade name: PFR-800 AUS410) having a thickness of 15 μm was vacuum-compression bonded to the circuit substrate 1 until completion of the process (D) using a vacuum laminator. The first solder mask layer 2-1 on the first side (the superimposed temperature is 75 ° C, the suction time is 30 seconds, and the pressurization time is 10 seconds). Thereby, the second solder resist layer 2-2 of the first surface is formed. In the second solder resist layer 2-2 of the first surface, the thickness from the surface of the insulating layer 8 is 30 μm.

<製程(C6)> <Process (C6)>

對第一面之第二防焊層2-2,使用對比距離電子構件連結用連結墊3之端部400μm之外周更為外側的區域照射活性光線6之圖案的光罩5,以曝光量200mJ/cm2實施接觸曝光。 For the second solder resist layer 2-2 of the first surface, the mask 5 of the pattern of the active light rays 6 is irradiated with a region on the outer side of the outer peripheral portion of the connecting pad 3 of the electronic component connecting connecting pad 3, which is 400 μm, to the exposure amount of 200 mJ. /cm 2 performs contact exposure.

<製程(D2)> <Process (D2)>

使用1質量%之碳酸鈉水溶液(液溫度30℃、噴霧壓0.15MPa)實施30秒鐘顯影,除去第一面之非曝光部的第二防焊層2-2。藉此,形成填膠堰塞用堤壩,而且,再度使從被第二防焊層2-2所覆蓋之第一防焊層2-1露出之狀態的電子構件連結用連結墊3及其周圍之第一防焊層 2-1露出。以光學顯微鏡進行觀察,結果,在第一面及第二面,於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外,至配置於第一面之電子構件連結用連結墊3之表面下5.5μm為止,充填著第一防焊層2-1。藉由製程(C3)之氧環境下的非接觸曝光,配置於第一面之電子構件連結用連結墊3之間之第一防焊層2-1表面的光聚合獲得抑制,結果,第一面之第一防焊層2-1的厚度減少0.5μm。 Development was carried out for 30 seconds using a 1% by mass aqueous sodium carbonate solution (liquid temperature: 30 ° C, spray pressure: 0.15 MPa) to remove the second solder resist layer 2-2 of the non-exposed portion on the first surface. In this way, the entangled plug dam is formed, and the electronic component connecting connecting pad 3 in a state in which the first solder resist layer 2-1 covered by the second solder resist layer 2-2 is exposed again and its surroundings is formed. First solder mask 2-1 exposed. As a result of observing with an optical microscope, the first solder resist layer 2-1 and the second solder resist layer were not found on the first and second surfaces of the electronic component connecting connecting pad 3 and the external connecting connecting pad 4. 2-2 residue. In addition, the first solder resist layer 2-1 is filled up to 5.5 μm below the surface of the connection pad 3 for electronic component connection disposed on the first surface. The photopolymerization of the surface of the first solder resist layer 2-1 disposed between the electronic component connection connecting pads 3 on the first surface is suppressed by the non-contact exposure in the oxygen atmosphere of the process (C3), and as a result, the first The thickness of the first solder resist layer 2-1 is reduced by 0.5 μm.

其次,為了使第一面之第一防焊層2-1、第二防焊層2-2、以及第二面之第一防焊層2-1硬化,以曝光量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理,而得到配線基板。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm及20μm之第一防焊層2-1及第二防焊層2-2所覆蓋,形成相當於該段差之厚度10μm的填膠堰塞用堤壩。此外,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度9.5μm之第一防焊層2-1。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之第一防焊層2-1的圓形開口部,而使外部連結用連結墊4之一部分露出。 Next, in order to harden the first solder resist layer 2-1, the second solder resist layer 2-2, and the first solder resist layer 2-1 of the second surface, the exposure amount is 1000 mJ/cm 2 . After exposure, heat-hardening treatment was performed at 150 ° C for 60 minutes to obtain a wiring board. As a result of observation with an optical microscope, as a result, on the first surface, the conductor wiring 7 having a thickness of 15 μm is covered by the first solder resist layer 2-1 and the second solder resist layer 2-2 having a thickness of 30 μm and 20 μm, forming a step corresponding to the step. The dam is filled with a plug of 10 μm in thickness. In addition, the electronic component connecting connecting pads 3 having a thickness of 15 μm are exposed, and a first solder resist layer 2-1 having a thickness of 9.5 μm is filled between the adjacent electronic component connecting connecting pads 3. Further, on the second surface, a part of the external connection connecting pad 4 having a thickness of 15 μm is formed with a circular opening portion of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm, and the external connection connecting pad is formed. One of the 4 parts is exposed.

其次,測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之第一防焊層2-1 的表面粗細度,表面粗細度Ra為0.05μm。此外,測定相鄰電子構件連結用連結墊3間之區域之第一防焊層2-1的表面粗細度,表面粗細度Ra為0.40μm。 Then, the first solder resist layer 2-1 having a thickness of 20 μm from the outer circumference of the end portion of the plurality of electronic component connection connecting pads 3 disposed on the first surface and the region between the outer portions of the end portion of 400 μm and the outer circumference of the end portion is measured. The surface roughness and the surface roughness Ra were 0.05 μm. Further, the surface roughness of the first solder resist layer 2-1 in the region between the adjacent electronic component connecting pads 3 was measured, and the surface roughness Ra was 0.40 μm.

(實施例18) (Embodiment 18)

除了更替製程(C1)與製程(C2)之順序以外,以與實施例17相同之方法,實施製程(A1)~製程(D2)。以光學顯微鏡進行觀察,結果,在第一面及第二面,於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外,至配置於第一面之電子構件連結用連結墊3之表面下5.5μm為止,充填著第一防焊層2-1。藉由製程(C3)之氧環境下的非接觸曝光,配置於第一面之電子構件連結用連結墊3之間之第一防焊層2-1表面的光聚合獲得抑制,結果,第一面之第一防焊層2-1的厚度減少0.5μm。 The process (A1) to the process (D2) were carried out in the same manner as in Example 17, except that the order of the process (C1) and the process (C2) were replaced. As a result of observing with an optical microscope, the first solder resist layer 2-1 and the second solder resist layer were not found on the first and second surfaces of the electronic component connecting connecting pad 3 and the external connecting connecting pad 4. 2-2 residue. In addition, the first solder resist layer 2-1 is filled up to 5.5 μm below the surface of the connection pad 3 for electronic component connection disposed on the first surface. The photopolymerization of the surface of the first solder resist layer 2-1 disposed between the electronic component connection connecting pads 3 on the first surface is suppressed by the non-contact exposure in the oxygen atmosphere of the process (C3), and as a result, the first The thickness of the first solder resist layer 2-1 is reduced by 0.5 μm.

其次,為了使第一面之第一防焊層2-1、第二防焊層2-2、以及第二面之第一防焊層2-1硬化,以曝光量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理,而得到配線基板。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm及20μm之第一防焊層2-1及第二防焊層2-2所覆蓋,形成相當於該段差之厚度10μm的填膠堰塞用堤壩。此外,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度9.5μm之第 一防焊層2-1。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之第一防焊層2-1的圓形開口部,而使外部連結用連結墊4之一部分露出。 Next, in order to harden the first solder resist layer 2-1, the second solder resist layer 2-2, and the first solder resist layer 2-1 of the second surface, the exposure amount is 1000 mJ/cm 2 . After exposure, heat-hardening treatment was performed at 150 ° C for 60 minutes to obtain a wiring board. As a result of observation with an optical microscope, as a result, on the first surface, the conductor wiring 7 having a thickness of 15 μm is covered by the first solder resist layer 2-1 and the second solder resist layer 2-2 having a thickness of 30 μm and 20 μm, forming a step corresponding to the step. The dam is filled with a plug of 10 μm in thickness. In addition, the electronic component connecting connecting pads 3 having a thickness of 15 μm are exposed, and a first solder resist layer 2-1 having a thickness of 9.5 μm is filled between the adjacent electronic component connecting connecting pads 3. Further, on the second surface, a part of the external connection connecting pad 4 having a thickness of 15 μm is formed with a circular opening portion of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm, and the external connection connecting pad is formed. One of the 4 parts is exposed.

其次,測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之第一防焊層2-1的表面粗細度,表面粗細度Ra為0.05μm。此外,測定相鄰電子構件連結用連結墊3間之區域之第一防焊層2-1的表面粗細度,表面粗細度Ra為0.40μm。 Then, the outer surface of the outer surface of the plurality of electronic component connection connecting pads 3 disposed on the first surface, and the first solder resist layer 2-1 having a thickness of 20 μm from the outer peripheral portion of the end portion of 400 μm are measured. The surface roughness and the surface roughness Ra were 0.05 μm. Further, the surface roughness of the first solder resist layer 2-1 in the region between the adjacent electronic component connecting pads 3 was measured, and the surface roughness Ra was 0.40 μm.

(實施例19) (Embodiment 19)

除了製程(C3)之曝光量為200mJ/cm2以外,以與實施例17相同之方法,實施製程(A1)~製程(D2)。以光學顯微鏡進行觀察,結果,在第一面及第二面,於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外,至配置於第一面之電子構件連結用連結墊3之表面下6.0μm為止,充填著第一防焊層2-1。藉由製程(C3)之氧環境下的非接觸曝光,配置於第一面之電子構件連結用連結墊3之間之第一防焊層2-1表面的光聚合獲得抑制,結果,第一面之第一防焊層2-1的厚度減少1.0μm。 The process (A1) to the process (D2) were carried out in the same manner as in Example 17, except that the exposure amount of the process (C3) was 200 mJ/cm 2 . As a result of observing with an optical microscope, the first solder resist layer 2-1 and the second solder resist layer were not found on the first and second surfaces of the electronic component connecting connecting pad 3 and the external connecting connecting pad 4. 2-2 residue. In addition, the first solder resist layer 2-1 is filled up to 6.0 μm below the surface of the connection pad 3 for electronic component connection disposed on the first surface. The photopolymerization of the surface of the first solder resist layer 2-1 disposed between the electronic component connection connecting pads 3 on the first surface is suppressed by the non-contact exposure in the oxygen atmosphere of the process (C3), and as a result, the first The thickness of the first solder resist layer 2-1 was reduced by 1.0 μm.

其次,為了使第一面之第一防焊層2-1、第二防焊層2-2、以及第二面之第一防焊層2-1硬化,以曝光 量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理,而得到配線基板。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm及20μm之第一防焊層2-1及第二防焊層2-2所覆蓋,形成相當於該段差之厚度10μm的填膠堰塞用堤壩。此外,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度9.0μm之第一防焊層2-1。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之第一防焊層2-1的圓形開口部,而使外部連結用連結墊4之一部分露出。 Next, in order to harden the first solder resist layer 2-1, the second solder resist layer 2-2, and the first solder resist layer 2-1 of the second surface, the exposure amount is 1000 mJ/cm 2 . After exposure, heat-hardening treatment was performed at 150 ° C for 60 minutes to obtain a wiring board. As a result of observation with an optical microscope, as a result, on the first surface, the conductor wiring 7 having a thickness of 15 μm is covered by the first solder resist layer 2-1 and the second solder resist layer 2-2 having a thickness of 30 μm and 20 μm, forming a step corresponding to the step. The dam is filled with a plug of 10 μm in thickness. In addition, the electronic component connecting connecting pads 3 having a thickness of 15 μm are exposed, and the first solder resist layer 2-1 having a thickness of 9.0 μm is filled between the adjacent electronic component connecting connecting pads 3. Further, on the second surface, a part of the external connection connecting pad 4 having a thickness of 15 μm is formed with a circular opening portion of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm, and the external connection connecting pad is formed. One of the 4 parts is exposed.

其次,測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之第一防焊層2-1的表面粗細度,表面粗細度Ra為0.05μm。此外,測定相鄰電子構件連結用連結墊3間之區域之第一防焊層2-1的表面粗細度,表面粗細度Ra為0.50μm。 Then, the outer surface of the outer surface of the plurality of electronic component connection connecting pads 3 disposed on the first surface, and the first solder resist layer 2-1 having a thickness of 20 μm from the outer peripheral portion of the end portion of 400 μm are measured. The surface roughness and the surface roughness Ra were 0.05 μm. Further, the surface roughness of the first solder resist layer 2-1 in the region between the adjacent electronic component connecting pads 3 was measured, and the surface roughness Ra was 0.50 μm.

(實施例20) (Embodiment 20)

除了製程(C3)之曝光量為1000mJ/cm2以外,以與實施例17相同之方法,實施製程(A1)~製程(D2)。以光學顯微鏡進行觀察,結果,在第一面及第二面,於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外,至配置 於第一面之電子構件連結用連結墊3之表面下5.0μm為止,充填著第一防焊層2-1,未確認到製程(C3)之氧之聚合妨礙所導致之第一面之第一防焊層2-1的膜減。 The process (A1) to the process (D2) were carried out in the same manner as in Example 17 except that the exposure amount of the process (C3) was 1000 mJ/cm 2 . As a result of observing with an optical microscope, the first solder resist layer 2-1 and the second solder resist layer were not found on the first and second surfaces of the electronic component connecting connecting pad 3 and the external connecting connecting pad 4. 2-2 residue. In addition, the first solder resist layer 2-1 was filled up to 5.0 μm below the surface of the connection pad 3 for electronic component connection disposed on the first surface, and the first cause of the polymerization inhibition of oxygen in the process (C3) was not confirmed. The film of the first solder resist layer 2-1 is reduced.

其次,為了使第一面之第一防焊層2-1、第二防焊層2-2、以及第二面之第一防焊層2-1硬化,以曝光量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理,而得到配線基板。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm及20μm之第一防焊層2-1及第二防焊層2-2所覆蓋,形成相當於該段差之厚度10μm的填膠堰塞用堤壩。此外,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度10.0μm之第一防焊層2-1。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之第一防焊層2-1的圓形開口部,而使外部連結用連結墊4之一部分露出。 Next, in order to harden the first solder resist layer 2-1, the second solder resist layer 2-2, and the first solder resist layer 2-1 of the second surface, the exposure amount is 1000 mJ/cm 2 . After exposure, heat-hardening treatment was performed at 150 ° C for 60 minutes to obtain a wiring board. As a result of observation with an optical microscope, as a result, on the first surface, the conductor wiring 7 having a thickness of 15 μm is covered by the first solder resist layer 2-1 and the second solder resist layer 2-2 having a thickness of 30 μm and 20 μm, forming a step corresponding to the step. The dam is filled with a plug of 10 μm in thickness. In addition, the electronic component connecting connecting pads 3 having a thickness of 15 μm are exposed, and a first solder resist layer 2-1 having a thickness of 10.0 μm is filled between the adjacent electronic component connecting connecting pads 3. Further, on the second surface, a part of the external connection connecting pad 4 having a thickness of 15 μm is formed with a circular opening portion of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm, and the external connection connecting pad is formed. One of the 4 parts is exposed.

其次,測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之第一防焊層2-1的表面粗細度,表面粗細度Ra為0.05μm。此外,測定相鄰電子構件連結用連結墊3間之區域之第一防焊層2-1的表面粗細度,表面粗細度Ra為0.30μm。 Then, the outer surface of the outer surface of the plurality of electronic component connection connecting pads 3 disposed on the first surface, and the first solder resist layer 2-1 having a thickness of 20 μm from the outer peripheral portion of the end portion of 400 μm are measured. The surface roughness and the surface roughness Ra were 0.05 μm. Further, the surface roughness of the first solder resist layer 2-1 in the region between the adjacent electronic component connecting pads 3 was measured, and the surface roughness Ra was 0.30 μm.

(實施例21) (Example 21)

製程(C3)時,除了以接觸曝光方式實施曝光以外,以與實施例17相同之方法,實施製程(A1)~製程(D2)。以光學顯微鏡進行觀察,結果,在第一面及第二面,於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外,至配置於第一面之電子構件連結用連結墊3之表面下5.0μm為止,充填著第一防焊層2-1。製程(C3)時,藉由充份執行接觸曝光時之排氣,而在非氧環境下實施曝光,故第一防焊層2-1表面未粗面化,結果,第一防焊層2-1的厚度未減少。 In the process (C3), the process (A1) to the process (D2) were carried out in the same manner as in Example 17 except that exposure was performed by contact exposure. As a result of observing with an optical microscope, the first solder resist layer 2-1 and the second solder resist layer were not found on the first and second surfaces of the electronic component connecting connecting pad 3 and the external connecting connecting pad 4. 2-2 residue. In addition, the first solder resist layer 2-1 is filled up to 5.0 μm below the surface of the connection pad 3 for electronic component connection disposed on the first surface. In the process (C3), the exposure is performed in a non-oxygen environment by sufficiently performing the exhaust gas during the contact exposure, so that the surface of the first solder resist layer 2-1 is not roughened, and as a result, the first solder resist layer 2 is obtained. The thickness of -1 is not reduced.

其次,為了使第一面之第一防焊層2-1、第二防焊層2-2、以及第二面之第一防焊層2-1硬化,以曝光量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm及20μm之第一防焊層2-1及第二防焊層2-2所覆蓋,形成相當於該段差之厚度10μm的填膠堰塞用堤壩。此外,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度10.0μm之第一防焊層2-1。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之第一防焊層2-1的圓形開口部,而使外部連結用連結墊4之一部分露出。 Next, in order to harden the first solder resist layer 2-1, the second solder resist layer 2-2, and the first solder resist layer 2-1 of the second surface, the exposure amount is 1000 mJ/cm 2 . Exposure, followed by heat hardening treatment at 150 ° C for 60 minutes. As a result of observation with an optical microscope, as a result, on the first surface, the conductor wiring 7 having a thickness of 15 μm is covered by the first solder resist layer 2-1 and the second solder resist layer 2-2 having a thickness of 30 μm and 20 μm, forming a step corresponding to the step. The dam is filled with a plug of 10 μm in thickness. In addition, the electronic component connecting connecting pads 3 having a thickness of 15 μm are exposed, and a first solder resist layer 2-1 having a thickness of 10.0 μm is filled between the adjacent electronic component connecting connecting pads 3. Further, on the second surface, a part of the external connection connecting pad 4 having a thickness of 15 μm is formed with a circular opening portion of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm, and the external connection connecting pad is formed. One of the 4 parts is exposed.

其次,測定距離配置於第一面之複數電子構 件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之第一防焊層2-1的表面粗細度,表面粗細度Ra為0.05μm。此外,測定相鄰電子構件連結用連結墊3之間之第一防焊層2-2的表面粗細度,表面粗細度Ra為0.10μm。 Secondly, measuring the complex electronic structure of the first surface The outer thickness of the end portion of the connection bonding pad 3 and the surface roughness of the first solder resist layer 2-1 having a thickness of 20 μm from the outer portion of the end portion of 400 μm, the surface roughness Ra was 0.05 μm. Further, the surface roughness of the first solder resist 2-2 between the adjacent electronic component connection pads 3 was measured, and the surface roughness Ra was 0.10 μm.

實施例17~21時,因為相鄰電子構件連結用連結墊3之間有足夠厚度之第一防焊層2-1,可以確實防止安裝電子構件時之焊劑所導致的電氣短路。因為第一防焊層2-1之殘渣不存在於外部連結用連結墊4上,安裝於外部電氣基板時,也可製作不會發生電氣絕緣不良之信賴性高的配線基板。比較實施例17~21的話,相較於電子構件連結用連結墊3之間之第一防焊層2-1之表面平滑的實施例21所製造的配線基板,實施例17~20所製造的配線基板,填膠之黏著性高,連結信賴性優良。 In the case of the first to the second embodiments, the first solder resist layer 2-1 having a sufficient thickness between the adjacent electronic component connecting pads 3 can reliably prevent an electrical short circuit caused by the solder when the electronic component is mounted. When the residue of the first solder resist layer 2-1 is not present on the external connection connecting pad 4, when it is mounted on an external electric board, it is possible to manufacture a wiring board having high reliability without causing electrical insulation failure. In Comparative Examples 17 to 21, the wiring boards manufactured in Example 21 which were smoother than the surface of the first solder resist layer 2-1 between the electronic component connecting pads 3 were produced in Examples 17 to 20. The wiring board has high adhesion to the glue and excellent connection reliability.

實施例22~25,係第8-1圖、第8-2圖及第8-3圖所示之配線基板的製造方法(5)的相關例。 Examples 22 to 25 are related examples of the method (5) for manufacturing the wiring board shown in Figs. 8-1, 8-2, and 8-3.

(實施例22) (Example 22) <製程(A1)> <Process (A1)>

利用半加法,製作於兩表面形成有導體配線7之電路基板1(面積170mm×200mm、導體厚度15μm、基板厚度0.4mm)。於表面(第一面),有當做電子構件連結用連結墊3來使用之線寬25μm、間隔50μm的導體配線。於背面(第二面),形成有當做外部連結用連結墊4來使用 之直徑600μm之圓形狀導體配線。其次,使用真空層合機,將厚度15μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱:PFR-800 AUS410)真空熱壓接合於上述電路基板1之表面,並將厚度25μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱:PFR-800 AUS410)真空熱壓接合於上述電路基板1之背面(疊合溫度75℃、吸引時間30秒、加壓時間10秒)。藉此,形成第一防焊層2-1。第一面之第一防焊層2-1時,從絕緣層8表面之厚度為20μm,電子構件連結用連結墊3上之厚度為5μm。第二面之第一防焊層2-1時,從絕緣層8表面之厚度為38μm,外部連結用連結墊4上的厚度為23μm。 The circuit board 1 (having an area of 170 mm × 200 mm, a conductor thickness of 15 μm, and a substrate thickness of 0.4 mm) on which conductor wirings 7 were formed on both surfaces was produced by a half addition method. On the surface (first surface), there is a conductor wiring having a line width of 25 μm and a spacing of 50 μm which is used as the connection pad 3 for electronic component connection. On the back side (second side), it is formed as a connection pad 4 for external connection. A circular conductor wire having a diameter of 600 μm. Next, a 15 mm-thick solder mask (manufactured by TAIYO INK MFG. CO., LTD., trade name: PFR-800 AUS410) was vacuum-compression bonded to the surface of the above-mentioned circuit board 1 using a vacuum laminator. A 25 μm solder mask (manufactured by TAIYO INK MFG. CO., LTD., trade name: PFR-800 AUS410) was vacuum-compression bonded to the back surface of the above-mentioned circuit board 1 (overlap temperature: 75 ° C, suction time: 30 seconds, pressurization) Time 10 seconds). Thereby, the first solder resist layer 2-1 is formed. In the first solder resist layer 2-1 of the first surface, the thickness from the surface of the insulating layer 8 is 20 μm, and the thickness of the connecting pad 3 for electronic component connection is 5 μm. In the first solder resist layer 2-1 on the second surface, the thickness from the surface of the insulating layer 8 was 38 μm, and the thickness of the external connection connecting pad 4 was 23 μm.

<製程(C2)> <Process (C2)>

對第二面之第一防焊層2-1,於外部連結用連結墊4上配設直徑500μm之圓形開口部區域,利用對圓形開口部區域以外照射活性光線6之圖案的光罩5,以曝光量200mJ/cm2實施接觸曝光。 In the first solder resist layer 2-1 on the second surface, a circular opening portion having a diameter of 500 μm is disposed on the external connection connecting pad 4, and a mask that irradiates the pattern of the active light 6 to the outside of the circular opening portion is used. 5. Contact exposure was performed at an exposure amount of 200 mJ/cm 2 .

<製程(B)> <Process (B)>

剝離第一面及第二面之第一防焊層2-1上的支撐層膜後,使用10質量%之偏矽酸鈉水溶液(液溫25℃)當做薄膜化處理液,使第一面朝上,將電路基板1浸漬於薄膜化處理液25秒鐘,實施膠束化處理(薄膜化處理)。其後,實施利用膠束除去液(液溫25℃)之噴霧的膠束除 去處理、水洗處理(液溫25℃)、及乾燥處理,至第一面之非曝光部的第一防焊層2-1之厚度成為電子構件連結用連結墊3之表面下5.0μm為止,實施平均10μm之第一防焊層2-1的薄膜化。以光學顯微鏡進行觀察,第一面之第一防焊層2-1表面沒有處理不均,而得到良好的面內均一性。另一方面,第二面之第一防焊層2-1也被實施平均10μm之薄膜化,然而,薄膜化處理液中之氣泡附著於第二面之非曝光部的第一防焊層2-1,出現膜厚不均一的部位。此外,於外部連結用連結墊4上,殘留有約13μm之第一防焊層2-1的殘渣。 After peeling off the support layer film on the first solder mask layer 2-1 on the first surface and the second surface, a 10% by mass aqueous sodium metasilicate solution (liquid temperature 25 ° C) is used as a thin film treatment liquid to make the first surface The circuit board 1 was immersed in the thin film processing liquid for 25 seconds, and subjected to micellization treatment (thinning treatment). Thereafter, the micelles of the spray using the micelle removal liquid (liquid temperature 25 ° C) are removed. After the treatment, the water washing treatment (liquid temperature: 25 ° C), and the drying treatment, the thickness of the first solder resist layer 2-1 in the non-exposed portion of the first surface is 5.0 μm below the surface of the connecting member 3 for the electronic component connection. Thinning of the first solder resist layer 2-1 having an average of 10 μm is performed. Observed by an optical microscope, the surface of the first solder resist layer 2-1 on the first side was not treated unevenly, and good in-plane uniformity was obtained. On the other hand, the first solder resist layer 2-1 of the second surface is also thinned by an average of 10 μm, however, the bubbles in the thin film processing liquid adhere to the first solder resist layer 2 of the non-exposed portion of the second surface. -1, where the film thickness is uneven. Further, on the external connection connecting pad 4, the residue of the first solder resist layer 2-1 of about 13 μm remains.

<製程(C3)> <Process (C3)>

對第一面之第一防焊層2-1,使用對於製程(B)被薄膜化區域照射活性光線6之圖案的光罩5,利用氧環境下之非接觸曝光,以曝光量400mJ/cm2實施曝光。 For the first solder resist layer 2-1 of the first surface, a mask 5 for irradiating the pattern of the active light rays 6 to the thinned region of the process (B) is used, and the non-contact exposure under an oxygen atmosphere is used for an exposure amount of 400 mJ/cm. 2 implementation of exposure.

<製程(A2)> <Process (A2)>

使用真空層合機,將厚度20μm之防焊膜(TAIYO INK MFG.CO.,LTD.製、商品名稱:PFR-800 AUS410)真空熱壓接合於完成至製程(C)為止之電路基板1之第一面之第一防焊層2-1上(疊合溫度75℃、吸引時間30秒、加壓時間10秒)。藉此,形成第一面之第二防焊層2-2。第一面之第二防焊層2-2時,從絕緣層8表面之厚度為30μm。 A solder resist film (manufactured by TAIYO INK MFG. CO., LTD., trade name: PFR-800 AUS410) having a thickness of 20 μm was vacuum-compression bonded to the circuit substrate 1 until completion of the process (C) using a vacuum laminator. The first solder mask layer 2-1 on the first side (the superimposed temperature is 75 ° C, the suction time is 30 seconds, and the pressurization time is 10 seconds). Thereby, the second solder resist layer 2-2 of the first surface is formed. In the second solder resist layer 2-2 of the first surface, the thickness from the surface of the insulating layer 8 is 30 μm.

<製程(C6)> <Process (C6)>

對第一面之第二防焊層2-2,使用對比距離電子構件連結用連結墊3之端部400μm之外周更為外側的區域照射活性光線6之圖案的光罩5,以曝光量200mJ/cm2實施接觸曝光。 For the second solder resist layer 2-2 of the first surface, the mask 5 of the pattern of the active light rays 6 is irradiated with a region on the outer side of the outer peripheral portion of the connecting pad 3 of the electronic component connecting connecting pad 3, which is 400 μm, to the exposure amount of 200 mJ. /cm 2 performs contact exposure.

<製程(B3)> <Process (B3)>

剝離第一面之第二防焊層2-2上的支撐層膜後,使用10質量%之偏矽酸鈉水溶液(液溫25℃)當做薄膜化處理液,使第一面朝上,將電路基板1浸漬於薄膜化處理液25秒鐘,實施膠束化處理(薄膜化處理)。其後,實施利用膠束除去液(液溫25℃)之噴霧的膠束除去處理、水洗處理(液溫25℃)、及乾燥處理,至第一面之非曝光部的第二防焊層2-2之厚度成為電子構件連結用連結墊3之表面上5.0μm為止,實施平均10μm之第二防焊層2-2的薄膜化。以光學顯微鏡進行觀察,第一面之第二防焊層2-2表面沒有處理不均,而得到良好的面內均一性。另一方面,第二面之第一防焊層2-1也被實施平均10μm之薄膜化,然而,薄膜化處理液中之氣泡附著於第二面之非曝光部的第一防焊層2-1,出現膜厚不均一的部位。此外,於外部連結用連結墊4上,殘留有約3μm之第一防焊層2-1的殘渣。 After peeling off the support layer film on the second solder resist layer 2-2 of the first surface, using a 10% by mass aqueous sodium metasilicate solution (liquid temperature: 25 ° C) as a thin film treatment liquid, with the first side facing up, The circuit board 1 was immersed in the thin film processing liquid for 25 seconds, and subjected to micellization treatment (thinning treatment). Thereafter, a micelle removal treatment, a water washing treatment (liquid temperature: 25° C.), and a drying treatment using a spray of a micelle removal liquid (liquid temperature: 25° C.) are performed to a second solder resist layer of the non-exposed portion of the first surface. The thickness of 2-2 is 5.0 μm on the surface of the connection pad 3 for electronic component connection, and the second solder resist layer 2-2 having an average thickness of 10 μm is formed into a thin film. Observed by an optical microscope, the surface of the second solder resist layer 2-2 on the first side was not treated unevenly, and good in-plane uniformity was obtained. On the other hand, the first solder resist layer 2-1 of the second surface is also thinned by an average of 10 μm, however, the bubbles in the thin film processing liquid adhere to the first solder resist layer 2 of the non-exposed portion of the second surface. -1, where the film thickness is uneven. Further, on the external connection connecting pad 4, the residue of the first solder resist layer 2-1 of about 3 μm remains.

<製程(C7)> <Process (C7)>

對第一面之第二防焊層2-2,使用對比距離電子構件連結用連結墊3之端部200μm之外周更為外側的區域照射活性光線6之圖案的光罩5,利用氧環境下之非接觸曝光,以曝光量400mJ/cm2實施曝光。 For the second solder resist layer 2-2 of the first surface, the mask 5 of the pattern of the active light rays 6 is irradiated with a region on the outer side of the outer portion of the connecting pad 3 of the connecting member 3 for a distance of 200 μm, and the oxygen mask is used. The non-contact exposure was carried out at an exposure amount of 400 mJ/cm 2 .

<製程(D1)> <Process (D1)>

使用1質量%之碳酸鈉水溶液(液溫度30℃、噴霧壓0.15MPa)實施30秒鐘顯影,除去第一面之非曝光部的第二防焊層2-2及第二面之非曝光部的第一防焊層2-1。藉此,形成填膠堰塞用堤壩,而且,再度使從被第二防焊層2-2所覆蓋之第一防焊層2-1露出之狀態的電子構件連結用連結墊3及其周圍之第一防焊層2-1露出。以光學顯微鏡進行觀察,結果,在第一面及第二面,於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外,至配置於第一面之電子構件連結用連結墊3之表面下5.5μm為止,充填著第一防焊層2-1。藉由製程(C3)之氧環境下的非接觸曝光,配置於第一面之電子構件連結用連結墊3之間之第一防焊層2-1表面的光聚合獲得抑制,結果,第一面之第一防焊層2-1的厚度減少0.5μm。此外,藉由製程(C7)之氧環境下的非接觸曝光,距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之第二防 焊層2-2之表面的光聚合獲得抑制,結果,厚度20μm之第二防焊層2-2之表面厚度減少0.5μm。 Development was carried out for 30 seconds using a 1% by mass aqueous sodium carbonate solution (liquid temperature: 30° C., spray pressure: 0.15 MPa) to remove the second solder resist layer 2-2 of the non-exposed portion of the first surface and the non-exposed portion of the second surface. The first solder mask layer 2-1. In this way, the entangled plug dam is formed, and the electronic component connecting connecting pad 3 in a state in which the first solder resist layer 2-1 covered by the second solder resist layer 2-2 is exposed again and its surroundings is formed. The first solder resist layer 2-1 is exposed. As a result of observing with an optical microscope, the first solder resist layer 2-1 and the second solder resist layer were not found on the first and second surfaces of the electronic component connecting connecting pad 3 and the external connecting connecting pad 4. 2-2 residue. In addition, the first solder resist layer 2-1 is filled up to 5.5 μm below the surface of the connection pad 3 for electronic component connection disposed on the first surface. The photopolymerization of the surface of the first solder resist layer 2-1 disposed between the electronic component connection connecting pads 3 on the first surface is suppressed by the non-contact exposure in the oxygen atmosphere of the process (C3), and as a result, the first The thickness of the first solder resist layer 2-1 is reduced by 0.5 μm. Further, by the non-contact exposure in the oxygen atmosphere of the process (C7), the outer circumference of the end portion of the plurality of electronic component connection connecting pads 3 disposed on the first surface is 200 μm, and the outer circumference of the end portion is 400 μm. The second defense of the thickness of the area 20μm The photopolymerization of the surface of the solder layer 2-2 was suppressed, and as a result, the surface thickness of the second solder resist layer 2-2 having a thickness of 20 μm was reduced by 0.5 μm.

其次,為了使第一面之第一防焊層2-1、第二防焊層2-2、以及第二面之第一防焊層2-1硬化,以曝光量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理,而得到配線基板。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm及19.5μm之第二防焊層2-2所覆蓋,形成相當於該段差之厚度10.5μm的填膠堰塞用堤壩。此外,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度9.5μm之第一防焊層2-1。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之第一防焊層2-1的圓形開口部,而使外部連結用連結墊4之一部分露出。 Next, in order to harden the first solder resist layer 2-1, the second solder resist layer 2-2, and the first solder resist layer 2-1 of the second surface, the exposure amount is 1000 mJ/cm 2 . After exposure, heat-hardening treatment was performed at 150 ° C for 60 minutes to obtain a wiring board. As a result of observation with an optical microscope, as a result, on the first surface, the conductor wiring 7 having a thickness of 15 μm was covered with the second solder resist layer 2-2 having a thickness of 30 μm and 19.5 μm, and a filler of 10.5 μm having a thickness corresponding to the step was formed. Plug the dam. In addition, the electronic component connecting connecting pads 3 having a thickness of 15 μm are exposed, and a first solder resist layer 2-1 having a thickness of 9.5 μm is filled between the adjacent electronic component connecting connecting pads 3. Further, on the second surface, a part of the external connection connecting pad 4 having a thickness of 15 μm is formed with a circular opening portion of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm, and the external connection connecting pad is formed. One of the 4 parts is exposed.

其次,測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度19.5μm之第二防焊層2-2的表面粗細度,表面粗細度Ra為0.40μm。此外,測定相鄰電子構件連結用連結墊3間之區域之第一防焊層2-1的表面粗細度,表面粗細度Ra為0.40μm。 Next, the second solder resist layer 2-2 having a thickness of 19.5 μm from the outer circumference of the end portion of the plurality of electronic component connection connecting pads 3 disposed on the first surface and the region between the outer portions of the end portion of 400 μm and the outer circumference is measured. The surface roughness and the surface roughness Ra were 0.40 μm. Further, the surface roughness of the first solder resist layer 2-1 in the region between the adjacent electronic component connecting pads 3 was measured, and the surface roughness Ra was 0.40 μm.

(實施例23) (Example 23)

除了製程(C3)及(C7)之曝光量為200mJ/cm2以 外,以與實施例22相同之方法,實施製程(A1)~製程(D1)。以光學顯微鏡進行觀察,結果,在第一面及第二面,於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外,至配置於第一面之電子構件連結用連結墊3之表面下6.0μm為止,充填著第一防焊層2-1。藉由製程(C3)之氧環境下的非接觸曝光,配置於第一面之電子構件連結用連結墊3之間之第一防焊層2-1表面的光聚合獲得抑制,結果,第一面之第一防焊層2-1的厚度減少1.0μm。此外,藉由製程(C7)之氧環境下的非接觸曝光,距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之第二防焊層2-2之表面的光聚合獲得抑制,結果,厚度20μm之第二防焊層2-2之表面的厚度減少1.0μm。 The process (A1) to the process (D1) were carried out in the same manner as in Example 22 except that the exposure amounts of the processes (C3) and (C7) were 200 mJ/cm 2 . As a result of observing with an optical microscope, the first solder resist layer 2-1 and the second solder resist layer were not found on the first and second surfaces of the electronic component connecting connecting pad 3 and the external connecting connecting pad 4. 2-2 residue. In addition, the first solder resist layer 2-1 is filled up to 6.0 μm below the surface of the connection pad 3 for electronic component connection disposed on the first surface. The photopolymerization of the surface of the first solder resist layer 2-1 disposed between the electronic component connection connecting pads 3 on the first surface is suppressed by the non-contact exposure in the oxygen atmosphere of the process (C3), and as a result, the first The thickness of the first solder resist layer 2-1 was reduced by 1.0 μm. Further, by the non-contact exposure in the oxygen atmosphere of the process (C7), the outer circumference of the end portion of the plurality of electronic component connection connecting pads 3 disposed on the first surface is 200 μm, and the outer circumference of the end portion is 400 μm. The photopolymerization of the surface of the second solder resist layer 2-2 having a thickness of 20 μm was suppressed, and as a result, the thickness of the surface of the second solder resist layer 2-2 having a thickness of 20 μm was reduced by 1.0 μm.

其次,為了使第一面之防焊層2-1及2-2、第二面之第一防焊層2-1硬化,以曝光量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理,而得到配線基板。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm及19μm之第一防焊層2-1及第二防焊層2-2所覆蓋,形成相當於該段差之厚度11μm的填膠堰塞用堤壩。此外,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度9.0μm之第一防焊層2-1。此 外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之第一防焊層2-1的圓形開口部,而使外部連結用連結墊4之一部分露出。 Next, in order to cure the solder resist layers 2-1 and 2-2 of the first surface and the first solder resist layer 2-1 of the second surface, full exposure is performed at an exposure amount of 1000 mJ/cm 2 , followed by 150 ° C. The wiring substrate was obtained by a heat hardening treatment for 60 minutes. Observation with an optical microscope revealed that the conductor wiring 7 having a thickness of 15 μm was covered by the first solder resist layer 2-1 and the second solder resist layer 2-2 having a thickness of 30 μm and 19 μm on the first surface, forming a step corresponding to the step. The dam is filled with a plug of 11 μm in thickness. In addition, the electronic component connecting connecting pads 3 having a thickness of 15 μm are exposed, and the first solder resist layer 2-1 having a thickness of 9.0 μm is filled between the adjacent electronic component connecting connecting pads 3. Further, on the second surface, a part of the external connection connecting pad 4 having a thickness of 15 μm is formed with a circular opening portion of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm, and the external connection connecting pad is formed. One of the 4 parts is exposed.

其次,測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度19μm之第二防焊層2-2的表面粗細度,表面粗細度Ra為0.50μm。此外,測定相鄰電子構件連結用連結墊3間之區域之第一防焊層2-1的表面粗細度,表面粗細度Ra為0.50μm。 Then, the second solder resist layer 2-2 having a thickness of 19 μm from the outer periphery of the end portion of the plurality of electronic component connecting connecting pads 3 disposed on the first surface and the region between the outer portions of the end portion of 400 μm and the outer periphery of the connecting portion 3 was measured. The surface roughness and the surface roughness Ra were 0.50 μm. Further, the surface roughness of the first solder resist layer 2-1 in the region between the adjacent electronic component connecting pads 3 was measured, and the surface roughness Ra was 0.50 μm.

(實施例24) (Example 24)

除了製程(C3)及(C7)之曝光量為1000mJ/cm2以外,以與實施例22相同之方法,實施製程(A1)~製程(D1)。以光學顯微鏡進行觀察,結果,在第一面及第二面,於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外,至配置於第一面之電子構件連結用連結墊3之表面下5.0μm為止,充填著第一防焊層2-1,未確認到製程(C3)及(C7)之氧之聚合妨礙所導致之第一面之第一防焊層2-1及第一面之第二防焊層2-2的膜減。 The process (A1) to the process (D1) were carried out in the same manner as in Example 22 except that the exposure amounts of the processes (C3) and (C7) were 1000 mJ/cm 2 . As a result of observing with an optical microscope, the first solder resist layer 2-1 and the second solder resist layer were not found on the first and second surfaces of the electronic component connecting connecting pad 3 and the external connecting connecting pad 4. 2-2 residue. In addition, the first solder resist layer 2-1 was filled up to 5.0 μm below the surface of the connection pad 3 for electronic component connection disposed on the first surface, and the polymerization polymerization of the processes (C3) and (C7) was not confirmed. The film of the first solder resist layer 2-1 on the first side and the second solder resist layer 2-2 on the first side is reduced.

其次,為了使第一面之第一防焊層2-1、第二防焊層2-2、以及第二面之第一防焊層2-1硬化,以曝光量1000mJ/cm2實施全面曝光,接著,以150℃實施60分 鐘之熱硬化處理,而得到配線基板。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm及20μm之第一防焊層2-1及第二防焊層2-2所覆蓋,形成相當於該段差之厚度10μm的填膠堰塞用堤壩。此外,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度10.0μm之第一防焊層2-1。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之第一防焊層2-1的圓形開口部,而使外部連結用連結墊4之一部分露出。 Next, in order to harden the first solder resist layer 2-1, the second solder resist layer 2-2, and the first solder resist layer 2-1 of the second surface, the exposure amount is 1000 mJ/cm 2 . After exposure, heat-hardening treatment was performed at 150 ° C for 60 minutes to obtain a wiring board. As a result of observation with an optical microscope, as a result, on the first surface, the conductor wiring 7 having a thickness of 15 μm is covered by the first solder resist layer 2-1 and the second solder resist layer 2-2 having a thickness of 30 μm and 20 μm, forming a step corresponding to the step. The dam is filled with a plug of 10 μm in thickness. In addition, the electronic component connecting connecting pads 3 having a thickness of 15 μm are exposed, and a first solder resist layer 2-1 having a thickness of 10.0 μm is filled between the adjacent electronic component connecting connecting pads 3. Further, on the second surface, a part of the external connection connecting pad 4 having a thickness of 15 μm is formed with a circular opening portion of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm, and the external connection connecting pad is formed. One of the 4 parts is exposed.

其次,測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之第二防焊層2-2的表面粗細度,表面粗細度Ra為0.30μm。此外,測定相鄰電子構件連結用連結墊3間之區域之第一防焊層2-1的表面粗細度,表面粗細度Ra為0.30μm。 Then, the second solder resist layer 2-2 having a thickness of 20 μm from the outer periphery of the end portion of the plurality of electronic component connection connecting pads 3 disposed on the first surface and the region between the outer portions of the end portion of 400 μm and the outer circumference of the connecting portion 3 was measured. The surface roughness and the surface roughness Ra were 0.30 μm. Further, the surface roughness of the first solder resist layer 2-1 in the region between the adjacent electronic component connecting pads 3 was measured, and the surface roughness Ra was 0.30 μm.

(實施例25) (Embodiment 25)

製程(C3)及(C7)時,除了以接觸曝光方式實施曝光以外,以與實施例22相同之方法,實施製程(A1)~製程(D1)。以光學顯微鏡進行觀察,結果,在第一面及第二面,於電子構件連結用連結墊3及外部連結用連結墊4上皆未發現第一防焊層2-1及第二防焊層2-2之殘渣。此外,至配置於第一面之電子構件連結用連結墊3之 表面下5.0μm為止,充填著第一防焊層2-1。製程(C3)及(C7)時,藉由充份執行接觸曝光時之排氣,而在非氧環境下實施曝光,故防焊層2表面未粗面化,結果,第一面之第一防焊層2-1及第一面之第二防焊層2-2的厚度未減少。 In the processes (C3) and (C7), the process (A1) to the process (D1) were carried out in the same manner as in Example 22 except that exposure was performed by contact exposure. As a result of observing with an optical microscope, the first solder resist layer 2-1 and the second solder resist layer were not found on the first and second surfaces of the electronic component connecting connecting pad 3 and the external connecting connecting pad 4. 2-2 residue. Further, to the connection pad 3 for electronic component connection disposed on the first surface The first solder resist layer 2-1 is filled up to 5.0 μm below the surface. In the processes (C3) and (C7), the exposure is performed in a non-oxygen environment by fully performing the exhaust gas during the contact exposure, so that the surface of the solder resist layer 2 is not roughened, and as a result, the first surface is first. The thickness of the solder resist layer 2-1 and the second solder resist layer 2-2 of the first surface is not reduced.

其次,為了使第一面之第一防焊層2-1、第二防焊層2-2、以及第二面之第一防焊層2-1硬化,以曝光量1000mJ/cm2實施全面曝光,接著,以150℃實施60分鐘之熱硬化處理。以光學顯微鏡進行觀察,結果,在第一面,厚度15μm之導體配線7為厚度30μm及20μm之第一防焊層2-1及第二防焊層2-2所覆蓋,形成相當於該段差之厚度10μm的填膠堰塞用堤壩。此外,厚度15μm之電子構件連結用連結墊3露出,於相鄰電子構件連結用連結墊3之間,充填著厚度10μm之第一防焊層2-1。此外,在第二面,於厚度15μm之外部連結用連結墊4上的一部分,形成有厚度38μm、直徑500μm之第一防焊層2-1的圓形開口部,而使外部連結用連結墊4之一部分露出。 Next, in order to harden the first solder resist layer 2-1, the second solder resist layer 2-2, and the first solder resist layer 2-1 of the second surface, the exposure amount is 1000 mJ/cm 2 . Exposure, followed by heat hardening treatment at 150 ° C for 60 minutes. As a result of observation with an optical microscope, as a result, on the first surface, the conductor wiring 7 having a thickness of 15 μm is covered by the first solder resist layer 2-1 and the second solder resist layer 2-2 having a thickness of 30 μm and 20 μm, forming a step corresponding to the step. The dam is filled with a plug of 10 μm in thickness. In addition, the electronic component connecting connecting pads 3 having a thickness of 15 μm are exposed, and a first solder resist layer 2-1 having a thickness of 10 μm is filled between the adjacent electronic component connecting connecting pads 3. Further, on the second surface, a part of the external connection connecting pad 4 having a thickness of 15 μm is formed with a circular opening portion of the first solder resist layer 2-1 having a thickness of 38 μm and a diameter of 500 μm, and the external connection connecting pad is formed. One of the 4 parts is exposed.

其次,測定距離配置於第一面之複數電子構件連結用連結墊3之端部200μm的外周、及距離該端部400μm之外周之間之區域之厚度20μm之第二防焊層2-2的表面粗細度,表面粗細度Ra為0.10μm。此外,測定相鄰電子構件連結用連結墊3之間之第一防焊層2-1的表面粗細度,表面粗細度Ra為0.10μm。 Then, the second solder resist layer 2-2 having a thickness of 20 μm from the outer periphery of the end portion of the plurality of electronic component connection connecting pads 3 disposed on the first surface and the region between the outer portions of the end portion of 400 μm and the outer circumference of the connecting portion 3 was measured. The surface roughness and the surface roughness Ra were 0.10 μm. Further, the surface roughness of the first solder resist layer 2-1 between the adjacent electronic component connecting pads 3 was measured, and the surface roughness Ra was 0.10 μm.

實施例22~25時,因為相鄰電子構件連結用連結墊3之間有足夠厚度之第一防焊層2-1,可以確實防止安裝電子構件時之焊劑所導致的電氣短路。因為第一防焊層2-1之殘渣不存在於外部連結用連結墊4上,安裝於外部電氣基板時,也可製作不會發生電氣絕緣不良之信賴性高的配線基板。比較實施例22~25的話,相較於電子構件連結用連結墊3之間之第一防焊層2-1及電子構件連結用連結墊3周圍之第二防焊層2-2之表面平滑的實施例25所製造的配線基板,實施例22~24所製造的配線基板,填膠之黏著性高,連結信賴性優良。 In the case of the second to fifth embodiments, the first solder resist layer 2-1 having a sufficient thickness between the adjacent electronic component connecting pads 3 can reliably prevent an electrical short circuit caused by the solder when the electronic component is mounted. When the residue of the first solder resist layer 2-1 is not present on the external connection connecting pad 4, when it is mounted on an external electric board, it is possible to manufacture a wiring board having high reliability without causing electrical insulation failure. Comparing the examples 22 to 25, the surface of the first solder resist layer 2-1 and the second solder resist layer 2-2 around the connecting pad 3 for electronic component connection are smoother than those of the electronic component connecting connecting pads 3. In the wiring board manufactured in Example 25, the wiring boards manufactured in Examples 22 to 24 had high adhesion to the glue and excellent connection reliability.

如上述說明所示,實施例1~6所製造之配線基板,第一面之電子構件連結用連結墊3的一部分從防焊層2露出。使用該配線基板進行覆晶連結時,即使為以高密度配置電子構件連結用連結墊3之配線基板時,因為相鄰電子構件連結用連結墊3之間有足夠厚度之防焊層2,可以確實防止安裝電子構件時之焊劑所導致的電氣短路。此外,絕緣層8與電子構件連結用連結墊3之接著強度、及電子構件連結用連結墊3與焊劑之接著強度增大,得到高連結信賴性。此外,以氧環境下之非接觸曝光方式來實施製程(C3)之曝光時,因為電子構件連結用連結墊3周圍之防焊層2的表面被充份粗面化,填膠之黏著性良好,而得到高連結信賴性。此外,因為第二面之外部連結用連結墊4之表面上也沒有防焊層2之殘渣,安裝於外部基板時,得到不會發生焊劑連結之電氣絕緣不良的高連結信賴 性。 As described above, in the wiring board manufactured in the first to sixth embodiments, a part of the electronic component connecting connecting pad 3 on the first surface is exposed from the solder resist layer 2. When the wiring board is connected by the wiring board, the wiring board of the connection pad 3 for the electronic component connection is disposed at a high density, and the solder resist layer 2 having a sufficient thickness between the adjacent electronic component connection pads 3 can be used. It does prevent electrical shorts caused by flux when mounting electronic components. In addition, the bonding strength of the insulating layer 8 and the connecting pad 3 for electronic component connection, and the bonding strength between the connecting pad 3 for electronic component connection and the flux are increased, and high connection reliability is obtained. In addition, when the process (C3) is performed by the non-contact exposure method in an oxygen atmosphere, the surface of the solder resist layer 2 around the connection pad 3 for electronic component connection is sufficiently roughened, and the adhesiveness of the glue is good. And get high link reliability. Further, since the surface of the external connection connecting pad 4 on the second surface does not have the residue of the solder resist layer 2, when it is mounted on the external substrate, high connection reliability is obtained in which electrical insulation failure that does not cause solder connection is obtained. Sex.

如上述說明所示,實施例7~26所製造之配線基板,電子構件連結用連結墊3之一部分從防焊層2(第一防焊層2-1)露出,此外,具有由二段構造之防焊層2(第一防焊層2-1及第二防焊層2-2)所形成的填膠堰塞用堤壩。使用該配線基板進行覆晶連結時,可以防止充填於電子構件與配線基板之間之填膠溢至周圍而對電氣連結信賴性產生的不良影響。此外,即使為以高密度配置電子構件連結用連結墊3之配線基板時,因為相鄰電子構件連結用連結墊3之間有足夠厚度之防焊層2(第一防焊層2-1),可以確實防止安裝電子構件時之焊劑所導致的電氣短路。絕緣層8與電子構件連結用連結墊3之接著強度、及電子構件連結用連結墊3與焊劑之接著強度增大,得到高連結信賴性。此外,配線基板的製造方法(2)之製程(C4)及(C5)、配線基板的製造方法(3)、(4)、(5)之製程(C3)、以及配線基板的製造方法(5)之製程(C7)之曝光以氧環境下之非接觸曝光方式來實施時,因為電子構件連結用連結墊3之間、及周圍之防焊層2(第一防焊層2-1、第二防焊層2-2)表面被充份粗面化,填膠之黏著性良好,得到高連結信賴性。此外,因為第二面之外部連結用連結墊4之表面上也沒有第一防焊層2-1之殘渣,安裝於外部基板時,得到不會發生焊劑連結之電氣絕緣不良的高連結信賴性。 As described above, in the wiring board manufactured in the examples 7 to 26, one portion of the connection pad 3 for electronic component connection is exposed from the solder resist layer 2 (first solder resist layer 2-1), and has a two-stage structure. A dam for filling the plug formed by the solder resist layer 2 (the first solder resist layer 2-1 and the second solder resist layer 2-2). When the wiring board is used for the flip chip connection, it is possible to prevent the rubber filling between the electronic component and the wiring board from overflowing to the surroundings and adversely affecting the electrical connection reliability. Further, even when the wiring board of the connection pad 3 for electronic component connection is disposed at a high density, the solder resist layer 2 (first solder resist layer 2-1) having a sufficient thickness between the adjacent connection pads 3 for electronic component connection is provided. It can surely prevent the electrical short circuit caused by the flux when the electronic component is mounted. The bonding strength between the insulating layer 8 and the connecting pad 3 for electronic component connection, and the bonding strength between the connecting pad 3 for electronic component connection and the flux are increased, and high connection reliability is obtained. Further, the processes (C4) and (C5) of the method (2) of manufacturing the wiring board, the manufacturing method (3) of the wiring board, the process (C3) of (4), (5), and the manufacturing method of the wiring board (5) When the exposure of the process (C7) is performed by a non-contact exposure method in an oxygen atmosphere, the solder resist layer 2 between the connection pads 3 for electronic components and the periphery (the first solder resist layer 2-1, the first) The surface of the second solder resist layer 2-2) is sufficiently roughened, and the adhesiveness of the filler is good, and high connection reliability is obtained. Further, since the surface of the external connection connecting pad 4 on the second surface does not have the residue of the first solder resist layer 2-1, when mounted on the external substrate, high connection reliability is obtained without causing electrical connection failure of the solder connection. .

[產業上的可利用性] [Industrial availability]

本發明之配線基板的製造方法,例如,適用於用以製造具有以連結半導體晶片及其他印刷線路板等電子構件為目的之複數連結墊之配線基板的用途。 The method for producing a wiring board of the present invention is, for example, applied to a wiring board having a plurality of connection pads for the purpose of connecting electronic components such as semiconductor wafers and other printed wiring boards.

1‧‧‧電路基板 1‧‧‧ circuit substrate

2‧‧‧防焊層 2‧‧‧ solder mask

3‧‧‧電子構件連結用連結墊、第一面之連結墊 3‧‧‧Connecting pads for electronic components and connecting pads for the first side

4‧‧‧外部連結用連結墊、第二面之連結墊 4‧‧‧Connecting mat for external connection and connecting mat for second side

7‧‧‧導體配線 7‧‧‧Conductor wiring

8‧‧‧絕緣層 8‧‧‧Insulation

Claims (21)

一種配線基板的製造方法,係具有於兩表面具有絕緣層、及形成於絕緣層表面之連結墊的電路基板,於電路基板之兩表面,具有防焊層,使連結墊之一部分從防焊層露出之配線基板的製造方法,其特徵為,含有:於兩表面具有絕緣層、及形成於絕緣層表面之連結墊之電路基板的兩表面,形成厚度不同之防焊層的製程(A);對厚度薄於第二面之防焊層的第一面之防焊層,實施於後製程之製程(B)被薄膜化區域以外部分之曝光的製程(C1);對第二面之防焊層,實施於後製程之製程(D)被顯影之區域以外部分之曝光的製程(C2);於第一面,以薄膜化處理液實施使非曝光部之防焊層成為連結墊之厚度以下為止的薄膜化,來使連結墊之一部分露出的製程(B);對第一面之防焊層,實施於製程(B)被薄膜化之區域部分之曝光的製程(C3);以及以顯影液除去第二面之非曝光部之防焊層的製程(D)。 A method of manufacturing a wiring board, comprising: a circuit board having an insulating layer on both surfaces and a bonding pad formed on a surface of the insulating layer; and having a solder resist layer on both surfaces of the circuit board, and a part of the bonding pad is removed from the solder resist layer The method for manufacturing an exposed wiring substrate, comprising: a process (A) for forming a solder resist layer having different thicknesses on both surfaces of a circuit board having an insulating layer on both surfaces and a connection pad formed on the surface of the insulating layer; The solder resist layer having a thickness smaller than the first surface of the solder mask of the second surface is subjected to a process (C1) of the process of the post-process (B) exposed to the portion outside the thinned region; and the solder resist for the second face The layer is subjected to a process (C2) of exposing a portion of the process other than the developed region in the process of the post-process (D2); and the film-forming treatment liquid is used to make the solder resist layer of the non-exposed portion equal to the thickness of the connection pad on the first surface a process (B) for exposing one portion of the connection pad to the film formation, a process for exposing the portion of the first surface to the exposed portion of the process (B), and a developing process (C3); The liquid removes the non-exposed portion of the second side Process solder layer (D). 一種配線基板的製造方法,係具有於兩表面具有絕緣層、及形成於絕緣層表面之連結墊的電路基板,於電路基板之兩表面,具有防焊層,使連結墊之一部分從防焊層露出之配線基板的製造方法,其特徵為,含有: 於兩表面具有絕緣層、及形成於絕緣層表面之連結墊之電路基板的兩表面,形成厚度不同之防焊層的製程(A);對厚度薄於第二面之防焊層的第一面之防焊層,實施後製程之製程(B1)被薄膜化區域以外部分之曝光的製程(C1);對第二面之防焊層,實施於後製程之製程(D)被顯影之區域以外部分之曝光的製程(C2);對第一面,在連結墊未露出之範圍,以薄膜化處理液,實施非曝光部之防焊層之薄膜化的製程(B1);於第一面之防焊層,實施於後製程之製程(B2)被薄膜化區域以外部分之曝光的製程(C4);於第一面,以薄膜化處理液實施使非曝光部之防焊層成為連結墊之厚度以下為止的薄膜化,來使連結墊之一部分露出的製程(B2);對第一面之防焊層,實施於製程(B2)被薄膜化之區域部分之曝光的製程(C5);以及以顯影液除去第二面之非曝光部之防焊層的製程(D)。 A method of manufacturing a wiring board, comprising: a circuit board having an insulating layer on both surfaces and a bonding pad formed on a surface of the insulating layer; and having a solder resist layer on both surfaces of the circuit board, and a part of the bonding pad is removed from the solder resist layer A method of manufacturing an exposed wiring substrate, comprising: a process (A) for forming a solder resist layer having different thicknesses on both surfaces of the circuit substrate having the insulating layer and the connection pads formed on the surface of the insulating layer; and the first solder resist layer having a thickness thinner than the second surface The solder resist layer of the surface, the process (B1) of the process of performing the post-process (B1) is exposed to a portion other than the thinned region (C1); the solder resist layer of the second surface is applied to the process of the post-process (D) developed region a process (C2) for exposing the other portion; a process for forming a thin film of the non-exposed portion of the non-exposed portion (B1) on the first surface in a range where the bonding pad is not exposed; The solder resist layer is subjected to a process (C4) of exposing a portion other than the thinned region in the process (B2) of the post-process; on the first side, the solder resist layer of the non-exposed portion is formed as a bonding pad by the thin film processing liquid. a process of thinning the thickness of the film to a portion of the bonding pad (B2); a process for exposing the solder resist layer of the first surface to a portion of the process (B2) to be thinned (C5); And a process (D) of removing the solder resist layer of the non-exposed portion of the second surface by the developer. 一種配線基板的製造方法,係具有於兩表面具有絕緣層、及形成於絕緣層表面之連結墊的電路基板,於電路基板之兩表面,具有防焊層,使連結墊之一部分從防焊層露出之配線基板的製造方法,其特徵為,含有:於兩表面具有絕緣層、及形成於絕緣層表面之連結墊 之電路基板的兩表面,形成厚度不同之第一防焊層的製程(A1);對厚度薄於第二面之第一防焊層的第一面之第一防焊層,實施於後製程之製程(B)被薄膜化區域以外部分之曝光的製程(C1);對第二面之第一防焊層,實施於後製程之製程(D1)被顯影區域以外部分之曝光的製程(C2);於第一面,以薄膜化處理液實施使非曝光部之第一防焊層成為連結墊之厚度以下為止的薄膜化,來使連結墊之一部分露出的製程(B);對第一面之第一防焊層,實施於製程(B)被薄膜化區域部分之曝光的製程(C3);於完成至(C3)製程為止之電路基板之第一面的第一防焊層上,形成第二防焊層之製程(A2);對第一面之第二防焊層,實施於後製程之製程(D1)被顯影區域以外部分之曝光的製程(C6);以及以顯影液除去第一面之非曝光部之第二防焊層及第二面之非曝光部之第一防焊層的製程(D1)。 A method of manufacturing a wiring board, comprising: a circuit board having an insulating layer on both surfaces and a bonding pad formed on a surface of the insulating layer; and having a solder resist layer on both surfaces of the circuit board, and a part of the bonding pad is removed from the solder resist layer A method of manufacturing an exposed wiring substrate, comprising: an insulating layer on both surfaces; and a bonding pad formed on a surface of the insulating layer a process for forming a first solder resist layer having a different thickness (A1) on both surfaces of the circuit board; and a first solder resist layer having a first surface of the first solder resist layer having a thickness thinner than the second surface, performing the post-process Process (B) is a process for exposing a portion other than the thinned region (C1); for the first solder resist layer of the second face, a process for performing a post-process (D1) exposure to a portion other than the developed region (C2) On the first surface, a thin film formation process is performed in which the first solder resist layer of the non-exposed portion is formed to have a thickness equal to or less than the thickness of the connection pad, and the process (B) of exposing one of the connection pads is performed; a first solder mask layer, a process (C3) for exposing the portion of the thinned region of the process (B); and a first solder resist layer on the first side of the circuit substrate until the process of (C3) is completed, a process for forming a second solder resist layer (A2); a second solder resist layer for the first surface, a process (C6) for performing a post-process (D1) exposure to a portion other than the developed region; and removing the developer The process (D1) of the first solder resist layer of the non-exposed portion of the first surface and the first solder resist layer of the non-exposed portion of the second surface. 一種配線基板的製造方法,係具有於兩表面具有絕緣層、及形成於絕緣層表面之連結墊的電路基板,於電路基板之兩表面,具有防焊層,使連結墊之一部分從防焊層露出之配線基板的製造方法,其特徵為,含有:於兩表面具有絕緣層、及形成於絕緣層表面之連結墊之電路基板的兩表面,形成厚度不同之第一防焊層的製程 (A1);對厚度薄於第二面之第一防焊層的第一面之第一防焊層,實施於後製程之製程(B)被薄膜化區域以外部分之曝光的製程(C1);對第二面之第一防焊層,實施於後製程之製程(D)被顯影之區域以外部分之曝光的製程(C2);於第一面,以薄膜化處理液實施使非曝光部之第一防焊層成為連結墊之厚度以下為止的薄膜化,來使連結墊之一部分露出的製程(B);對第一面之第一防焊層,實施於製程(B)被薄膜化區域部分之曝光的製程(C3);以顯影液除去第二面之非曝光部之第一防焊層的製程(D);於完成至(D)製程為止之電路基板之第一面的第一防焊層上,形成第二防焊層之製程(A2);對第一面之第二防焊層,實施於後製程之製程(D2)被顯影區域以外部分之曝光的製程(C6);以及以顯影液除去第一面之非曝光部之第二防焊層的製程(D2)。 A method of manufacturing a wiring board, comprising: a circuit board having an insulating layer on both surfaces and a bonding pad formed on a surface of the insulating layer; and having a solder resist layer on both surfaces of the circuit board, and a part of the bonding pad is removed from the solder resist layer A method of manufacturing an exposed wiring board, comprising: a process of forming a first solder resist layer having different thicknesses by providing an insulating layer on both surfaces and a circuit board formed on a connection pad on a surface of the insulating layer (A1); a first solder resist layer having a thickness thinner than a first surface of the first solder resist layer of the second surface, a process (C1) of performing a post-process process (B) exposure of a portion other than the thinned region The first solder resist layer on the second side is subjected to a process (C2) for exposing a portion of the process other than the developed region in the process of the post-process; on the first side, the non-exposed portion is implemented by using a thin film processing solution The first solder resist layer is formed into a film having a thickness equal to or less than the thickness of the bonding pad, and a part (b) of the bonding pad is exposed; and the first solder resist layer on the first surface is formed into a thin film in the process (B). a process for exposing a portion of the region (C3); a process for removing the first solder resist layer of the non-exposed portion of the second face by the developer (D); and a first face of the circuit substrate until the process of completing the process (D) a process for forming a second solder resist layer on a solder resist layer (A2); a process for exposing a portion of the second solder resist layer on the first side to a portion of the process (D2) outside the developed region (C6) And a process (D2) of removing the second solder resist layer of the non-exposed portion of the first surface by the developer. 一種配線基板的製造方法,係具有於兩表面具有絕緣層、及形成於絕緣層表面之連結墊的電路基板,於電路基板之兩表面,具有防焊層,使連結墊之一部分從防焊層露出之配線基板的製造方法,其特徵為,含有:於兩表面具有絕緣層、及形成於絕緣層表面之連結墊 之電路基板的兩表面,形成厚度不同之第一防焊層的製程(A1);對第二面之第一防焊層,實施於後製程之製程(D1)被顯影區域以外部分之曝光的製程(C2);於第一面,以薄膜化處理液實施使非曝光部之第一防焊層成為連結墊之厚度以下為止的薄膜化,來使連結墊之一部分露出的製程(B);對第一面之第一防焊層,實施於製程(B)被薄膜化區域部分之曝光的製程(C3);於完成至(C3)製程為止之電路基板之第一面的第一防焊層上,形成第二防焊層之製程(A2);對第一面之第二防焊層,實施於後製程之製程(B3)被薄膜化區域以外部分之曝光的製程(C6);於第一面,在連結墊未露出之範圍,以薄膜化處理液實施非曝光部之第二防焊層之薄膜化的製程(B3);對第一面之第二防焊層,實施於後製程之製程(D1)被顯影區域以外部分之曝光的製程(C7);以及以顯影液除去第一面之非曝光部之第二防焊層及第二面之非曝光部之第一防焊層的製程(D1)。 A method of manufacturing a wiring board, comprising: a circuit board having an insulating layer on both surfaces and a bonding pad formed on a surface of the insulating layer; and having a solder resist layer on both surfaces of the circuit board, and a part of the bonding pad is removed from the solder resist layer A method of manufacturing an exposed wiring substrate, comprising: an insulating layer on both surfaces; and a bonding pad formed on a surface of the insulating layer a process for forming a first solder resist layer having a different thickness on both surfaces of the circuit substrate (A1); and a first solder resist layer on the second surface, a process (D1) of the post-process is exposed by a portion other than the developed region Process (C2); in the first surface, the first solder resist layer of the non-exposed portion is formed into a film thickness equal to or less than the thickness of the connection pad, and a part of the connection pad is exposed (B); a first solder resist layer on the first side, a process (C3) for exposing the portion of the process (B) to the thinned region; and a first solder resist on the first side of the circuit substrate until the (C3) process is completed a process of forming a second solder resist layer on the layer (A2); a process for exposing the second solder resist layer on the first side to a portion of the post-process (B3) that is exposed outside the thinned region (C6); In the first surface, in the range where the bonding pad is not exposed, the thinning process of the second solder resist layer in the non-exposed portion is performed by the thin film processing liquid (B3); the second solder resist layer on the first surface is applied to the second surface Process (D1) of the process of exposure outside the developed area (C7); and removal of the first side by the developer The second portion of the solder resist layer and the second surface of the non-exposed portion of the process of the first solder resist layer (D1). 如申請專利範圍第1~4項之其中任一項所記載之配線基板的製造方法,其中在製程(C1)之前,實施製程(C2)。 The method of manufacturing a wiring board according to any one of claims 1 to 4, wherein the process (C2) is performed before the process (C1). 如申請專利範圍第1~4項之其中任一項所記載之配線基板的製造方法,其中 同時實施製程(C1)及製程(C2)。 The method of manufacturing a wiring board according to any one of the first to fourth aspects of the invention, wherein At the same time, the process (C1) and the process (C2) are implemented. 如申請專利範圍第1、3、4項之其中任一項所記載之配線基板的製造方法,其中以氧環境下之非接觸曝光方式來實施製程(C3)之曝光。 The method for producing a wiring board according to any one of claims 1, 3, and 4, wherein the exposure of the process (C3) is performed by a non-contact exposure method in an oxygen atmosphere. 如申請專利範圍第5項所記載之配線基板的製造方法,其中以氧環境下之非接觸曝光方式來實施製程(C3)及製程(C7)之曝光。 The method for producing a wiring board according to the fifth aspect of the invention, wherein the exposure of the process (C3) and the process (C7) is performed by a non-contact exposure method in an oxygen atmosphere. 如申請專利範圍第2項所記載之配線基板的製造方法,其中以氧環境下之非接觸曝光方式來實施製程(C4)及製程(C5)之曝光。 The method for producing a wiring board according to the second aspect of the invention, wherein the exposure of the process (C4) and the process (C5) is performed by a non-contact exposure method in an oxygen atmosphere. 如申請專利範圍第1、3、4項之其中任一項所記載之配線基板的製造方法,其中製程(C3)之曝光量為製程(C1)之曝光量之1倍以上、5倍以下。 The method for producing a wiring board according to any one of the first to third aspects, wherein the exposure amount of the process (C3) is one time or more and five times or less the exposure amount of the process (C1). 如申請專利範圍第5或9項所記載之配線基板的製造方法,其中製程(C3)及製程(C7)之曝光量為製程(C6)之曝光量之1倍以上、5倍以下。 The method of manufacturing a wiring board according to the fifth or ninth aspect of the invention, wherein the exposure amount of the process (C3) and the process (C7) is 1 time or more and 5 times or less of the exposure amount of the process (C6). 如申請專利範圍第2或10項所記載之配線基板的製造方法,其中製程(C4)及製程(C5)之曝光量為製程(C1)之 曝光量之1倍以上、5倍以下。 The method for manufacturing a wiring board according to claim 2, wherein the exposure amount of the process (C4) and the process (C5) is a process (C1). The exposure amount is 1 time or more and 5 times or less. 如申請專利範圍第1、3、4項之其中任一項所記載之配線基板的製造方法,其中製程(B)之防焊層的薄膜化處理係以薄膜化處理面朝上來實施。 The method for producing a wiring board according to any one of the items 1 to 3, wherein the film formation treatment of the solder resist layer of the process (B) is performed with the film processing surface facing upward. 如申請專利範圍第5或9項所記載之配線基板的製造方法,其中製程(B)及製程(B3)之防焊層的薄膜化處理係以薄膜化處理面朝上來實施。 The method for producing a wiring board according to the fifth or ninth aspect of the invention, wherein the thinning treatment of the solder resist layer of the process (B) and the process (B3) is performed with the film-formed surface facing upward. 如申請專利範圍第2或10項所記載之配線基板的製造方法,其中製程(B1)及製程(B2)之防焊層的薄膜化處理係以薄膜化處理面朝上來實施。 The method for producing a wiring board according to the second or tenth aspect of the invention, wherein the thinning treatment of the solder resist layer of the process (B1) and the process (B2) is performed with the film-formed surface facing upward. 如申請專利範圍第8項所記載之配線基板的製造方法,其中製程(C3)之曝光量為製程(C1)之曝光量之1倍以上、5倍以下。 The method for producing a wiring board according to the eighth aspect of the invention, wherein the exposure amount of the process (C3) is one time or more and five times or less the exposure amount of the process (C1). 如申請專利範圍第8項所記載之配線基板的製造方法,其中製程(B)之防焊層的薄膜化處理係以薄膜化處理面朝上來實施。 The method for producing a wiring board according to the eighth aspect of the invention, wherein the thinning treatment of the solder resist layer of the process (B) is performed with the thinned surface facing up. 如申請專利範圍第11項所記載之配線基板的製造方法,其中製程(B)之防焊層的薄膜化處理係以薄膜化處理面 朝上來實施。 The method for producing a wiring board according to the eleventh aspect of the invention, wherein the thinning treatment of the solder resist layer of the process (B) is a thinned surface Implement it upwards. 如申請專利範圍第12項所記載之配線基板的製造方法,其中製程(B)及製程(B3)之防焊層的薄膜化處理係以薄膜化處理面朝上來實施。 The method for producing a wiring board according to claim 12, wherein the thinning treatment of the solder resist layer of the process (B) and the process (B3) is performed with the film-formed surface facing upward. 如申請專利範圍第13項所記載之配線基板的製造方法,其中製程(B1)及製程(B2)之防焊層的薄膜化處理係以薄膜化處理面朝上來實施。 The method for producing a wiring board according to claim 13, wherein the thinning treatment of the solder resist layer of the process (B1) and the process (B2) is performed with the film-formed surface facing upward.
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