WO2014187063A1 - 芯片的绑定设备和方法 - Google Patents

芯片的绑定设备和方法 Download PDF

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Publication number
WO2014187063A1
WO2014187063A1 PCT/CN2013/085114 CN2013085114W WO2014187063A1 WO 2014187063 A1 WO2014187063 A1 WO 2014187063A1 CN 2013085114 W CN2013085114 W CN 2013085114W WO 2014187063 A1 WO2014187063 A1 WO 2014187063A1
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Prior art keywords
chip
substrate
curvature
arc
base
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PCT/CN2013/085114
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English (en)
French (fr)
Inventor
李�瑞
权宁万
宋勇
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Priority to US14/387,804 priority Critical patent/US20160254246A1/en
Publication of WO2014187063A1 publication Critical patent/WO2014187063A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07188—Apparatus chuck
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07332—Compression bonding, e.g. thermocompression bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H10W72/325—Die-attach connectors having a filler embedded in a matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • Embodiments of the present invention relate to a bonding apparatus and method for a chip. Background technique
  • the current small-size liquid crystal display products basically use the chip bonding process of COG (Chip On Glas s) to drive the liquid crystal display panel. Specifically, after forming a bump on the chip, the substrate is directly connected to the lead of the liquid crystal display.
  • COG Chip On Glas s
  • the high temperature indenter first contacts the chip, and the heat is conducted to the anisotropic conductive paste and the substrate through the chip.
  • the temperature difference between the substrate and the platform is large, which causes a difference in the expansion size between the two.
  • the anisotropic conductive paste is cured, the relative position between the chip and the substrate is fixed.
  • the main pressure is over, the chip and the substrate are cooled down, and the size of the chip shrinks is larger than that of the substrate, so that the two ends of the chip generate a large stress on the substrate, which causes warpage of the chip and the substrate.
  • the warpage of the chip and the substrate may cause chip peeling, chip breakage, and display effects such as uneven brightness.
  • Embodiments of the present invention provide a bonding apparatus and method for a chip, which can greatly improve the warpage problem of the chip and the substrate after binding.
  • a first aspect of the present invention provides a bonding apparatus for a chip, comprising: a base and a ram, wherein a side of the base for carrying the substrate has a first curvature that is recessed downward, and the ram is in contact with the chip a side having a second curvature that is downwardly convex, having the first curvature and having the first The indenter of the second arc matches.
  • the first radians and the second radians have equal radii of curvature.
  • the angle between the tangential direction of the edge of the first arc and the horizontal plane is 0.5° to 1.5.
  • the binding device is used for COG chip binding.
  • a second aspect of the present invention provides a chip bonding process method, including:
  • Anisotropic conductive paste is coated on the substrate, and the chip is placed on the anisotropic conductive paste and pre-fixed;
  • the chip is bonded to the substrate using a ram having a downwardly convex second curvature; wherein the pedestal having a first curvature matches the ram having a second curvature.
  • the first radians and the second radians have equal radii of curvature.
  • the angle between the tangential direction of the edge of the first arc and the horizontal plane is 0.5° to 1.5.
  • the anisotropic conductive paste is applied to two adjacent edge sides of the substrate.
  • binding the chip to the substrate includes:
  • the temperature of the indenter is from 150 ° C to 170 ° C.
  • the substrate is a glass substrate.
  • the binding method is a COG chip binding method.
  • FIG. 1 is a schematic structural diagram of a binding device of a chip according to an embodiment of the present invention
  • 2 is a schematic diagram of the use of a binding device for a chip in an embodiment of the present invention
  • FIG. 3 is a schematic diagram showing deformation of a chip and a substrate during a main pressing process according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of the test results in the embodiment of the present invention
  • FIG. 6 is a schematic flowchart diagram of a method for binding a chip according to an embodiment of the present invention.
  • the embodiment of the present invention provides a binding device for a chip.
  • the binding device of the chip includes a base 1 and a ram 2, and one side of the base 1 for carrying the substrate has a downward recess.
  • the first arc, the side of the indenter 2 in contact with the chip has a second curvature that is convex downward, and the base 1 having the first curvature matches the indenter 2 having the second curvature.
  • the base 1 has a first curvature that is recessed downward, the radius of curvature of the first curvature is ri
  • the indenter 2 has a second curvature that is convex downward, the second curvature
  • the radius of curvature is r 2 .
  • the base 1 and the indenter 2 are matched as shown in FIG. Since the substrate 3 and the chip 4 have a certain elasticity, especially the chip 4 has a certain ductility, when the base 1 and the indenter 2 perform a main pressing process, the substrate 3 and the chip 4 have a certain downward curved curvature. As shown in Figure 3. After the chip 4 and the substrate 3 are cooled In the process, since the size of the shrinkage of the chip 4 is larger than that of the substrate, the substrate 3 and the chip 4 which are originally bent downward are deformed toward the center of the arc during cooling, and the chip 4 and the substrate 3 become flat after the cooling is completed. , As shown in Figure 4.
  • the embodiment of the present invention greatly reduces the stress between the chip 4 and the substrate 3, prevents the chip 4 and the substrate 3 from being warped, and further prevents the chip 4 from being peeled off, the chip 4 from being broken, and the display effect from being uneven.
  • the anisotropic conductive paste 5 mainly comprises two parts of a resin adhesive and conductive particles.
  • the resin adhesive is mainly used to bind the chip 4 to the substrate 3, fix the relative positions of the electrodes between the chip 4 and the substrate 3, and provide a pressing force to maintain the electrode. Contact area with conductive particles.
  • the size and shape of one side of the base 1 for carrying the substrate 3 substantially corresponds to the size and shape of the substrate 3.
  • the size of one side of the base 1 for carrying the substrate 3 is substantially equal to or slightly larger than the size of the substrate 3.
  • the edge of the base 1 is substantially aligned with the edge of the substrate 3.
  • the radii of curvature of the first radii and the second radians should be equal, that is, for example, to prevent the chip 4 or the substrate 3 during the main pressing process.
  • An adverse effect such as a fracture occurs, and the angle between the tangential direction of the edge of the first curvature and the horizontal plane is generally 0.5 to 1.5.
  • the angle between the tangential direction of the edge of the first arc and the horizontal plane should be determined depending on the size of the substrate.
  • the table below shows the effect of the values of ruthenium on several common sized substrates on the substrate.
  • L3 L3 L2 L2 L1 L0 L1 L2 L3 rupture L0 ⁇ L3 in the above table indicates the severity of the problem caused by the substrate.
  • the L0 defect is the lightest, L0 to L3 are sequentially increased, and L3 is the heaviest.
  • each size of the substrate has a most suitable angle ⁇ .
  • the substrate 3 and the chip 4 of this size are bonded by the base 1 and the indenter 2 having the arc corresponding to the most suitable angle.
  • the flatness test was performed on the cooled substrate 3 and the chip 2, that is, the degree of warpage of the bonded chip 2 was tested.
  • the degree of warpage is measured by continuously testing the height of the surface to be measured in the bonded chip using a non-contact probe to obtain a continuous curve, and then taking the height difference between the highest point and the lowest point of the curve to indicate the degree of warpage.
  • the greater the height difference the greater the degree of warpage of the chip 2; conversely, the smaller the height difference, the smaller the degree of warpage of the chip 2.
  • the substrate 3 and the chip 2 are approximately horizontal, and the highest point and the lowest point are obtained.
  • the difference between the points is only 0.01 mm (see the dotted line in Fig. 5); the reverse side test (that is, the chip 2 is located below the substrate 3, and the non-contact probe is measured through the substrate from above) between the highest point and the lowest point.
  • the difference is 0.15mm (see solid line in Figure 5).
  • the bonding device of the chip provided by the embodiment of the invention greatly reduces the stress on the substrate 3 at both ends of the chip 4, and can effectively prevent the chip and the substrate from being bent.
  • the base of the chip-bonded device has a first curvature that is recessed downward
  • the indenter has a second curvature that is convex downward
  • the base has the first curvature
  • the base and the indenter have a certain downward curved curvature during the process of pressing the chip and the substrate to bond the chip to the substrate.
  • the chip and the substrate since the chip shrinks in size larger than the substrate, the downwardly bent substrate and the chip are deformed toward the center of the arc during cooling.
  • the chip and substrate become flat after cooling
  • the stress between the chip and the substrate is greatly reduced, and the chip and the substrate are prevented from warping, thereby preventing the occurrence of adverse effects such as chip glass, chip breakage, and display unevenness.
  • the embodiment of the present invention further provides a binding method of a chip of a binding device using the foregoing chip. Specifically, as shown in FIG. 6, the method includes:
  • Step S101 disposing a substrate on a base having a first curvature that is recessed downward;
  • step S102 coating an anisotropic conductive paste on the substrate, placing a chip on the anisotropic conductive paste, and performing Pre-fixed;
  • Step S103 Binding the chip to the substrate by using an indenter having a second curvature downwardly convex
  • the base having a first curvature matches the one having a second curvature.
  • the radii of curvature of the first radii and the second radians are equal.
  • the angle between the tangential direction of the edge of the first curvature and the horizontal plane is 0.5° to 1.5°.
  • the anisotropic conductive paste 5 is applied to the two adjacent edge sides of the substrate 3.
  • the anisotropic conductive paste 5 needs to have a temperature of 150 ° C to 170 ° C to melt the resin adhesive inside and bond it. Therefore, in step S103, the temperature of the indenter 2 is preferably 150 ° C to 170 ° C. In other embodiments of the invention, the temperature of the indenter 2 should be selected based on the applicable temperature of the anisotropic conductive paste 5.
  • the substrate 3 is a glass substrate.
  • the substrate 3 may also be a transparent material such as plastic.

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  • Wire Bonding (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Adhesives Or Adhesive Processes (AREA)

Abstract

一种芯片（4）的绑定设备和方法，芯片（4）的绑定设备包括：基台（1）和压头（2），基台（1）用于承载基板（3）的一面具有向下凹陷的第一弧度，压头（2）与芯片（4）接触的一面具有向下凸起的第二弧度，具有第一弧度的基台（1）和具有第二弧度的压头（2）匹配，能够改善芯片（4）和基板（3）在绑定后发生的翘曲问题。

Description

芯片的绑定设备和方法 技术领域
本发明的实施例涉及一种芯片的绑定设备和方法。 背景技术
为了更好的降低成本， 目前小尺寸液晶显示产品基本采用 COG ( Chip On Glas s )的芯片绑定工艺方法对液晶显示面板进行驱动。具体为在棵芯片上形 成凸点后， 在基板上直接与液晶显示屏的引线相连接。
在 COG 绑定工艺过程中， 进行主压时， 高温的压头先接触到芯片， 通 过芯片将热量传导到各向异性导电胶和基板。 此时， 基板与所在平台的温度 差异较大， 造成两者之间膨胀尺寸有差异。 各向异性导电胶固化后， 芯片与 基板之间的相对位置就固定下来。 主压结束后， 芯片和基板冷却下来， 芯片 收缩的尺寸比基板大， 使得芯片的两端产生较大的对基板的应力， 这样就导 致芯片和基板产生翘曲。而芯片和基板产生翘曲会导致芯片剥离、芯片断裂、 显示效果明暗不均等不良后果。
目前解决芯片和基板翘曲的问题主要采用低温各向异性导电胶产品， 但 是目前该产品价格昂贵， 而且技术不成熟。 发明内容
本发明的实施例提供了一种芯片的绑定设备和方法， 能够很大程度改善 芯片和基板在绑定后发生的翘曲问题。
本发明的第一方面提供了一种芯片的绑定设备， 包括基台和压头， 所述基台用于承载基板的一面具有向下凹陷的第一弧度， 所述压头与芯 片接触的一面具有向下凸起的第二弧度， 具有第一弧度的所述基台和具有第 二弧度的所述压头匹配。
例如， 所述第一弧度和所述第二弧度的曲率半径相等。
例如， 所述第一弧度的边缘的切线方向与水平面的夹角为 0.5° ~1.5。 。 例如， 该绑定设备用于 COG芯片绑定。
本发明的第二方面提供了一种芯片的绑定工艺方法， 包括：
将基板设置于具有向下凹陷的第一弧度的基台上；
在所述基板上涂覆各向异性导电胶， 将芯片放置于所述各向异性导电胶 上并进行预固定；
利用具有向下凸起的第二弧度的压头， 将所述芯片绑定在所述基板上； 其中， 具有第一弧度的所述基台和具有第二弧度的所述压头匹配。
例如， 所述第一弧度和所述第二弧度的曲率半径相等。
例如， 所述第一弧度的边缘的切线方向与水平面的夹角为 0.5° ~1.5。 。 例如， 所述各向异性导电胶涂覆于所述基板的两个相邻的边缘侧。
例如， 利用具有第二弧度的所述压头， 将所述芯片绑定在所述基板上包 括：
所述压头的温度为 150°C ~170°C。
例如， 所述基板为玻璃基板。
例如， 该绑定方法是 COG芯片绑定方法。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例描述中所 需要使用的附图作筒单地介绍。 显而易见地， 下面描述中的附图仅仅是本发 明的一些实施例， 而非对本发明的限制。
图 1为本发明实施例中的芯片的绑定设备的结构示意图； 图 2为本发明实施例中的芯片的绑定设备的使用示意图； 图 3为本发明实施例中的主压过程中芯片和基板的形变情况示意图； 图 4为本发明实施例中的冷却后的芯片和基板的形变情况示意图； 图 5为本发明实施例中的测试结果示意图；
图 6为本发明实施例中的芯片的绑定方法的流程示意图。
附图标记说明：
1—基台； 2—压头； 3—基板；
4一芯片； 5—各向异性导电胶。 具体实施方式
下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案进行 清楚、 完整地描述。 显然， 所描述的实施例是本发明一部分实施例， 而不是 全部的实施例。 基于所描述的本发明的实施例， 本领域普通技术人员在无需 创造性劳动前提下所获得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例提供了一种芯片的绑定设备， 如图 1所示， 该芯片的绑定 设备包括基台 1和压头 2, 所述基台 1用于承载基板的一面具有向下凹陷的第一弧度， 所述压头 2 与芯片接触的一面具有向下凸起的第二弧度， 具有第一弧度的所述基台 1和 具有第二弧度的所述压头 2匹配。 如图 1所示， 所述基台 1具有向下凹陷的第一弧度， 该第一弧度的曲率 半径为 ri, 所述压头 2具有向下凸起的第二弧度， 该第二弧度的曲率半径为 r2。 当利用该基台 1和压头 2进行芯片绑定工艺时， 该基台 1和所述压头 2 相配合， 如图 2所示。 由于基板 3和芯片 4具有一定的弹性， 尤其芯片 4具 有一定的延展性， 故而基台 1和压头 2在进行主压过程时， 该基板 3和芯片 4具有一定的向下弯曲的弧度， 如图 3所示。 在芯片 4和基板 3在冷却的过 程中， 由于芯片 4收缩的尺寸比基板大， 就使得原本向下弯曲的基板 3和芯 片 4在冷却过程中向着弧形的圓心方向发生形变， 冷却结束后芯片 4和基板 3变得较为平整， 如图 4所示。 本发明的实施例大大减小了芯片 4和基板 3 之间的应力， 防止芯片 4和基板 3产生翘曲， 进而防止芯片 4剥离、 芯片 4 断裂、 显示效果明暗不均等不良后果的产生。
如图 2-4所示， 位于芯片 4和基板 3之间的为一层各向异性导电胶 5。 各向异性导电胶 5主要包括树脂黏着剂、 导电粒子两大部分。 树脂黏着剂的 功能除了防湿气、 黏着、 耐热及绝缘功能外， 主要用于将芯片 4绑定在基板 3上， 固定芯片 4与基板 3间电极的相对位置， 并提供压迫力量以维持电极 与导电粒子间的接触面积。
在本发明的一些实施例中， 基台 1用于承载基板 3的一面的尺寸和形状 基本对应于基板 3的尺寸和形状。 例如， 基台 1用于承载基板 3的一面的尺 寸基本等于或略大于基板 3的尺寸。 例如， 如图 2所示， 在本发明实施例的 绑定过程中， 当基板 3设置于基台 1上时， 基台 1的边缘与基板 3的边缘基 本对准。
例如， 为了提高基台 1和压头 2之间的配合程度， 所述第一弧度和所述 第二弧度的曲率半径应相等， 即 例如， 为了防止在主压过程中， 芯片 4或基板 3发生断裂等不良后果， 所述第一弧度的边缘的切线方向与水平面 的夹角 Θ—般为 0.5° ~1.5。 。 例如， 第一弧度的边缘的切线方向与水平面的 夹角 Θ取值应视基板的尺寸而定。 下表示出了几种常见尺寸的基板的 Θ的取 值对基板的影响。
Θ
尺寸 0.25° 0.50° 0.75° 1.00° 1.25° 1.50° 1.75° 2.00° 2.25° 2.50°
4.3" L1 L0 L1 L2 破裂 - - - - -
6.0" L3 L2 L0 L1 L2 破裂 - - - -
10.1" L3 L2 L1 L0 L0 L1 L2 L3 破裂
14.0" L3 L3 L2 L2 L1 L0 L1 L2 L3 破裂 上表中的 L0~L3表示基板产生的不良现象的轻重程度， L0不良现 象最轻， L0至 L3依次加重， L3为最重。
由上表中可知， 每一尺寸的基板都有一个最为合适的夹角 Θ的取值。 一 般来说， 该尺寸的基板 3和芯片 4在具有最合适的夹角对应的弧度的基台 1 和压头 2的作用下进行绑定。 对冷却后的基板 3和芯片 2进行平坦度测试， 即测试绑定后的芯片 2的翘曲程度。 翘曲程度的测量方法是使用非接触式探 头连续测试绑定后的芯片中的被测表面的高度， 得到一条连续的曲线， 然后 取曲线最高点与最低点的高度差来表示翘曲程度。 一般的， 高度差越大， 表 示该芯片 2的翘曲程度越厉害； 反之， 高度差越小， 表示该芯片 2的翘曲程 度越小。
在本发明实施例中， 如图 5所示， 正面测试（即芯片 2位于基板 3的上 方， 非接触式探头从上方测量） 时基板 3和芯片 2近似处于水平状态， 此时 最高点和最低点之间的差值仅为 0.01mm (见图 5中虚线）； 反面测试（即芯 片 2位于基板 3的下方， 非接触式探头从上方透过基板测量） 时最高点和最 低点之间的差值为 0.15mm (见图 5中实线）。 对于本发明实施例所提供的基 板 3和芯片 2而言， 重力的影响较小。 由此可知本发明实施例所提供的芯片 的绑定设备大大减小了芯片 4两端对基板 3的应力， 能有效地防止芯片和基 板产生 曲。
在本实施例的技术方案中， 芯片绑定的设备的基台具有向下凹陷的第一 弧度， 压头具有向下凸起的第二弧度， 具有第一弧度的所述基台和具有第二 弧度的所述压头匹配。 该基台和压头在对芯片和基板进行主压以将芯片绑定 在基板上的过程中， 芯片与基板具有一定的向下弯曲的弧度。 芯片与基板在 冷却的过程中， 由于芯片收缩的尺寸比基板大， 向下弯曲的基板和芯片在冷 却过程中向着弧形的圓心方向发生形变。 冷却结束后芯片和基板变得较为平 整， 大大减小了芯片和基板之间的应力， 防止芯片和基板产生翘曲， 进而防 止芯片玻璃、 芯片断裂、 显示效果明暗不均等不良后果的产生。
进一步的， 本发明实施例还提供了一种利用上述的芯片的绑定设备的芯 片的绑定方法， 具体如图 6所示， 该方法包括：
步骤 S101 : 将基板设置于具有向下凹陷的第一弧度的基台上； 步骤 S102: 在所述基板上涂覆各向异性导电胶， 将芯片放置于所述各向 异性导电胶上并进行预固定；
步骤 S103: 利用具有向下凸起的第二弧度的压头， 将所述芯片绑定在所 述基板上；
具有第一弧度的所述基台和具有第二弧度的所述压头匹配。
例如， 为了提高基台 1和压头 2的配合程度， 所述第一弧度和所述第二 弧度的曲率半径相等。
例如， 为了防止基板 3在主压的过程中破损， 所述第一弧度的边缘的切 线方向与水平面的夹角为 0.5° ~1.5° 。
例如， 由于芯片 4通常设置在基板的两个相邻的边缘侧， 所述各向异性 导电胶 5涂覆于所述基板 3的两个相邻的边缘侧。
通常， 各向异性导电胶 5需要得到 150°C~170°C的温度， 才能进行熔化 其内部的树脂黏着剂， 进行绑定处理。 所以步骤 S103中， 所述压头 2的温 度优选为 150°C~170°C。 在本发明的其它实施例中， 压头 2的温度应根据各 向异性导电胶 5的适用温度来选择。
例如， 所述基板 3玻璃基板。 在本发明的其它实施例中， 所述基板 3还 可为塑料等透明材质。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局限 于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易 想到变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保护 范围应以所述权利要求的保护范围为准。

Claims

权利要求书
1、 一种芯片的绑定设备， 包括基台和压头， 其中，
所述基台用于承载基板的一面具有向下凹陷的第一弧度， 所述压头与芯 片接触的一面具有向下凸起的第二弧度， 具有第一弧度的所述基台和具有第 二弧度的所述压头匹配。
2、 根据权利要求 1所述的芯片的绑定设备， 其中，
所述第一弧度和所述第二弧度的曲率半径相等。
3、 根据权利要求 1所述的芯片的绑定设备， 其中，
所述第一弧度的边缘的切线方向与水平面的夹角为 0.5° ~1.5。 。
4、 根据权利要求 1所述的芯片的绑定设备， 其中，
所述绑定设备用于 COG芯片绑定。
5、 一种芯片的绑定方法， 包括：
将基板设置于具有向下凹陷的第一弧度的基台上；
在所述基板上涂覆各向异性导电胶， 将芯片放置于所述各向异性导电胶 上并进行预固定；
利用具有向下凸起的第二弧度的压头， 将所述芯片绑定在所述基板上； 其中， 具有第一弧度的所述基台和具有第二弧度的所述压头匹配。
6、 ^据权利要求 5所述的芯片的绑定方法， 其中，
所述第一弧度和所述第二弧度的曲率半径相等。
7、 ^据权利要求 5所述的芯片的绑定方法， 其中，
所述第一弧度的边缘的切线方向与水平面的夹角为 0.5° -1.5° 。
8、 ^据权利要求 5所述的芯片的绑定方法， 其中，
所述各向异性导电胶涂覆于所述基板的两个相邻的边缘侧。
9、 ^^据权利要求 5 所述的芯片的绑定方法， 其中， 所述利用具有向下 凸起的第二弧度的压头， 将所述芯片绑定在所述基板上包括：
所述压头的温度为 150°C ~170°C。
10、 根据权利要求 5所述的芯片的绑定方法， 其中，
所述基板为玻璃基板。
11、 ^据权利要求 5所述的芯片的绑定方法， 其中，
所述绑定方法是 COG芯片绑定方法。
PCT/CN2013/085114 2013-05-21 2013-10-12 芯片的绑定设备和方法 Ceased WO2014187063A1 (zh)

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