WO2014169721A1 - 一种发光二极管封装基板与封装结构及其制作方法 - Google Patents

一种发光二极管封装基板与封装结构及其制作方法 Download PDF

Info

Publication number
WO2014169721A1
WO2014169721A1 PCT/CN2014/071051 CN2014071051W WO2014169721A1 WO 2014169721 A1 WO2014169721 A1 WO 2014169721A1 CN 2014071051 W CN2014071051 W CN 2014071051W WO 2014169721 A1 WO2014169721 A1 WO 2014169721A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
emitting diode
substrate
groove structure
light emitting
Prior art date
Application number
PCT/CN2014/071051
Other languages
English (en)
French (fr)
Inventor
夏德玲
Original Assignee
厦门市三安光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 厦门市三安光电科技有限公司 filed Critical 厦门市三安光电科技有限公司
Publication of WO2014169721A1 publication Critical patent/WO2014169721A1/zh
Priority to US14/748,393 priority Critical patent/US20150295148A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/54—Encapsulations having a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/56—Materials, e.g. epoxy or silicone resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/005—Processes relating to semiconductor body packages relating to encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Definitions

  • the invention belongs to the field of packaging of light-emitting diodes, and in particular relates to a package substrate and a package structure and a manufacturing method thereof.
  • flip-chip flip-chip, FC for short
  • FC flip-chip packaging technology
  • the application of flip-chip packaging technology to LEDs It is one of the important topics.
  • the application of flip-chip package in LEDs is mainly divided into two kinds of packaging methods: the first one is the gold bump bonding process (English is Au-stub bumping process), which firstly implants gold bumps onto the package substrate.
  • the relative position of the gold bumps on the board is the same as that of the electrodes on the chip, and then the electrodes on the chip are bonded to the gold bumps on the package substrate by ultrasonic pressing, and the method requires the package substrate.
  • the degree is low, the process flexibility is large, but the cost of the gold bump is high, and the chip alignment requires high precision, so the machine is expensive, the production speed is slow, and the whole production cost is too high;
  • the second is the eutectic bonding process (Eutectic bonding process in English), the selected eutectic metal is formed on the chip by evaporation or sputtering, and the chip is pre-bonded to the package substrate by a low temperature flux, at a melting point higher than the eutectic metal. Reflowing enables the chip to form a joint with the package substrate, the metal cost is low, the production speed is fast, and the accuracy of the machine is low, but the process requires high flatness of the package substrate and precision of the process.
  • the growth substrate of the LED is further removed, which is a method for effectively increasing the luminous efficiency of the flip-chip LED, but the gap between the chip and the package substrate is covered by the flip-chip package. , seriously affecting the yield of growth substrate removal.
  • the invention provides a package substrate and a package structure and a fabrication method thereof for a flip-chip light-emitting diode suitable for a eutectic bonding process, and solves the problem that the original eutectic process flip-chip light-emitting diode cannot be underfilled due to the distance between the chip and the substrate being too small material(
  • the under-fill process causes problems such as subsequent substrate removal and surface roughening processes.
  • the present invention provides a package substrate for a flip-chip light-emitting diode suitable for a eutectic bonding process, comprising: a substrate body having a first surface on which at least one unit is distributed, each unit corresponding to one LED core And having a first region and a second region electrically isolated from each other; a groove structure between the two regions, the top opening width being smaller than the width of the core particles to be packaged.
  • the groove structure has at least one side opening located on a sidewall of the substrate body.
  • the cross-sectional shape of the groove structure is rectangular or inverted trapezoidal or inverted triangle or curved.
  • the groove structure has a height difference between 50 microns and 300 microns.
  • the groove structure has a top opening width between 100 microns and 1000 microns.
  • the package substrate when the groove structure is rectangular or inverted trapezoid, is defined to have a first surface, a second surface and a third surface, wherein the second surface is located at a first surface at a relative height And the second surface is located between the two first surfaces, and the third surface is connected to the first surface and the second surface. It is easy to understand that the two second surfaces and the third surface constitute a groove structure.
  • the second surface intersects the third surface at an angle of 45 degrees to 90 degrees. Between degrees.
  • the substrate body may be a material such as Si, AlN, Al 2 O 3 , epoxy resin molding compound (English Epoxy Molding Compound, abbreviated as EMC).
  • EMC epoxy resin molding compound
  • the present invention also provides a package structure for a flip-chip light-emitting diode suitable for a eutectic bonding process, comprising: a substrate body having a first surface on which at least one unit is distributed, each unit corresponding to one LED core a particle having a first region and a second region electrically isolated from each other; a groove structure between the two regions, a top opening width of which is smaller than a width of the core particle to be packaged, and the groove structure has at least one The side opening is located at a sidewall of the substrate body; the first conductive layer is located above the first region; the second conductive layer is located above the second region; and the LED chip has the first electrode and the second electrode, and the two electrodes There is a gap between the first conductive layer and the first electrode, the second conductive layer and the second electrode are two-positioned and solid-crystal bonded; the glue material is filled into the gap between the first electrode and the second electrode and concave Slot structure.
  • the present invention further provides a method for fabricating a package structure of a flip-chip type light emitting diode, comprising: providing a substrate body having a first surface on which at least one unit is distributed, each unit corresponding to one light emitting diode core particle having a first region and a second region electrically isolated from each other; an opening is formed on the first surface of the substrate body, a groove structure is formed between the two regions, and a width of the top opening is smaller than a width of the core particle to be packaged, the groove
  • the structure has at least one side opening on a sidewall of the substrate body to form a package substrate; a first conductive layer is formed on the first region; a second conductive layer is formed on the second region; and a light emitting diode is provided, having the first electrode And a second electrode, a gap exists between the two electrodes; the first conductive layer is aligned with the first electrode, the second conductive layer and the second electrode, and the flip-chip packaging process is used to make the LED solid crystal connection
  • the top opening is formed on the first surface of the package substrate body, and may be passed through a diamond knife or a yellow light mask, dry / Made by wet etching.
  • the light-emitting diodes that are flip-chip packaged onto the package substrate may be further removed by laser lift-off.
  • the surface exposed after the growth of the substrate is removed, and the surface roughening treatment can be further performed.
  • the package substrate of the present invention can be applied to a flip-chip light-emitting diode, and the height difference between the first surface and the second surface can effectively avoid component failure caused by contact failure during chip solidification.
  • the gap between the first electrode and the second electrode and the groove structure can be filled by the glue material, which can avoid damage to the chip caused by subsequent laser stripping of the growth substrate, and finally, by roughening the surface of the epitaxial layer, increasing Light-emitting efficiency of LEDs.
  • 1A is a cross-sectional view showing a package substrate of a first embodiment of the present invention.
  • Figure 1B is a top plan view of the package substrate of Figure 1A.
  • Figure 2A is a cross-sectional view showing a package substrate of a second embodiment of the present invention.
  • FIG. 2B is a top plan view of the package substrate of FIG. 2A.
  • FIG. 3 to FIG. 6 are partial cross-sectional views showing a method of fabricating a flip chip type light emitting diode according to an embodiment of the present invention.
  • W1 width of two first surfaces adjacent to the second surface
  • the present invention provides a package substrate and related manufacturing method for the flip-chip light-emitting diode suitable for the eutectic bonding process, and simultaneously solves the subsequent growth.
  • the substrate may be damaged during the substrate removal process.
  • FIG. 1A is a cross-sectional view showing a package substrate according to a first embodiment of the present invention
  • FIG. 1B is a view of FIG. A top view of the package substrate.
  • the package substrate 100 includes: a substrate body 101 having a first surface 102 There are at least one unit distributed thereon, each unit corresponding to one LED core particle having a first region and a second region electrically isolated from each other.
  • the cross-sectional shape of the groove structure is a rectangle between two regions, and the top opening width W1 is smaller than the width of the core particles to be packaged.
  • both sides of the groove structure are located on the side walls of the substrate body.
  • the cross-sectional shape of the groove structure is a rectangle.
  • the first conductive layer 105A is located above the first region, and the second conductive layer 105B , located above the second area.
  • the substrate body includes a second surface 103 at a relative height below the first surface and a second surface between the two first surfaces; the third surface 104 Connected to the first surface and the second surface, respectively, wherein the first surface 102, the second surface 103, and the third surface 104 form a recess 106.
  • the first surface 102 and the second surface 103 are not coplanar, and the height difference d is between 50 micrometers and 300 degrees. Between the micrometers, but not limited to this, the height difference can effectively solve the problem of the eutectic failure caused by the poor flatness of the substrate in the conventional eutectic process.
  • the top opening width W1 of the groove 106 is between 100 micrometers and Between 1000 microns.
  • the bottom opening width W2 of the groove 106 is equal to the top opening width W1 of the groove 106.
  • the second surface intersects the third surface at an angle ⁇ of 90 Degree, but not limited to this.
  • the substrate body 101 may be an AlN substrate, but is not limited thereto.
  • FIG. 2A is a cross-sectional view of a package substrate according to a second embodiment of the present invention
  • FIG. 2B is a diagram of FIG. 2A A top view of the package substrate.
  • the package substrate 100' includes: a substrate body 101 having a first surface 102 There are at least one unit distributed thereon, each unit corresponding to one LED core particle having a first region and a second region electrically isolated from each other.
  • the cross-sectional shape of the groove structure is a rectangle between two regions, and the top opening width W1 is smaller than the width of the core particles to be packaged.
  • one side opening of the groove structure is located on the side wall of the substrate body.
  • the cross-sectional shape of the groove structure is an inverted trapezoid.
  • the first conductive layer 105A is located above the first region, and the second conductive layer 105B , located above the second area.
  • the substrate body includes a second surface 103 at a relative height below the first surface and a second surface between the two first surfaces; the third surface 104 Connected to the first surface and the second surface, respectively, wherein the first surface 102, the second surface 103, and the third surface 104 form a recess 106.
  • the first surface 102 and the second surface 103 are not coplanar, and the height difference d is between 50 micrometers and Between 300 microns, but not limited to this.
  • the top opening width W1 of the groove 106 is between 100 micrometers and 1000 micrometers.
  • the bottom opening width of the groove 106 is W2 It is smaller than the top opening width W1 of the groove 106.
  • the angle ⁇ at which the second surface intersects the third surface is between 45 degrees and 90 degrees, but is not limited thereto.
  • FIG. 3 to FIG. 6 are partial cross-sectional views of a method for fabricating a flip-chip LED package structure according to an embodiment of the present invention.
  • a sapphire (Al 2 O 3 ) substrate body 100 ′ is provided having a first surface 102 , a second surface 103 , and a third surface 104 , the third surface being connected to the first surface and the second surface; Forming an opening on the first surface of the substrate body by the diamond knife, so that the second surface and the third surface form a groove structure; forming a first conductive layer on the first surface; respectively in the first region and the second region The first conductive layer 105A and the second conductive layer 105B are formed on top.
  • An LED chip 201 is provided, including: a growth substrate 202, an epitaxial layer 203, and a first electrode 205A and a second electrode 205B. A gap exists between the two electrodes; and the first conductive layer 105A and the first electrode 205A are second. The conductive layer 105B is aligned with the second electrode 205B in a flip-chip packaging process such that the light emitting diode is crystallized on the package substrate 100 ′.
  • the glue 107 is filled into the gap between the first electrode and the second electrode and the groove structure, and the rubber material is selected from silica gel.
  • the growth substrate 202 of the LED chip 201 is removed by a laser lift-off process to expose the surface of the epitaxial layer 203 of the LED chip 201.
  • the filling type of 107 can effectively prevent the damage of the epitaxial layer 203 caused by the change of the stress of the LED chip 201 when the laser strip is grown.
  • the growth substrate is removed.
  • the light-emitting surface of the exposed epitaxial layer 203 is processed by a chemical etching process to form a roughened surface 204, which further increases the efficiency of the light-emitting diode.
  • the application of the LED package substrate and the package structure of the present invention can solve the problem of the eutectic failure caused by the poor flatness of the substrate in the conventional flip chip process, and further can be solved by the package substrate.
  • the luminous efficiency of the diode is luminous efficiency of the diode.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Abstract

一种发光二极管的封装基板，其至少包含：基板本体（101），具有第一表面，其上分布有至少一个单元，所述每个单元对应一个发光二极管芯粒，其具有彼此相互电隔离的第一区域和第二区域；凹槽结构（106），介于两个区域之间，其顶部开口宽度小于所述待封装芯粒的宽度。其可解决发光二极管因芯片与基板间距离过小而无法进行底层填充胶材而导致后续基板移除及表面粗化无法进行的问题。

Description

一种发光二极管封装基板与封装结构及其制作方法
本申请主张如下优先权：中国发明专利申请号201310137420.X，题为 ' 一种发光二极管封装基板与封装结构及其制作方法 ' ，于 2013 年 4 月 19 日提交。上述申请的全部内容通过引用结合在本申请中。
技术领域
本发明属发光二极管之封装领域，具体涉及一种封装基板与封装结构及其制作方法。
背景技术
覆晶式（英文为 Flip-chip ，简称 FC ）封装于发光二极管的应用随着其优越的散热特性及较佳的组件机械强度逐渐被证实与量产，覆晶式封装技术于发光二极管的应用即为重要课题之一。覆晶式封装应用于发光二极管的应用主要分为两种封装方式：第一种为金凸块键合制程（英文为 Au-stub bumping process ），系先将金凸块种至封装基板上，其金凸块于板材上的相对位置与芯片上的电极相同，而后藉由超音波压合，使芯片上的电极与封装基板上的金凸块接合完成电性连接，此法对封装基板要求度低，制程弹性大，但其金凸块成本高，且芯片对位需要较高之精准度，因此机台昂贵，生产速度慢，导致整个生产成本过高；第二种为共晶接合制程（英文为 Eutectic bonding process ），以蒸镀或溅镀将选定之共晶金属制作于芯片上，藉由低温助焊剂将芯片预贴合至封装基板上，在高于共晶金属之熔点下回焊，使芯片与封装基板形成接合，金属成本低，生产速度快，对机台精度要求低，但是该制程对封装基板平整度以及其制程精度要求高。此外，为了增加发光二极管之发光效率，进一步将发光二极管之生长基板移除，此为一有效增加覆晶式发光二极管发光效率的方法，但覆晶式封装于芯片与封装基板间留下的空隙，严重影响生长基板移除的良率。
发明内容
本发明提供适用于共晶接合制程之覆晶式发光二极管之封装基板与封装结构及其制作方，解决原本共晶制程覆晶型发光二极管因芯片与基板间距离过小而无法进行底层填充胶材（ under-fill ）制程而导致后续基板移除及表面粗化制程无法进行的问题。
本发明提供一种适用于共晶接合制程之覆晶式发光二极管之封装基板，包含：基板本体，具有第一表面，其上分布有至少一个单元，所述每个单元对应一个发光二极管芯粒，其具有彼此相互电隔离的第一区域和第二区域；凹槽结构，介于两个区域之间，其顶部开口宽度小于所述待封装芯粒的宽度。
在本发明的一些实施例中，所述凹槽结构至少具有一侧开口位于基板本体的侧壁。
在本发明的一些实施例中，所述凹槽结构的截面形状为矩形或者倒梯形或者倒三角形或者弧形。
在本发明的一些实施例中，所述凹槽结构的高度差介于 50 微米至 300 微米之间。
在本发明的一些实施例中，所述凹槽结构的顶部开口宽度介于 100 微米至 1000 微米之间。
在本发明的一些实施例中，所述凹槽结构为矩形或倒梯形时，定义封装基板具有第一表面，第二表面以及第三表面，其中第二表面在相对高度上位于第一表面之下且第二表面位于两个第一表面间，第三表面与第一表面及第二表面相连，则容易理解，两个第二表面与第三表面构成凹槽结构。
在本发明的一些实施例中，所述凹槽结构为矩形或倒梯形时，第二表面与第三表面相交角度介于 45 度至 90 度之间。
在本发明的一些实施例中，所述基板本体可为 Si ， AlN ， Al2O3 ，环氧树脂模塑料（英文为 Epoxy Molding Compound ，缩写为 EMC ）等材料。
本发明还提供一种适用于共晶接合制程之覆晶式发光二极管之封装结构，包括：基板本体，具有第一表面，其上分布有至少一个单元，所述每个单元对应一个发光二极管芯粒，其具有彼此相互电隔离的第一区域和第二区域；凹槽结构，介于两个区域之间，其顶部开口宽度小于所述待封装芯粒的宽度，且凹槽结构至少具有一侧开口位于基板本体的侧壁；第一导电层，位于第一区域之上；第二导电层，位于第二区域之上；发光二极管芯片，具有第一电极和第二电极，两个电极之间存有间隙；第一导电层与第一电极，第二导电层与第二电极两两对位并固晶连接；胶材，填入至第一电极与第二电极之间的间隙及凹槽结构。
本发明再提供一种覆晶式发光二极管之封装结构制作方法，包含：提供基板本体，具有第一表面，其上分布有至少一个单元，所述每个单元对应一个发光二极管芯粒，其具有彼此相互电隔离的第一区域和第二区域；在基板本体第一表面上形成开口，在两个区域之间形成凹槽结构，且顶部开口宽度小于所述待封装芯粒的宽度，凹槽结构至少具有一侧开口位于基板本体的侧壁，制得封装基板；在第一区域之上制作第一导电层；在第二区域之上制作第二导电层；提供发光二极管，具有第一电极和第二电极，两个电极之间存有间隙；将第一导电层与第一电极，第二导电层与第二电极两两对位，采用覆晶封装制程使得发光二极管固晶连接于所述封装基板上；将胶材填入至第一电极与第二电极之间的间隙及凹槽结构，如此构成发光二极管封装结构。
在本发明的一些实施例中，于封装基板本体第一表面上形成顶部开口的方式，可以通过钻石刀或者经黄光光罩、干 / 湿法蚀刻制作而成。
在本发明的一些实施例中，经覆晶封装至封装基板上之发光二极管，可进一步利用激光剥离移除其生长基板。
在本发明的一些实施例中，移除生长基板后裸露之表面，可进一步做表面粗化处理。
本发明的封装基板可应用于覆晶式发光二极管，藉由第一表面及第二表面的高度差，可有效避免芯片固晶时产生接触不良造成组件失效。同时，可利用胶材填入至第一电极与第二电极之间的间隙及凹槽结构，可避免后续激光剥离生长基板时对芯片造成的损伤，最后藉由外延层表面粗化处理，增加发光二极管之出光效率。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例一起用于解释本发明，并不构成对本发明的限制。此外，附图数据是描述概要，不是按比例绘制。
图 1A 系本发明第一实施例之封装基板的剖面图。
图 1B 系图 1A 之封装基板的俯视图。
图 2A 系本发明第二实施例之封装基板的剖面图。
图 2B 系图 2A 之封装基板的俯视图。
图 3~ 图 6 系根据本发明实施的一种覆晶式发光二极管制造方法之部分步骤剖面图。
图中各标号表示：
100 ：封装基板
100 '：封装基板
101 ：基板本体
102 ：第一表面
103 ：第二表面
104 ：第三表面
105A ：第一导电层
105B ：第二导电层
106 ：凹槽
107 ：胶材
201 ：发光二极管
202 ：生长基板
203 ：磊晶层
204 ：粗糙化表面
205A ：第一电极
205B ：第二电极
W1 ：与第二表面相邻的两个第一表面的宽度
W2 ：第二表面的宽度
d ：第一表面与第二表面之高度差
θ：第二表面与第三表面相交角度
具体实施方式
为了能彻底地了解本发明，将在下列的描述中提出详尽的步骤及其组成，另外，众所周知的组成或步骤并未描述于细节中，以避免造成本发明不必要之限制。本发明的较佳实施例会详细描述如下，然而除了这些详细描述之外，本发明还可以广泛地施行在其它的实施例中，且本发明的范围不受限定，以专利权利要求范围为准。
为解决习知之封装基板于覆晶式发光二极管在共晶制程所面临到的缺点，本发明提出一适用于共晶接合制程之覆晶式发光二极管之封装基板及相关制造方法，同时解决后续生长基板移除制程中可能对芯片造成的损伤，下面实施例将配合图示说明本发明之封装基板及其应用方法。
请参考图 1A~ 图 1B 。图 1A 系本发明第一实施例之封装基板的剖面图，图 1B 系图 1A 之封装基板的俯视图。封装基板 100 ，包括：基板本体 101 ，具有第一表面 102 ，其上分布有至少一个单元，所述每个单元对应一个发光二极管芯粒，其具有彼此相互电隔离的第一区域和第二区域。如图 1A 所示，凹槽结构的截面形状为矩形，介于两个区域之间，其顶部开口宽度 W1 小于所述待封装芯粒的宽度。如图 1B 所示，凹槽结构的两侧位于基板本体的侧壁。
在本实施例中，凹槽结构的截面形状为矩形。第一导电层 105A 位于第一区域之上，第二导电层 105B ，位于第二区域之上。基板本体上包含第二表面 103 ，其相对高度上位于第一表面之下且第二表面位于两个第一表面间；第三表面 104 分别与第一表面及第二表面间相连，其中，第一表面 102 ，第二表面 103 ，以及第三表面 104 形成凹槽 106 。
在本实施例中，第一表面 102 与第二表面 103 非共平面，其高度差 d 介于 50 微米至 300 微米之间，但不以此为限，此高度差可以有效解决习知之共晶制程因基板平整度不佳所造成共晶失效的问题。其中，凹槽 106 的顶部开口宽度 W1 介于 100 微米至 1000 微米之间。凹槽 106 的底部开口宽度 W2 等于凹槽 106 的顶部开口宽度 W1 。第二表面与第三表面相交角度θ为 90 度，但不以此为限。此外，基材本体 101 可为 AlN 基材，但亦不以此为限。
请参考图 2A~ 图 2B 。图 2A 系本发明第二实施例之封装基板的剖面图，图 2B 系图 2A 之封装基板的俯视图。封装基板 100 '，包括：基板本体 101 ，具有第一表面 102 ，其上分布有至少一个单元，所述每个单元对应一个发光二极管芯粒，其具有彼此相互电隔离的第一区域和第二区域。如图 2A 所示，凹槽结构的截面形状为矩形，介于两个区域之间，其顶部开口宽度 W1 小于所述待封装芯粒的宽度。如图 2B 所示，凹槽结构的一侧开口位于基板本体的侧壁。
在本实施例中，凹槽结构的截面形状为倒梯形。第一导电层 105A ，位于第一区域之上，第二导电层 105B ，位于第二区域之上。基板本体上包含第二表面 103 ，其相对高度上位于第一表面之下且第二表面位于两个第一表面间；第三表面 104 分别与第一表面及第二表面间相连，其中，第一表面 102 ，第二表面 103 ，以及第三表面 104 形成凹槽 106 。
在本实施例中，在本实施例中，第一表面 102 与第二表面 103 非共平面，其高度差 d 介于 50 微米至 300 微米之间，但不以此为限。其中，凹槽 106 的顶部开口宽度 W1 介于 100 微米至 1000 微米之间。凹槽 106 的底部开口宽度 W2 小于凹槽 106 的顶部开口宽度 W1 。第二表面与第三表面相交角度θ介于 45 度至 90 度之间，但不以此为限。
请参考图 3~ 图 6 ，系根据本发明实施的一种覆晶式发光二极管封装结构制造方法之部分步骤剖面图。在图 3 中，提供蓝宝石（ Al2O3 ）基板本体 100 '，具有第一表面 102 ，第二表面 103 以及第三表面 104 ，所述第三表面与第一表面及第二表面相连；于基板本体第一表面上通过钻石刀形成一个开口，使得第二表面与第三表面构成凹槽结构；制作第一导电层，位于所述第一表面之上；分别在第一区域、第二区域之上制作第一导电层 105A 、第二导电层 105B 。提供发光二极管芯片 201 ，包括：生长基板 202 、磊晶层 203 以及第一电极 205A 和第二电极 205B ，两个电极之间存有间隙；将第一导电层 105A 与第一电极 205A ，第二导电层 105B 与第二电极 205B 两两对位，以覆晶封装制程使得发光二极管固晶于所述封装基板 100 '上。
在图 4 中，将胶材 107 填充至第一电极与第二电极之间的间隙及凹槽结构，胶材选用硅胶。在图 5 中，使用激光剥离制程去除发光二极管芯片 201 之生长基板 202 ，使发光二极管芯片 201 的磊晶层 203 表面裸露。藉由凹槽 106 的形成以及胶材 107 的填充固型，可有效避免发光二极管芯片 201 于激光剥离生长基板 202 时因应力的改变对磊晶层 203 所造成的损伤。在图 6 中，去除生长基板 202 后，利用化学蚀刻制程处理裸露的磊晶层 203 之出光面，使其形成粗糙化表面 204 ，如此可进一步增加发光二极管之效率。
由上述本发明实施方式可知，应用本发明的发光二极管封装基板与封装结构，可解决习知覆晶制程因基板平整度不佳所造成之共晶失效的问题，进一步可藉由封装基板凹槽结构，在发光二极管覆晶固晶至封装基板后，利用胶材填入此凹槽，可解决后续激光剥离生长基板制程可能对芯片造成的损伤，最后藉由表面粗化制程的处理进而增加发光二极管之发光效率。

Claims (11)

  1. 一种发光二极管封装基板，包含：
    基板本体，具有第一表面，其上分布有至少一个单元，所述每个单元对应一个发光二极管芯粒，其具有彼此相互电隔离的第一区域和第二区域；
    凹槽结构，介于两个区域之间，其顶部开口宽度小于所述待封装芯粒的宽度。
  2. 根据权利要求 1 所述的一种发光二极管封装基板，其特征在于：所述凹槽结构至少具有一侧开口位于基板本体的侧壁。
  3. 根据权利要求 1 所述的一种发光二极管封装基板，其特征在于：所述凹槽结构的截面形状为矩形或者倒梯形或者倒三角形或者弧形。
  4. 根据权利要求 1 所述的一种发光二极管封装基板，其特征在于：所述凹槽结构的高度差介于 50 微米至 300 微米之间。
  5. 根据权利要求 1 所述的一种发光二极管封装基板，其特征在于：所述凹槽结构的顶部开口宽度介于 100 微米至 1000 微米之间。
  6. 一种发光二极管封装结构，包含：
    基板本体，具有第一表面，其上分布有至少一个单元，所述每个单元对应一个发光二极管芯粒，其具有彼此相互电隔离的第一区域和第二区域；
    凹槽结构，介于两个区域之间，其顶部开口宽度小于所述待封装芯粒的宽度，且凹槽结构至少具有一侧位于基板本体的侧壁；
    第一导电层，位于第一区域之上；
    第二导电层，位于第二区域之上；
    发光二极管芯片，具有第一电极和第二电极，两个电极之间存有间隙；
    将第一导电层与第一电极，第二导电层与第二电极两两对位并固晶连接；
    胶材，填入至第一电极与第二电极之间的间隙及凹槽结构。
  7. 一种发光二极管封装结构的制作方法，包含：
    提供基板本体，具有第一表面，其上分布有至少一个单元，所述每个单元对应一个发光二极管芯粒，其具有彼此相互电隔离的第一区域和第二区域；
    在基板本体第一表面上形成开口，在两个区域之间形成凹槽结构，且顶部开口宽度小于所述待封装芯粒的宽度，凹槽结构至少具有一侧位于基板本体的侧壁，制得封装基板；
    在第一区域之上制作第一导电层；
    在第二区域之上制作第二导电层；
    提供发光二极管，具有生长基板、磊晶层、第一电极和第二电极，两个电极之间存有间隙；
    将第一导电层与第一电极，第二导电层与第二电极两两对位，以覆晶封装制程使得发光二极管固晶于所述封装基板上；
    将胶材填入至第一电极与第二电极之间的间隙及凹槽结构，如此构成发光二极管封装结构。
  8. 根据权利要求 7 所述的一种发光二极管封装结构的制作方法，其特征在于：所述胶材为环氧树脂或硅胶或前述组合。
  9. 根据权利要求 7 所述的一种发光二极管封装结构的制作方法，其特征在于：其特征在于：利用胶材填充至第一电极与第二电极之间的间隙及凹槽结构后，还包含采用剥离制程，去除发光二极管芯片的生长基板，使其磊晶层表面裸露。
  10. 根据权利要求 7 所述的一种发光二极管封装结构的制作方法，其特征在于：所述凹槽结构的高度差介于 50 微米至 300 微米之间。
  11. 根据权利要求 7 所述的一种发光二极管封装结构的制作方法，其特征在于：所述凹槽结构的顶部开口宽度介于 100 微米至 1000 微米之间。
PCT/CN2014/071051 2013-04-19 2014-01-22 一种发光二极管封装基板与封装结构及其制作方法 WO2014169721A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/748,393 US20150295148A1 (en) 2013-04-19 2015-06-24 Package Substrate and Package Structure of Light Emitting Diode and Fabrication Thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310137420.X 2013-04-19
CN201310137420.XA CN103199187B (zh) 2013-04-19 2013-04-19 一种发光二极管封装基板与封装结构及其制作方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14/748,393 Continuation US20150295148A1 (en) 2013-04-19 2015-06-24 Package Substrate and Package Structure of Light Emitting Diode and Fabrication Thereof

Publications (1)

Publication Number Publication Date
WO2014169721A1 true WO2014169721A1 (zh) 2014-10-23

Family

ID=48721621

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/071051 WO2014169721A1 (zh) 2013-04-19 2014-01-22 一种发光二极管封装基板与封装结构及其制作方法

Country Status (3)

Country Link
US (1) US20150295148A1 (zh)
CN (1) CN103199187B (zh)
WO (1) WO2014169721A1 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103199187B (zh) * 2013-04-19 2015-11-25 安徽三安光电有限公司 一种发光二极管封装基板与封装结构及其制作方法
CN104141904B (zh) * 2014-07-22 2017-12-05 上海博恩世通光电股份有限公司 一种插入式双面固晶全周发光led功率型灯丝模组
CN104638090B (zh) * 2014-12-18 2018-03-06 上海大学 倒装led封装模组
CN107134511A (zh) * 2016-02-26 2017-09-05 上海博恩世通光电股份有限公司 一种在封装过程中提升倒装led芯片性能的方法
CN111293199A (zh) * 2017-01-20 2020-06-16 光宝光电(常州)有限公司 发光二极管封装结构、发光二极管封装模块
KR102356216B1 (ko) * 2017-05-30 2022-01-28 쑤저우 레킨 세미컨덕터 컴퍼니 리미티드 발광소자 패키지 및 광원 장치
TWI735645B (zh) * 2017-09-06 2021-08-11 優顯科技股份有限公司 用於批量移轉微半導體結構之方法、及其具微半導體結構之目標基板
CN111326609B (zh) 2018-12-14 2021-05-25 成都辰显光电有限公司 发光器件、发光器件的制作方法及显示装置
JP7239823B2 (ja) * 2019-04-05 2023-03-15 日亜化学工業株式会社 発光装置の製造方法及び発光装置
CN113964260B (zh) * 2021-10-09 2022-07-29 深圳市美丽微半导体有限公司 一种二极管封装方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100878327B1 (ko) * 2007-07-06 2009-01-14 한국광기술원 웨이퍼레벨 패키징된 발광다이오드 및 그의 제조 방법
CN101471407A (zh) * 2007-12-24 2009-07-01 亿光电子工业股份有限公司 薄型发光二极管装置的封装方法
WO2009096619A1 (en) * 2008-02-01 2009-08-06 Ytel Photonics Inc. Optical device package and method for manufacturing thereof
CN103199187A (zh) * 2013-04-19 2013-07-10 安徽三安光电有限公司 一种发光二极管封装基板与封装结构及其制作方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6599768B1 (en) * 2002-08-20 2003-07-29 United Epitaxy Co., Ltd. Surface mounting method for high power light emitting diode
CN102804428B (zh) * 2010-03-30 2016-09-21 大日本印刷株式会社 Led用引线框或基板、半导体装置和led用引线框或基板的制造方法
US20120043639A1 (en) * 2010-08-19 2012-02-23 MOS Art Pack Corporation Fabricating method and structure of submount
JP2013033910A (ja) * 2011-06-29 2013-02-14 Hitachi Cable Ltd 発光素子搭載用基板、ｌｅｄパッケージ、及びｌｅｄパッケージの製造方法
CN102569287A (zh) * 2012-01-19 2012-07-11 日月光半导体制造股份有限公司 半导体光源模块及其制造方法
CN104488096B (zh) * 2012-09-26 2017-09-22 日亚化学工业株式会社 发光装置
TWI483434B (zh) * 2013-02-18 2015-05-01 Lextar Electronics Corp 發光二極體的轉置基材與使用該轉置基材的發光裝置製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100878327B1 (ko) * 2007-07-06 2009-01-14 한국광기술원 웨이퍼레벨 패키징된 발광다이오드 및 그의 제조 방법
CN101471407A (zh) * 2007-12-24 2009-07-01 亿光电子工业股份有限公司 薄型发光二极管装置的封装方法
WO2009096619A1 (en) * 2008-02-01 2009-08-06 Ytel Photonics Inc. Optical device package and method for manufacturing thereof
CN103199187A (zh) * 2013-04-19 2013-07-10 安徽三安光电有限公司 一种发光二极管封装基板与封装结构及其制作方法

Also Published As

Publication number Publication date
US20150295148A1 (en) 2015-10-15
CN103199187A (zh) 2013-07-10
CN103199187B (zh) 2015-11-25

Similar Documents

Publication Publication Date Title
WO2014169721A1 (zh) 一种发光二极管封装基板与封装结构及其制作方法
US7843074B2 (en) Underfill for light emitting device
CN109935664B (zh) 光电半导体戳记及其制造方法与光电半导体装置
JP5096782B2 (ja) 半導体装置
JP4757398B2 (ja) 半導体装置の製造方法
KR100433781B1 (ko) 반도체장치의 제조방법
US11538785B2 (en) Method of using optoelectronic semiconductor stamp to manufacture optoelectronic semiconductor device
WO2001015223A1 (fr) Dispositif semi-conducteur et son procede de fabrication
TWI668827B (zh) 半導體裝置、半導體裝置之製造方法及半導體封裝之製造方法
JP4595265B2 (ja) 半導体装置の製造方法
JP2003017513A5 (zh)
JP2007123362A (ja) デバイスの製造方法
JP2001338932A (ja) 半導体装置及び半導体装置の製造方法
TWI731712B (zh) 發光裝置及發光裝置的製造方法
JP2000173952A (ja) 半導体装置及びその製造方法
TWI793933B (zh) 半導體封裝方法、半導體元件以及包含其的電子設備
TWI566343B (zh) 保護片服貼於晶片感應面之晶片封裝構造
KR20190130082A (ko) 마이크로 발광소자 기판의 제조 방법
WO2022183393A1 (zh) Led封装器件及其制备方法
JPS63143851A (ja) 半導体装置
KR100389226B1 (ko) 방열판 구조체 및 이를 이용한 반도체 장치의 제조방법
JP2003110144A (ja) 半導体発光装置
JP2005142452A (ja) 半導体装置及びその製造方法
JP3976964B2 (ja) 半導体装置の組立方法
TWI837993B (zh) 顯示裝置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14784833

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14784833

Country of ref document: EP

Kind code of ref document: A1