WO2014167882A1 - Circuit à gain variable - Google Patents

Circuit à gain variable Download PDF

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Publication number
WO2014167882A1
WO2014167882A1 PCT/JP2014/052250 JP2014052250W WO2014167882A1 WO 2014167882 A1 WO2014167882 A1 WO 2014167882A1 JP 2014052250 W JP2014052250 W JP 2014052250W WO 2014167882 A1 WO2014167882 A1 WO 2014167882A1
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WO
WIPO (PCT)
Prior art keywords
capacitor
variable gain
input
gain circuit
terminal
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Application number
PCT/JP2014/052250
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English (en)
Japanese (ja)
Inventor
靖也 原田
Original Assignee
オリンパス株式会社
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Filing date
Publication date
Application filed by オリンパス株式会社 filed Critical オリンパス株式会社
Publication of WO2014167882A1 publication Critical patent/WO2014167882A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/008—Control by switched capacitors

Definitions

  • the present invention relates to a variable gain circuit that amplifies an input signal and blocks unnecessary frequency components.
  • FIG. 5 shows the configuration of the variable gain circuit described in Non-Patent Document 1.
  • a variable gain circuit 100 illustrated in FIG. 5 includes an OTA 101 that is a transconductance circuit, an input capacitor 102, a changeover switch 103, a feedback capacitor 104, a feedback resistor 105, a changeover switch 106, and a load capacitor 107. .
  • the OTA 101 has at least a positive input terminal, a negative input terminal, and an output terminal, and amplifies and outputs the input signal Vin input to the positive input terminal.
  • the input capacitor 102 has a plurality of capacitors whose first ends are connected to the negative input terminal of the OTA 101.
  • the changeover switch 103 has a plurality of switches having a first end connected to the second end of the input capacitor 102 and a second end connected to the reference potential or the lowest potential.
  • the first ends of the feedback capacitor 104 and the feedback resistor 105 are connected to the negative input terminal of the OTA 101 and the first end of the input capacitor 102, and the second ends of the feedback capacitor 104 and the feedback resistor 105 are connected to the output terminal of the OTA 101. .
  • the changeover switch 106 has a plurality of switches whose first ends are connected to the output terminal of the OTA 101.
  • the first end of the load capacitor 107 is connected to the second end of the changeover switch 106, and the second end of the load capacitor 107 is connected to the lowest potential.
  • FIG. 6 shows the configuration of the OTA 101.
  • the OTA 101 includes transistors M1, M2, M3, M4, M5, M6, M7, and M8, and a current source I1.
  • the transistors M1, M2, M7, and M8 are composed of PMOS transistors, and the transistors M3, M4, M5, and M6 are composed of NMOS transistors.
  • the gate terminal of the transistor M1 is connected to the positive input terminal of the OTA 101.
  • the gate terminal of the transistor M2 is connected to the negative input terminal of the OTA 101, and the source terminal of the transistor M2 is connected to the source terminal of the transistor M1.
  • the first end of the current source I1 is connected to the highest potential, and the second end of the current source I1 is connected to the source terminal of the transistor M1 and the source terminal of the transistor M2.
  • the gate terminal and the drain terminal of the transistor M3 are connected to the drain terminal of the transistor M1, and the source terminal of the transistor M3 is connected to the lowest potential.
  • the gate terminal and the drain terminal of the transistor M4 are connected to the drain terminal of the transistor M2, and the source terminal of the transistor M4 is connected to the lowest potential.
  • the gate terminal of the transistor M5 is connected to the gate terminal and the drain terminal of the transistor M3, the source terminal of the transistor M5 is connected to the lowest potential, and the drain terminal of the transistor M5 is connected to the output terminal of the OTA 101.
  • the gate terminal of the transistor M6 is connected to the gate terminal and the drain terminal of the transistor M4, and the source terminal of the transistor M6 is connected to the lowest potential.
  • the gate terminal and drain terminal of the transistor M7 are connected to the drain terminal of the transistor M6.
  • the gate terminal of the transistor M8 is connected to the gate terminal and the drain terminal of the transistor M7, the source terminal of the transistor M8 is connected to the highest potential, and the drain terminal of the transistor M8 is connected to the output terminal of the OTA 101.
  • variable gain circuit 100 amplifies the input signal applied to the positive input terminal with a predetermined gain (amplification factor), and removes unnecessary frequency band noise included in the input signal. More specifically, the variable gain circuit 100 defines the input signal applied to the positive input terminal as a ratio of the input capacitor 102 whose value is controlled by the changeover switch 103 and the feedback capacitor 104 (1 ) Is amplified with a gain (Av) shown in the equation.
  • variable gain circuit 100 converts unnecessary low frequency band side noise included in the input signal to a cutoff frequency (fc HPF ) expressed by the equation (2) defined by the product of the feedback capacitor 104 and the feedback resistor 105. Remove accordingly.
  • variable gain circuit 100 controls unnecessary high frequency band noise included in the input signal by the transconductance gm101 controlled by the current source I1 and the changeover switch 106. It is removed according to the cutoff frequency (fc LPF ) shown in the equation (3) defined by the product of the load capacity 107 and the gain (Av).
  • FIG. 7 shows an example of the relationship between the gain (Av) and the cut-off frequencies (fc LPF , fc HPF ) indicated by the equations (1) to (3).
  • the horizontal axis in FIG. 7 indicates the cutoff frequency [Hz]
  • the vertical axis in FIG. 7 indicates the gain [dB].
  • the variable gain circuit 100 amplifies the input signal applied to the positive input terminal to Av [times], and removes noise in a frequency band of fc HPF [Hz] or less and fc LPF [Hz] or more included in the input signal. To do.
  • variable gain circuit 100 can change the value of the input capacitor 102 and change the gain (Av) by controlling the changeover switch 103.
  • the gain (Av ′) in the variable gain circuit 100 in which the input capacitor 102 is changed ⁇ times is defined by the ratio of the input capacitor 102 and the feedback capacitor 104 as shown in the equation (4).
  • equation (4) represents the gain when the capacitance value is multiplied by ⁇ with reference to the capacitance value of the feedback capacitor 104 in equation (1).
  • Equation (5) is the same as Equation (2) above.
  • the cutoff frequency (fc LPF ) on the high frequency band side is defined by the product of transconductance gm101, load capacitance 107, and gain (Av ′), as shown in equation (6).
  • FIG. 8 shows an example of the relationship between the gain (Av ′) and the cut-off frequencies (fc LPF ′, fc HPF ′) indicated by the equations (4) to (6).
  • the horizontal axis in FIG. 8 indicates the cutoff frequency [Hz]
  • the vertical axis in FIG. 8 indicates the gain [dB].
  • the variable gain circuit 100 amplifies an input signal applied to the positive input terminal to Av ′ [times] and has a frequency band of fc HPF ′ [Hz] or less and fc LPF ′ [Hz] or more included in the input signal. Remove noise.
  • the expressions (1) to (3) are compared with the expressions (4) to (6) with reference to FIGS.
  • the cut-off frequencies (fc LPF and fc LPF ′) on the high frequency band side are in a relationship opposite to the gains (Av and Av ′).
  • the gain (Av) increases ⁇ times
  • the cut-off frequency (fc LPF ) becomes 1 / Since it decreases to ⁇ times, the input signal on the high frequency band side input to the variable gain circuit 100 cannot be amplified correctly.
  • the transconductance gm101 of the OTA 101 is increased ⁇ times, and the cutoff frequency (fc LPF ) on the high frequency band side is increased. It is possible to offset the fluctuations in In general, the transconductance gm101 of the OTA 101 that is small and has ultra-low power consumption is proportional to the source-drain current (Ids) of the transistor as shown in the equation (7).
  • Ids source-drain current
  • the present invention provides a variable gain circuit capable of maintaining a constant signal pass band even when the gain is changed while realizing miniaturization and low power consumption.
  • the variable gain circuit has at least a first input terminal, a second input terminal, and an output terminal, and amplifies a signal input to the first input terminal.
  • a transconductance circuit that outputs from the output terminal; a first capacitor having a first end connected to a first reference potential; a second end connected to the second input terminal of the transconductance circuit; One end connected to the second input terminal of the transconductance circuit, a second end connected to the output terminal of the transconductance circuit, and a first end connected to the transconductance circuit.
  • a third capacitor connected to the output terminal and having a second end connected to the second reference potential, and a fourth capacitor connected in parallel with either the first capacitor or the third capacitor; Capacity and said Capacity has a selector switch for controlling the connection of said fourth capacitor to be connected to one parallel with the third capacitor and the first capacitor.
  • the capacitance value of the fourth capacitor may be variable.
  • variable gain circuit may further include a resistor connected in parallel with the second capacitor.
  • the signal passband can be kept constant even when the gain is changed while realizing miniaturization and low power consumption. it can.
  • FIG. 1 is a circuit diagram showing a configuration of a variable gain circuit according to an embodiment of the present invention. It is a graph which shows the relationship between the gain and cutoff frequency of the variable gain circuit which concerns on one Embodiment of this invention. It is a graph which shows the relationship between the gain and cutoff frequency of the variable gain circuit which concerns on one Embodiment of this invention. It is a circuit diagram which shows the structure of the feedback resistance which the variable gain circuit which concerns on one Embodiment of this invention has. It is a circuit diagram which shows the structure of the conventional variable gain circuit. It is a circuit diagram which shows the structure of OTA which the conventional variable gain circuit has. It is a graph which shows the relationship between the gain and cutoff frequency of the conventional variable gain circuit. It is a graph which shows the relationship between the gain and cutoff frequency of the conventional variable gain circuit.
  • FIG. 1 shows a configuration of a variable gain circuit according to the present embodiment.
  • the variable gain circuit 10 includes a transconductance circuit OTA1, an input capacitor C1 (first capacitor), a feedback capacitor C2 (second capacitor), a feedback resistor R1, and a load capacitor.
  • C3 third capacitor
  • change-over switches SW1a, SW1b, SW1c, SW1d and a shared capacitor C4 (fourth capacitor).
  • the shared capacitor C4 can be configured as a variable capacitor.
  • OTA1 has at least a positive input terminal (first input terminal), a negative input terminal (second input terminal), and an output terminal, and amplifies and outputs an input signal Vin input to the positive input terminal.
  • the first end of the input capacitor C1 is connected to the negative input terminal of OTA1, and the second end of the input capacitor C1 is connected to the reference potential Vref (first reference potential).
  • the first ends of the feedback capacitor C2 and the feedback resistor R1 are connected to the negative input terminal of the OTA1, and the second ends of the feedback capacitor C2 and the feedback resistor R1 are connected to the output terminal of the OTA1.
  • the first end of the load capacitor C3 is connected to the output terminal of the OTA1, and the second end of the load capacitor C3 is connected to the lowest potential (second reference potential).
  • the first end of the changeover switch SW1a is connected to the output terminal of OTA1.
  • the first end of the shared capacitor C4 is connected to the second end of the changeover switch SW1a.
  • the shared capacitor C4 is connected in parallel with either the input capacitor C1 or the load capacitor C3.
  • the first end of the changeover switch SW1b is connected to the second end of the shared capacitor C4, and the second end of the changeover switch SW1b is connected to the lowest potential.
  • the first end of the changeover switch SW1c is connected to the first end of the shared capacitor C4, and the second end of the changeover switch SW1c is connected to the second end of the input capacitor C1.
  • the first end of the changeover switch SW1d is connected to the second end of the shared capacitor C4, and the second end of the changeover switch SW1d is connected to the first end of the input capacitor C1.
  • the changeover switches SW1a, SW1b, SW1c, and SW1d can be switched ON and OFF, and the first end and the second end are short-circuited when the switches are ON.
  • the changeover switches SW1a, SW1b, SW1c, and SW1d control the connection of the shared capacitor C4 so that the shared capacitor C4 is connected in parallel with either the input capacitor C1 or the load capacitor C3.
  • OTA1 has the same configuration as OTA101 shown in FIG. 6, description of the configuration of OTA1 is omitted.
  • the change-over switches SW1a to SW1d are controlled before the input signal is applied to the variable gain circuit 10 and during the application of the input signal, and are controlled to amplify the input signal with a desired gain (amplification factor). .
  • the selector switches SW1a and SW1b are controlled to be ON and the selector switches SW1c and SW1d are controlled to be OFF.
  • the first ends of the shared capacitor C4 and the load capacitor C3 are commonly connected to the output terminal of the OTA1, and the second ends of the shared capacitor C4 and the load capacitor C3 are commonly connected to the lowest potential.
  • a load capacitor C3 are connected in parallel. At this time, the variable gain circuit 10 amplifies the input signal with a relatively low gain.
  • the changeover switches SW1a and SW1b are controlled to be OFF, and the changeover switches SW1c and SW1d are controlled to be ON.
  • the first end of the shared capacitor C4 and the input capacitor C1 are commonly connected to the first end of the input capacitor C1
  • the second end of the shared capacitor C4 and the input capacitor C1 are commonly connected to the reference potential Vref.
  • the shared capacitor C4 and the input capacitor C1 are connected in parallel. At this time, the variable gain circuit 10 amplifies the input signal with a relatively high gain.
  • variable gain circuit 10 amplifies the input signal applied to the positive input terminal with a predetermined gain, and removes unnecessary frequency band noise included in the input signal.
  • variable gain circuit 10 When load capacity C3 and shared capacity C4 are connected in parallel, The gain and cut-off frequency of the variable gain circuit 10 when the load capacitor C3 and the shared capacitor C4 are connected in parallel when the changeover switches SW1a and SW1b are turned on and the changeover switches SW1c and SW1d are turned off will be described.
  • the variable gain circuit 10 amplifies the input signal applied to the positive input terminal with the gain (Av) shown in the equation (8) according to the ratio of the input capacitance C1 and the feedback capacitance C2.
  • variable gain circuit 10 removes unnecessary low frequency band noise included in the input signal at a cutoff frequency (fc HPF ) shown in the equation (9) according to the product of the feedback capacitor C2 and the feedback resistor R1. To do.
  • variable gain circuit 10 uses the common frequency controlled by the transconductance gm1, the load capacitor C3, and the change-over switches SW1a to SW1d as noise on the high frequency band side included in the input signal. According to C4, it removes according to the cut-off frequency (fc LPF ) shown in the equation (10).
  • FIG. 2 shows an example of the relationship between the gain (Av) and the cut-off frequencies (fc LPF , fc HPF ) indicated by the equations (8) to (10).
  • the horizontal axis in FIG. 2 indicates the cutoff frequency [Hz]
  • the vertical axis in FIG. 2 indicates the gain [dB].
  • the variable gain circuit 10 amplifies the input signal applied to the positive input terminal to Av [times] and removes noise in the frequency band of fc HPF [Hz] or less and fc LPF [Hz] or more included in the input signal. To do.
  • variable gain circuit 100 When input capacitor C1 and shared capacitor C4 are connected in parallel, the cutoff frequency (fc LPF ) on the low frequency side, which is in a contradictory relationship, decreases. For this reason, the input signal on the high frequency band side input to the variable gain circuit 100 cannot be correctly amplified.
  • the gain (Av) in the variable gain circuit 10 when the gain (Av) in the variable gain circuit 10 is increased, by controlling the changeover switches SW1a to SW1d, the input capacitor C1 and the shared capacitor C4 are connected in parallel, and the load capacitor C3 and the shared capacitor C4 are It is not a parallel connection. As a result, the high-frequency cutoff frequency (fc LPF ) can be kept constant.
  • the gain and cutoff frequency of the variable gain circuit 10 when the input capacitor C1 and the shared capacitor C4 are connected in parallel when the changeover switches SW1a and SW1b are turned off and the changeover switches SW1c and SW1d are turned on will be described.
  • the switches SW1a and SW1b By controlling the switches SW1a and SW1b to be OFF and controlling the switches SW1c and SW1d to be ON so that the gain of the variable gain circuit 10 is ⁇ times the gain (Av), the sum of the input capacitances is controlled.
  • the gain (Av ′) in the variable gain circuit 10 is expressed by equation (11).
  • the load capacitance of the variable gain circuit 10 is 1 / ⁇ Doubled.
  • the cut-off frequency (fc LPF ′) on the wide area side in the variable gain circuit 10 is expressed by equation (13). This is the same as the above equation (10).
  • FIG. 3 shows an example of the relationship between the gain (Av ′) and the cut-off frequencies (fc LPF ′, fc HPF ′) indicated by the equations (11) to (13).
  • the horizontal axis in FIG. 3 indicates the cutoff frequency [Hz]
  • the vertical axis in FIG. 3 indicates the gain [dB].
  • the variable gain circuit 10 amplifies an input signal applied to the positive input terminal to Av ′ [times], and at the same time, noise in a frequency band of fc HPF [Hz] or less and fc LPF [Hz] or more included in the input signal. Remove.
  • variable gain circuit 10 can correctly amplify the input signal on the high frequency band side as compared with the prior art.
  • the load capacity of the variable gain circuit 10 is only the load capacity C3, the load capacity becomes 1 / ⁇ times as compared with the case where the load capacity C3 and the shared capacity C4 are connected in parallel. Becomes the equation (15).
  • the capacitance values of the input capacitor C1, the feedback capacitor C2, the load capacitor C3, and the shared capacitor C4 are adjusted in advance so as to satisfy the equations (14) and (15). That is, the capacitance values of the input capacitance C1, the feedback capacitance C2, and the load capacitance C3 are adjusted in advance so that the sum of the capacitance values of the input capacitance C1 and the feedback capacitance C2 is the same as the capacitance value of the load capacitance C3.
  • the shared capacitor C4 can be configured as a variable capacitor having a variable capacitance value.
  • variable gain circuit 10 includes the changeover switches SW1a, SW1b, and the like so that the shared capacitor C4 and only one of the input capacitor C1 and the load capacitor C3 are connected in parallel.
  • the signal passband fc HPF to fc LPF [Hz]
  • the shared capacitor C4 as a variable capacitor and changing the capacitance value, the relationship between the gain of the variable gain circuit 10 and the cutoff frequency can be arbitrarily adjusted.
  • the feedback resistor R1 may be configured as a pseudo MOS resistor including at least four PMOS transistors T1, T2, T3, and T4.
  • the present invention can be widely applied to a variable gain circuit.
  • the signal pass band can be kept constant even when the gain is changed while realizing miniaturization and low power consumption.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Control Of Amplification And Gain Control (AREA)
  • Amplifiers (AREA)

Abstract

L'invention porte sur un circuit à gain variable qui comprend : un circuit à transconductance qui est pourvu d'au moins une première borne d'entrée, une seconde borne d'entrée et une borne de sortie et qui amplifie un signal appliqué à la première borne d'entrée et délivre le signal par la borne de sortie ; un premier condensateur ayant une première borne connectée à un premier potentiel de référence et une seconde borne connectée à la seconde borne d'entrée du circuit à transconductance ; un deuxième condensateur ayant une première borne connectée à la seconde borne d'entrée du circuit à transconductance et une seconde borne connectée à la borne de sortie du circuit à transconductance ; un troisième condensateur ayant une première borne connectée à la borne de sortie du circuit à transconductance et une seconde borne connectée à un second potentiel de référence ; un quatrième condensateur connecté en parallèle au premier condensateur ou au troisième condensateur ; et des commutateurs pour commander les connexions du quatrième condensateur de manière que le quatrième condensateur soit connecté en parallèle au premier condensateur ou au troisième condensateur.
PCT/JP2014/052250 2013-04-12 2014-01-31 Circuit à gain variable WO2014167882A1 (fr)

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JP2013-084229 2013-04-12
JP2013084229A JP2014207577A (ja) 2013-04-12 2013-04-12 可変利得回路

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017150468A1 (fr) * 2016-02-29 2017-09-08 株式会社ニコン Élément d'imagerie, dispositif d'imagerie et dispositif de condensateur

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05114835A (ja) * 1991-10-22 1993-05-07 Toshiba Corp 集積フイルタ回路とその調整方法
JPH06270462A (ja) * 1993-03-24 1994-09-27 Canon Inc 画像形成装置の光量制御装置
JP2002185298A (ja) * 2000-12-11 2002-06-28 Toyota Central Res & Dev Lab Inc 物理量検出回路
JP2005323131A (ja) * 2004-05-10 2005-11-17 Sony Corp 利得制御増幅回路および記録再生装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05114835A (ja) * 1991-10-22 1993-05-07 Toshiba Corp 集積フイルタ回路とその調整方法
JPH06270462A (ja) * 1993-03-24 1994-09-27 Canon Inc 画像形成装置の光量制御装置
JP2002185298A (ja) * 2000-12-11 2002-06-28 Toyota Central Res & Dev Lab Inc 物理量検出回路
JP2005323131A (ja) * 2004-05-10 2005-11-17 Sony Corp 利得制御増幅回路および記録再生装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017150468A1 (fr) * 2016-02-29 2017-09-08 株式会社ニコン Élément d'imagerie, dispositif d'imagerie et dispositif de condensateur

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