WO2014155701A1 - シーケンサシステムおよびアドレス設定方法 - Google Patents
シーケンサシステムおよびアドレス設定方法 Download PDFInfo
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- WO2014155701A1 WO2014155701A1 PCT/JP2013/059616 JP2013059616W WO2014155701A1 WO 2014155701 A1 WO2014155701 A1 WO 2014155701A1 JP 2013059616 W JP2013059616 W JP 2013059616W WO 2014155701 A1 WO2014155701 A1 WO 2014155701A1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/20—Hop count for routing purposes, e.g. TTL
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/22—Pc multi processor system
- G05B2219/2207—Microcontroller combined with state sequencer
Definitions
- the present invention relates to a sequencer system and an address setting method.
- Patent Document 1 a multistage sequencer system in which a plurality of bases are connected has been used. Each base is equipped with a plurality of sequencer units. In such a sequencer system, for example, the following method may be adopted as a method for setting an address to each base.
- the address setting signal for address setting in each extension base is short-circuited by a jumper line, and this signal is connected to a logic circuit. There is a way to read.
- the address setting is fixed
- an adder circuit is provided in each base and an address designation signal is used.
- the base address of the base base generated in the base base is transmitted to each extension base by an address designation signal, and each extension base adds +1 to the base address by the adder circuit.
- a base address is generated.
- automating address setting there is a method using an address confirmation signal.
- a control unit mounted on the basic base transmits an address through a composite signal line and outputs an address determination signal.
- the logic circuit receives the address and the address confirmation signal in the address unset state, the contents of the address are self-set, and a response is transmitted to the control unit using the composite signal line.
- the logic circuit outputs an address determination transmission signal to the gate, and the gate that has received this signal is ready to transmit the address determination signal to the expansion base connected to the next stage. By repeating the expansion base of the stage, the base address setting is automated.
- the method of performing address setting by short-circuiting the address setting signal with a jumper wire as described above increases the amount of work for the user when starting up the system or changing the system configuration. Further, from the viewpoint of emphasizing system expandability in recent years, labor saving of these operations is desired. In addition, since a large amount of work is required when starting up the system or changing the system configuration, unset or erroneous settings are likely to occur, and thus automation of work is desired.
- the addresses are sequentially incremented by 1 on the extension base, the addresses are allocated in order from the upper stage, so that an arbitrary address cannot be allocated to a specific stage. Further, if the base is added to the intermediate stage, all the addresses after the next stage are changed, so the user must also change the addresses used in the program.
- An object of the present invention is to provide a sequencer system capable of improving system expandability by enabling flexible implementation of address setting setting order and setting change while automating base address setting.
- the present invention is a sequencer system including a plurality of bases, and the base includes a basic base and a plurality of stages of extension bases.
- the extension base of the stage is connected in series with the basic base as one end by a bus using a composite signal line, and transmission between the bases in a relay format enables communication between adjacent bases and different bases.
- the control unit can transmit the HOP designation packet designating the number of HOPs toward the base.
- the base receives a HOP designation packet having a number other than 0, the control unit decrements the HOP number by 1 and continues to the next.
- the HOP designation packet is a packet addressed to itself. And judging as that.
- the sequencer system according to the present invention is a sequencer system capable of improving system expandability by enabling flexible implementation of address setting setting order and setting change while automating base address setting. There is an effect that it can be obtained.
- FIG. 1 is a block diagram showing a schematic configuration of the sequencer system according to the first embodiment of the present invention.
- FIG. 2 is a flowchart for explaining the operation procedure of the control unit at the time of base connection detection and base address setting.
- FIG. 3 is a flowchart for explaining the operation procedure of the relay unit.
- FIG. 4 is a block diagram showing a schematic configuration of a sequencer system shown as the first comparative example.
- FIG. 5 is a block diagram showing a schematic configuration of a sequencer system shown as the second comparative example.
- FIG. 6 is a block diagram showing a schematic configuration of a sequencer system shown as Comparative Example 3.
- FIG. 1 is a block diagram showing a schematic configuration of the sequencer system according to the first embodiment of the present invention.
- the sequencer system 10 is a multistage sequencer system having a three-stage base including a basic base B0 and two extension bases B1 and B2.
- the basic base B0 is equipped with a control unit U00 and controlled units U01 to 03 as sequencer units.
- the basic base B0 includes a relay unit HUB0.
- the extension base B1 is equipped with controlled units U10 to U13 as sequencer units.
- the extension base B2 is equipped with controlled units U20 to U23 as sequencer units.
- the expansion base B1 has a relay unit HUB1, and the expansion base B2 has a relay unit HUB2.
- the basic base B0 is configured with one control unit and three controlled units, but the number of control units and controlled units is not limited to this. For example, two or more control units may be mounted, or four or more controlled units may be mounted. Of course, the number of controlled units may be two or less.
- extension bases B1 and B2 are each configured to be equipped with four controlled units, the number of controlled units is not limited to four, and any number may be installed.
- the sequencer system 10 has a three-stage configuration including the basic base B0 and the expansion bases B1 and B2.
- the number of expansion bases is not limited to two and is arbitrary. For example, three or more extension bases may be provided.
- the bases B0 to B2 are connected in a line type by the relay units HUB0 to HUB2.
- the relay unit HUB0 mounted on the basic base B0 and the relay unit HUB1 mounted on the extension base B1 are connected by the composite signal line BUS04.
- the relay unit HUB1 mounted on the extension base B1 and the relay unit HUB2 mounted on the extension base B2 are connected by the composite signal line BUS14.
- the basic base B0 and the multiple-stage expansion bases B1 and B2 are connected in series with the basic base B0 as one end using the composite signal lines BUS04 to 24. Note that, from the HUB 2 mounted on the extension base B 2, a composite signal line BUS 24 for connection with the relay unit of the next extension base is drawn out when an extension base is further provided.
- control unit U00, the controlled units U01 to U03, and the relay unit HUB0 are connected in a star shape with the relay unit HUB0 as the center. More specifically, in the basic base B0, the control unit U00 and the controlled units U01 to 03 are connected to the relay unit HUB0 via the composite signal lines BUS00 to 03.
- the controlled units U10 to U13 and the relay unit HUB1 are connected in a star shape with the relay unit HUB1 as the center. More specifically, the controlled units U10 to U13 are connected to the relay unit HUB1 through composite signal lines BUS10 to 13.
- the controlled units U20 to U23 and the relay unit HUB2 are connected in a star shape centered on the relay unit HUB2. More specifically, the controlled units U20 to U23 are connected to the relay unit HUB2 by composite signal lines BUS20 to 23.
- the composite signal lines BUS00 to BUS24 are independent connections.
- a signal transmitted from the relay unit HUB0 to the relay unit HUB1 can be received only by the relay unit HUB1, and the relay unit HUB2, the control unit U00, The controlled units U01 to U23 are connected so that they cannot be received.
- the communication between the control unit U00 and the controlled units U01 to U23 uses a communication system for transmitting a packet with a unit address having a base address and a slot number as a destination.
- control unit U00 reads data from the controlled unit U13 when the unit address of the control unit U00 is 00 and the unit address of the controlled unit U13 is 13.
- a packet has a header and data.
- the control unit U00 stores the unit address 13 of the controlled unit U13 as a destination in the header portion, and transmits a packet storing a read command in the data portion to the relay unit HUB0.
- the unit address “13” has a base address “1” and a slot number “3”.
- the relay unit HUB0 transfers the read command packet to the relay unit HUB1 according to the destination.
- the relay unit HUB1 determines that the packet is addressed to its own base based on the information of the base address “1” included in the unit address “13”, and reads it to the controlled unit U13 in the third slot according to the information of the slot number “3”. Transfer the instruction packet.
- the controlled unit U13 that has received the read command packet transmits a response packet to which the unit address 00 of the control unit U00 is added as a destination to the relay unit HUB1.
- the relay unit HUB1 transfers the response packet to the relay unit HUB0 according to the destination.
- the relay unit HUB0 transfers the response packet to the control unit U00 in the 0th slot according to the destination.
- the setting of the base address when the base address of each base is not set will be described.
- the connection of each base is detected and the base address is set by the control unit U00 using the HOP designation packet designating the number of HOPs in a state where the base address of each base is not set.
- a packet in which the number of HOPs is stored as the number of times of data transfer in the header portion is set as a HOP designation packet.
- FIG. 2 is a flowchart for explaining the operation procedure of the control unit U00 when the base connection is detected and the base address is set.
- step S103 if it is before the time is up (step S103, No), the process returns to step S102.
- step S102 and step S103 are repeated and a response packet is received before the time is up (step S102, Yes)
- the control unit U00 transmits a HOP designation packet to which an address setting command for the extension base B1 is added.
- step S104 If the response packet for the transmission packet transmitted in step S104 cannot be received (step S105, No) and the response packet cannot be received within a predetermined time and the time is up (step S106, Yes), step S102 There will be no response from the expansion base that has been confirmed connection. Therefore, the control unit U00 determines that the error is caused by a failure of the relay unit or disconnection of the composite signal line, and ends the flow.
- step S106 if it is before the time is up (No in step S106), the process returns to step S105.
- step S105 and step S106 are repeated, and if the response packet can be received before the time is up (step S105, Yes), it is determined that the address setting to the extension base is completed. Then, returning to step S100, the connection confirmation to the next expansion base and address setting are performed. This flow is repeated until it is determined that the extension base for the number of HOPs is not connected (Yes in step S103).
- step S105 generation of an HOP designation packet in which the number of HOPs for the extension base B2 is set to 2 after it is determined in step S105 that the address setting for the extension base B1 has been completed. To the address setting (steps S100 to S105) are performed again.
- the time is up in step S103, and this flow ends.
- packets can be transmitted and received using the unit address configured with the base address and the slot number.
- the number of HOPs of the HOP designation packet generated in step S100 is designated in ascending order with 1 being the initial value, which means the first stage of the extension base. It is possible to specify numbers in descending order with initial values, and it is also possible to specify arbitrary values in arbitrary order. This means that the address setting of the extension base is not performed in the order of connection, but the address setting can be performed only for an arbitrary extension base.
- FIG. 3 is a flowchart for explaining the operation procedure of the relay units HUB0-2.
- the relay unit When the relay unit receives the HOP designation packet (step S200), it determines whether the number of HOPs in the received HOP designation packet is 0 (step S201). If the number of HOPs in the received HOP designation packet is not 0 (No in step S201), the HOP designation packet is transferred to the base relay unit connected to the next stage after subtracting 1 from the HOP number ( Step S202), the flow ends.
- step S203 If the number of HOPs in the received HOP designation packet is 0 (step S201, Yes), it is determined whether an address setting command is added to the HOP designation packet (step S203). If an address setting command is added to the HOP designation packet (step S203, Yes), the base address is self-set according to the address setting command (step S204), and a response packet is transmitted to the control unit U00 ( Step S205), the flow ends.
- Step S203 if an address setting command is not added to the HOP designation packet (No at Step S203), the process proceeds to Step S205, a response packet is transmitted to the control unit U00, and the flow ends.
- a HOP designation packet is generated with the number of HOPs corresponding to the number of stages of the corresponding base, and the base address is set according to the flow of FIG. can do.
- the relay unit since the relay unit only transfers the packet to the other base, the state in which the base address is set is maintained. Therefore, changing the address of some bases has little effect on other bases. For this reason, it is possible to perform part of the base address changing process even while the control to another base is being executed.
- a HOP designation packet is generated with the number of HOPs obtained by adding 1 to the number of stages confirmed to be connected at that time, and the base address is determined according to the flow of FIG. Can be set. At this time, the base address is still set in the other bases and is not affected by the addition of the base address. Therefore, the base address addition process can be performed even while the control to the other base is being executed. .
- FIG. 4 is a block diagram showing a schematic configuration of a sequencer system shown as the first comparative example.
- a sequencer system 20 shown as Comparative Example 1 a basic base B0a and a plurality of stages of extension bases B1a and B2a are connected in a bus type by a composite signal line BUSa.
- the control unit U0a0 controls the controlled unit by designating an address composed of a base number and a slot number to which each unit is connected. For example, when control is performed such that when a signal is input to the controlled unit U1a3 connected to the extension base B1a, the signal of the controlled unit U2a2 connected to the extension base B2a is output, the control unit U0a0 A data read command is issued to the third slot of the stage to acquire input data, and after performing an operation according to the program, a data write command is issued to the second slot of the second stage of the base to output data.
- write is performed such that when a signal is input to the controlled unit U1a3 connected to the extension base B1a, the signal of the controlled unit U2a2 connected to the extension base B2a is output, the control unit U0a0 A data read command is issued to the third slot of the stage to acquire input data, and after performing an operation according to the program, a data write command is issued to the second slot of the second stage of the base to output data. Write.
- connection of each base and each unit can be changed by the user depending on the application, so that the control unit U0a0 has the base number and the slot immediately after the system is started. It is necessary to assign addresses consisting of numbers.
- the logic circuit GA reads that it is an access to the unit of its own base from the composite signal line BUSa, and the logic circuit GA designates the corresponding unit using a technique such as outputting the select signal CS to the corresponding unit. In response, the controlled unit responds.
- FIG. 5 is a block diagram showing a schematic configuration of a sequencer system shown as Comparative Example 2.
- the sequencer system 30 in which the address setting is fixed will be described as an example.
- the sequencer system 30 is provided with an addition circuit GS.
- the base address of the basic base B0b generated by the basic base B0b is transmitted to the respective extension bases B1b and B2b by the address designation signal BA, and each of the extension bases B1b and B2b adds +1 to the base address by the adder circuit GS. By doing so, the base address of each extension base B1b, B2b is generated.
- the generated base address is also transmitted to the logic circuit GA by the address designation signal BA.
- the logic circuit GA determines whether the access of the composite signal line BUSb is an access to its own base, and the logic circuit GA designates the corresponding unit using a method such as outputting the select signal CS to the corresponding unit, The controlled unit that receives this responds.
- FIG. 6 is a block diagram showing a schematic configuration of a sequencer system shown as Comparative Example 3.
- the sequencer system 40 in which address setting is automated will be described as an example.
- the control unit U0c0 transmits an address through the composite signal line BUSc and outputs an address determination signal AA.
- the logic circuit GA When the logic circuit GA receives the composite signal line BUSc and the address determination signal AA in the address unset state, the content of the composite signal line BUSc is self-set, and a response is transmitted to the control unit U0c0 using the composite signal line BUSc.
- the logic circuit GA outputs the address determination transmission signal AT to the gate G, and the gate G receiving the address is in a state where it can transmit the address determination signal AA to the extension base connected to the next stage.
- the base address setting is automated.
- the address setting signal is short-circuited by a jumper line and the address setting is performed, the amount of work of the user increases when starting up the system or changing the system configuration. Further, from the viewpoint of emphasizing system expandability in recent years, labor saving of these operations is desired. In addition, since a large amount of work is required when starting up the system or changing the system configuration, unset or erroneous settings are likely to occur, and thus automation of work is desired.
- an address designation signal is separately required. Since the addresses are sequentially incremented by 1 on the extension base, the addresses are allocated in order from the upper stage, so that an arbitrary address cannot be allocated to a specific stage. Further, if the base is added to the intermediate stage, all the addresses after the next stage are changed, so the user must also change the addresses used in the program.
- an address determination signal is separately required. Since the address confirmation signal is transmitted to the expansion base connected to the next stage after the address setting is completed, it is necessary to set the addresses in order from the upper stage. After all addresses are set, the address confirmation signal is transmitted to the base of the final stage, and each extension base ignores the address confirmation signal. It is necessary to release the address and set the address again from the top. Therefore, while the address is reset, the control unit cannot access all other controlled units, and the control of the sequencer system must be stopped.
- the sequencer system 10 since the bases are connected one-to-one by one bus, the communication between the bases is independent of the other bases, and the base address is not set. Even in a bad state, it will not be broadcast to all bases.
- a command is transmitted between the bases in a relay format, and information added to the command can be changed while relaying according to a certain rule.
- each base transmits a command while relaying by using a rule that adds information on the number of HOPs and transmits a command and subtracts 1 from the number of HOPs.
- each base recognizes that the instruction is for its own base, and if the base stage number is added to the instruction as the number of HOPs even when the base address is not set, it depends on the connection order of the bases. Any base can be accessed. For this reason, it is not necessary to use an address designation signal or an address determination signal separately.
- control unit can transmit a packet to a base connected to an arbitrary stage, and can determine whether or not the extension base is connected based on the presence or absence of a response from the base within a predetermined time.
- control unit can transmit a packet to a base connected to an arbitrary stage, and can determine whether or not the extension base is connected based on the presence or absence of a response from the base within a predetermined time.
- a rule for specifying the number of HOPs a rule for subtracting this number of HOPs, and a rule for each base to send a response packet when the number of HOPs becomes 0, any base connection order can be used.
- the extension base connection can be detected in order.
- the packet is transmitted.
- the base determined to be a packet addressed to the own base can be set to the specified unique address.
- sequencer system according to the present invention is useful for a sequencer system having a basic base and an extension base.
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Abstract
Description
図1は、本発明の実施の形態1にかかるシーケンサシステムの概略構成を示すブロック図である。シーケンサシステム10は、基本ベースB0と2つの増設ベースB1,B2からなる3段のベースを有する多段式のシーケンサシステムである。基本ベースB0には、シーケンサユニットとして、制御ユニットU00、被制御ユニットU01~03が装着される。また、基本ベースB0は、中継部HUB0を有する。
Claims (4)
- 複数のベースを備えるシーケンサシステムであって、
前記ベースには、制御ユニットが装着された基本ベースと、複数段の増設ベースとが含まれ、
前記基本ベースと複数段の前記増設ベースとが、複合信号線を用いたバスによって前記基本ベースを一端とする直列に接続され、
前記ベース間をリレー形式で伝送することで、隣接する前記ベースと異なるベースとの通信が可能とされ、
前記制御ユニットは、HOP数を指定したHOP指定パケットを前記ベースに向けて送信可能とされ、
前記ベースは、前記HOP数が0以外の前記HOP指定パケットを受信した場合には、HOP数を1減算して次段に接続された前記ベースへ前記HOP指定パケットを転送し、前記HOP数が0の前記HOP指定パケットを受信した場合に、そのHOP指定パケットが自己宛てのパケットであると判定することを特徴とするシーケンサシステム。 - 前記ベースは、前記HOP数が0の前記HOP指定パケットを受信した場合に、前記制御ユニットに向けて応答パケットを送信することを特徴とする請求項1に記載のシーケンサシステム。
- 前記制御ユニットは、前記ベースに固有のアドレスを設定する命令のアドレス設定命令を前記HOP指定パケットに追加可能とされ、
前記ベースは、前記HOP数が0の前記HOP指定パケットを受信した場合に、前記HOP指定パケットに追加されている前記アドレス設定命令で指定されたアドレスに自己設定することを特徴とする請求項2に記載のシーケンサシステム。 - 制御ユニットが装着された基本ベースと、被制御ユニットが装着された複数の増設ベースと、を備え、前記基本ベースと前記増設ベースとが、前記基本ベースを一端とする直列に接続された多段式のシーケンサシステムにおける前記増設ベースのアドレス設定方法であって、
前記制御ユニットが、HOP数を指定したHOP指定パケットを生成するステップと、
前記制御ユニットが、前記HOP指定パケットにアドレス設定命令を追加するステップと、
前記制御ユニットが、前記基本ベースおよび前記増設ベースに対して、前記アドレス設定命令が追加されたHOP指定パケットを送信するステップと、
前記基本ベースおよび前記増設ベースが、前記HOP数が0以外の前記HOP指定パケットを受信した場合に、HOP数を1減算して次段に接続された前記増設ベースへ前記HOP指定パケットを転送するステップと、
前記増設ベースが、HOP数が0の前記HOP指定パケットを受信した場合に、前記HOP指定パケットに追加されている前記アドレス設定命令で指定されたアドレスに自己設定するステップと、を有することを特徴とするアドレス設定方法。
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US14/758,816 US9971326B2 (en) | 2013-03-29 | 2013-03-29 | Sequencer system and address setting method |
KR1020157025797A KR101743856B1 (ko) | 2013-03-29 | 2013-03-29 | 시퀀서 시스템 및 어드레스 설정 방법 |
CN201380075133.9A CN105103062B (zh) | 2013-03-29 | 2013-03-29 | 定序器系统及地址设定方法 |
DE112013006760.9T DE112013006760T5 (de) | 2013-03-29 | 2013-03-29 | Ablaufsteuerungssystem und Adresseneinstellungsverfahren |
JP2013528416A JP5389301B1 (ja) | 2013-03-29 | 2013-03-29 | シーケンサシステムおよびアドレス設定方法 |
PCT/JP2013/059616 WO2014155701A1 (ja) | 2013-03-29 | 2013-03-29 | シーケンサシステムおよびアドレス設定方法 |
TW102135491A TWI471710B (zh) | 2013-03-29 | 2013-10-01 | 定序器系統及位址設定方法 |
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US20220026859A1 (en) * | 2021-07-16 | 2022-01-27 | Delta Electronics (Shanghai) Co., Ltd. | Multi-unit cooperative distributed electrical control system and electrical system |
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- 2013-03-29 WO PCT/JP2013/059616 patent/WO2014155701A1/ja active Application Filing
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- 2013-03-29 CN CN201380075133.9A patent/CN105103062B/zh active Active
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DE112013006760T5 (de) | 2015-12-03 |
KR20150122188A (ko) | 2015-10-30 |
US20150355617A1 (en) | 2015-12-10 |
CN105103062B (zh) | 2017-06-23 |
JP5389301B1 (ja) | 2014-01-15 |
CN105103062A (zh) | 2015-11-25 |
JPWO2014155701A1 (ja) | 2017-02-16 |
KR101743856B1 (ko) | 2017-06-05 |
TWI471710B (zh) | 2015-02-01 |
TW201437774A (zh) | 2014-10-01 |
US9971326B2 (en) | 2018-05-15 |
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