WO2014155691A1 - Dispositif à semi-conducteur et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur et son procédé de fabrication Download PDF

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Publication number
WO2014155691A1
WO2014155691A1 PCT/JP2013/059586 JP2013059586W WO2014155691A1 WO 2014155691 A1 WO2014155691 A1 WO 2014155691A1 JP 2013059586 W JP2013059586 W JP 2013059586W WO 2014155691 A1 WO2014155691 A1 WO 2014155691A1
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Prior art keywords
insulating film
pixel electrode
semiconductor device
film
forming
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PCT/JP2013/059586
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English (en)
Japanese (ja)
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芳夫 ▲松▼澤
富康 斉藤
宏道 市川
辰也 三瀬
竹内　哲也
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富士通セミコンダクター株式会社
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Priority to PCT/JP2013/059586 priority Critical patent/WO2014155691A1/fr
Publication of WO2014155691A1 publication Critical patent/WO2014155691A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80518—Reflective anodes, e.g. ITO combined with thick metallic layers

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof.
  • An organic EL display using a light emission phenomenon by organic electroluminescence has features such as self-light emission and high-speed response, and is being applied to a portable terminal, a large-sized television, and the like.
  • organic layer structures in organic EL displays.
  • the basic structure of an organic EL display is to form a hole transport layer, a light emitting layer, and an electron transport layer in this order as an organic layer on the pixel electrode, and to form a transparent electrode as the uppermost layer.
  • the light emitting layer and the electron transport layer are formed as one layer.
  • An organic EL display is provided as a part of a semiconductor device together with a transistor for driving a pixel electrode and the like, and displays a predetermined image by injecting holes and electrons from each of the pixel electrode and the transparent electrode into the light emitting layer.
  • a semiconductor device equipped with such an organic EL display has room for improvement in terms of improving reliability.
  • An object of the present invention is to improve the reliability of a semiconductor device in the semiconductor device and the manufacturing method thereof.
  • a semiconductor substrate a first insulating film formed on the semiconductor substrate, and a plurality of pixel electrodes formed on the first insulating film at intervals And a second insulating film formed on the first insulating film between adjacent pixel electrodes, and the upper surface of the second insulating film is higher than the upper surface of the pixel electrode,
  • a semiconductor device is provided in which the entire upper surface of the pixel electrode is exposed.
  • a semiconductor substrate a first insulating film formed on the semiconductor substrate, and an upper surface formed on the first insulating film with a space therebetween.
  • a plurality of pixel electrodes having side surfaces, a second insulating film formed on the first insulating film between adjacent pixel electrodes, and formed on the pixel electrode and the first insulating film
  • the upper surface of the pixel electrode is positioned higher than the upper surface of the second insulating film between the plurality of pixel electrodes, and the organic layer is on the upper surface of the pixel electrode.
  • a semiconductor device having a first bottom surface positioned at a first bottom surface and a second bottom surface that is continuous with the first bottom surface and has an obtuse angle with the first bottom surface.
  • a step of forming a first insulating film on a semiconductor substrate and a plurality of pixel electrodes are formed on the first insulating film at intervals.
  • a step of forming a first insulating film on a semiconductor substrate, a step of forming a conductive film on the first insulating film, and patterning the conductive film As a result, a plurality of pixel electrodes each having an upper surface and a side surface are formed at intervals, and the second electrode is formed on the pixel electrode and on the first insulating film between the adjacent pixel electrodes. Forming the insulating film, removing the second insulating film from above the pixel electrode while leaving the second insulating film between the adjacent pixel electrodes, and the second insulating film.
  • a first bottom surface located on the surface, contiguous with said first bottom surface, a method of manufacturing a semiconductor device having a second bottom outer corner formed by the first bottom surface is obtuse is provided.
  • the organic layer can be formed thick on the shoulder of the pixel electrode by making the upper surface of the second insulating film higher than the upper surface of the pixel electrode. Therefore, the organic layer can withstand a current having a high current density caused by the electric field concentrated on the shoulder, and the reliability of the semiconductor device can be improved.
  • FIG. 1 is a cross-sectional view (part 1) of the semiconductor device used for the investigation in the course of manufacturing.
  • FIG. 2 is a cross-sectional view (part 2) of the semiconductor device used for the investigation during manufacturing.
  • FIG. 3 is a cross-sectional view (part 3) of the semiconductor device used for the investigation in the middle of manufacture.
  • FIG. 4 is a cross-sectional view (part 4) of the semiconductor device used for the investigation in the course of manufacturing.
  • FIG. 5 is a cross-sectional view (part 5) of the semiconductor device used for the investigation in the middle of manufacture.
  • FIG. 6 is a cross-sectional view (part 6) of the semiconductor device used for the investigation in the middle of manufacture.
  • FIG. 7 is a sectional view (No.
  • FIG. 8 is a cross-sectional view (part 8) of the semiconductor device used for the investigation in the middle of manufacture.
  • FIG. 9 is an enlarged cross-sectional view (part 1) in the middle of manufacturing the semiconductor device according to the first embodiment.
  • FIG. 10 is an enlarged cross-sectional view (part 2) in the middle of manufacturing the semiconductor device according to the first embodiment.
  • FIG. 11 is an enlarged cross-sectional view (part 3) in the middle of manufacturing the semiconductor device according to the first embodiment.
  • FIG. 12 is an enlarged cross-sectional view (part 4) of the semiconductor device according to the first embodiment during manufacture.
  • FIG. 13 is an enlarged cross-sectional view (part 5) in the course of manufacturing the semiconductor device according to the first embodiment.
  • FIG. 14 is an enlarged cross-sectional view (part 6) of the semiconductor device according to the first embodiment in the middle of manufacture.
  • FIG. 15 is an enlarged cross-sectional view (part 7) in the middle of manufacturing the semiconductor device according to the first embodiment.
  • FIG. 16 is an enlarged cross-sectional view (part 6) of the semiconductor device according to the first embodiment in the middle of manufacture.
  • FIG. 17 is a cross-sectional view of the semiconductor device according to the first embodiment including a transistor.
  • FIG. 18 is an enlarged cross-sectional view (part 1) in the middle of manufacturing the semiconductor device according to the second embodiment.
  • FIG. 19 is an enlarged cross-sectional view (part 2) of the semiconductor device according to the second embodiment during manufacture.
  • FIG. 20 is an enlarged cross-sectional view (part 3) during the manufacturing of the semiconductor device according to the second embodiment.
  • FIG. 21 is a cross-sectional view of the semiconductor device according to the second embodiment including a transistor.
  • FIG. 22 is an enlarged cross-sectional view (part 1) in the middle of manufacturing the semiconductor device according to the third embodiment.
  • FIG. 23 is an enlarged cross-sectional view (part 2) of the semiconductor device according to the third embodiment during manufacture.
  • FIG. 24 is an enlarged cross-sectional view (part 3) in the middle of manufacturing the semiconductor device according to the third embodiment.
  • FIG. 25 is an enlarged cross-sectional view (part 4) in the middle of manufacturing the semiconductor device according to the third embodiment.
  • FIG. 26 is a cross-sectional view of the semiconductor device according to the third embodiment including a transistor.
  • FIG. 27 is an enlarged cross-sectional view (part 1) in the middle of manufacturing the semiconductor device according to the fourth embodiment.
  • FIG. 28 is an enlarged cross-sectional view (part 2) in the middle of manufacturing the semiconductor device according to the fourth embodiment.
  • FIG. 29 is an enlarged cross-sectional view (part 3) during the manufacturing of the semiconductor device according to the fourth embodiment.
  • FIG. 30 is an enlarged cross-sectional view (part 4) of the semiconductor device according to the fourth embodiment during manufacture.
  • FIG. 31 is a cross-sectional view of a semiconductor device according to the fourth embodiment including a transistor.
  • 1 to 8 are cross-sectional views of the semiconductor device used for the investigation in the course of manufacturing. Hereinafter, a method for manufacturing the semiconductor device will be described.
  • a trench for STI Shallow Trench Isolation
  • a semiconductor substrate 1 such as a silicon substrate
  • an element isolation insulating film 2 such as a silicon oxide film is formed therein.
  • LOCOS Local Oxidation of Silicon
  • a thermal oxide film and a polysilicon film to be the gate insulating film 3 are formed in the active region of the semiconductor substrate 1 defined by the element isolation insulating film 2, and the polysilicon film is patterned to form the gate electrode 4.
  • impurities are introduced into the semiconductor substrate 1 by ion implantation using the gate electrode 4 and the insulating sidewall 5 as a mask, and next to the gate electrode 4.
  • a source / drain region 6 is formed.
  • a refractory metal silicide layer such as a cobalt silicide layer may be formed on the surface layer of the source / drain region 6 in order to reduce the resistance of the source / drain region 6.
  • the first insulating film 10, the first wiring layer 12, the second insulating film 13, the second wiring layer 15, and the third insulating film 16 are formed in this order.
  • a silicon oxide film is formed as a first insulating film 10, a second insulating film 13, and a third insulating film 16 by a CVD (Chemical Vapor Deposition) method.
  • first wiring layer 12 and the second wiring layer 15 a titanium nitride film, a copper-containing aluminum film, and a titanium nitride film are formed in this order by sputtering.
  • the conductor plug 14 and the third conductor plug 17 are embedded.
  • Each of the conductor plugs 11, 14, and 17 plays a role of electrically connecting the wiring layers above and below them.
  • a first titanium nitride film 21a, a copper-containing aluminum film 21b, and a second nitride are formed on each of the third insulating film 16 and the third conductor plug 17 by sputtering.
  • a titanium film 21 c is formed, and these laminated films are used as the conductive film 21.
  • the first titanium nitride film 21a plays a role of improving the adhesion between the third insulating film 16 and the copper-containing aluminum film 21b.
  • the second titanium nitride film 21c plays a role of preventing oxidation of the copper-containing aluminum film 21b.
  • a photoresist is applied on the conductive film 21, and it is exposed and developed to form a resist film 22.
  • the conductive film 21 is dry-etched using the resist film 22 as a mask to form a plurality of pixel electrodes 21p at intervals.
  • a gas used in the dry etching for example, there is a mixed gas of chlorine gas (Cl 2 ) and oxygen gas (O 2 ).
  • a silicon oxide film is formed as the fourth insulating film 25 on the entire upper surface of the semiconductor substrate 1, and the gaps between the pixel electrodes 21p are filled with the fourth insulating film 25.
  • a silicon oxide film having a thickness of 700 nm to 1000 nm formed by a CVD method using TEOS® (Tetraethyl orthosilicate) gas is employed as the fourth insulating film 25.
  • the fourth insulating film 25 may be formed by HDP (High Density Plasma) CVD using silane gas.
  • the lower side of the fourth insulating film 25 is first formed using TEOS gas, and the upper side of the fourth insulating film 25 is formed thereon by HDPCVD using silane (SiH 4 ) gas. Good.
  • An organic layer such as a hole transport layer is formed later on the pixel electrode 21p.
  • holes are formed from the pixel electrode 21p to the organic layer. Can not be injected.
  • the thickness of the fourth insulating film 25 is increased by polishing using a CMP (Chemical-Mechanical-Polishing) method. make it thin.
  • the fourth insulating film 25 on the pixel electrode 21p is completely removed by the CMP method, the upper surface of the pixel electrode 21p is damaged by a polishing pad (not shown). In this example, the pixel electrode 21p The polishing is stopped before the upper surface of the surface appears.
  • the fourth insulating film 25 remaining on the pixel electrode 21p is completely removed by etching, and the upper surface 21x of the pixel electrode 21p is exposed.
  • the etching is performed by dry etching.
  • a mixed gas of CF 4 gas, argon gas, and oxygen gas is used as the etching gas for the dry etching, and the entire surface of the fourth insulating film 25 is covered with the etching gas. Expose.
  • over-etching is performed so as not to leave a residue of the fourth insulating film 25 on the pixel electrode 21p. Since the etching rate of the fourth insulating film 25 with respect to the etching gas is faster than that of the pixel electrode 21p, the upper surface 25x of the fourth insulating film 25 is lower than the upper surface 21x of the pixel electrode 21p by this overetching.
  • the fourth insulating film 25 is previously polished and flattened in the step of FIG. 5, the flatness of the upper surface 25x of the fourth insulating film 25 is good even after the etching in this step.
  • the basic structure of the semiconductor device 30 for the organic EL display is completed through the steps so far.
  • a hole transport layer 31 and a light emitting layer 32 are formed in this order by a vapor deposition method, thereby forming an organic layer 33 having a two-layer structure.
  • the light emitting layer 32 also functions as an electron transport layer.
  • each layer is not particularly limited.
  • ⁇ -NPD diphenylnaphthyldiamine
  • Alq3 tris (8-quinolinolato) aluminum
  • the thickness of each layer is not particularly limited, and the hole transport layer 31 can be formed to a thickness of about 50 nm, and the light emitting layer 32 can be formed to a thickness of about 50 nm.
  • the heights of the upper surfaces 21x and 25x of the pixel electrode 21p and the fourth insulating film 25 are different as described above due to the over-etching of FIG. It is formed on a base with a step.
  • the film thickness T of the hole transport layer 31 is not uniform in the substrate plane due to the step.
  • the shoulder portion 21s of the pixel electrode 21p protrudes above the fourth insulating film 25, it is difficult for the hole transport layer 31 to be deposited on the shoulder portion 21s, and the hole transport layer 31 in the shoulder portion 21s.
  • the film thickness T becomes thinner than other portions.
  • an ITO (Indium-Tin-Oxide) film is formed on the organic layer 33 as a transparent electrode film 34 by vapor deposition, and a transparent glass substrate 35 is further adhered thereon.
  • the organic EL display unit 40 including the organic layer 33, the transparent electrode film 34, and the transparent glass substrate 35 is formed in the semiconductor device 30.
  • a predetermined voltage is applied between the transparent electrode film 34 and the pixel electrode 21p with the transparent electrode film 34 of the organic EL display unit 40 as a cathode and the pixel electrode 21p as an anode.
  • holes and electrons are injected from the pixel electrode 21p and the transparent electrode film 34, respectively, and are combined in the light emitting layer 32 to generate light L.
  • a part of the light L travels upward and passes through the transparent glass substrate 35, and the rest of the light L is reflected by the pixel electrode 21p and then passes through the transparent glass substrate 35.
  • the second titanium nitride film 21c containing titanium nitride that is harder to be oxidized than aluminum is formed on the uppermost layer of the pixel electrode 21p, it is possible to prevent the surface of the pixel electrode 21p from being oxidized and its reflectance from being lowered, The light L can be efficiently reflected by the pixel electrode 21p.
  • the film thickness T of the hole transport layer 31 in the shoulder portion 21s of the pixel electrode 21p is thinner than the other portions.
  • the shoulder portion 21s located at the edge of the pixel electrode 21p is a portion where the electric field E tends to concentrate originally, and a lot of current flows along the electric field E and the current density is high. Easy to be.
  • the hole transport layer 31 becomes thin at such a portion as described above, the hole transport layer 31 may be destroyed due to a high current density, and holes may be directly injected from the pixel electrode 21p into the light emitting layer 32. As a result, a light emission failure occurs in the vicinity of the pixel electrode 21p, and the reliability of the semiconductor device 30 decreases.
  • the hole transport layer 31 is formed thick overall, and the film thickness T of the hole transport layer 31 at the shoulder 21s is increased.
  • the hole transport layer 31 is thickened, the distance between the pixel electrode 21p and the transparent electrode film 34 is widened and the electric field between them is weakened. Therefore, the current flowing along the electric field is also weakened, and the organic EL display unit 40 The brightness will be reduced.
  • 9 to 16 are enlarged sectional views in the middle of manufacturing the semiconductor device according to the present embodiment, and correspond to the enlarged sectional views in the vicinity of the third insulating film 16 described above.
  • FIGS. 9 to 16 the same elements as those described in FIGS. 1 to 8 are denoted by the same reference numerals as those in FIGS. 1 to 8, and description thereof will be omitted below.
  • this semiconductor device To manufacture this semiconductor device, the steps shown in FIGS. 1 and 2 are performed, and as shown in FIG. 9, sputtering is performed on each of the third insulating film 16 and the third conductor plug 17. Then, the conductive film 21 is formed.
  • a first titanium nitride film 21a, a copper-containing aluminum film 21b, and a second titanium nitride film 21c are formed in this order from the bottom.
  • a titanium film may be formed by sputtering before forming these films in order to improve the adhesion of the first titanium nitride film 21a and the second titanium nitride film 21c.
  • the film thickness of the conductive film 21 is not particularly limited, but in this embodiment, the first titanium nitride film 21a is formed to a thickness of 50 nm to 100 nm, and the copper-containing aluminum film 21b is formed to a thickness of about 100 nm to 200 nm. .
  • the second titanium nitride film 21c is formed to a thickness of about 100 nm to 200 nm, which is the same as the copper-containing aluminum film 21b.
  • a photoresist is applied on the conductive film 21, and it is exposed and developed to form a resist film 22.
  • the conductive film 21 is dry-etched using the resist film 22 as a mask to form a plurality of pixel electrodes 21p at intervals.
  • a gas used in the dry etching for example, there is a mixed gas of chlorine gas and oxygen gas.
  • a silicon oxide film is formed as the fourth insulating film 25 on the pixel electrode 21p and on the third insulating film 16 between the adjacent pixel electrodes 21p.
  • a silicon oxide film having a thickness of 700 nm to 1000 nm formed by a CVD method using TEOS gas is employed as the fourth insulating film 25.
  • the fourth insulating film 25 may be formed by HDPCVD using silane gas.
  • the lower side of the fourth insulating film 25 may be formed first using TEOS gas, and the upper side of the fourth insulating film 25 may be formed thereon by HDPCVD using silane gas.
  • the fourth insulating film 25 is formed to fill a gap between the adjacent pixel electrodes 21p, and the fourth insulating film 25 on the pixel electrodes 21p is unnecessary.
  • the thickness of the fourth insulating film 25 is reduced by polishing by the CMP method.
  • the polishing is stopped before the upper surface 21x of the pixel electrode 21p appears in this step, and the upper surface 21x.
  • the fourth insulating film 25 is left on the surface.
  • This etching is performed by dry etching using a mixed gas of CF 4 gas, argon gas, and oxygen gas as an etching gas, and the entire surface of the fourth insulating film 25 is exposed to the etching gas.
  • over-etching is performed so as not to leave a residue of the fourth insulating film 25 on the pixel electrode 21p.
  • the etching rate of the fourth insulating film 25 with respect to the etching gas is higher than that of the pixel electrode 21p. Is also fast. Therefore, as described with reference to FIG. 6, in this embodiment, the upper surface 25x of the fourth insulating film 25 is lower than the upper surface 21x of the pixel electrode 21p by this over-etching.
  • the upper surfaces 21x and 25x of the pixel electrode 21p and the fourth insulating film 25 are exposed to an etching gas, whereby the height of the upper surface 21x of the pixel electrode 21p is set to the fourth insulating film 25. Lower than the height of the upper surface 25x.
  • etching gas a gas that makes the etching rate of the pixel electrode 21p faster than that of the fourth insulating film 25 is used.
  • a gas for example, there is a mixed gas of a chlorine-based gas obtained by mixing a chlorine (Cl 2 ) gas and a boron trichloride (BCl 3 ) gas and oxygen (O 2 ).
  • the second titanium nitride film 21c as the uppermost layer of the pixel electrode 21p is completely removed by this etching, the surface of the copper-containing aluminum film 21b that is easily oxidized is oxidized and the reflectance of the surface is lowered. End up.
  • the etching is stopped at a depth in the middle of the second titanium nitride film 21c to leave the second titanium nitride film 21c on the copper-containing aluminum film 21b, and the reflectance of the pixel electrode 21p is increased. Prevent it from dropping.
  • the etching is performed at a depth in the middle of the second titanium nitride film 21c by controlling the etching time. It is easy to stop.
  • the basic structure of the semiconductor device 50 for the organic EL display is completed through the steps so far.
  • an organic layer 33 having a two-layer structure is formed on each of the pixel electrode 21p and the fourth insulating film 25 by performing the same process as described in FIG.
  • the organic layer 33 is formed by laminating the hole transport layer 31 made of ⁇ -NPD as a material and the light emitting layer 32 made of Alq3 in this order, and the light emitting layer 32 is an electron transport layer. It also serves as a function.
  • the thickness of the organic layer 33 is not particularly limited, and the hole transport layer 31 can be formed to a thickness of about 50 nm, and the light emitting layer 32 can be formed to a thickness of about 50 nm.
  • the upper surface 25x of the fourth insulating film 25 is positioned higher than the upper surface 21x of the pixel electrode 21p. Therefore, the hole transport layer 31 is deposited thick on the shoulder 21s of the pixel electrode 21p, and the film thickness T of the hole transport layer 31 on the shoulder 21s can be increased.
  • an ITO film is formed as a transparent electrode film 34 on the organic layer 33 by a vapor deposition method, and a transparent glass substrate 35 is further stuck thereon.
  • the transparent electrode film 34 is not limited to the ITO film, and an IZO (Indium Zinc Oxide) film may be formed as the transparent electrode film 34.
  • the organic EL display unit 40 including the organic layer 33, the transparent electrode film 34, and the transparent glass substrate 35 is formed in the semiconductor device 50.
  • FIG. 17 is a cross-sectional view of the semiconductor device 50 including the transistor TR.
  • a predetermined image is displayed on the organic EL display unit 40 by applying a predetermined voltage to the pixel electrode 21p by using the transistor TR as a switch while using the transparent electrode film 34 as a cathode.
  • the shoulder portion of the pixel electrode 21p is increased.
  • the electric field E concentrates on the shoulder 21s of the pixel electrode 21p due to the voltage applied under actual use, and the current density of the current flowing through the shoulder 21s is increased by the electric field E, the electric field E is thickly deposited on the shoulder 21s.
  • the hole transport layer 31 can withstand a high current density.
  • the entire upper surface 21x of the pixel electrode 21p is exposed by the etching of FIG. 13, the light L (see FIG. 17) generated by the light emitting layer 32 is reflected by the entire upper surface 21x, and the organic EL display unit The luminance of 40 can also be improved.
  • the reliability of the semiconductor device is further improved by adding a process to the first embodiment.
  • 18 to 20 are enlarged cross-sectional views of the semiconductor device according to the present embodiment during manufacture. 18 to 20, the same elements as those described in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and the description thereof is omitted below.
  • the upper surface 21x of the pixel electrode 21p is replaced with the upper surface of the fourth insulating film 25 as shown in FIG.
  • a semiconductor device 50 having a structure lower than 25x is obtained.
  • the corners of the fourth insulating film 25 are cut by exposing each of the pixel electrode 21p and the fourth insulating film 25 to an etching atmosphere.
  • the fourth insulating film 25 has a side surface 25y at a position higher than the upper surface 21x of the pixel electrode 21p, and the side surface 25y is inclined by the etching in this step so that the upper surface 25x of the fourth insulating film 25
  • the internal angle ⁇ between the side surface 25y becomes an obtuse angle.
  • the etching gas used in the dry etching is not particularly limited as long as it has an action of etching the fourth insulating film 25.
  • an etching gas that makes the etching rate of the pixel electrode 21p slower than that of the fourth insulating film 25.
  • an etching gas for example, there is a mixed gas of CF 4 gas, argon gas, and oxygen gas.
  • the organic EL display unit 40 is formed in the semiconductor device 50 as shown in FIG.
  • the hole transport layer 31 is formed in the organic EL portion 40.
  • the hole transport layer 31 is formed in the organic EL portion 40.
  • FIG. 21 is a cross-sectional view of the semiconductor device 50 including the transistor TR.
  • the interval S between the side surface 25y of the fourth insulating film 25 and the hole transport layer 31 is widened as shown in FIG.
  • Some electric fields E concentrated on the shoulder 21s of the pixel electrode 21p face the direction along the side surface 25y, and the current I flows in the direction along the side surface 25y in the plane of the hole transport layer 31 due to the electric field E.
  • the current density does not increase excessively in the hole transport layer 31 on the side of the side surface 25y by widening the interval S in this embodiment, and the hole transport layer 31 is generated by the current. It can be suppressed from being destroyed.
  • the reliability of the semiconductor device is improved by a method different from that in the first embodiment or the second embodiment.
  • 22 to 25 are enlarged cross-sectional views of the semiconductor device according to the present embodiment during manufacture. 22 to 25, the same elements as those described in the first embodiment and the second embodiment are denoted by the same reference numerals as those in these embodiments, and the description thereof is omitted below.
  • sputtering is performed on each of the third insulating film 16 and the third conductor plug 17 in the same manner as in FIG. 9 of the first embodiment.
  • the conductive film 21 is formed by the method.
  • the second titanium nitride film 21c is formed to be as thick as the copper-containing aluminum film 21b, but in this embodiment, the second titanium nitride film 21c is formed thinner than the first embodiment. May be.
  • the second titanium nitride film 21c is formed to a thickness of about 50 nm to 100 nm, which is the same as that of the first titanium nitride film 21a.
  • the film thickness of the copper-containing aluminum film 21b is about 100 nm to 200 nm.
  • a photoresist is applied on the conductive film 21, and it is exposed and developed to form a resist film 22.
  • the conductive film 21 is dry-etched using the resist film 22 as a mask, thereby forming a plurality of pixel electrodes 21p having inclined side surfaces 21y at intervals.
  • a mixed gas of chlorine (Cl 2 ) gas, boron trichloride (BCl 3 ) gas, and oxygen (O 2 ) gas can be used as an etching gas.
  • the etching conditions for inclining the side surface 21y are not particularly limited. However, by adopting an etching condition in which a large amount of aluminum oxidation product generated from the conductive film 21 during etching adheres to the lower portion of the side surface 21y, the lower portion of the side surface 21y is protected by the oxidation product, and the upper portion of the side surface 21y. Is preferably etched. Examples of such etching conditions include a condition in which the flow rate of the oxygen gas is set higher than the flow rate of a chlorine-based gas that is a mixed gas of chlorine gas and boron trichloride gas.
  • the side surface 21y may be inclined by adjusting the flow rate ratio of the above chlorine gas and boron trichloride gas. Further, the side surface 21y may be inclined by inclining the side surface of the resist film 22 in advance.
  • the angle ⁇ of the shoulder portion 21s defined as the angle between the upper surface 21x and the side surface 21y of the pixel electrode 21p becomes an obtuse angle, as shown in the circle of FIG.
  • the organic EL display section 40 is formed in the semiconductor device 60 as shown in FIG. 25 by performing the steps of FIGS. 15 to 16 described in the first embodiment.
  • the hole transport layer 31 is formed in the organic EL portion 40. Since the angle ⁇ of the shoulder portion 21s of the pixel electrode 21p is made obtuse as described above, the hole transport layer 31 is deposited thickly around the shoulder portion 21s. To do. As a result, compared to the case where the angle ⁇ is 90 ° or less, the film thickness T of the hole transport layer 31 at the shoulder 21s can be increased in the present embodiment.
  • the organic layer 33 includes a first bottom surface 33x located on the upper surface 21x of the pixel electrode 21p, and a second bottom surface 33y located on the side surface 21y of the pixel electrode 21p and continuing to the first bottom surface 33x.
  • the outer angle ⁇ between the bottom surfaces 33x and 33y is an obtuse angle.
  • FIG. 26 is a cross-sectional view of the semiconductor device 60 including the transistor TR.
  • the film thickness T of the hole transport layer 31 is increased in the shoulder portion 21s. To do.
  • the hole transport layer 31 deposited thickly on the shoulder portion 21s can withstand a high current density, The reliability of the semiconductor device 60 can be improved.
  • the reliability of the semiconductor device is improved by a method different from the first to third embodiments.
  • FIG. 27 to 30 are enlarged cross-sectional views of the semiconductor device according to this embodiment in the middle of manufacture.
  • the same elements as those described in the first to third embodiments are denoted by the same reference numerals as those in these embodiments, and the description thereof is omitted below.
  • a silicon oxide film having a thickness of 500 nm to 1000 nm is formed on each of the pixel electrode 21p and the fourth insulating film 25 by plasma CVD using silane gas as a film forming gas.
  • the silicon oxide film is used as a fifth insulating film 37.
  • the fifth insulating film 37 is not limited to the silicon oxide film, and an insulating film having an etching rate faster than that of the pixel electrode 21p can be formed as the fifth insulating film 37.
  • Examples of such an insulating film include a silicon nitride film and a silicon oxynitride film in addition to a silicon oxide film.
  • the fifth insulating film 37 is etched back to remove the fifth insulating film 37 from the upper surface 21x of the pixel electrode 21p, and the fifth insulating film 37 is formed on the side surface 21y of the pixel electrode 21p.
  • the insulating film 37 is left as a sidewall 37a.
  • the etch back can be performed, for example, by anisotropically etching the fifth insulating film 37 by dry etching using a mixed gas of CF 4 gas, argon gas, and oxygen gas as an etching gas.
  • the basic structure of the semiconductor device 70 for an organic EL display is obtained through the steps so far.
  • the organic EL display section 40 is formed in the semiconductor device 70 as shown in FIG.
  • the hole transport layer 31 included in the organic EL portion 40 is deposited along the gently inclined surface 37b of the sidewall 37a, and therefore the film thickness T at the shoulder portion 21s of the pixel electrode 21p is set. It can be thick enough.
  • the organic layer 33 has a first bottom surface 33x on the pixel electrode 21p and a second bottom surface 33y located on the sidewall 37a and continuing to the first bottom surface 33x. These bottom surfaces 33x,
  • the outer angle ⁇ between 33y is an obtuse angle.
  • FIG. 31 is a cross-sectional view of the semiconductor device 70 including the transistor TR.
  • the film of the hole transport layer 31 on the shoulder portion 21s of the pixel electrode 21p is formed by forming the sidewall 37a beside the pixel electrode 21p. Increase the thickness T.
  • the hole transport layer 31 having a sufficiently thick film thickness T can withstand the current.
  • the film thickness T is thus thick, the current density of the current I flowing in the in-plane direction through the hole transport layer 31 due to the electric field E does not increase excessively, and the hole transport layer 31 is destroyed by the current I. Can be suppressed.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

Cette invention concerne un dispositif à semi-conducteur et son procédé de fabrication conçus pour améliorer la fiabilité du dispositif à semi-conducteur. Ledit dispositif à semi-conducteur comprend : un substrat semi-conducteur (1), un premier film isolant (16) formé sur le substrat semi-conducteur (1), une pluralité d'électrodes de pixel (21p) formées par intervalles sur le premier film isolant (16), et un second film isolant (25) formé sur le premier film isolant (16) entre électrodes de pixel adjacentes (21p), la surface supérieure (25x) du second film isolant (25) étant plus élevée que les surfaces supérieures (21x) des électrodes de pixel (21p) et toutes les surfaces supérieures (21x) des électrodes de pixel (21p) étant exposées.
PCT/JP2013/059586 2013-03-29 2013-03-29 Dispositif à semi-conducteur et son procédé de fabrication WO2014155691A1 (fr)

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US20210091329A1 (en) * 2019-09-23 2021-03-25 Taiwan Semiconductor Manufacturing Co., Ltd. Display device and method of fabricating the same

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