WO2014153768A1 - 一种液晶显示装置及其驱动方法 - Google Patents

一种液晶显示装置及其驱动方法 Download PDF

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Publication number
WO2014153768A1
WO2014153768A1 PCT/CN2013/073421 CN2013073421W WO2014153768A1 WO 2014153768 A1 WO2014153768 A1 WO 2014153768A1 CN 2013073421 W CN2013073421 W CN 2013073421W WO 2014153768 A1 WO2014153768 A1 WO 2014153768A1
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Prior art keywords
mos transistor
type mos
scan
driving signal
resistor
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PCT/CN2013/073421
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English (en)
French (fr)
Inventor
韩丙
朱江
罗时勲
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US13/878,563 priority Critical patent/US9159289B2/en
Publication of WO2014153768A1 publication Critical patent/WO2014153768A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a liquid crystal display device and a driving method thereof.
  • FIG. 1 is a waveform diagram of a scan driving signal and a data driving signal input to a pixel unit of the same row in the prior art.
  • the thin film transistor liquid crystal display device Thin Film Transistor-Liquid Crystal In the display (TFT-LCD)
  • the scan line is used to transmit the scan drive signal Gate into the thin film transistor to open the thin film transistor
  • the data line is used to transmit the data drive signal Data to the pixel unit Pix when the thin film transistor is turned on, to the pixel unit
  • the Pix is charged to control the display of the pixel unit Pix.
  • the pixel unit Pix displays colors R (red, Red), G (green, Green), and B (blue, blue), respectively.
  • the scan drive signal Gate causes a delay phenomenon when changing from a low potential to a high potential due to the influence of resistance and capacitance.
  • the waveform of the post-input scan drive signal Gate is more perfect than the waveform of the previous input scan drive signal Gate, resulting in the waveform of the data signal Data input to the pixel unit Pix of the color R as shown in FIG.
  • the waveform of the data signal Data that is input to the pixel unit Pix of the color G is perfect, so the voltage of the pixel unit Pix input to the color R is higher. Therefore, the color R and the color G are unevenly displayed under the color mixing screen, and the color R is prominent, which seriously affects the display quality of the TFT-LCD.
  • the technical problem to be solved by the present invention is to provide a liquid crystal display device and a driving method thereof, which can reduce the voltage difference transmitted to the pixel electrode and eliminate the color shift phenomenon, thereby improving the display quality of the liquid crystal display device.
  • a technical solution adopted by the present invention is to provide a liquid crystal display device including: a pixel unit including a thin film transistor and a pixel electrode, the thin film transistor including a gate, a source and a drain; a pixel electrode connected to the drain; a scan driver for generating a scan driving signal; a chamfering circuit connected to the scan driver, the chamfering circuit chamfering a rising edge of the scan driving signal; a scan line, a scan line connecting the gate, for Transmitting the scan driving signal to the gate, thereby controlling the conduction of the thin film transistor; the data line and the data line are connected to the source to transmit the data driving signal to the pixel electrode through the source when the thin film transistor is turned on; The rising edge of the scanning drive signal after the corner is at least inclined to a first inclined portion.
  • the first inclined portion is inclined from the first level to a high level of the scan driving signal, and the first level is between a high level of the scan driving signal and a low level of the scan driving signal.
  • the chamfering circuit further chamfers the falling edge of the scan driving signal.
  • the falling edge of the scan driving signal after the chamfering is inclined at least into a second inclined portion.
  • the second inclined portion is inclined from the second level to a low level of the scan driving signal, and the second level is between a high level of the scan driving signal and a low level of the scan driving signal.
  • the chamfering circuit includes a first N-type MOS transistor, a second N-type MOS transistor, a P-type MOS transistor, a first resistor, a second resistor, a third resistor, an RC circuit, and a first capacitor, wherein the first N-type
  • the gate of the MOS transistor receives the scan driving signal, the source of the first N-type MOS transistor is grounded, and the drain of the first N-type MOS transistor is connected to the source of the P-type MOS transistor via the first resistor and the second resistor, and receives the reference The voltage signal, the gate of the P-type MOS transistor is connected between the first resistor and the second resistor, the drain of the P-type MOS transistor is connected to the scan line, the source of the second N-type MOS transistor is grounded, and the second N-type MOS transistor The gate is connected to the inverted signal of the scan driving signal, the drain of the second N-type MOS transistor is connected to the drain of the P-type MOS transistor via the third resistor
  • the RC circuit includes a second capacitor and a fourth resistor disposed in series, and controls a voltage span of the first inclined portion by a resistance value of the fourth resistor, and a time span of the first inclined portion by a capacitance value of the second capacitor.
  • a liquid crystal display device including: a pixel unit; a data line for transmitting a data driving signal to the pixel unit; and a scan driver for Generating a scan driving signal; a chamfering circuit connected to the scan driver, the chamfering circuit chamfering a rising edge of the scan driving signal; and a scan line for transmitting the chamfered scan driving signal to the pixel unit.
  • the pixel unit comprises a thin film transistor and a pixel electrode
  • the thin film transistor comprises a gate, a source and a drain
  • the pixel electrode is connected to the drain
  • the scan line is connected to the gate to transmit the chamfered scan driving signal to the gate
  • the control thin film transistor is turned on, and the data line is connected to the source to transmit a data driving signal to the pixel electrode through the source when the thin film transistor is turned on.
  • the rising edge of the scan driving signal after the chamfering is at least inclined to a first inclined portion.
  • the first inclined portion is inclined from the first level to a high level of the scan driving signal, and the first level is between a high level of the scan driving signal and a low level of the scan driving signal.
  • the chamfering circuit further chamfers the falling edge of the scan driving signal.
  • the falling edge of the scan driving signal after the chamfering is inclined at least into a second inclined portion.
  • the second inclined portion is inclined from the second level to a low level of the scan driving signal, and the second level is between a high level of the scan driving signal and a low level of the scan driving signal.
  • the chamfering circuit includes a first N-type MOS transistor, a second N-type MOS transistor, a P-type MOS transistor, a first resistor, a second resistor, a third resistor, an RC circuit, and a first capacitor, wherein the first N-type
  • the gate of the MOS transistor receives the scan driving signal, the source of the first N-type MOS transistor is grounded, and the drain of the first N-type MOS transistor is connected to the source of the P-type MOS transistor via the first resistor and the second resistor, and receives the reference The voltage signal, the gate of the P-type MOS transistor is connected between the first resistor and the second resistor, the drain of the P-type MOS transistor is connected to the scan line, the source of the second N-type MOS transistor is grounded, and the second N-type MOS transistor The gate is connected to the inverted signal of the scan driving signal, the drain of the second N-type MOS transistor is connected to the drain of the P-type MOS transistor via the third resistor
  • the RC circuit includes a second capacitor and a fourth resistor disposed in series, and controls a voltage span of the first inclined portion by a resistance value of the fourth resistor, and a time span of the first inclined portion by a capacitance value of the second capacitor.
  • another technical solution adopted by the present invention is to provide a driving method of a liquid crystal display device, the driving method comprising: providing a scan driving signal; chamfering a rising edge of the scan driving signal; The subsequent scan drive signal is transmitted to the scan line.
  • the invention has the beneficial effects that the liquid crystal display device of the present invention discriminates the rising edge of the scan driving signal by using the chamfering circuit, and then transmits the scan driving signal after the chamfering by using the scanning line, different from the prior art.
  • the pixel unit so that the voltages of the data driving signals input into each pixel unit are similar or equal, ensuring that the brightness of the color displayed by each pixel unit is similar or the same, thereby reducing the color shift phenomenon and improving the display of the display device. quality.
  • 1 is a waveform diagram of a scan driving signal and a data driving signal input to a pixel unit of the same row in the prior art
  • FIG. 2 is a schematic structural view of a liquid crystal display device according to a first embodiment of the present invention
  • Figure 3 is a circuit diagram of a chamfering circuit of the present invention.
  • Figure 4 is a waveform diagram of signals received and output by the chamfering circuit of the present invention.
  • Figure 5 is a waveform diagram of a scan driving signal after chamfering according to the present invention.
  • Fig. 6 is a flow chart showing a driving method of a liquid crystal display device according to a second embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a liquid crystal display device according to a first embodiment of the present invention.
  • the liquid crystal display device 20 of the present invention includes a plurality of pixel units 21, a scan driver 22, a chamfering circuit 23, a data driver 24, a plurality of scanning lines A, and a plurality of data lines C.
  • the data driver 24 is used to generate a data driving signal.
  • the data line C is connected to the data driver 24 for transmitting the data driving signal to the pixel unit 21.
  • Scan driver 22 is used to generate a scan drive signal.
  • the chamfering circuit 23 is connected to the scan driver 22, and the chamfering circuit 23 chamfers the rising edge of the scan driving signal.
  • the scanning line A is connected to the chamfering circuit 23 for transmitting the chamfered scanning drive signal to the pixel unit 21.
  • the chamfering circuit 23 of the present embodiment further chamfers the falling edge of the scan driving signal.
  • the pixel unit 21 includes a thin film transistor T and a pixel electrode P
  • the thin film transistor T includes a gate G0, a source S0, and a drain D0.
  • the pixel electrode P is connected to the drain D0
  • the scan line A is connected to the gate G0 to transmit the chamfered scan driving signal to the gate G0, thereby controlling the thin film transistor T to be turned on
  • the data line C is connected to the source S0.
  • the thin film transistor T is turned on, the data driving signal is transmitted to the pixel electrode P via the source S0.
  • the same scanning line A drives a plurality of pixel units 21, and the plurality of pixel units 21 respectively display colors G, R, and B as shown in FIG.
  • the scan line A transmits the scan driving signal
  • the thin film transistors T of the plurality of pixel units 21 driven by the same scan line A are turned on.
  • the plurality of data lines C simultaneously transmit the data drive signals to the corresponding pixel units 21.
  • the pixel electrode P is charged to the pixel unit 21 that displays different colors.
  • the scan driving signal is chamfered by the chamfering circuit 23, and the specific chamfering circuit 23 is as shown in FIG.
  • the chamfering circuit 23 of the present invention includes a first N-type MOS transistor 231, a second N-type MOS transistor 232, a P-type MOS transistor 233, a first resistor 234, a second resistor 235, and a third resistor 236.
  • the gate G1 of the first N-type MOS transistor 231 receives the scan driving signal GVOF, the source S1 of the first N-type MOS transistor 231 is grounded, and the drain D1 of the first N-type MOS transistor 231 passes through the first resistor 234 and the
  • the second resistor 235 is connected to the source S3 of the P-type MOS transistor 233 and receives the reference voltage signal VGHF.
  • the gate G3 of the P-type MOS transistor 233 is connected between the first resistor 234 and the second resistor 235.
  • the P-type MOS transistor 233 The drain D3 is connected to the scan line A, the source S2 of the second N-type MOS transistor 232 is grounded, the gate G2 of the second N-type MOS transistor 232 is connected to the inverted signal GVON of the scan driving signal, and the second N-type MOS transistor 232 is connected.
  • the drain D2 is connected to the drain D3 of the P-type MOS transistor 233 via the third resistor 236, and the first end of the RC circuit 237 and the first end of the first capacitor 238 are connected to the drain D3 and the third of the P-type MOS transistor 233. Between the connection node of the resistor 236 and the scan line A, the second end of the RC circuit 237 and the second end of the first capacitor 238 are grounded.
  • the Zener diode 239 is further included between the second N-type MOS transistor and the third resistor 236, and the anode of the Zener diode 239 is connected to the drain D2 of the second N-type MOS transistor 232, and the negative electrode and the third resistor 236 are connected. connection.
  • the RC circuit 237 includes a second capacitor 2371 and a fourth resistor 2372 arranged in series, and the first end of the second capacitor 2371 is connected to the connection node of the drain D3 and the third resistor 236 of the P-type MOS transistor 233 and the scan line A. The second end of the second capacitor 2371 is connected to the first end of the fourth resistor 2372, and the second end of the fourth resistor 2372 is grounded.
  • the scan driving signal GVOF when the scan driving signal GVOF is at a low level, the first N-type MOS transistor 231 is turned off, the voltage of the gate G3 of the P-type MOS transistor 233 is equal to the voltage of the source S3, and the P-type MOS transistor 233 is turned off.
  • the inverted signal GVON of the scan driving signal is at a high level, the second N-type MOS transistor 232 is turned on, the anode of the Zener diode 239 is grounded, and the falling edge of the scan driving signal VGH of the scanning line A is chamfered. deal with.
  • the scan driving signal GVOF When the scan driving signal GVOF is at a high level, the first N-type MOS transistor 231 is turned on, the gate G3 of the P-type MOS transistor 233 is at a low level, is smaller than the voltage of the source S3, and the P-type MOS transistor 233 is turned on, and the reference is made.
  • the voltage signal VGHF is transmitted to the scanning line A, and at this time, the rising edge of the scanning driving signal VGH is subjected to chamfering processing by the RC circuit 237.
  • the inverted signal GVON of the scan driving signal is at a low level
  • the second N-type MOS transistor 232 is turned off
  • the circuit of the Zener diode 239 is turned off
  • the scanning drive signal VGH of the scanning line A is not subjected to chamfering processing.
  • FIG. 4 is a waveform diagram of signals received and outputted by the chamfering circuit 23 of the present invention.
  • the original scan driving signal GVOF generated by the scan driver 22 passes through the chamfering circuit 23 to obtain the chamfered scan driving signal VGH.
  • both the rising edge and the falling edge of the chamfered scanning drive signal VGH are inclined at least into an inclined portion.
  • both the rising edge and the falling edge are inclined into an arc-shaped inclined portion.
  • the rising and falling edges of the chamfered scan drive signal VGH may also be inclined into a linear inclined portion, as shown in FIG.
  • the rising edge of the scan driving signal VGH after the chamfering is inclined to the first inclined portion 501.
  • the first inclined portion 501 is inclined from the first level to the high level of the scan driving signal VGH after the chamfering, and the first level is located at the high level of the scan driving signal VGH after the chamfering and the scanning drive after the chamfering
  • the signal is low between VGH.
  • the voltage span of the first inclined portion 501 is controlled by the resistance value of the fourth resistor 2372
  • the time span of the first inclined portion 501 is controlled by the capacitance value of the second capacitor 2371.
  • the larger the resistance value of the fourth resistor 2372 is, the smaller the voltage span of the first inclined portion 501 is.
  • the larger the capacitance value of the second capacitor 2371 is, the larger the time span of the first inclined portion 501 is, that is, the time of the chamfering The longer it is.
  • the falling edge of the scan drive signal VGH after the chamfer is inclined to the second inclined portion 502.
  • the second inclined portion 502 is tilted from the second level to the low level of the scan drive signal VGH after the chamfer, and the second level is located at the high level of the scan drive signal VGH after the chamfer and the scan drive after the chamfering
  • the signal is low between VGH.
  • This embodiment controls the lowest point of the voltage span of the second inclined portion 502 by the circuit of the Zener diode 239.
  • the chamfering circuit 23 only chamfers the rising edge and the falling edge of the scanning driving signal GVOF, and therefore, the high level and the low level of the scanning driving signal VGH after the chamfering are respectively higher than the scanning driving signal GVOF.
  • the level is equal to the low level.
  • the waveforms of the rising edges of the scan driving signals VGH after each chamfer are similar or identical, so that the time for opening each thin film transistor T is close or equal, so that the voltage of the pixel electrode P charged in each pixel unit 21 is made. Similar or equal, therefore, it is ensured that the brightness of the color displayed by each pixel unit 21 is similar or the same, thereby reducing the color shift phenomenon and improving the display quality of the display device.
  • FIG. 6 is a flowchart of a driving method of a liquid crystal display device according to a second embodiment of the present invention. As shown in FIG. 6, the driving method of the present invention includes:
  • Step S61 providing a scan driving signal
  • Step S62 chamfering the rising edge of the scan driving signal
  • step S62 in order to eliminate the influence of horizontal lines between two adjacent pixel units, the present invention further performs chamfering of the falling edge of the scan driving signal.
  • Step S63 transmitting the chamfered scan driving signal to the scan line.
  • step S63 the scan line transmits the chamfered scan drive signal to the gate of the thin film transistor to turn on the thin film transistor.
  • the data line transmits the data driving signal to the source of the thin film transistor, and is further transported to the pixel electrode through the source of the thin film transistor, and the pixel electrode performs color display according to the received data driving signal. Since the present invention chamfers the rising edge of the scan driving signal, the time for opening each of the thin film transistors is similar or equal, so that the voltages of the pixel electrodes charged in each pixel unit are similar or equal, thus ensuring that each The brightness of the colors displayed by the pixel units is similar or the same, thereby reducing the color shift phenomenon and improving the display quality of the display device.

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  • Crystallography & Structural Chemistry (AREA)
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  • Computer Hardware Design (AREA)
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Abstract

公开了一种液晶显示装置（20）及其驱动方法。该液晶显示装置（20）包括：像素单元（21）；数据线（C），用于传输数据驱动信号至像素单元（21）；扫描驱动器（22），用于产生扫描驱动信号；削角电路（23），与扫描驱动器（22）连接，削角电路（23）对扫描驱动信号的上升沿进行削角；扫描线（A），用于将削角后的扫描驱动信号传输至像素单元（21）。上述方式能够降低传输到像素电极的电压差异，消除色偏现象，从而提高液晶显示装置的显示品质。

Description

一种液晶显示装置及其驱动方法
【技术领域】
本发明涉及显示技术领域，特别是涉及一种液晶显示装置及其驱动方法。
【背景技术】
请参阅图1，图1是现有技术中输入同一行像素单元的扫描驱动信号和数据驱动信号的波形图。如图1所示，在薄膜晶体管液晶显示装置（Thin Film Transistor-Liquid Crystal Display，TFT-LCD）中，扫描线用于传输扫描驱动信号Gate到薄膜晶体管中，以打开薄膜晶体管，数据线用于在薄膜晶体管打开时传输数据驱动信号Data到像素单元Pix，以向像素单元Pix充电，从而控制像素单元Pix的显示。其中，像素单元Pix分别显示颜色R（红色，Red）、G（绿色，Green）以及B（蓝色，Blue）。
现有技术的液晶显示装置中，扫描驱动信号Gate由于电阻和电容的影响，使得由低电位变化到高电位时产生延迟现象。如图1所示，后输入的扫描驱动信号Gate的波形较前一个输入的扫描驱动信号Gate的波形完美，从而导致如图1所示的输入到颜色R的像素单元Pix的数据信号Data的波形较输入到颜色G的像素单元Pix的数据信号Data的波形完美，故输入到颜色R的像素单元Pix的电压较高。因此，导致在混色画面下颜色R和颜色G显示不均匀，其中，颜色R会凸显的现象，严重影响TFT-LCD的显示品质。
【发明内容】
本发明主要解决的技术问题是提供一种液晶显示装置及其驱动方法，能够降低传输到像素电极的电压差异，消除色偏现象，从而提高液晶显示装置的显示品质。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种液晶显示装置，该液晶显示装置包括：像素单元，包括薄膜晶体管和像素电极，薄膜晶体管包括栅极、源极和漏极，像素电极连接漏极；扫描驱动器，用于产生扫描驱动信号；削角电路，与扫描驱动器连接，削角电路对扫描驱动信号的上升沿进行削角；扫描线，扫描线连接栅极，用于将削角后的扫描驱动信号传输至栅极，进而控制薄膜晶体管导通；数据线，数据线连接源极，以在薄膜晶体管导通时经源极传输数据驱动信号至像素电极；其中，削角后的扫描驱动信号的上升沿至少倾斜成一第一倾斜部。
其中，第一倾斜部从第一电平倾斜上升至扫描驱动信号的高电平，第一电平位于扫描驱动信号的高电平和扫描驱动信号的低电平之间。
其中，削角电路进一步对扫描驱动信号的下降沿进行削角。
其中，削角后的扫描驱动信号的下降沿至少倾斜成一第二倾斜部。
其中，第二倾斜部从第二电平倾斜下降至扫描驱动信号的低电平，第二电平位于扫描驱动信号的高电平和扫描驱动信号的低电平之间。
其中，削角电路包括第一N型MOS管、第二N型MOS管、P型MOS管、第一电阻、第二电阻、第三电阻、RC电路以及第一电容，其中，第一N型MOS管的栅极接收扫描驱动信号，第一N型MOS管的源极接地，第一N型MOS管的漏极经第一电阻和第二电阻连接P型MOS管的源极，并接收基准电压信号，P型MOS管的栅极连接于第一电阻和第二电阻之间，P型MOS管的漏极连接扫描线，第二N型MOS管的源极接地，第二N型MOS管的栅极连接扫描驱动信号的反相信号，第二N型MOS管的漏极经第三电阻连接至P型MOS管的漏极，RC电路的第一端和第一电容的第一端连接于P型MOS管的漏极与第三电阻的连接节点与扫描线之间，RC电路的第二端和第一电容的第二端接地。
其中，RC电路包括串联设置第二电容和第四电阻，并通过第四电阻的电阻值控制第一倾斜部的电压跨度，通过第二电容的电容值控制第一倾斜部的时间跨度。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种液晶显示装置，该液晶显示装置包括：像素单元；数据线，用于传输数据驱动信号至像素单元；扫描驱动器，用于产生扫描驱动信号；削角电路，与扫描驱动器连接，削角电路对扫描驱动信号的上升沿进行削角；扫描线，用于将削角后的扫描驱动信号传输至像素单元。
其中，像素单元包括薄膜晶体管和像素电极，薄膜晶体管包括栅极、源极和漏极，像素电极连接漏极，扫描线连接栅极，以将削角后的扫描驱动信号传输至栅极，进而控制薄膜晶体管导通，数据线连接源极，以在薄膜晶体管导通时经源极传输数据驱动信号至像素电极。
其中，削角后的扫描驱动信号的上升沿至少倾斜成一第一倾斜部。
其中，第一倾斜部从第一电平倾斜上升至扫描驱动信号的高电平，第一电平位于扫描驱动信号的高电平和扫描驱动信号的低电平之间。
其中，削角电路进一步对扫描驱动信号的下降沿进行削角。
其中，削角后的扫描驱动信号的下降沿至少倾斜成一第二倾斜部。
其中，第二倾斜部从第二电平倾斜下降至扫描驱动信号的低电平，第二电平位于扫描驱动信号的高电平和扫描驱动信号的低电平之间。
其中，削角电路包括第一N型MOS管、第二N型MOS管、P型MOS管、第一电阻、第二电阻、第三电阻、RC电路以及第一电容，其中，第一N型MOS管的栅极接收扫描驱动信号，第一N型MOS管的源极接地，第一N型MOS管的漏极经第一电阻和第二电阻连接P型MOS管的源极，并接收基准电压信号，P型MOS管的栅极连接于第一电阻和第二电阻之间，P型MOS管的漏极连接扫描线，第二N型MOS管的源极接地，第二N型MOS管的栅极连接扫描驱动信号的反相信号，第二N型MOS管的漏极经第三电阻连接至P型MOS管的漏极，RC电路的第一端和第一电容的第一端连接于P型MOS管的漏极与第三电阻的连接节点与扫描线之间，RC电路的第二端和第一电容的第二端接地。
其中，RC电路包括串联设置第二电容和第四电阻，并通过第四电阻的电阻值控制第一倾斜部的电压跨度，通过第二电容的电容值控制第一倾斜部的时间跨度。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种液晶显示装置的驱动方法，该驱动方法包括：提供扫描驱动信号；对扫描驱动信号的上升沿进行削角；将削角后的扫描驱动信号传输至扫描线。
本发明的有益效果是：区别于现有技术的情况，本发明的液晶显示装置通过用削角电路对扫描驱动信号的上升沿进行削角，然后利用扫描线将削角后的扫描驱动信号传输至像素单元，使得输入每个像素单元中的数据驱动信号的电压相近或相等，保证了每个像素单元显示的颜色的亮度相近或相同，从而减小了色偏现象，提高了显示装置的显示品质。
【附图说明】
图1是现有技术中输入同一行像素单元的扫描驱动信号和数据驱动信号的波形图；
图2是本发明第一实施例的一种液晶显示装置的结构示意图；
图3是本发明的削角电路的电路图；
图4是本发明的削角电路接收和输出的信号的波形图；
图5是本发明的削角后的扫描驱动信号的波形图；
图6是本发明第二实施例的一种液晶显示装置的驱动方法的流程图。
【具体实施方式】
请参阅图2，图2是本发明第一实施例的一种液晶显示装置的结构示意图。如图2所示，本发明的液晶显示装置20包括多个像素单元21、扫描驱动器22、削角电路23、数据驱动器24、多条扫描线A以及多条数据线C。其中，数据驱动器24用于产生数据驱动信号。数据线C与数据驱动器24连接，用于传输该数据驱动信号至像素单元21。扫描驱动器22用于产生扫描驱动信号。削角电路23与扫描驱动器22连接，并且削角电路23对扫描驱动信号的上升沿进行削角。扫描线A连接削角电路23，用于将削角后的扫描驱动信号传输至像素单元21。
为了消除两个相邻的像素单元21之间水平线的影响，本实施例的削角电路23进一步对扫描驱动信号的下降沿进行削角。
具体而言，像素单元21包括薄膜晶体管T和像素电极P，薄膜晶体管T包括栅极G0、源极S0和漏极D0。其中，像素电极P连接漏极D0，扫描线A连接栅极G0，以将削角后的扫描驱动信号传输至栅极G0，进而控制薄膜晶体管T导通，数据线C连接源极S0，以在薄膜晶体管T导通时经源极S0传输数据驱动信号至像素电极P。
本实施例中，同一条扫描线A驱动多个像素单元21，并且该多个像素单元21分别显示如图2所示的颜色G、R以及B。在扫描线A传输扫描驱动信号时，同一条扫描线A驱动的多个像素单元21的薄膜晶体管T都打开，此时，多条数据线C同时传输数据驱动信号到相应的像素单元21中的像素电极P，以向显示不同颜色的像素单元21进行充电。本实施例中，由于液晶显示装置20中的电阻和电容的影响，使得扫描驱动器22产生的扫描驱动信号由低电位变化到高电位时产生延迟现象。因此本实施例采用削角电路23对扫描驱动信号进行削角，具体的削角电路23如图3所示。
请参阅图3，本发明的削角电路23包括第一N型MOS管231、第二N型MOS管232、P型MOS管233、第一电阻234、第二电阻235、第三电阻236、RC电路237以及第一电容238。其中，第一N型MOS管231的栅极G1接收扫描驱动信号GVOF，第一N型MOS管231的源极S1接地，第一N型MOS管231的漏极D1经第一电阻234和第二电阻235连接P型MOS管233的源极S3，并接收基准电压信号VGHF，P型MOS管233的栅极G3连接于第一电阻234和第二电阻235之间，P型MOS管233的漏极D3连接扫描线A，第二N型MOS管232的源极S2接地，第二N型MOS管232的栅极G2连接扫描驱动信号的反相信号GVON，第二N型MOS管232的漏极D2经第三电阻236连接至P型MOS管233的漏极D3，RC电路237的第一端和第一电容238的第一端连接于P型MOS管233的漏极D3与第三电阻236的连接节点与扫描线A之间，RC电路237的第二端和第一电容238的第二端接地。
其中，第二N型MOS管与第三电阻236之间还包括一稳压二极管239，并且稳压二极管239的正极与第二N型MOS管232的漏极D2连接，负极与第三电阻236连接。RC电路237包括串联设置的第二电容2371和第四电阻2372，并且第二电容2371的第一端连接于P型MOS管233的漏极D3与第三电阻236的连接节点与扫描线A之间，第二电容2371的第二端连接第四电阻2372的第一端，第四电阻2372的第二端接地。
以下对图3所示的削角电路23的工作原理进行详细说明：
在本实施例中，扫描驱动信号GVOF为低电平时，第一N型MOS管231截止，P型MOS管233的栅极G3的电压等于源极S3的电压，P型MOS管233截止。此时，扫描驱动信号的反相信号GVON为高电平，第二N型MOS管232导通，使稳压二极管239的正极接地，对扫描线A的扫描驱动信号VGH的下降沿进行削角处理。扫描驱动信号GVOF为高电平时，第一N型MOS管231导通，P型MOS管233的栅极G3为低电平，小于其源极S3的电压，P型MOS管233导通，基准电压信号VGHF传输至扫描线A，此时通过RC电路237，使扫描驱动信号VGH的上升沿进行削角处理。此时，扫描驱动信号的反相信号GVON为低电平，第二N型MOS管232截止，稳压二极管239的电路断开，对扫描线A的扫描驱动信号VGH不进行削角处理。
请一并参阅图4，图4是本发明削角电路23接收和输出的各信号的波形图。其中，扫描驱动器22产生的原始的扫描驱动信号GVOF经过削角电路23后得到削角后的扫描驱动信号VGH。本实施例中，削角后的扫描驱动信号VGH的上升沿和下降沿均至少倾斜成一倾斜部，如图4所示，上升沿和下降沿均倾斜成一弧线型的倾斜部。在其他实施例中，削角后的扫描驱动信号VGH的上升沿和下降沿也可倾斜成直线型的倾斜部，具体如图5所示。
请参阅图5，削角后的扫描驱动信号VGH的上升沿倾斜成第一倾斜部501。并且第一倾斜部501从第一电平倾斜上升至削角后的扫描驱动信号VGH的高电平，第一电平位于削角后的扫描驱动信号VGH的高电平和削角后的扫描驱动信号VGH的低电平之间。本实施例通过第四电阻2372的电阻值控制第一倾斜部501的电压跨度，并通过第二电容2371的电容值控制第一倾斜部501的时间跨度。具体的，第四电阻2372的电阻值越大，第一倾斜部501的电压跨度越小；第二电容2371的电容值越大，第一倾斜部501的时间跨度越大，即削角的时间越长。
同理，削角后的扫描驱动信号VGH的下降沿倾斜成第二倾斜部502。第二倾斜部502从第二电平倾斜下降至削角后的扫描驱动信号VGH的低电平，并且第二电平位于削角后的扫描驱动信号VGH的高电平和削角后的扫描驱动信号VGH的低电平之间。本实施例通过稳压二极管239的电路控制第二倾斜部502的电压跨度的最低点。
值得注意的是，削角电路23只对扫描驱动信号GVOF的上升沿和下降沿进行削角，因此，削角后的扫描驱动信号VGH的高电平和低电平分别与扫描驱动信号GVOF的高电平和低电平相等。
因此，每个削角之后的扫描驱动信号VGH的上升沿的波形相似或相同，使得打开每个薄膜晶体管T的时间相近或相等，从而使得充入每个像素单元21中的像素电极P的电压相近或相等，因此，保证了每个像素单元21显示的颜色的亮度相近或相同，从而减小了色偏现象，提高了显示装置的显示品质。
请参阅图6，图6是本发明第二实施例的一种液晶显示装置的驱动方法的流程图。如图6所示，本发明的驱动方法包括：
步骤S61：提供扫描驱动信号；
步骤S62：对扫描驱动信号的上升沿进行削角；
在步骤S62中，为了消除两个相邻的像素单元之间水平线的影响，本发明进一步对扫描驱动信号的下降沿进行削角。
具体的削角电路如前文所述，在这里不再赘述。
步骤S63：将削角后的扫描驱动信号传输至扫描线。
在步骤S63中，扫描线将削角后的扫描驱动信号传输到薄膜晶体管的栅极，以打开薄膜晶体管。在薄膜晶体管打开时，数据线将数据驱动信号传输到薄膜晶体管的源极，通过薄膜晶体管的源极进一步输送到像素电极，像素电极根据接收到的数据驱动信号进行颜色的显示。因为本发明对扫描驱动信号的上升沿进行了削角，使得打开每个薄膜晶体管的时间相近或相等，从而使得充入每个像素单元中的像素电极的电压相近或相等，因此，保证了每个像素单元显示的颜色的亮度相近或相同，从而减小了色偏现象，提高了显示装置的显示品质。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (17)

  1. 一种液晶显示装置，其中，所述液晶显示装置包括：
    像素单元，包括薄膜晶体管和像素电极，所述薄膜晶体管包括栅极、源极和漏极，所述像素电极连接所述漏极；
    扫描驱动器，用于产生扫描驱动信号；
    削角电路，与所述扫描驱动器连接，所述削角电路对所述扫描驱动信号的上升沿进行削角；
    扫描线，所述扫描线连接所述栅极，用于将削角后的所述扫描驱动信号传输至所述栅极，进而控制所述薄膜晶体管导通；
    数据线，所述数据线连接所述源极，以在所述薄膜晶体管导通时经所述源极传输数据驱动信号至所述像素电极；
    其中，削角后的所述扫描驱动信号的上升沿至少倾斜成一第一倾斜部。
  2. 根据权利要求1所述的液晶显示装置，其中，所述第一倾斜部从第一电平倾斜上升至所述扫描驱动信号的高电平，所述第一电平位于所述扫描驱动信号的高电平和所述扫描驱动信号的低电平之间。
  3. 根据权利要求2所述的液晶显示装置，其中，所述削角电路进一步对所述扫描驱动信号的下降沿进行削角。
  4. 根据权利要求3所述的液晶显示装置，其中，削角后的所述扫描驱动信号的下降沿至少倾斜成一第二倾斜部。
  5. 根据权利要求4所述的液晶显示装置，其中，所述第二倾斜部从第二电平倾斜下降至所述扫描驱动信号的低电平，所述第二电平位于所述扫描驱动信号的高电平和所述扫描驱动信号的低电平之间。
  6. 根据权利要求1所述的液晶显示装置，其中，所述削角电路包括第一N型MOS管、第二N型MOS管、P型MOS管、第一电阻、第二电阻、第三电阻、RC电路以及第一电容，其中，所述第一N型MOS管的栅极接收所述扫描驱动信号，所述第一N型MOS管的源极接地，所述第一N型MOS管的漏极经所述第一电阻和所述第二电阻连接所述P型MOS管的源极，并接收基准电压信号，所述P型MOS管的栅极连接于所述第一电阻和所述第二电阻之间，所述P型MOS管的漏极连接所述扫描线，所述第二N型MOS管的源极接地，所述第二N型MOS管的栅极连接所述扫描驱动信号的反相信号，所述第二N型MOS管的漏极经第三电阻连接至所述P型MOS管的漏极，所述RC电路的第一端和所述第一电容的第一端连接于所述P型MOS管的漏极与所述第三电阻的连接节点与所述扫描线之间，所述RC电路的第二端和所述第一电容的第二端接地。
  7. 根据权利要求6所述的液晶显示装置，其中，所述RC电路包括串联设置第二电容和第四电阻，并通过所述第四电阻的电阻值控制所述第一倾斜部的电压跨度，通过所述第二电容的电容值控制所述第一倾斜部的时间跨度。
  8. 一种液晶显示装置，其中，所述液晶显示装置包括：
    像素单元；
    数据线，用于传输数据驱动信号至所述像素单元；
    扫描驱动器，用于产生扫描驱动信号；
    削角电路，与所述扫描驱动器连接，所述削角电路对所述扫描驱动信号的上升沿进行削角；
    扫描线，用于将削角后的所述扫描驱动信号传输至所述像素单元。
  9. 根据权利要求8所述的液晶显示装置，其中，所述像素单元包括薄膜晶体管和像素电极，所述薄膜晶体管包括栅极、源极和漏极，所述像素电极连接所述漏极，所述扫描线连接所述栅极，以将削角后的所述扫描驱动信号传输至所述栅极，进而控制所述薄膜晶体管导通，所述数据线连接所述源极，以在所述薄膜晶体管导通时经所述源极传输数据驱动信号至所述像素电极。
  10. 根据权利要求8所述的液晶显示装置，其中，削角后的所述扫描驱动信号的上升沿至少倾斜成一第一倾斜部。
  11. 根据权利要求10所述的液晶显示装置，其中，所述第一倾斜部从第一电平倾斜上升至所述扫描驱动信号的高电平，所述第一电平位于所述扫描驱动信号的高电平和所述扫描驱动信号的低电平之间。
  12. 根据权利要求11所述的液晶显示装置，其中，所述削角电路进一步对所述扫描驱动信号的下降沿进行削角。
  13. 根据权利要求12所述的液晶显示装置，其中，削角后的所述扫描驱动信号的下降沿至少倾斜成一第二倾斜部。
  14. 根据权利要求13所述的液晶显示装置，其中，所述第二倾斜部从第二电平倾斜下降至所述扫描驱动信号的低电平，所述第二电平位于所述扫描驱动信号的高电平和所述扫描驱动信号的低电平之间。
  15. 根据权利要求8所述的液晶显示装置，其中，所述削角电路包括第一N型MOS管、第二N型MOS管、P型MOS管、第一电阻、第二电阻、第三电阻、RC电路以及第一电容，其中，所述第一N型MOS管的栅极接收所述扫描驱动信号，所述第一N型MOS管的源极接地，所述第一N型MOS管的漏极经所述第一电阻和所述第二电阻连接所述P型MOS管的源极，并接收基准电压信号，所述P型MOS管的栅极连接于所述第一电阻和所述第二电阻之间，所述P型MOS管的漏极连接所述扫描线，所述第二N型MOS管的源极接地，所述第二N型MOS管的栅极连接所述扫描驱动信号的反相信号，所述第二N型MOS管的漏极经第三电阻连接至所述P型MOS管的漏极，所述RC电路的第一端和所述第一电容的第一端连接于所述P型MOS管的漏极与所述第三电阻的连接节点与所述扫描线之间，所述RC电路的第二端和所述第一电容的第二端接地。
  16. 根据权利要求15所述的液晶显示装置，其中，所述RC电路包括串联设置第二电容和第四电阻，并通过所述第四电阻的电阻值控制所述第一倾斜部的电压跨度，通过所述第二电容的电容值控制所述第一倾斜部的时间跨度。
  17. 一种液晶显示装置的驱动方法，其中，所述驱动方法包括：
    提供扫描驱动信号；
    对所述扫描驱动信号的上升沿进行削角；
    将所述削角后的所述扫描驱动信号传输至扫描线。
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