WO2014146418A1 - 一种锗基肖特基结的制备方法 - Google Patents

一种锗基肖特基结的制备方法 Download PDF

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WO2014146418A1
WO2014146418A1 PCT/CN2013/084721 CN2013084721W WO2014146418A1 WO 2014146418 A1 WO2014146418 A1 WO 2014146418A1 CN 2013084721 W CN2013084721 W CN 2013084721W WO 2014146418 A1 WO2014146418 A1 WO 2014146418A1
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substrate
germanium
metal
schottky junction
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French (fr)
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黄如
林猛
李志强
安霞
黎明
云全新
李敏
刘朋强
张兴
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Peking University
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    • H—ELECTRICITY
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    • H10D64/00—Electrodes of devices having potential barriers
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    • H10D64/012—Manufacture or treatment of electrodes comprising a Schottky barrier to a semiconductor
    • H10D64/0121—Manufacture or treatment of electrodes comprising a Schottky barrier to a semiconductor to Group IV semiconductors
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
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    • H10D64/649—Schottky drain or source electrodes for FETs having rectifying junction gate electrodes
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    • H10P14/6326—Deposition processes
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    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
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    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6339—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD
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    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
    • H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
    • H10P14/69396—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
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    • H10P70/15—Cleaning before device manufacture, i.e. Begin-Of-Line process by wet cleaning only

Definitions

  • the present invention relates to the field of semiconductor devices, and in particular to a method for preparing a bismuth-based Schottky junction. Background technique
  • germanium material As silicon-based CMOS devices shrink to nanometer scales, traditional methods of reducing device performance by shrinking size are facing the double test of physical and technological limits. In order to further increase the operating speed of the device, a high mobility channel material is required.
  • the hole mobility of the germanium material under low electric field is four times that of silicon material, and the electron mobility is twice that of silicon material. Therefore, germanium material as a new channel material with its higher and more symmetrical current carrying capacity Sub-mobility is one of the potential development directions for high-performance MOSFET devices.
  • the fabrication technology of germanium-based MOS devices is still immature, and the performance of MOSFET devices is not satisfactory. High source-drain series resistance is one of the key factors affecting the performance improvement of bismuth-based MOSFETs.
  • N-type impurities such as phosphorus
  • ruthenium a metal-type impurities
  • a fast diffusion a metal-type impurities
  • Schottky is a very promising structure because it can effectively overcome the above problems.
  • the main difference between it and the traditional PN junction is that it replaces the traditional highly doped region with metal or metal telluride. This structure not only avoids the problem of low solid solubility and fast diffusion of impurities, but also obtains abrupt junction and low resistance. rate.
  • a key factor affecting performance is the carrier barrier height between the substrate and the metal.
  • the Fermi level is pinned near the top of the valence band, and the height of the electron barrier is large, which is not conducive to the improvement of the Schottky junction performance.
  • the factors causing the surface of the ⁇ surface Fermi level pinning have the following two aspects: First, the surface state formed by factors such as dangling bonds and defects on the surface of the semiconductor; Second, according to the Heine theory, the electron wave function of the metal is in the ⁇ The incomplete decay leads to the metal induced band gap state (MIGS) produced in the forbidden band of germanium semiconductors.
  • MIGS metal induced band gap state
  • a dielectric layer may be interposed between the two, and on the one hand, the dangling surface dangling bond may be passivated to improve the interface quality between the tantalum substrate and the metal;
  • the inserted dielectric layer blocks the electron wave function from entering the germanium substrate, thereby reducing the MIGS interface state.
  • rare earth oxides such as Y 2 O 3 , La 2 0 3 , Ce0 2 , etc.
  • Y 2 O 3 a stable X-0-Ge bond
  • La 2 0 3 a rare earth metal element such as Y, La, Ce, etc.
  • the technical solution provided by the present invention is as follows:
  • a method for preparing a bismuth-based Schottky junction surface-cleaning an N-type ruthenium-based substrate, then depositing a layer of Ce0 2 on the surface thereof, and depositing a layer of metal.
  • the surface of the ruthenium-based substrate is cleaned prior to deposition of Ce0 2 to remove surface contamination and a natural oxide layer.
  • Ce0 2 may be deposited by ALD, PLD, MBE, CVD or the like, but is not limited to the above method of depositing Ce0 2 .
  • the thickness of Ce0 2 deposited is 0.3 to 2 nm.
  • the deposited metal may be Al, Pt, Au, Ti, Ni,
  • a metal may be deposited, followed by photolithography, etching, annealing, and the like.
  • the method for preparing a bismuth-based Schottky junction of the present invention is suitable for a bulk Ge substrate, a GOI (on-insulator) substrate or any substrate having a Ge epitaxial layer on the surface, and is also suitable for a ruthenium-containing compound semiconductor substrate, such as SiGe, GeSn, etc.
  • the advantages of the invention are as follows:
  • the rare earth vaporized Ce0 2 is in contact with the ruthenium substrate, and a stable Ce-0-Ge bond can be formed at the interface, which is advantageous for reducing the interface state density, improving the interface quality, reducing the MIGS, and suppressing the Fermi pinning.
  • the tunneling resistance of Ce0 2 introduced between its metal and germanium substrate is small compared to Si 3 N 4 , A1 2 0 3 , Ge 3 N 4 , etc.
  • the forbidden band width of Si 3 N 4 is 5.3 eV
  • the offset of the conduction band with ⁇ substrate is ⁇ 2.03eV
  • the forbidden band width of A1 2 0 3 is 6.1eV
  • the deviation of the conduction band with ⁇ substrate is ⁇ 1.74eV
  • the forbidden band width of Ge 3 N 4 is 4.4 eV
  • the offset of the conduction band with ⁇ substrate is ⁇ 1.5eV.
  • the forbidden band width of Ce0 2 is ⁇ 3.3eV
  • the deviation from the conduction band of ⁇ substrate is ⁇ 0.4eV, as shown in Figure 1. Show).
  • the insertion of the CeO 2 dielectric layer is suitable for preparing a low resistivity fluorenyl Schottky junction in view of good interfacial properties with a germanium substrate and small conduction band offset.
  • Figure 1 shows the energy band diagram of the material of Si 3 N 4 , A1 2 0 3 , Ge 3 N 4 Ce0 2 and the germanium substrate;
  • Figure 2 - Figure 6 shows the schematic diagram of the preparation of the germanium-based Schottky junction. ;
  • an N-type semiconductor germanium substrate which may be a bulk germanium substrate, a GeOI (Germanium on Insulator) substrate, or a germanium-on-silicon or the like.
  • This embodiment is preferably a bulk germanium substrate, such as Figure 2;
  • the ruthenium substrate was first organically cleaned, washed successively with acetone and ethanol, and then rinsed with DI water to remove oil and organic contaminants from the ruthenium substrate. Then use hydrochloric acid to clean, boil in dilute hydrochloric acid, then rinse with DI water to remove inorganic pollutants, metal particles, etc.
  • Ce02 can be deposited by methods such as ALD, PLD, MBE, CVD, and the like. This embodiment is preferably 0.6 nm, as shown in FIG. 3;
  • the deposited metal may be Al, Pt, Au, Ti, Ni, TiN, TaN, W, etc.
  • a layer of 200 nm of Al is deposited by sputtering, as shown in FIG. 4;
  • this embodiment preferably deposits 200 nm of Al, as shown in FIG. 6;

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Abstract

一种锗基肖特基结的制备方法，包括：对N型锗基衬底（1）进行表面清洗，然后在其表面淀积一层CeO2（2），再淀积一层金属（3）。稀土气化物CeO2与锗衬底接触，可在界面处形成稳定的Ce-O-Ge键，有利于降低界面态密度，提高界面质量，并减小MIGS，抑制费米级钉扎。同时，CeO2在其金属与锗衬底之间引入的隧穿电阻相对于Si3N4、Al2O3、Ge3N4等情况要小。鉴于与锗衬底良好的界面特性与小的导带偏移量，CeO2介质层的插入适合制备低电阻率的锗基肖特基结。

Description

一种锗基尚特基结的制备方法
技术领域 本发明属于半导体器件领域， 具体涉及一种锗基肖特基结的制备方法。 背景技术
随着硅基 CMOS器件尺寸缩小到纳米尺度， 传统通过缩小尺寸提高器件性能的 方法正面临物理与技术极限的双重考验。为了进一步提高器件工作速度， 需要采用高 迁移率沟道材料。锗材料在低电场下的空穴迁移率是硅材料的 4倍， 电子迁移率是硅 材料的 2倍， 因此， 锗材料作为一种新的沟道材料以其更高、 更加对称的载流子迁移 率成为高性能 MOSFET器件很有潜力的发展方向之一。 但是目前锗基 MOS器件的 制备技术还不成熟， MOSFET 器件性能不理想。 高源漏串联电阻是影响锗基 MOSFET性能提高的关键因素之一。 与硅材料相比， N型杂质 （如磷） 在锗材料中激活浓度低， 且扩散快， 不利于 浅结的制备。 肖特基结由于能有效克服以上问题而成为一种非常具有发展潜力的结 构。它与传统 PN结的主要区别是：采用金属或者金属锗化物替代了传统的高掺杂区， 此结构不仅避免了杂质固溶度低和扩散快的问题， 而且还能获得突变结和低电阻率。 对于肖特基结， 影响性能的关键因素是衬底与金属之间的载流子势垒高度。但是对于 金属与锗衬底接触时， 费米能级被钉扎在价带顶附近， 电子势垒高度大， 不利于肖特 基结性能的提升。 导致锗表面费米能级钉扎的因素有以下两方面： 第一， 锗半导体表 面的悬挂键和缺陷等因素形成的表面态； 第二， 根据海涅理论， 金属的电子波函数在 锗中的不完全衰减而导致在锗半导体的禁带当中产生的金属诱导带隙态（MIGS)。为 了消除锗衬底与金属之间的费米能级钉扎，可在二者之间插入介质层， 一方面可以钝 化锗表面悬挂键， 改善锗衬底与金属的界面质量； 另一方面， 插入的介质层可以阻挡 电子波函数进入锗衬底， 进而减少 MIGS 界面态。 目前已被用做介质层的材料有 Si3N4,Al203,Ge3N4等，但这些材料与锗之间的导带偏移量较大，会在锗衬底与金属之 间引入较大的隧穿电阻， 不利于增大肖特基结的开态电流。
对于锗衬底表面的钝化， 稀土氧化物， 如 Y203,La203,Ce02等， 被认为是锗衬底 表面良好的钝化物。这是由于稀土氧化物与锗衬底接触，界面处可生成稳定的 X-0-Ge 键 （X指 Y， La, Ce等稀土金属元素）， 有效钝化锗表面悬挂键， 提高锗衬底与金属 的界面质量。 发明内容
本发明的目的在于提供一种锗基肖特基结的制备方法， 以减小锗基肖特基结的 电阻率。 本发明提供的技术方案如下：
一种锗基肖特基结的制备方法： 对 N型锗基衬底进行表面清洗， 然后在其表面 淀积一层 Ce02， 再淀积一层金属。 上述一种锗基肖特基结的制备方法中，在淀积 Ce02之前先对锗基衬底表面进行 清洗， 以去除表面沾污和自然氧化层。
上述一种锗基肖特基结的制备方法中， Ce02可通过 ALD、 PLD、 MBE、 CVD 等方法淀积， 但并不局限于上述淀积 Ce02的方法。 上述一种锗基肖特基结的制备方法中， 淀积 Ce02的厚度为 0.3~2nm。
上述一种锗基肖特基结的制备方法中， 淀积的金属可以是 Al， Pt， Au, Ti， Ni,
TiN, TaN, W等， 但并不局限于上述淀积金属。 上述一种锗基肖特基结的制备方法中， 淀积金属后可进行光刻、 刻蚀、 退火等 工艺。 本发明的锗基肖特基结的制备方法适用于体 Ge衬底、 GOI (绝缘体上锗）衬底 或任何表面含有 Ge外延层的衬底， 也适用于含锗的化合物半导体衬底， 比如 SiGe， GeSn等。 本发明的优点如下：
稀土气化物 Ce02与锗衬底接触， 可在界面处形成稳定的 Ce-0-Ge键， 有利于降 低界面态密度低， 提高界面质量， 并减小 MIGS， 抑制费米级钉扎。 同时， Ce02在其 金属与锗衬底之间引入的隧穿电阻相对于 Si3N4、 A1203、 Ge3N4等情况要小 （Si3N4 的禁带宽度为 5.3eV， 与锗衬底导带偏移量为〜 2.03eV， A1203的禁带宽度为 6.1eV， 与锗衬底导带偏移量为〜 1.74eV， Ge3N4的禁带宽度为 4.4eV， 与锗衬底导带偏移量为 ~1.5eV。 而 Ce02的禁带宽度为 ~3.3eV， 与锗衬底导带偏移量为〜 0.4eV， 如附图 1所 示）。 鉴于与锗衬底良好的界面特性与小的导带偏移量， Ce02介质层的插入适合制备 低电阻率的锗基肖特基结。 附图说明
图 1所示 Si3N4、 A1203、 Ge3N4 Ce02等材料与锗衬底接触的能带图； 图 2 - 图 6 所示实施例为锗基肖特基结制备示意图；
其中， 1一体锗衬底； 2— Ce02 ; 3—金属 A1; 4—背电极 Al。 具体实施方式
以下结合附图， 通过具体的实施例对本发明所述的方法做进一步描述， 实施步 骤如下：
1) 选择 N型半导体锗衬底， 可以是体锗衬底、 GeOI(Germanium on Insulator)衬 底或硅上外延锗（Germanium-on-silicon)等， 本实施例优选为体锗衬底， 如 图 2所示；
2) 对锗衬底进行清洗。 首先对锗衬底进行有机清洗， 依次用丙酮和乙醇浸泡清 洗， 再用 DI水冲洗干净， 去除锗衬底上的油污和有机污染物。 再用盐酸清 洗， 在稀盐酸中加热煮沸， 随后用 DI水冲洗干净， 去除无机污染物、 金属 颗粒等；
3) 去除锗衬底表面的氧化物。 可以采用 HF或 HC1溶液浸泡的方法， 亦可采用 高温真空退火的方法。本实施例优选为 HF溶液浸泡的方法。具体过程如下： 先用稀释的 HF (HF: H20= l : 5 ~1： 60) 溶液浸泡 10 50秒， 再用 DI水 冲洗 10 50秒， 如此循环 5~10次；
4) 在衬底上淀积一层 Ce02， 厚度为 0.3~2nm。 Ce02可通过 ALD、 PLD、 MBE、 CVD等方法淀积。 本实施例优选为 0.6nm， 如图 3所示；
5) 淀积金属。 淀积的金属可以是 Al， Pt， Au， Ti， Ni, TiN, TaN, W等， 本 实施例是用溅射的方法淀积一层 200nm的 Al， 如图 4所示；
6) 光刻， 刻蚀金属形成所需要的图形， 如图 5所示；
7) 淀积背电极， 本实施例优选为淀积 200nm的 Al， 如图 6所示；
8) 淀积金属后退火。 在 350°C的 N2气氛中退火 15min。 以上通过优选实施例详细描述了本发明所提出的一种锗基肖特基结的制备方 法， 本领域的技术人员应当理解， 以上所述仅为本发明的优选实施例， 在不脱离本发 明实质的范围内，可以对本发明的器件结构做一定的变形或修改； 其制备方法也不限 于实施例中所公开的内容， 凡依本发明权利要求所做的均等变化与修饰， 皆应属本发 明的涵盖范围。

Claims

权 利 要 求
1. 一种锗基肖特基结的制备方法， 其特征是， 对 N型锗基衬底进行表面清 洗， 然后在其表面淀积一层 Ce02， 再淀积一层金属。
2. 如权利要求 1所述的制备方法， 其特征是， 所述 Ce02通过 ALD PLD MBE或 CVD方法淀积。
3. 如权利要求 1所述的制备方法， 其特征是， 淀积 Ce02的厚度为 0.3~2
4. 如权利要求 1所述的制备方法， 其特征是， 淀积的金属是 Al Pt Au, Ti Ni, TiN, TaN, W。
5. 如权利要求 1所述的制备方法， 其特征是， 淀积金属后进行光刻、 刻蚀、 退火。
6. 如权利要求 1所述的制备方法， 其特征是， 所述 N型锗基衬底为体 Ge 衬底、 GOI衬底或任何表面含有 Ge外延层的衬底。
7. 如权利要求 1所述的制备方法， 其特征是， 所述 N型锗基衬底为含锗的 化合物半导体衬底。
8. 如权利要求 7所述的制备方法， 其特征是， 所述的含锗的化合物为 SiGe
GeSn。
PCT/CN2013/084721 2013-03-18 2013-09-30 一种锗基肖特基结的制备方法 Ceased WO2014146418A1 (zh)

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