WO2014141972A1 - 半導体発光素子の製造方法 - Google Patents

半導体発光素子の製造方法 Download PDF

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Publication number
WO2014141972A1
WO2014141972A1 PCT/JP2014/055651 JP2014055651W WO2014141972A1 WO 2014141972 A1 WO2014141972 A1 WO 2014141972A1 JP 2014055651 W JP2014055651 W JP 2014055651W WO 2014141972 A1 WO2014141972 A1 WO 2014141972A1
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Prior art keywords
layer
semiconductor structure
structure layer
openings
semiconductor
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PCT/JP2014/055651
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English (en)
French (fr)
Japanese (ja)
Inventor
孝信 赤木
竜舞 斎藤
宮地　護
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スタンレー電気株式会社
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Application filed by スタンレー電気株式会社 filed Critical スタンレー電気株式会社
Priority to BR112015021734-6A priority Critical patent/BR112015021734B1/pt
Priority to CN201480019270.5A priority patent/CN105122476B/zh
Priority to KR1020157025042A priority patent/KR20150127096A/ko
Priority to EP14763431.5A priority patent/EP2975653B1/de
Priority to US14/774,579 priority patent/US9349908B2/en
Publication of WO2014141972A1 publication Critical patent/WO2014141972A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • the present invention relates to a method for manufacturing a semiconductor light emitting device such as a light emitting diode (LED).
  • a semiconductor light emitting device such as a light emitting diode (LED).
  • a semiconductor light emitting device such as a light emitting diode
  • an n type semiconductor layer, a light emitting layer, and a p type semiconductor layer are usually grown on a growth substrate, and a voltage is applied to the n type semiconductor layer and the p type semiconductor layer, respectively. It is fabricated by forming an electrode and a p-electrode.
  • a p-electrode is formed on a p-type semiconductor layer, and then the device is bonded to a support substrate through a bonding layer, and the growth substrate is removed.
  • a semiconductor light emitting device having a so-called bonded structure is known.
  • Patent Document 1 discloses wet etching using an alkaline solution on the surface of the n-type semiconductor layer exposed after the growth substrate is removed. And a technique for forming a plurality of protrusions derived from a semiconductor crystal structure is disclosed.
  • GaN-based semiconductors have a wurtzite crystal structure.
  • a concavo-convex structure composed of hexagonal pyramidal projections derived from a wurtzite crystal structure is formed.
  • this concavo-convex structure is formed on the surface of the n-type semiconductor layer, which is the light extraction surface, the probability that light emitted from the light emitting layer passes through the concavo-convex structure is high. Therefore, a lot of light can be taken out.
  • the protrusions derived from this crystal structure are referred to as micro cones.
  • Patent Document 1 The main point of the technique described in Patent Document 1 is that a plurality of recesses arranged along the crystal axis of the semiconductor material are formed on the C-plane of the n-type semiconductor layer exposed by removing the growth substrate. Then, wet etching using an alkaline solution is performed on the n-type semiconductor layer.
  • the concave portion provided on the surface of the n-type semiconductor layer functions as an etching control point having an etching rate lower than that of the other surface portion of the n-type semiconductor layer in the subsequent wet etching.
  • various crystal planes other than the C-plane are exposed in the concave portion.
  • the concave portion may be a mortar shape, a cone shape, or a hemisphere. It is described that it is preferable to have a shape.
  • the difficulty of etching in the concave portion is the same as the difficulty of etching in portions other than the concave portion, and the concave portion It does not function as an etching control point.
  • problems such as a problem that the electrode material diffuses into the element and a current leak occur due to partial excessive etching.
  • Patent Document 1 describes that the concave portion is formed by using dry etching such as reactive ion etching.
  • dry etching such as reactive ion etching.
  • the inventors of the present application have focused on the fact that it is difficult to control the shape and depth of the recess as the control point when using dry etching. That is, when dry etching is used, concave portions having various shapes such as a cylindrical shape and a polygonal column shape are formed. Therefore, it is difficult to form microcones that are uniformly and regularly arranged and have a uniform size.
  • the present invention has been made in view of the above points, and an object thereof is to provide a highly reliable method for manufacturing a semiconductor light emitting device having regularly arranged and uniform projections of uniform size. .
  • a method of manufacturing a semiconductor light emitting device is a method of manufacturing a semiconductor light emitting device including a semiconductor structure layer having a hexagonal crystal structure, and is formed on the surface of the semiconductor structure layer along the crystal axis of the semiconductor structure layer.
  • Forming a mask layer having a plurality of openings arranged at equal intervals performing a plasma treatment on the surface of the semiconductor structure layer exposed from the openings of the mask layer, removing the mask layer, and semiconductor Forming a plurality of protrusions arranged on the surface of the semiconductor structure layer according to the arrangement form of the plurality of openings and derived from the crystal structure of the semiconductor structure layer by performing wet etching on the surface of the structure layer It is characterized by that.
  • A)-(d) is sectional drawing explaining the process in the manufacturing method of the semiconductor light-emitting device of an Example.
  • A) And (b) is a figure explaining the arrangement
  • A)-(d) is sectional drawing explaining the wet etching process of an Example.
  • A)-(d) is a figure which shows the surface of the n-type semiconductor layer in the wet etching process of an Example. It is a figure which shows the surface of the n-type semiconductor layer in the wet etching process of a comparative example.
  • a plasma treatment is performed on the C-plane of GaN having a hexagonal crystal structure, that is, a N-polar plane (N-polar plane), and then an alkaline solution is used. It is characterized by performing wet etching. First, this plasma treatment will be briefly described.
  • FIG. 1 shows an electron microscope observation image (Scanning / Electron / Microscope: SEM image) as a result of the comparative experiment. In this experiment, Ar gas plasma was used for the plasma treatment.
  • the four images in the left part of FIG. 1 show the surface of GaN when wet etching is performed without performing plasma treatment, and the four images in the right part of FIG. 1 are subjected to wet etching after performing plasma treatment.
  • the surface of GaN in the case is shown.
  • the entire surface of the GaN surface shown in the right part of FIG. 1 is subjected to plasma treatment.
  • the images when the size of the microcones in both cases are approximately the same (4 levels) are arranged on the left and right.
  • each time (1 min, 2.5 min, etc.) in the figure indicates an elapsed time (etching elapsed time) after GaN is immersed in TMAH (trimethylammonia solution) maintained at about 83 ° C. to 84 ° C. .
  • this principle is applied to a method for manufacturing a semiconductor light emitting device.
  • FIGS. 2A to 2D are cross-sectional views illustrating a method for manufacturing a semiconductor light emitting device according to Example 1 of the present invention.
  • Example 1 the two adjacent semiconductor light emitting elements 10 of the semiconductor wafer will be described.
  • FIG. 2A is a cross-sectional view illustrating a process for manufacturing a semiconductor light emitting element having a bonded structure.
  • the composition of the growth substrate used for crystal growth on (not shown), Al x In y Ga z N (0 ⁇ x ⁇ 1,0 ⁇ y ⁇ 1,0 ⁇ z ⁇ 1, x + y + z 1)
  • An n-type semiconductor layer (first semiconductor layer) 11, an active layer 12, and a p-type semiconductor layer (second semiconductor layer) 13 having the above structure are sequentially grown.
  • the entire n-type semiconductor layer 11, active layer 12, and p-type semiconductor layer 13 are referred to as a semiconductor structure layer 14.
  • MOCVD method metal organic chemical vapor deposition
  • a buffer layer (not shown), an n-GaN layer 11, an active layer 12 made of an InGaN layer / GaN layer, and a p-AlGaN cladding layer are formed on a sapphire substrate whose crystal growth surface is a C-plane. (Not shown) and the p-GaN layer 13 were sequentially grown.
  • a p-electrode 15 is formed on the p-type semiconductor layer 13.
  • sputtering and electron beam evaporation can be used to form the p-electrode 15.
  • a patterned mask (not shown) is formed on the p-type semiconductor layer 13, and a Ni layer, an Ag layer, and a Ni layer are sequentially formed by an electron beam evaporation method, and then a lift-off method.
  • a p-electrode 15 was formed by removing the mask.
  • a metal layer 16 is formed so as to cover the entire p electrode 15.
  • the metal layer 16 includes a cap layer (not shown) that prevents migration of the material of the p-electrode 15 and a bonding layer (not shown) used for bonding to a support substrate described later.
  • a metal material such as Ti, TiW, Pt, Ni, Au, AuSn, or Cu can be used.
  • a sputtering method and an electron beam evaporation method can be used for the formation of the metal layer 16.
  • a Ti layer, a Pt layer, and an AuSn layer were formed so as to cover the entire p electrode 15.
  • a protective film 17 is formed on the side portion of the semiconductor structure layer 14.
  • a sputtering method was used to form the protective film 17.
  • an insulating material such as SiO 2 or SiN can be used.
  • the SiO 2 film is formed on the side portion of the semiconductor structure layer 14.
  • the support substrate 18 is separately prepared and bonded to the semiconductor structure layer 14 through the metal layer 15.
  • a known material such as a Si substrate having a metal layer (not shown) such as AuSn or Au formed on the surface or a plated Cu alloy can be used.
  • thermocompression bonding was used for the bonding of the semiconductor structure layer 14 and the support substrate 18.
  • the Si substrate 18 on which the AuSn layer was formed and the metal layer 15 formed on the semiconductor structure layer 14 side were joined by heating and pressure bonding.
  • the growth substrate used for the growth of the semiconductor structure layer 14 is removed from the semiconductor structure layer 14.
  • Laser lift-off was used to remove the growth substrate.
  • a sapphire substrate was irradiated using a KrF excimer laser, and the sapphire substrate was peeled off from the n-GaN layer 11. By removing the sapphire substrate, the C-plane of the n-GaN layer 11, that is, the N-polar plane of GaN appears.
  • a mask layer having a pattern composed of a plurality of openings 19A arranged at equal intervals along the crystal axis of the semiconductor material. 19 is formed.
  • a material of the mask layer 19 for example, a photoresist can be used.
  • a mask layer 19 having a pattern in which circular openings 19A having a diameter of 300 nm are arranged in a triangular lattice at a pitch of 1.5 ⁇ m is formed on the surface of the n-GaN layer 11.
  • a resist layer was applied to the entire surface of the n-GaN layer 11 and prebaked using a hot plate.
  • the above pattern was exposed to the photoresist using UV light.
  • the wafer was dipped in the developer, and the pattern was developed.
  • the surface of the n-type semiconductor layer 11 exposed from the opening 19A of the mask layer 19 was subjected to plasma treatment with an inert gas.
  • an inert gas for example, Ar can be used as the material of the inert gas.
  • a sputtering apparatus or a dry etching apparatus can be used.
  • Ar plasma was irradiated to the exposed portion of the n-GaN layer 11 for about 5 minutes using the reverse sputtering function of the sputtering apparatus.
  • TMAH tetramethylammonia solution
  • KOH potassium hydroxide solution
  • the wafer was immersed in TMAH at about 70 ° C.
  • a plurality of hexagonal pyramidal projections, that is, micro cones 20, which are arranged according to the arrangement form of the openings 19 A of the mask layer 19 and are derived from the crystal structure, are formed on the surface of the n-type semiconductor layer 11.
  • a protective layer 21 was formed on the surface of the n-type semiconductor layer 11.
  • an insulating material such as SiO 2 and SiN can be used.
  • a sputtering method was used to form the protective layer 21.
  • an n-electrode 22 is formed on the surface of the n-type semiconductor layer 11.
  • a sputtering method and an electron beam evaporation method can be used for the formation of the n-electrode 22.
  • a patterned mask (not shown) is formed on the n-type semiconductor layer 11.
  • a Ti layer, an Al layer, a Ti layer, a Pt layer, and an Au layer were sequentially formed by electron beam evaporation, and then the n-electrode 22 was formed by removing the mask by lift-off. Thereafter, the support substrate 18 is divided for each element to obtain the semiconductor light emitting element 10.
  • FIG. 3A and FIG. 3B schematically show the surface of the mask layer 19, and the broken line in the figure shows the crystal axis of the semiconductor structure layer 14.
  • the openings 19A of the mask layer 19 were formed so as to form an arrangement as shown in FIG. That is, each of the other openings 19A adjacent to the arbitrary one opening 19A is arranged at each vertex of the regular hexagon, and two opposite sides constituting the regular hexagon are the crystal axes of the semiconductor structure layer 14 [ [0120]
  • the openings 19A are arranged at equal intervals so as to be parallel to the 11-20] direction. In other words, the openings 19A are aligned at equal intervals in the [11-20] direction of the crystal axis of the semiconductor structure layer 14 and are also aligned at equal intervals in the [2-1-10] direction. 19A is arranged.
  • the direction of the crystal axis of the semiconductor structure layer 14 can be grasped based on, for example, a notch portion called an orientation flat (OF) indicating a crystal orientation that is usually formed on the growth substrate.
  • OF orientation flat
  • the openings 19A of the mask layer 19 may be formed so as to have an arrangement form as shown in FIG. That is, each of the other openings 19A adjacent to the arbitrary one opening 19A is arranged at each vertex of the regular hexagon, and two opposite sides constituting the regular hexagon are [1 of the crystal axis of the semiconductor film 20.
  • the openings 19A are arranged at equal intervals so as to be parallel to the ⁇ 100] direction.
  • the openings 19A are arranged so that the plurality of openings 19A are aligned at equal intervals in the [1-100] direction of the crystal axis of the semiconductor film 20 and also at equal intervals in the [10-10] direction.
  • This arrangement form corresponds to a case where the arrangement of the openings 19A in FIG.
  • the formation of the microcone is completed when the sides of the regular hexagons at the bottom of the adjacent microcone contact each other. Therefore, the deepest part of the microcone in this case is the side part of the regular hexagonal surface provided at the bottom.
  • the formation of the microcone is completed when the regular hexagonal apexes at the bottoms of the adjacent microcones contact each other. Therefore, the deepest part of the microcone in this case is the apex part of the regular hexagonal surface provided at the bottom.
  • the arrangement form shown in FIG. 3A has a shorter time until the formation of the microcone is completed, and the bottom part of the microcone is easier to control, which is preferable from the viewpoint of improving the light extraction efficiency and reliability. It can be said that it is a form.
  • FIG. 4A is an enlarged view of the cross section of the surface of the n-type semiconductor layer 11 from which the mask 19 has been removed after the plasma processing step.
  • the portion 20A irradiated with plasma (plasma irradiation portion) is recessed as compared with other surface portions.
  • the depression at this time has a substantially columnar shape. That is, the bottom of the recess is a flat surface parallel to the other surface portion that is the C-plane.
  • the depression is very shallow and has a depth of, for example, less than 50 nm, preferably 30 to 40 nm.
  • FIG. 5A shows an SEM image when the surface of the n-type semiconductor layer 11 in this state is viewed from the upper surface of the element, that is, a surface perpendicular to the n-type semiconductor layer 11.
  • FIG. 4B shows an SEM image when the surface of the n-type semiconductor layer 11 in this state is viewed from the upper surface of the element.
  • FIG. 4C shows an SEM image when the surface of the n-type semiconductor layer 11 in this state is viewed from the upper surface of the element.
  • FIG. 4D shows an SEM image when the surface of the n-type semiconductor layer 11 in this state is viewed from the upper surface of the element.
  • the close-packed arrangement refers to an arrangement in which a plurality of microcones having a regular hexagonal bottom surface are arranged without gaps on a plane, which is a so-called honeycomb-like arrangement.
  • FIG. 6 is an SEM image showing a time-series change at the time of wet etching on the surface of the n-GaN layer formed by the method for manufacturing a semiconductor light emitting device in the comparative example of this example.
  • the semiconductor light emitting device manufactured according to the manufacturing method of this comparative example has a portion (comparison portion) 25 that is not subjected to the plasma treatment on the half of the surface of the n-GaN layer, and the surface portion of the other n-GaN layer.
  • Has a portion (plasma processing section) 26 that has been subjected to the same plasma processing as in the present embodiment.
  • This comparative example is the same as the present example except that a mask layer having a portion having no opening (corresponding to the comparison portion 25) and a portion having the opening (corresponding to the plasma processing portion 26) is used.
  • a semiconductor light emitting device was fabricated through the steps.
  • each image in FIG. 6 is an SEM image of the surface of the n-GaN layer, and each image time (3 min, 4 min, etc.) is an elapsed time after etching the wafer in TMAH (etching elapsed time) in the wet etching process. ).
  • the material for the mask layer is not limited to the resist.
  • the mask layer may be formed using an insulating material such as SiO 2 or SiN, or a metal material such as Ag or Pt.
  • the shape of the opening may not be circular.
  • the opening may have a polygonal shape or an elliptical shape.
  • the diameter of the opening is not limited to 300 nm.
  • the opening preferably has a diameter of 50 to 1000 nm.
  • the plasma irradiation part that is, the part irradiated with plasma in the opening is removed at an early stage after the start of wet etching, and the shape and size of the microcone cannot be controlled.
  • the pitch between the openings is 1.5 ⁇ m
  • the pitch between the openings is not limited to 1.5 ⁇ m.
  • the openings are preferably formed at a pitch of 1 to 5.5 ⁇ m.
  • the optimum pitch that improves the light extraction efficiency can be determined according to the wavelength of light emitted from the active layer.
  • each condition (plasma gas, treatment time, etc.) in the plasma treatment can be appropriately adjusted according to the apparatus used for the plasma treatment, the composition and state of the surface to be treated, the size of the projection to be formed, and the like.
  • the method for manufacturing a semiconductor light emitting device has a plurality of openings arranged at equal intervals along the crystal axis of the semiconductor structure layer on the surface of the hexagonal semiconductor structure layer.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)
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  • Drying Of Semiconductors (AREA)
PCT/JP2014/055651 2013-03-12 2014-03-05 半導体発光素子の製造方法 WO2014141972A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
BR112015021734-6A BR112015021734B1 (pt) 2013-03-12 2014-03-05 Método para fabricação de elemento emissor de luz semicondutor
CN201480019270.5A CN105122476B (zh) 2013-03-12 2014-03-05 用于制造半导体发光元件的方法
KR1020157025042A KR20150127096A (ko) 2013-03-12 2014-03-05 반도체 발광소자 제조방법
EP14763431.5A EP2975653B1 (de) 2013-03-12 2014-03-05 Verfahren zur herstellung eines lichtemittierenden halbleiterelements
US14/774,579 US9349908B2 (en) 2013-03-12 2014-03-05 Method for manufacturing semiconductor light-emitting element

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013049003A JP6001476B2 (ja) 2013-03-12 2013-03-12 半導体発光素子の製造方法
JP2013-049003 2013-03-12

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US (1) US9349908B2 (de)
EP (1) EP2975653B1 (de)
JP (1) JP6001476B2 (de)
KR (1) KR20150127096A (de)
CN (1) CN105122476B (de)
BR (1) BR112015021734B1 (de)
WO (1) WO2014141972A1 (de)

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CN111525010B (zh) * 2020-04-30 2022-05-17 南京大学 高发光效率的深紫外发光二极管芯片及其制作方法

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US9276170B2 (en) * 2012-10-23 2016-03-01 Toyoda Gosei Co., Ltd. Semiconductor light emitting element and method of manufacturing semiconductor light emitting element

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KR20150127096A (ko) 2015-11-16
EP2975653B1 (de) 2020-04-08
CN105122476A (zh) 2015-12-02
US20160027956A1 (en) 2016-01-28
EP2975653A1 (de) 2016-01-20
US9349908B2 (en) 2016-05-24
EP2975653A4 (de) 2016-08-24
BR112015021734A2 (pt) 2017-07-18
JP2014175583A (ja) 2014-09-22
CN105122476B (zh) 2018-01-23
JP6001476B2 (ja) 2016-10-05
BR112015021734B1 (pt) 2021-04-27

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