Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/16—Constructional details or arrangements
  • G06F1/20—Cooling means
  • G06F1/203—Cooling means for portable computers, e.g. for laptops
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/16—Constructional details or arrangements
  • G06F1/20—Cooling means
  • G06F1/206—Cooling means comprising thermal management
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
  • G06F1/3234—Power saving characterised by the action undertaken
  • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
  • G06F1/3234—Power saving characterised by the action undertaken
  • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
  • G06F2119/08—Thermal analysis or thermal optimisation
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
  • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

• PCDs typically do not have active cooling devices, like fans, which are often found in larger computing devices such as laptop and desktop computers. Instead of using fans, PCDs may rely on the spatial arrangement of electronic packaging so that two or more active and heat producing components are not positioned proximally to one another. Many PCDs may also rely on passive cooling devices, such as heat sinks, to manage thermal energy among the electronic components which collectively form a respective PCD.
• active cooling devices like fans
• thermal management policies may be applied to any functional component within a PCD including, but not limited to, a modem, a camera, a wireless network interface controller ("WNIC"), a display, a video encoder, a peripheral device, a battery, etc.
• WNIC wireless network interface controller
• thermo load thermal load
• thermal distribution thermo distribution
• thermal signature thermo processing load
• Efficient management of thermal energy generation in a PCD can be accomplished by using one or more sensor measurements that correlate with the temperatures of silicon junctions in core(s) in combination with an instantaneous thermal resistance value of the core(s).
• exemplary embodiments of the systems and methods are described herein in the context of temperature measurements associated with silicon junctions of cores, it will be understood that alternative embodiments may use temperature measurements and thermal resistance values associated with other components in a PCD. That is, although exemplary embodiments of thermal management methods that use predicted power level settings are described herein in the context of cores within a central processing unit (“CPU"), application of such thermal management methodologies are not limited to cores within a CPU.
• CPU central processing unit
• FIG. 3B is a schematic diagram illustrating an exemplary software architecture of the PCD 100 of FIG. 2 for thermal management using thermal resistance values to predict optimum power level settings.
• Any number of algorithms may form or be part of at least one thermal management policy that may be applied by the PLP module 101 when certain thermal conditions are met, however, in a preferred embodiment the PLP module 101 works with the DVFS module 26 to adjust voltage and frequency scaling policies to individual thermal aggressors in chip 102 including, but not limited to, cores 222, 224 and 230.
• the voltage and frequency scaling policies may be based on an optimum power level calculated from instantaneous thermal resistance values and targeted operating temperature levels.
• the PLP module 101 may be triggered to calculate the optimum power level when a temperature threshold associated with a silicon junction aspect of a core is met or exceeded.
• the various logic may be implemented with any or a combination of the following technologies, which are each well known in the art: a discrete logic circuit(s) having logic gates for implementing logic functions upon data signals, an application specific integrated circuit (ASIC) having appropriate combinational logic gates, a programmable gate array(s) (PGA), a field programmable gate array (FPGA), etc.
• ASIC application specific integrated circuit
• PGA programmable gate array
• FPGA field programmable gate array

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Human Computer Interaction (AREA)
• Computer Hardware Design (AREA)
• Power Sources (AREA)

Priority Applications (4)

Applications Claiming Priority (2)

Publications (1)

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Family Applications (1)

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Cited By (2)

Families Citing this family (35)

Citations (3)

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• 2013
  • 2013-02-27 US US13/779,153 patent/US9037882B2/en active Active
• 2014
  • 2014-02-26 CN CN201480010310.XA patent/CN105009021B/zh not_active Expired - Fee Related
  • 2014-02-26 KR KR1020157025751A patent/KR101814264B1/ko not_active Expired - Fee Related
  • 2014-02-26 JP JP2015559308A patent/JP6162262B2/ja not_active Expired - Fee Related
  • 2014-02-26 EP EP14711648.7A patent/EP2962169B1/en not_active Not-in-force
  • 2014-02-26 WO PCT/US2014/018774 patent/WO2014134211A1/en not_active Ceased
• 2015
  • 2015-04-17 US US14/690,330 patent/US9465423B2/en active Active

Patent Citations (3)

Non-Patent Citations (1)

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