WO2014123018A1 - データ処理装置、及びデータ処理方法 - Google Patents
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/1177—Regular LDPC codes with parity-check matrices wherein all rows and columns have the same row weight and column weight, respectively
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/033—Theoretical methods to calculate these checking codes
- H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
- H03M13/2707—Simple row-column interleaver, i.e. pure block interleaving
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
- H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
- H03M13/356—Unequal error protection [UEP]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
Definitions
- the present technology relates to a data processing device and a data processing method, and more particularly, to a data processing device and a data processing method capable of providing, for example, an LDPC code having a good error rate.
- LDPC Low Density Parity Check
- DVB Digital Video Broadcasting
- S.2 Satellite Digital Broadcasting
- LDPC codes are also used in next-generation terrestrial digital broadcasting such as DVB-T.2.
- LDPC codes have been found to have performance close to the Shannon limit as the code length is increased, as is the case with turbo codes and the like.
- the LDPC code has the property that the minimum distance is proportional to the code length, its characteristic is that the block error probability characteristic is good, and furthermore, the so-called error floor phenomenon observed in the decoding characteristic such as turbo code is observed.
- An advantage is that it hardly occurs.
- LDPC code is a linear code and does not necessarily need to be binary, but will be described here as being binary.
- LDPC code is characterized by the fact that the parity check matrix that defines the LDPC code is sparse.
- a sparse matrix is a matrix in which the number of “1” s in the matrix is very small (a matrix in which most elements are 0).
- FIG. 1 shows an example of a parity check matrix H of an LDPC code.
- the weight of each column (column weight) (the number of “1”) (weight) is “3”, and the weight of each row (row weight) is “6”. .
- a generator matrix G is generated based on the check matrix H, and the generator matrix G is multiplied by binary information bits to generate a codeword (LDPC code). ) Is generated.
- the generator matrix G is a K ⁇ N matrix
- the encoding device multiplies the generator matrix G by a bit string (vector u) of information bits made up of K bits to generate a code made up of N bits.
- Generate the word c ( uG).
- the code word (LDPC code) generated by this encoding device is received on the receiving side via a predetermined communication path.
- LDPC code decoding is an algorithm proposed by Gallager called probabilistic decoding (Probabilistic Decoding), consisting of variable nodes (also called message nodes) and check nodes (check nodes). This can be done by a message passing algorithm based on belief propagation on a so-called Tanner graph.
- the variable node and the check node are also simply referred to as nodes as appropriate.
- FIG. 2 shows a procedure for decoding the LDPC code.
- a real value (reception LLR) expressing the “0” likelihood of the value of the i-th code bit of the LDPC code (1 codeword) received on the receiving side as a log likelihood ratio as appropriate. ) Is also referred to as a received value u 0i . Further, a message output from the check node is u j and a message output from the variable node is v i .
- step S11 the LDPC code is received, the message (check node message) u j is initialized to “0”, and the counter of the iterative process is used.
- the variable k taking the integer of is initialized to “0”, and the process proceeds to step S12.
- step S12 a message (variable node message) v i is obtained by performing the calculation (variable node calculation) shown in Expression (1) based on the received value u 0i obtained by receiving the LDPC code.
- the message u j is obtained by performing the calculation (check node calculation) shown in Expression (2).
- Equation (1) and Equation (2) can be arbitrarily selected to indicate the number of “1” s in the vertical direction (column) and horizontal direction (row) of the parity check matrix H, respectively.
- variable node calculation of Expression (1) the message input from the edge (line connecting the variable node and the check node) to which the message is to be output, respectively.
- the computation range is 1 to d v -1 or 1 to d c -1.
- the check node calculation of equation (2) actually creates a table of function R (v 1 , v 2 ) shown in equation (3) defined by one output for two inputs v 1 and v 2 in advance. In addition, this is performed by using it continuously (recursively) as shown in Equation (4).
- step S12 the variable k is further incremented by “1”, and the process proceeds to step S13.
- step S13 it is determined whether or not the variable k is larger than a predetermined iterative decoding count C. If it is determined in step S13 that the variable k is not greater than C, the process returns to step S12, and thereafter the same processing is repeated.
- step S13 determines whether the variable k is larger than C. If it is determined in step S13 that the variable k is larger than C, the process proceeds to step S14, and a message v i as a decoding result to be finally output is obtained by performing the calculation shown in equation (5). And the LDPC code decoding process ends.
- equation (5) is performed using messages u j from all branches connected to the variable node.
- FIG. 3 shows an example of a parity check matrix H of a (3, 6) LDPC code (coding rate 1/2, code length 12).
- the column weight is 3 and the row weight is 6, as in FIG.
- FIG. 4 shows a Tanner graph of the check matrix H in FIG.
- a plus “+” represents a check node
- Check nodes and variable nodes correspond to the rows and columns of the parity check matrix H, respectively.
- the connection between the check node and the variable node is an edge, and corresponds to “1” of the check matrix element.
- the branch represents that the sign bit corresponding to the variable node has a constraint condition corresponding to the check node.
- FIG. 5 shows variable node calculation performed in the variable node.
- the message v i corresponding to the branch to be calculated is the variable node of the formula (1) using the messages u 1 and u 2 from the remaining branches connected to the variable node and the received value u 0i. It is obtained by calculation. Messages corresponding to other branches are obtained in the same manner.
- FIG. 6 shows a check node operation performed at the check node.
- sign (x) is 1 when x ⁇ 0, and ⁇ 1 when x ⁇ 0.
- Equation (6) can be transformed into Equation (7).
- the message u j corresponding to the branch to be calculated is the messages v 1 , v 2 , v 3 , v 4 , v from the remaining branches connected to the check node. It is obtained by the check node calculation of Equation (7) using 5 . Messages corresponding to other branches are obtained in the same manner.
- ⁇ (x) and ⁇ ⁇ 1 (x) are mounted on hardware, they may be mounted using a LUT (Look Up Table), but both are the same LUT.
- DVB-S.2 ETSI EN 302 307 V1.2.1 (2009-08)
- the LDPC code is a symbol of quadrature modulation (digital modulation) such as QPSK (Quadrature Phase Shift Keying). (Symbolized), and the symbol is mapped to a signal point and transmitted.
- quadrature modulation digital modulation
- QPSK Quadrature Phase Shift Keying
- an LDPC code having a coding rate that can easily set a certain number of coding rates (for example, more than the number required for data transmission).
- the error resistance is high (strong), that is, the error rate is good, regardless of the coding rate of the LDPC code.
- the present technology has been made in view of such a situation, and is capable of providing an LDPC code having a good error rate.
- the first data processing apparatus or data processing method according to the present technology converts an information bit into an LDPC code having a code length of 64800 bits and a code rate of 24/30 based on a parity check matrix of an LDPC (Low Density Parity Check) code.
- LDPC Low Density Parity Check
- An encoding unit or encoding step for encoding wherein the LDPC code includes information bits and parity bits, and the parity check matrix includes an information matrix unit corresponding to the information bits and a parity matrix unit corresponding to the parity bits
- the information matrix part is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table that represents the position of one element of the information matrix part for every 360 columns, 1504 2103 2621 2840 3869 4594 5246 6314 7327 7364 10425 11934 12898 12954 27 1903 3923 4513 7812 8098 8428 9789 10519 11345 12032 12157 12573 12930 17 191 660 2451 2475 2976 3398 3616 5769 6724 8641 10046 11552 12842 13 1366 4993 6468 7689 8563 9131 10012 10914 11574 11837 12203 12715 12946 432 872 2603 3286 3306 33
- the second data processing apparatus or the data processing method of the present technology includes a decoding unit that decodes an LDPC code having a code length of 64,800 bits and a code rate of 24/30 based on a parity check matrix of an LDPC (Low Density Parity Check) code Or the decoding step, wherein the LDPC code includes information bits and parity bits, and the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, and the information matrix Part is represented by a parity check matrix initial value table, the parity check matrix initial value table is a table that represents the position of one element of the information matrix part every 360 columns, 1504 2103 2621 2840 3869 4594 5246 6314 7327 7364 10425 11934 12898 12954 27 1903 3923 4513 7812 8098 8428 9789 10519 11345 12032 12157 12573 12930 17 191 660 2451 2475 2976 3398
- the third data processing apparatus or data processing method of the present technology converts an information bit into an LDPC code having a code length of 64,800 bits and a code rate of 25/30 based on a check matrix of an LDPC (Low Density Parity Check) code.
- LDPC Low Density Parity Check
- An encoding unit or encoding step for encoding wherein the LDPC code includes information bits and parity bits, and the parity check matrix includes an information matrix unit corresponding to the information bits and a parity matrix unit corresponding to the parity bits
- the information matrix part is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table that represents the position of one element of the information matrix part for every 360 columns, 1860 2354 3967 4292 4488 5243 5373 5766 8378 9111 10468 10505 10774 24 2266 2380 3282 4255 4779 8729 9140 9566 10102 10661 10711 10797 605 650 1108 1669 2251 3133 5847 6197 6902 7545 10521 10600 10773 1016 1428 1612 2335 3102 3810 4926 5953 9964 10246 10569 10734 10784 3195 6308 8029 9030 9397 9461 9833 10239 10499
- a fourth data processing apparatus or data processing method of the present technology includes a decoding unit that decodes an LDPC code having a code length of 64,800 bits and a code rate of 25/30 based on a parity check matrix of an LDPC (Low Density Parity Check) code Or the decoding step, wherein the LDPC code includes information bits and parity bits, and the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, and the information matrix Part is represented by a parity check matrix initial value table, the parity check matrix initial value table is a table that represents the position of one element of the information matrix part every 360 columns, 1860 2354 3967 4292 4488 5243 5373 5766 8378 9111 10468 10505 10774 24 2266 2380 3282 4255 4779 8729 9140 9566 10102 10661 10711 10797 605 650 1108 1669 2251 3133 5847 6197 6902 7545
- the fifth data processing apparatus or data processing method according to the present technology converts an information bit into an LDPC code having a code length of 64,800 bits and a code rate of 26/30 based on a parity check matrix of an LDPC (Low Density Parity Check) code.
- LDPC Low Density Parity Check
- An encoding unit or encoding step for encoding wherein the LDPC code includes information bits and parity bits, and the parity check matrix includes an information matrix unit corresponding to the information bits and a parity matrix unit corresponding to the parity bits
- the information matrix part is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table that represents the position of one element of the information matrix part for every 360 columns, 142 2307 2598 2650 4028 4434 5781 5881 6016 6323 6681 6698 8125 2932 4928 5248 5256 5983 6773 6828 7789 8426 8494 8534 8539 8583 899 3295 3833 5399 6820 7400 7753 7890 8109 8451 8529 8564 8602 21 3060 4720 5429 5636 5927 6966 8110 8170 8247 8355 8365 8616 20 1745 2838 3799 4380 4418 4646 5059 7343 81
- a sixth data processing apparatus or data processing method of the present technology includes a decoding unit that decodes an LDPC code having a code length of 64,800 bits and a code rate of 26/30 based on a parity check matrix of an LDPC (Low Density Parity Check) code Or the decoding step, wherein the LDPC code includes information bits and parity bits, and the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, and the information matrix Part is represented by a parity check matrix initial value table, the parity check matrix initial value table is a table that represents the position of one element of the information matrix part every 360 columns, 142 2307 2598 2650 4028 4434 5781 5881 6016 6323 6681 6698 8125 2932 4928 5248 5256 5983 6773 6828 7789 8426 8494 8534 8539 8583 899 3295 3833 5399 6820 7400 7753 7890 8
- the seventh data processing apparatus or the data processing method of the present technology converts an information bit into an LDPC code having a code length of 64,800 bits and a code rate of 27/30 based on a parity check matrix of an LDPC (Low Density Parity Check) code.
- LDPC Low Density Parity Check
- the parity check matrix initial value table is a table that represents the position of one element of the information matrix part for every 360 columns, 658 706 898 1149 2577 2622 2772 3266 3329 5243 6079 6271 289 784 1682 3584 3995 4821 4856 5063 5974 6168 6437 6453 658 1426 2043 2065 2986 4118 4284 5394 5444 5477 5727 6018 641 928 1225 2841 4052 4840 4992 5268 5533 6249 6461 6475 2312 2917 3713 3849 4059 4241 4610 5440 5727 6101 6397 6444 1165 1592 1891 2154 3981 4817 5181 5748 5788 6012
- An eighth data processing apparatus or data processing method includes a decoding unit that decodes an LDPC code having a code length of 64,800 bits and a code rate of 27/30 based on a parity check matrix of an LDPC (Low Density Parity Check) code Or the decoding step, wherein the LDPC code includes information bits and parity bits, and the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, and the information matrix Part is represented by a parity check matrix initial value table, the parity check matrix initial value table is a table that represents the position of one element of the information matrix part every 360 columns, 658 706 898 1149 2577 2622 2772 3266 3329 5243 6079 6271 289 784 1682 3584 3995 4821 4856 5063 5974 6168 6437 6453 658 1426 2043 2065 2986 4118 4284 5394 5444 5477 5727 6018 641 928 1225 2841
- the ninth data processing apparatus or data processing method of the present technology converts an information bit into an LDPC code having a code length of 64,800 bits and a code rate of 28/30 based on a parity check matrix of an LDPC (Low Density Parity Check) code.
- LDPC Low Density Parity Check
- An encoding unit or encoding step for encoding wherein the LDPC code includes information bits and parity bits, and the check matrix is an information matrix unit corresponding to the information bits and a parity matrix unit corresponding to the parity bits
- the information matrix part is represented by a parity check matrix initial value table
- the parity check matrix initial value table is a table that represents the position of one element of the information matrix part for every 360 columns, 85 314 1602 1728 1929 2295 2729 2924 3779 4054 4276 918 1378 1838 1903 2399 2524 2937 3615 3740 4140 4213 1361 1430 2639 2648 2910 3418 3511 3543 4177 4209 4248 472 1143 1318 1545 1830 2228 2249 2256 3626 3839 3991 226 1401 2154 2318 2851 3317 3468 3944 3983 4047 4093 490 1145 1247 1851 2671 2776 3152 3229 3345 3758 3786 522 1393 1473 2196 2707 3052 3398 3814 38
- a tenth data processing apparatus or data processing method of the present technology includes a decoding unit that decodes an LDPC code having a code length of 64,800 bits and an encoding rate of 28/30 based on a parity check matrix of an LDPC (Low Density Parity Check) code Or the decoding step, wherein the LDPC code includes information bits and parity bits, and the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, and the information matrix Part is represented by a parity check matrix initial value table, the parity check matrix initial value table is a table that represents the position of one element of the information matrix part every 360 columns, 85 314 1602 1728 1929 2295 2729 2924 3779 4054 4276 918 1378 1838 1903 2399 2524 2937 3615 3740 4140 4213 1361 1430 2639 2648 2910 3418 3511 3543 4177 4209 4248 472 1143 1318 1545 1830 2228 2249 2256
- the eleventh data processing apparatus or data processing method of the present technology converts an information bit into an LDPC code having a code length of 64800 bits and a code rate of 29/30 based on a parity check matrix of an LDPC (Low Density Parity Check) code.
- LDPC Low Density Parity Check
- An encoding unit or encoding step for encoding wherein the LDPC code includes information bits and parity bits, and the parity check matrix includes an information matrix unit corresponding to the information bits and a parity matrix unit corresponding to the parity bits
- the information matrix part is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table that represents the position of one element of the information matrix part for every 360 columns, 212 499 911 940 1392 316 563 1527 2006 2077 2 1906 2043 2112 2123 537 901 1582 1812 1955 5 978 1280 1933 2145 5 2035 2044 2108 2121 5 939 1874 1974 4 1069 1758 694 2096 2106 1129 1511 1659 1564 2089 2159 2 1605 2004 474 1341 2003 103 2128 2150 1656 1993 2153 1881 2122 2138 1088 1968 2141 1 298 2073 1042 1724 2137 1253 1758 2145 1209 1566 2123 1466 2116 2155 43 2006 2049
- a twelfth data processing device or data processing method of the present technology includes a decoding unit that decodes an LDPC code having a code length of 64,800 bits and a coding rate of 29/30 based on a parity check matrix of an LDPC (Low Density Parity Check) code Or the decoding step, wherein the LDPC code includes information bits and parity bits, and the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, and the information matrix Part is represented by a parity check matrix initial value table, the parity check matrix initial value table is a table that represents the position of one element of the information matrix part every 360 columns, 212 499 911 940 1392 316 563 1527 2006 2077 2 1906 2043 2112 2123 537 901 1582 1812 1955 5 978 1280 1933 2145 5 2035 2044 2108 2121 5 939 1874 1974 4 1069 1758 694 2096 2106 1129 1511 1659 1564 20
- the information bit is 64800 bits and the coding rate is 24/30, 25/30, 26/30, 27/30, 28 It is encoded into / 30 or 29/30 LDPC code.
- LDPC Low Density Parity Check
- the code length is 64800 bits and the coding rate is 24/30, 25/30, 26/30, 27/30, 28/30.
- 29/30 LDPC codes are decoded.
- the LDPC code includes information bits and parity bits
- the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits
- the information matrix portion is an initial parity check matrix.
- the parity check matrix initial value table is a table that represents the position of one element of the information matrix portion for every 360 columns.
- the parity check matrix initial value table with a coding rate of 24/30 is 1504 2103 2621 2840 3869 4594 5246 6314 7327 7364 10425 11934 12898 12954 27 1903 3923 4513 7812 8098 8428 9789 10519 11345 12032 12157 12573 12930 17 191 660 2451 2475 2976 3398 3616 5769 6724 8641 10046 11552 12842 13 1366 4993 6468 7689 8563 9131 10012 10914 11574 11837 12203 12715 12946 432 872 2603 3286 3306 3385 4137 5563 7540 9339 9948 12315 12656 12929 1113 1394 4104 4186 7240 8827 11522 11833 12359 12363 12629 12821 12904 12946 14 441 1432 1677 2432 8981 11478 11507 12599 12783 12793 12912 129
- the parity check matrix initial value table with a coding rate of 25/30 is 1860 2354 3967 4292 4488 5243 5373 5766 8378 9111 10468 10505 10774 24 2266 2380 3282 4255 4779 8729 9140 9566 10102 10661 10711 10797 605 650 1108 1669 2251 3133 5847 6197 6902 7545 10521 10600 10773 1016 1428 1612 2335 3102 3810 4926 5953 9964 10246 10569 10734 10784 3195 6308 8029 9030 9397 9461 9833 10239 10499 10675 10736 10757 10773 2 27 3641 4566 7332 9318 9323 9916 10365 10438 10561 10581 10750 2405 2458 4820 6232 6254 6347 7139 7474 8623 8779 8798 10747 10794 3164 4736 6474 7162 7420 7517
- the parity check matrix initial value table with a coding rate of 26/30 is 142 2307 2598 2650 4028 4434 5781 5881 6016 6323 6681 6698 8125 2932 4928 5248 5256 5983 6773 6828 7789 8426 8494 8534 8539 8583 899 3295 3833 5399 6820 7400 7753 7890 8109 8451 8529 8564 8602 21 3060 4720 5429 5636 5927 6966 8110 8170 8247 8355 8365 8616 20 1745 2838 3799 4380 4418 4646 5059 7343 8161 8302 8456 8631 9 6274 6725 6792 7195 7333 8027 8186 8209 8273 8442 8548 8632 494 1365 2405 3799 5188 5291 7644 7926 8139 8458 8504 8594 8625 192 574 1179 4387 4695 5089 5831 7673
- the parity check matrix initial value table with a coding rate of 27/30 is 658 706 898 1149 2577 2622 2772 3266 3329 5243 6079 6271 289 784 1682 3584 3995 4821 4856 5063 5974 6168 6437 6453 658 1426 2043 2065 2986 4118 4284 5394 5444 5477 5727 6018 641 928 1225 2841 4052 4840 4992 5268 5533 6249 6461 6475 2312 2917 3713 3849 4059 4241 4610 5440 5727 6101 6397 6444 1165 1592 1891 2154 3981 4817 5181 5748 5788 6012 6266 6350 13 2758 3069 4233 4697 5100 5279 5677 5919 5969 6280 6422 818 1500 2125 2340 3774 4707 4901 5170 5744 6008 6316 6353 857 3054 3409 3496 3704 4868 5326 6211 6292 6356 6367 6381 0 7 12
- the parity check matrix initial value table with a coding rate of 28/30 is 85 314 1602 1728 1929 2295 2729 2924 3779 4054 4276 918 1378 1838 1903 2399 2524 2937 3615 3740 4140 4213 1361 1430 2639 2648 2910 3418 3511 3543 4177 4209 4248 472 1143 1318 1545 1830 2228 2249 2256 3626 3839 3991 226 1401 2154 2318 2851 3317 3468 3944 3983 4047 4093 490 1145 1247 1851 2671 2776 3152 3229 3345 3758 3786 522 1393 1473 2196 2707 3052 3398 3814 3827 4148 4301 417 1982 2176 2336 2459 2806 3005 3771 3870 4080 4243 112 1040 1596 1621 1685 2118 2571 3359 3945 4034 4171 646 1705 2181 2439 2808 2851 2987 3044 3494 4049 4312 6 11 115 245 663 1773 2624 3444 3601 3952
- the parity check matrix initial value table with a coding rate of 29/30 is 212 499 911 940 1392 316 563 1527 2006 2077 2 1906 2043 2112 2123 537 901 1582 1812 1955 5 978 1280 1933 2145 5 2035 2044 2108 2121 5 939 1874 1974 4 1069 1758 694 2096 2106 1129 1511 1659 1564 2089 2159 2 1605 2004 474 1341 2003 103 2128 2150 1656 1993 2153 1881 2122 2138 1088 1968 2141 1 298 2073 1042 1724 2137 1253 1758 2145 1209 1566 2123 1466 2116 2155 43 2006 2049 592 1806 1865 3 143 2149 1158 1448 2002 1422 2152 2157 485 2119 2150 371 1831 2086 204 2042 2151 174 544 974 1469 1795 1995 13 708 1683 5 1144 2030 486 1309 1576 165 2030 2147 504 2073 2126 263 565 1798 239 861 1861 8
- the data processing apparatus may be an independent apparatus or an internal block constituting one apparatus.
- This technology can provide an LDPC code with a good error rate.
- FIG. 3 is a block diagram illustrating a configuration example of a transmission device 11.
- FIG. 3 is a block diagram illustrating a configuration example of a bit interleaver 116.
- FIG. It is a figure which shows a check matrix.
- FIG. 6 is a diagram for explaining processing of a demultiplexer 25.
- FIG. 6 is a diagram for explaining processing of a demultiplexer 25. It is a figure which shows the Tanner graph about decoding of an LDPC code. And the parity matrix H T having a staircase structure, a diagram illustrating a Tanner graph corresponding to the parity matrix H T.
- An error rate obtained by the simulation is a diagram showing the relationship between the Doppler frequency f d of the flutter.
- An error rate obtained by the simulation is a diagram showing the relationship between the Doppler frequency f d of the flutter.
- 3 is a block diagram illustrating a configuration example of an LDPC encoder 115.
- FIG. 5 is a flowchart for explaining processing of an LDPC encoder 115.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 1/4 and the code length 16200. It is a figure explaining the method of calculating
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 2/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 3/30 and the code length 64800.
- Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 4/30 and the code length 64800.
- FIG. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 5/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 6/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 7/30 and the code length 64800.
- Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 8/30 and the code length 64800.
- FIG. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 8/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 9/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 9/30 and the code length 64800.
- Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 10/30 and the code length 64800.
- FIG. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 10/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 11/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 11/30 and the code length 64800.
- Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 12/30 and the code length 64800.
- FIG. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 12/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 13/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 13/30 and the code length 64800.
- Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 14/30 and the code length 64800.
- FIG. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 14/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 15/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 15/30 and the code length 64800.
- Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 16/30 and the code length 64800.
- FIG. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 16/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 16/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 17/30 and the code length 64800.
- Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 17/30 and the code length 64800.
- Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 17/30 and the code length 64800.
- FIG. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 17/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 18/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 18/30 and the code length 64800.
- Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 18/30 and the code length 64800.
- Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 18/30 and the code length 64800.
- FIG. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 19/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 19/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 19/30 and the code length 64800.
- Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 20/30 and the code length 64800.
- FIG. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 20/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 20/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 21/30 and the code length 64800.
- Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 21/30 and the code length 64800.
- Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 21/30 and the code length 64800.
- FIG. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 21/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 22/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 22/30 and the code length 64800.
- Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 22/30 and the code length 64800.
- Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 22/30 and the code length 64800.
- FIG. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 23/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 23/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 23/30 and the code length 64800.
- Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 24/30 and the code length 64800.
- FIG. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 24/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 24/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 25/30 and the code length 64800.
- Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 25/30 and the code length 64800.
- Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 25/30 and the code length 64800.
- FIG. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 25/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 26/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 26/30 and the code length 64800.
- Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 26/30 and the code length 64800.
- Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 26/30 and the code length 64800.
- FIG. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 27/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 27/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 27/30 and the code length 64800.
- Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 27/30 and the code length 64800.
- Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 27/30 and the code length 64800.
- FIG. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 28/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 28/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 28/30 and the code length 64800.
- Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 28/30 and the code length 64800.
- Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 28/30 and the code length 64800.
- FIG. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 29/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 29/30 and the code length 64800.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 29/30 and the code length 64800.
- Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 29/30 and the code length 64800. It is a figure which shows the example of the Tanner graph of the ensemble of a degree sequence that column weight is 3 and row weight is 6.
- FIG. 38 shows the example of the Tanner graph of the ensemble of a degree sequence that column weight is 3 and row weight is 6.
- FIG. 12 is a flowchart for describing processing performed by a QAM decoder 164, a bit deinterleaver 165, and an LDPC decoder 166. It is a figure which shows the example of the check matrix of a LDPC code. It is a figure which shows the matrix (conversion test matrix) which performed row substitution and column substitution to the check matrix.
- FIG. 3 is a block diagram illustrating a configuration example of an LDPC decoder 166.
- FIG. It is a figure explaining the process of the multiplexer 54 which comprises the bit deinterleaver 165.
- FIG. It is a figure explaining the process of the column twist deinterleaver.
- FIG. It is a block diagram which shows the 1st structural example of the receiving system which can apply the receiving device.
- FIG. 18 is a block diagram illustrating a configuration example of an embodiment of a computer to which the present technology is applied.
- FIG. 7 shows a transmission system to which the present technology is applied (a system is a logical collection of a plurality of devices, regardless of whether or not each component device is in the same housing). The structural example of embodiment is shown.
- the transmission system includes a transmission device 11 and a reception device 12.
- the transmission device 11 transmits (broadcasts) (transmits) a television broadcast program, for example. That is, the transmission device 11 encodes target data to be transmitted, such as image data and audio data as a program, into an LDPC code, for example, a satellite line, a terrestrial wave, a cable (wired line), or the like. It transmits via the communication path 13.
- target data to be transmitted such as image data and audio data as a program
- an LDPC code for example, a satellite line, a terrestrial wave, a cable (wired line), or the like. It transmits via the communication path 13.
- the receiving device 12 receives the LDPC code transmitted from the transmitting device 11 via the communication path 13, decodes it into the target data, and outputs it.
- the LDPC code used in the transmission system of FIG. 7 exhibits extremely high capability in an AWGN (Additive White Gaussian Noise) channel.
- AWGN Additional White Gaussian Noise
- a burst error or erasure may occur in the communication path 13.
- D / U Desired to Undesired Ratio
- Desired main path power
- a burst error may occur due to the state of the wiring from the receiving unit (not shown) such as an antenna that receives a signal from the transmitting device 11 to the receiving device 12 on the receiving device 12 side or the instability of the power supply of the receiving device 12. May occur.
- the code bit (received value u 0i of the LDPC code) at the variable node corresponding to the column of the parity check matrix H and thus the code bit of the LDPC code. Since the variable node operation of the expression (1) with the addition of) is performed, if an error occurs in the sign bit used for the variable node operation, the accuracy of the required message is reduced.
- the check node performs the check node calculation of Expression (7) using the message obtained by the variable node connected to the check node, so that a plurality of connected variable nodes ( When the number of check nodes in which the error (including erasure) of the code bits of the LDPC code corresponding to) simultaneously increases, the decoding performance deteriorates.
- the check node sends a message with an equal probability of a probability of 0 and a probability of 1 to all the variable nodes. return.
- a check node that returns an equiprobable message does not contribute to one decoding process (one set of variable node calculation and check node calculation), and as a result, requires a large number of repetitions of the decoding process. As a result, the decoding performance deteriorates, and the power consumption of the receiving apparatus 12 that decodes the LDPC code increases.
- FIG. 8 is a block diagram illustrating a configuration example of the transmission device 11 of FIG.
- one or more input streams (Input Streams) as target data are supplied to a Mode Adaptation / Multiplexer 111.
- the mode adaptation / multiplexer 111 performs processing such as mode selection and multiplexing of one or more input streams supplied thereto as necessary, and supplies the resulting data to a padder 112. .
- the padder 112 performs necessary zero padding (Null insertion) on the data from the mode adaptation / multiplexer 111 and supplies the resulting data to the BB scrambler 113.
- the BB scrambler 113 subjects the data from the padder 112 to BB scramble (Base-Band Scrambling), and supplies the resulting data to a BCH encoder (BCH encoder) 114.
- BCH encoder BCH encoder
- the BCH encoder 114 BCH-encodes the data from the BB scrambler 113, and supplies the resulting data to an LDPC encoder 115 as LDPC target data that is an LDPC encoding target.
- the LDPC encoder 115 performs LDPC encoding on the LDPC target data from the BCH encoder 114 according to a parity check matrix in which a parity matrix that is a part corresponding to the parity bits of the LDPC code has a staircase structure. Output LDPC code as information bits.
- the LDPC encoder 115 sets the LDPC target data to the LDPC (corresponding to the check matrix) defined in a predetermined standard such as DVB-S.2, DVB-T.2, or DVB-C.2.
- LDPC encoding is performed to encode a code, a predetermined LDPC code (corresponding to the parity check matrix), and the resulting LDPC code is output.
- the LDPC code defined in the DVB-S.2, DVB-T.2, and DVB-C.2 standards is an IRA (Irregular Repeat Accumulate) code, and the parity in the parity check matrix of the LDPC code
- the matrix has a staircase structure. The parity matrix and the staircase structure will be described later.
- IRA codes for example, “Irregular Repeat-Accumulate Codes,” H. Jin, A. Khandekar, and R. J. McEliece, in Proceedings of 2nd International Symposium on Turbo codes and Related Topics-8 , Sept. 2000.
- the LDPC code output from the LDPC encoder 115 is supplied to the bit interleaver 116.
- the bit interleaver 116 performs bit interleaving described later on the LDPC code from the LDPC encoder 115, and supplies the LDPC code after the bit interleaving to a QAM encoder (QAM encoder) 117.
- QAM encoder QAM encoder
- the QAM encoder 117 maps the LDPC code from the bit interleaver 116 to a signal point representing one symbol of orthogonal modulation in units of one or more code bits (symbol unit) of the LDPC code and performs orthogonal modulation ( Multilevel modulation).
- the QAM encoder 117 converts the LDPC code from the bit interleaver 116 into an IQ plane (IQ constellation) defined by an I axis representing an I component in phase with the carrier and a Q axis representing a Q component orthogonal to the carrier. ) Perform the quadrature modulation by mapping to the signal points determined by the modulation method that performs the quadrature modulation of the LDPC code.
- IQ plane IQ constellation
- a modulation method of quadrature modulation performed by the QAM encoder 117 for example, a modulation method defined in the DVB-S.2, DVB-T.2, DVB-C.2 standard, or the like Modulation method, for example, BPSK (Binary Phase Shift Keying), QPSK (Quadrature Phase Shift Shift Keying), 16APSK (Amplitude Phase Shift-Keying), 32APSK, 16QAM (Quadrature Amplitude Modulation), 64QAM, 256QAM, 1024QAM, 4096QAM, 4PAM (Pulse Amplitude Modulation) etc.
- Which modulation method is used to perform quadrature modulation in the QAM encoder 117 is set in advance in accordance with, for example, the operation of the operator of the transmission apparatus 11.
- Time Interleaver Time Interleaver
- the time interleaver 118 performs time interleaving (interleaving in the time direction) on the data (symbol) from the QAM encoder 117, and obtains the resulting data as a MISO / MIMO encoder (MISO / MIMO encoder) 119. To supply.
- the MISO / MIMO encoder 119 performs space-time coding on the data (symbol) from the time interleaver 118 and supplies it to a frequency interleaver 120.
- the frequency interleaver 120 performs frequency interleaving (interleaving in the frequency direction) on the data (symbol) from the MISO / MIMO encoder 119 and supplies the data to a frame builder / resource allocation unit (Frame Builder & Resource Allocation) 131. To do.
- the BCH encoder 121 is supplied with control data (signalling) for transmission control such as BB signaling (Base Band Signaling) (BB Header).
- BB signaling Basic Band Signaling
- the BCH encoder 121 performs BCH encoding on the control data supplied thereto in the same manner as the BCH encoder 114, and supplies the resulting data to the LDPC encoder 122.
- the LDPC encoder 122 performs LDPC encoding on the data from the BCH encoder 121 as LDPC target data in the same manner as the LDPC encoder 115, and supplies the resulting LDPC code to the QAM encoder 123.
- the QAM encoder 123 converts the LDPC code from the LDPC encoder 122 into a signal point representing one symbol of orthogonal modulation in units of one or more code bits (symbol unit) of the LDPC code.
- the orthogonal modulation is performed by mapping, and data (symbol) obtained as a result is supplied to the frequency interleaver 124.
- the frequency interleaver 124 performs frequency interleaving on the data (symbol) from the QAM encoder 123 in units of symbols and supplies the data to the frame builder / resource allocation unit 131.
- the frame builder / resource allocation unit 131 inserts pilot symbols at necessary positions of the data (symbols) from the frequency interleavers 120 and 124, and from the resulting data (symbols), a predetermined number
- a frame composed of a number of symbols for example, a PL (Physical Layer) frame, a T2 frame, a C2 frame, etc.
- OFDM generation OFDM generation
- the OFDM generation unit 132 generates an OFDM signal corresponding to the frame from the frame from the frame builder / resource allocation unit 131, and transmits the OFDM signal via the communication path 13 (FIG. 7).
- the transmission apparatus 11 is configured without providing some of the blocks illustrated in FIG. 8 such as the time interleaver 118, the MISO / MIMO encoder 119, the frequency interleaver 120, and the frequency interleaver 124, for example. Can do.
- FIG. 9 shows a configuration example of the bit interleaver 116 of FIG.
- the bit interleaver 116 is a data processing device that interleaves data, and includes a parity interleaver 23, a column twist interleaver 24, and a demultiplexer (DEMUX) 25. Note that the bit interleaver 116 can be configured without providing one or both of the parity interleaver 23 and the column twist interleaver 24.
- the parity interleaver 23 performs parity interleaving for interleaving the parity bits of the LDPC code from the LDPC encoder 115 to the positions of other parity bits, and supplies the LDPC code after the parity interleaving to the column twist interleaver 24.
- the column twist interleaver 24 performs column twist interleaving on the LDPC code from the parity interleaver 23 and supplies the LDPC code after the column twist interleaving to the demultiplexer 25.
- the LDPC code is transmitted in the QAM encoder 117 of FIG. 8 by mapping one or more code bits of the LDPC code to a signal point representing one symbol of orthogonal modulation.
- the column twist interleaver 24 uses a parity interleaver 23 so that a plurality of code bits of the LDPC code corresponding to 1 in any one row of the parity check matrix used in the LDPC encoder 115 are not included in one symbol. As rearrangement processing for rearranging the code bits of the LDPC code, for example, column twist interleaving as described later is performed.
- the demultiplexer 25 obtains an LDPC code with enhanced resistance to AWGN by performing an exchange process for exchanging positions of two or more code bits of the LDPC code as a symbol for the LDPC code from the column twist interleaver 24. Then, the demultiplexer 25 supplies two or more code bits of the LDPC code obtained by the replacement process to the QAM encoder 117 (FIG. 8) as a symbol.
- FIG. 10 shows a parity check matrix H used for LDPC encoding by the LDPC encoder 115 of FIG.
- LDGM Low-Density Generation Matrix
- the number of information bits and the number of parity bits in the code bits of one LDPC code are referred to as information length K and parity length M, respectively, and one LDPC.
- the information length K and the parity length M for an LDPC code having a certain code length N are determined by the coding rate.
- the parity check matrix H is an M ⁇ N matrix with rows ⁇ columns. Then, the information matrix H A, becomes the matrix of M ⁇ K, the parity matrix H T is a matrix of M ⁇ M.
- DVB-S.2 shows a parity matrix H T of the parity DVB-T.2, and parity check matrix H of an LDPC code prescribed in DVB-C.2 standards.
- DVB-T.2 like parity matrix H T of the parity check matrix H of an LDPC code of which is specified in the Standard, as shown in FIG. 11, first element is, so to speak a matrix of step structure arranged stepwise (lower bidiagonal matrix).
- the row weight of the parity matrix H T is 1 for the first row and 2 for all the remaining rows.
- the column weight is 1 for the last column and 2 for all the remaining columns.
- LDPC codes of the check matrix H the parity matrix H T has a staircase structure can be using the check matrix H, readily produced.
- an LDPC code (one codeword), together represented by a row vector c, and column vector obtained by transposing the row vector is represented as c T. Further, in the row vector c which is an LDPC code, the information bit portion is represented by the row vector A, and the parity bit portion is represented by the row vector T.
- FIG. 12 is a diagram for explaining a parity check matrix H of an LDPC code defined in a standard such as DVB-T.2.
- the column weight is X, and for the subsequent K3 column, the column weight is 3, and then For the M-1 column, the column weight is 2, and for the last column, the column weight is 1.
- KX + K3 + M-1 + 1 is equal to the code length N.
- FIG. 13 is a diagram showing the number of columns KX, K3, and M, and the column weight X for each coding rate r of the LDPC code defined in the DVB-T.2 standard and the like.
- Standards such as DVB-T.2 specify LDPC codes with code length N of 64800 bits and 16200 bits.
- LDPC code having a code length N of 64,800 bits 11 coding rates (nominal rates) 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3 / 4, 4/5, 5/6, 8/9, and 9/10 are defined, and for an LDPC code having a code length N of 16200 bits, 10 coding rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, and 8/9 are specified.
- the code length N of 64800 bits is also referred to as 64k bits
- the code length N of 16200 bits is also referred to as 16k bits.
- the column weight on the head side (left side) tends to be large.
- the LDPC code corresponding to H the first code bit tends to be more resistant to errors (tolerant to errors), and the last code bit tends to be weaker to errors.
- FIG. 14 shows an example of arrangement of 16 symbols (corresponding signal points) on the IQ plane when 16QAM is performed by the QAM encoder 117 of FIG.
- a in FIG. 14 shows a 16QAM symbol of DVB-T.2.
- the 16 symbols are arranged so that the I direction ⁇ Q direction is a 4 ⁇ 4 square shape with the origin of the IQ plane as the center.
- bit y i + 1 bit from the most significant bit in the bit string represented by one symbol is represented as bit y i
- the four bits represented by one symbol of 16QAM are bit y 0 in order from the most significant bit. , y 1 , y 2 , y 3 .
- 4 code bits of the LDPC code is (symbolized) into 4-bit y 0 to y 3 symbol (symbol value).
- FIG. 14B shows bit boundaries for each of 4 bits (hereinafter also referred to as symbol bits) y 0 to y 3 represented by a 16QAM symbol.
- the symbol bit y i represented by a symbol is more likely to be erroneous (lower error probability) the more symbols are away from the bit boundary, and more likely to be error (higher error probability) as there are more symbols near the bit boundary.
- strong to errors a bit that is hard to error
- weak to errors a bit that is easy to error
- 4 symbol bits y 0 to y 3 of a 16QAM symbol 4 symbol bits y 0 to y 3 of a 16QAM symbol .
- the most significant symbol bit y 0 and the second symbol bit y 1 are strong bits
- the third symbol bit y 2 and the fourth symbol bit y 3 are weak bits. .
- 15 to 17 show examples of arrangement of 64 symbols (corresponding signal points) on the IQ plane when 64QAM is performed by the QAM encoder 117 of FIG. 8, that is, 16QAM of DVB-T.2. The symbol is shown.
- One symbol bit of 64QAM can be expressed as bits y 0 , y 1 , y 2 , y 3 , y 4 , y 5 in order from the most significant bit.
- the 6 code bits of the LDPC code are the symbol bit y 0 no 6-bit to the symbol y 5.
- FIG. 15 shows bit boundaries for the most significant symbol bit y 0 and the second symbol bit y 1 among the symbol bits y 0 to y 5 of the 64QAM symbol, and FIG. th symbol bit y 2, the bit boundaries for the fourth symbol bit y 3, respectively, FIG. 17, the fifth symbol bit y 4, the bit boundaries for the sixth symbol bit y 5, respectively, each Show.
- the symbol bits y 0 of the uppermost bit boundaries for the second symbol bit y 1, respectively, has at one place. Also, as shown in FIG. 16, there are two bit boundaries for each of the third symbol bit y 2 and the fourth symbol bit y 3 , and as shown in FIG. 17, the fifth symbol bit There are four bit boundaries for bit y 4 and sixth symbol bit y 5 .
- the most significant symbol bit y 0 and the second symbol bit y 1 are strong bits, and the third symbol bits y 2 and 4 th symbol bit y 3 has become a strong bit to the next.
- the fifth symbol bit y 4 and the sixth symbol bit y 5 are weak bits.
- FIG. 18 shows an arrangement of four symbols (corresponding signal points) on the IQ plane when a satellite channel is adopted as the communication path 13 (FIG. 7) and QPSK is performed by the QAM encoder 117 of FIG. It is a figure which shows the example, ie, the symbol of QPSK of DVB-S.2, for example.
- a symbol is mapped to one of four signal points on a circle with a radius ⁇ of 1 centered on the origin on the IQ plane.
- FIG. 19 shows an example of arrangement of 8 symbols on the IQ plane when a satellite channel is employed as the communication path 13 (FIG. 7) and 8PSK is performed by the QAM encoder 117 of FIG. 8, that is, for example, DVB It is a figure which shows the symbol of 8PSK of -S.2.
- DVB-S.2 8PSK a symbol is mapped to one of eight signal points on the circumference of a circle with a radius ⁇ of 1 centered on the origin on the IQ plane.
- FIG. 20 shows an example of arrangement of 16 symbols on the IQ plane when a satellite channel is adopted as the communication path 13 (FIG. 7) and 16 APSK is performed by the QAM encoder 117 of FIG. 8, that is, for example, DVB It is a figure which shows the symbol of 16APSK of -S.2.
- 20A shows the arrangement of 16 APSK signal points in DVB-S.2.
- a symbol has four signal points on the circumference of a circle with a radius of R 1 centered at the origin on the IQ plane, and a radius of R 2 (> R 1 ).
- the 12 signal points on the circumference of the circle are mapped to any one of 16 signal points in total.
- the ratio ⁇ between the radii R 2 and R 1 is different for each coding rate.
- FIG. 21 shows an example of arrangement of 32 symbols on the IQ plane when a satellite channel is employed as the communication path 13 (FIG. 7) and 32APSK is performed by the QAM encoder 117 of FIG. 8, that is, for example, DVB It is a figure which shows the symbol of -32 APSK of -S.2.
- 21A shows the arrangement of the 32APSK signal points of DVB-S.2.
- a symbol consists of four signal points on the circumference of a circle with a radius of R 1 centered at the origin on the IQ plane and a circle with a radius of R 2 (> R 1 ). 12 signal points on the circumference and 16 signal points on the circumference of the circle having a radius of R 3 (> R 2 ) are mapped to any one of 32 signal points in total.
- the ratio gamma 1 and radius R 2 and R 1 and the radius R 3 and the ratio gamma 2 and R 1 are different for each code rate.
- the LDPC code output from the LDPC encoder 115 includes a code bit that is resistant to errors and a code bit that is vulnerable to errors.
- the symbol bits of the orthogonal modulation symbols performed by the QAM encoder 117 include strong bits and weak bits.
- FIG. 22 is a diagram for explaining the processing of the demultiplexer 25 in FIG.
- a in FIG. 22 shows a functional configuration example of the demultiplexer 25.
- the demultiplexer 25 includes a memory 31 and a replacement unit 32.
- the memory 31 is supplied with the LDPC code from the LDPC encoder 115.
- the memory 31 has a storage capacity for storing mb bits in the row (horizontal) direction and N / (mb) bits in the column (vertical) direction, and the LDPC supplied thereto The sign bit of the code is written in the column direction, read in the row direction, and supplied to the switching unit 32.
- N information length K + parity length M
- m represents the number of code bits of an LDPC code that is one symbol
- b is a predetermined positive integer, which is a multiple used to multiply m by an integer.
- the demultiplexer 25 uses the sign bit of the LDPC code as a symbol (symbolizes), and the multiple b represents the number of symbols that the demultiplexer 25 obtains by so-called symbolization.
- FIG. 22A shows a configuration example of the demultiplexer 25 in the case where the modulation scheme is 64QAM or the like that maps symbols to any of 64 signal points. Therefore, the sign bit of the LDPC code that becomes one symbol The number of bits m is 6 bits.
- the multiple b is 1. Therefore, the memory 31 has a storage capacity of N / (6 ⁇ 1) ⁇ (6 ⁇ 1) bits in the column direction ⁇ row direction.
- the storage area of the memory 31 extending in the column direction and having a 1-bit row direction is hereinafter referred to as a column as appropriate.
- the code bits of the LDPC code are written from the top to the bottom (column direction) of the columns constituting the memory 31 from the left to the right columns.
- the sign bit When writing of the sign bit is completed to the bottom of the rightmost column, the sign bit is changed in units of 6 bits (mb bits) in the row direction from the first row of all the columns constituting the memory 31. It is read out and supplied to the replacement unit 32.
- the exchanging unit 32 performs an exchanging process of exchanging the positions of the 6-bit code bits from the memory 31, and the 6 bits obtained as a result are replaced with 6 symbol bits y 0 , y 1 , y 2 , y representing one symbol of 64QAM. 3, and outputs a y 4, y 5.
- mb bits (6 bits in this case) of code bits are read from the memory 31 in the row direction, and the i-th bit from the most significant bit of the mb bits of code bits read from the memory 31 is read out.
- bit b i the 6-bit code bits read out from the memory 31 in the row direction are bits b 0 , It can be expressed as b 1 , b 2 , b 3 , b 4 , b 5 .
- the sign bit in the direction of bit b 0 is a sign bit that is resistant to errors in the relationship of the column weights described in FIGS. 12 and 13, and the sign bit in the direction of bit b 5 is a sign that is vulnerable to errors. It is a bit.
- the 6-bit code bits b 0 to b 5 from the memory 31 are assigned the error-sensitive code bits to the strong bits of the 64QAM 1-symbol symbol bits y 0 to y 5. As shown in the figure, it is possible to perform an exchange process for exchanging the positions of the 6-bit code bits b 0 to b 5 from the memory 31.
- FIG. 22B shows the first replacement method
- FIG. 22C shows the second replacement method
- FIG. 22D shows the third replacement method.
- FIG. 23 shows 64QAM or the like in which the modulation scheme maps a symbol to one of 64 signal points (therefore, the number m of code bits of an LDPC code mapped to one symbol is 6 as in FIG.
- a configuration example of the demultiplexer 25 when the multiple b is 2) and a fourth replacement method are shown.
- FIG. 23A shows the order of writing LDPC codes to the memory 31.
- the code bits of the LDPC code are written from the top to the bottom (column direction) of the columns constituting the memory 31. Is called.
- the sign bit When the writing of the sign bit is completed to the bottom of the rightmost column, the sign bit is set in units of 12 bits (mb bits) in the row direction from the first row of all the columns constituting the memory 31. It is read out and supplied to the replacement unit 32.
- the exchanging unit 32 performs an exchanging process of exchanging the positions of the 12-bit code bits from the memory 31 by the fourth exchanging method, and the 12 bits obtained as a result represent 2 symbols (b symbols) of 64QAM. 12 bits, that is, 6 symbol bit y 0 representing a symbol of 64QAM, y 1, y 2, y 3, y 4, and y 5, 6 symbol bits y 0 representing the next one symbol, y 1, y 2 , y 3 , y 4 , y 5
- B in FIG. 23 shows a fourth replacement method of the replacement processing by the replacement unit 32 in A of FIG.
- mb code bits are allocated to mb symbol bits of b consecutive symbols.
- bit (symbol bit) y i the (i + 1) -th bit from the most significant bit of the mb bit of b consecutive symbols.
- parity interleaving by the parity interleaver 23 in FIG. 9 will be described with reference to FIGS.
- FIG. 24 shows (part of) a Tanner graph of a parity check matrix of an LDPC code.
- variable nodes corresponding code bits
- all of the check nodes connected to the check node are connected.
- a message having a probability that the value is 0 and the probability that the value is 1 is returned to the variable node. For this reason, if a plurality of variable nodes connected to the same check node simultaneously become erasures or the like, the decoding performance deteriorates.
- LDPC encoder 115 of FIG. 8 outputs, LDPC code prescribed in standards such as DVB-S.2 is IRA code, parity matrix H T of the parity check matrix H, as shown in FIG. 11 It has a staircase structure.
- FIG. 25 shows a parity matrix H T having a staircase structure and a Tanner graph corresponding to the parity matrix H T.
- a in FIG. 25 shows a parity matrix H T having a staircase structure
- B in FIG. 25 shows a Tanner graph corresponding to the parity matrix H T in A in FIG.
- parity matrix H T has a staircase structure, in each row (except the first row) first element is adjacent. Therefore, in the Tanner graph of the parity matrix H T, the value of the parity matrix H T corresponding to the columns of two adjacent elements are set to 1, the two variable nodes adjacent, connected to the same check node Yes.
- the parity bits corresponding to the two adjacent variable nodes mentioned above simultaneously become an error due to a burst error, an erasure, or the like, two variable nodes corresponding to the two parity bits in error (using the parity bit). Since the check node connected to the variable node that seeks the message returns the message having the same probability of 0 and 1 to the variable node connected to the check node, the decoding performance is improved. to degrade. When the burst length (the number of parity bits that continuously cause an error) increases, the number of check nodes that return messages with equal probability increases, and the decoding performance further deteriorates.
- the parity interleaver 23 (FIG. 9) performs parity interleaving for interleaving the parity bits of the LDPC code from the LDPC encoder 115 to the positions of other parity bits in order to prevent the above-described degradation in decoding performance. .
- Figure 26 illustrates a parity matrix H T of the parity check matrix H corresponding to the LDPC code after parity interleave to the parity interleaver 23 of FIG. 9 is performed.
- the information matrix H A of the parity check matrix H corresponding to the LDPC code defined in the DVB-S.2 standard and the like output from the LDPC encoder 115 has a cyclic structure.
- a cyclic structure is a structure in which a column matches a cyclic shift of another column.For example, for each P column, the position of 1 in each row of the P column is the first of the P column.
- a structure in which the column is cyclically shifted in the column direction by a value proportional to the value q obtained by dividing the parity length M is also included.
- the P column in the cyclic structure is referred to as the number of columns in the cyclic structure unit as appropriate.
- LDPC codes having a code length N of 64800 bits and 16200 bits as LDPC codes defined in the DVB-S.2 standard.
- N 64800 bits
- 16200 bits 16200 bits
- the number P of columns in the unit of the cyclic structure is defined as 360, which is one of the divisors excluding 1 and M among the divisors of the parity length M.
- the parity interleaver 23 sets the information length to K, sets x to an integer between 0 and less than P, and sets y to an integer between 0 and less than q.
- the K + qx + y + 1-th code bit is interleaved at the position of the K + Py + x + 1-th code bit.
- the K + qx + y + 1-th code bit and the K + Py + x + 1-th code bit are both the K + 1-th code bit and the subsequent parity bits, and are therefore parity bits. According to interleaving, the position of the parity bit of the LDPC code is moved.
- variable nodes connected to the same check node are separated by the number of columns P of the cyclic structure unit, that is, 360 bits here, so the burst length is In the case of less than 360 bits, it is possible to avoid a situation in which a plurality of variable nodes connected to the same check node cause an error at the same time, and as a result, it is possible to improve resistance to burst errors.
- the LDPC code after parity interleaving that interleaves the K + qx + y + 1-th code bit at the position of the K + Py + x + 1-th code bit is K + qx + of the original parity check matrix H.
- the pseudo cyclic structure means a structure in which a part except for a part has a cyclic structure.
- the transform parity check matrix obtained by performing column replacement equivalent to parity interleaving on the parity check matrix of the LDPC code specified in the DVB-S.2 standard, etc. is 360 rows by 360 columns.
- the part the shift matrix described later
- only one element of 1 is present (it is an element of 0), and in this respect, it is not a (complete) cyclic structure but a pseudo cyclic structure.
- the conversion check matrix in FIG. 26 replaces the original check matrix H with column replacement corresponding to parity interleaving, as well as row replacement so that the conversion check matrix is configured with a configuration matrix described later. (Row replacement) is also applied to the matrix.
- LDPC 8 transmits one or more code bits of the LDPC code as one symbol. That is, for example, when 2 bits of code bits are used as one symbol, QPSK is used as a modulation system, for example. When 4 bits of code bits are used as 1 symbol, a modulation system is used. For example, 16APSK or 16QAM is used.
- the information matrix HA has a cyclic structure
- the parity matrix H T Has a staircase structure.
- FIG. 27 shows a conversion check matrix
- a in FIG. 27 shows a conversion parity check matrix of a parity check matrix H of an LDPC code having a code length N of 64,800 bits and a coding rate (r) of 3/4.
- FIG. 27B shows processing performed by the demultiplexer 25 (FIG. 9) for the LDPC code of the conversion check matrix of FIG. 27A, that is, the LDPC code after parity interleaving.
- the modulation method is a method of mapping symbols to any of 16 signal points, such as 16APSK or 16QAM
- the four columns constituting the memory 31 of the demultiplexer 25 are subjected to parity interleaving.
- the sign bit of the LDPC code is written in the column direction.
- the sign bit written in the column direction in the four columns constituting the memory 31 is read out in units of 4 bits in the row direction to become one symbol.
- 4-bit code bits B 0 , B 1 , B 2 , and B 3 that are one symbol are code bits corresponding to 1 in any one row of the conversion check matrix of A in FIG.
- the variable nodes corresponding to the sign bits B 0 , B 1 , B 2 , and B 3 are connected to the same check node.
- the column twist interleaver 24 performs a process after parity interleaving from the parity interleaver 23 so that a plurality of code bits corresponding to 1 in any one row of the conversion check matrix are not included in one symbol. Column twist interleaving is performed to interleave the code bits of the LDPC code.
- FIG. 28 is a diagram for explaining column twist interleaving.
- FIG. 28 shows the memory 31 (FIGS. 22 and 23) of the demultiplexer 25.
- the memory 31 stores N / (mb) bits in the column (vertical) direction and has a storage capacity for storing mb bits in the row (horizontal) direction.
- Consists of The column twist interleaver 24 performs column twist interleaving by controlling the write start position when writing the code bits of the LDPC code in the column direction and reading in the row direction to the memory 31.
- a plurality of code bits, which are read as one symbol, are read out in the row direction by appropriately changing the write start position at which code bit writing is started for each of a plurality of columns.
- the sign bit corresponding to 1 in any one row of the conversion parity check matrix is prevented (a plurality of code bits corresponding to 1 in any one row of the parity check matrix are not included in the same symbol.
- the code bits of the LDPC code are rearranged).
- the column twist interleaver 24 writes the code bits of the LDPC code from the top to the bottom (column direction) of the four columns constituting the memory 31 (instead of the demultiplexer 25 in FIG. 22). Towards the direction column.
- the column twist interleaver 24 starts from the first row of all the columns constituting the memory 31 in the row direction in units of 4 bits (mb bits).
- the code bit is read out and output to the switching unit 32 (FIGS. 22 and 23) of the demultiplexer 25 as an LDPC code after column twist interleaving.
- the address at the top (top) position of each column is 0 and the address at each position in the column direction is expressed as an integer in ascending order
- the starting position of writing is the position where the address is 0, the second column (from the left) is the starting position of writing, the address is the position 2, and the third column is the starting position of writing.
- the address is at position 4, and for the fourth column, the write start position is the position at address 7.
- the writing start position is other than the position where the address is 0
- the writing start position After writing the sign bit to the lowest position, it returns to the beginning (position where the address is 0), and the writing start position. Writing up to the position immediately before is performed. Thereafter, writing to the next (right) column is performed.
- FIG. 29 shows the number of columns of the memory 31 necessary for column twist interleaving and the writing of LDPC codes of 11 coding rates defined in the DVB-T.2 standard and having a code length N of 64800. The address of the starting position is shown for each modulation method.
- the write start position of the first column of the two columns of the memory 31 is the position where the address is 0, and the write start position of the second column is the position where the address is 2.
- the memory 31 is arranged in the row direction according to FIG. It has 4 columns for storing 2 ⁇ 2 bits and stores 64800 / (2 ⁇ 2) bits in the column direction.
- the first column write start position is the address 0 position
- the second column write start position is the address 2 position
- the third column The start position of writing in the column is the position where the address is 4
- the start position of writing in the fourth column is the position where the address is 7.
- the multiple b is 2.
- the memory 31 is arranged in the row direction according to FIG. It has four columns for storing 4 ⁇ 1 bits, and stores 64800 / (4 ⁇ 1) bits in the column direction.
- the first column write start position is the address 0 position
- the second column write start position is the address 2 position
- the write start position of the second column is the position where the address is 4
- the write start position of the fourth column is the position where the address is 7.
- the memory 31 is arranged in the row direction according to FIG. It has 8 columns for storing 4 ⁇ 2 bits and stores 64800 / (4 ⁇ 2) bits in the column direction.
- the first column write start position is the address 0 position
- the second column write start position is the address 0 position
- the start position of the second column is the position where the address is 2
- the start position of the fourth column is the position where the address is 4
- the start position of the fifth column is the position where the address is 4.
- the position and the start position of writing in the sixth column are the position where the address is 5
- the start position of writing in the seventh column is the position where the address is 7, and the starting position of the eighth column is The address is made with 7 positions, respectively.
- the memory 31 is arranged in the row direction according to FIG. It has 6 columns for storing 6 ⁇ 1 bits, and stores 64800 / (6 ⁇ 1) bits in the column direction.
- the first column write start position is the address 0 position
- the second column write start position is the address 2 position
- the first column write position is the address 5 position
- the fourth column write start position is the address 9 position
- the fifth column write start position is the address 10.
- the position and the position at the beginning of writing in the sixth column are the position where the address is 13, respectively.
- the memory 31 is arranged in the row direction according to FIG. It has 12 columns for storing 6 ⁇ 2 bits, and stores 64800 / (6 ⁇ 2) bits in the column direction.
- the first column write start position is the address 0 position
- the second column write start position is the address 0 position
- the start position of the second column is the position where the address is 2
- the start position of the fourth column is the position where the address is 2
- the start position of the fifth column is the position where the address is 3.
- the position and the start position of the 6th column are the position where the address is 4
- the start position of the 7th column is the position where the address is 4
- the start position of the 8th column is
- the position where the address is 5 and the start position of writing in the ninth column are the position where the address is 5,
- the start position of writing in the 10th column is the position where the address is 7 and the start position of writing in the 11th column.
- the position of is the position of address 8 and the 12th color Position of the writing start is set to the position whose address is 9, are respectively.
- the memory 31 is arranged in the row direction according to FIG. It has 8 columns for storing 8 ⁇ 1 bits and stores 64800 / (8 ⁇ 1) bits in the column direction.
- the first column write start position is the address 0 position
- the second column write start position is the address 0 position
- the start position of the second column is the position where the address is 2
- the start position of the fourth column is the position where the address is 4
- the start position of the fifth column is the position where the address is 4.
- the position and the start position of writing in the sixth column are the position where the address is 5
- the start position of writing in the seventh column is the position where the address is 7, and the starting position of the eighth column is The address is made with 7 positions, respectively.
- the memory 31 is arranged in the row direction according to FIG. It has 16 columns for storing 8 ⁇ 2 bits, and stores 64800 / (8 ⁇ 2) bits in the column direction.
- the first column write start position is the address 0 position
- the second column write start position is the address 2 position
- the start position of the second column is the position where the address is 2
- the start position of the fourth column is the position where the address is 2
- the start position of the fifth column is the address where the address is 2.
- the position and the start position of writing the sixth column are the position where the address is 3
- the start position of the seventh column is the position where the address is 7
- the start position of the eighth column is
- the position where the address is 15 and the start position of the 9th column are the position where the address is 16 and the start position where the 10th column is written are the position where the address is 20 and the start position of the 11th column.
- the positions of the address 22 and the 12th The start position of the program is the position where the address is 22, the start position of the 13th column is the position where the address is 27, and the start position of the 14th column is the position where the address is 27.
- the write start position of the 15th column is the position where the address is 28, and the write start position of the 16th column is the position where the address is 32.
- the memory 31 is arranged in the row direction according to FIG. It has 10 columns for storing 10 ⁇ 1 bits, and stores 64800 / (10 ⁇ 1) bits in the column direction.
- the first column write start position is the address 0 position
- the second column write start position is the address 3 position
- the first column write position is the address 6 position
- the fourth column write start position is the address 8 position
- the fifth column start position is the address 11
- the position and the start position of the 6th column are the position of the address 13
- the start position of the 7th column is the position of the address 15
- the start position of the 8th column is The address 17 position, the 9th column write start position, the address 18 position, and the 10th column write start position, the address 20 position, respectively.
- the memory 31 is arranged in the row direction according to FIG. It has 20 columns for storing 10 ⁇ 2 bits and stores 64800 / (10 ⁇ 2) bits in the column direction.
- the first column write start position is the address 0 position
- the second column write start position is the address 1 position
- the start position of the second column is the position where the address is 3
- the start position of the fourth column is the position where the address is 4
- the start position of the fifth column is the position where the address is 5.
- the position and the start position of writing in the sixth column are the position where the address is 6
- the start position of writing in the seventh column is the position where the address is 6
- the starting position of the eighth column is
- the position where the address is 9 and the start position of writing the ninth column are the position where the address is 13, and the start position of writing the tenth column is the position where the address is 14 and the start of writing the eleventh column.
- the position of is the position of address 14 and the 12th
- the start position of the program is the position where the address is 16, the start position of the 13th column is the position where the address is 21, and the start position of the 14th column is the position where the address is 21.
- the 15th column write start position is the address 23
- the 16th column write start position is the address 25 position
- the 17th column write start position is the address
- the 25th position and the 18th column start position are the address 26
- the 19th column start position are the address 28 and the 20th column start position. Is addressed with 30 positions, respectively.
- the memory 31 is arranged in the row direction according to FIG. It has 12 columns for storing 12 ⁇ 1 bits, and stores 64800 / (12 ⁇ 1) bits in the column direction.
- the first column write start position is the address 0 position
- the second column write start position is the address 0 position
- the start position of the second column is the position where the address is 2
- the start position of the fourth column is the position where the address is 2
- the start position of the fifth column is the position where the address is 3.
- the position and the start position of the 6th column are the position where the address is 4
- the start position of the 7th column is the position where the address is 4
- the start position of the 8th column is
- the position where the address is 5 and the start position of writing in the ninth column are the position where the address is 5,
- the start position of writing in the 10th column is the position where the address is 7 and the start position of writing in the 11th column.
- the position of is the position of address 8 and the 12th color Position of the writing start is set to the position whose address is 9, are respectively.
- the memory 31 is arranged in the row direction according to FIG. It has 24 columns for storing 12 ⁇ 2 bits, and stores 64800 / (12 ⁇ 2) bits in the column direction.
- the first column write start position is the address 0 position
- the second column write start position is the address 5 position
- the start position of the second column is the position where the address is 8
- the start position of the fourth column is the position where the address is 8
- the start position of the fifth column is the position where the address is 8.
- the position and the writing start position of the sixth column are the position where the address is 8
- the writing start position of the seventh column is the position of the address 10
- the writing start position of the eighth column is
- the position where the address is 10 and the start position of the 9th column are the position where the address is 10 and the start position where the 10th column is written are the position where the address is 12 and the start position of the 11th column.
- the position of is the position of address 13 and the 12th
- the starting position of the ram writing is the position of address 16, the starting position of the 13th column is the position of address 17, the starting position of the 14th column is the position of address 19
- the 15th column write start position is the address 21 position
- the 16th column write start position is the address 22 position
- the 17th column write start position is the address
- the position of 23 and the start position of writing of the 18th column are the position of address 26
- the start position of writing of the 19th column is the position of address 37 and the start position of writing of the 20th column.
- the position of the address 39 and the start position of the 21st column are the position of the address 40 and the start position of the 22nd column is the position of the address 41 and the position of the 23rd column.
- the address at the beginning of writing is 41 Position and, writing starting the 24th column position is set to the position whose address is 41, are respectively.
- FIG. 30 shows the number of columns of the memory 31 necessary for column twist interleaving and the LDPC code for each of the 10 coding rates with a code length N of 16200 defined in the DVB-T.2 standard. The address of the starting position is shown for each modulation method.
- the memory 31 is arranged in the row direction according to FIG. It has two columns that store 2 ⁇ 1 bits and stores 16200 / (2 ⁇ 1) bits in the column direction.
- the first column write start position is the address 0 position
- the second column write start position is the address 0 position. Is done.
- the memory 31 is arranged in the row direction according to FIG. It has four columns for storing 2 ⁇ 2 bits, and stores 16200 / (2 ⁇ 2) bits in the column direction.
- the first column write start position is the address 0 position
- the second column write start position is the address 2 position
- the writing start position of the second column is the position where the address is 3
- the writing start position of the fourth column is the position where the address is 3.
- the memory 31 is arranged in the row direction according to FIG. It has four columns for storing 4 ⁇ 1 bits, and stores 16200 / (4 ⁇ 1) bits in the column direction.
- the first column write start position is the address 0 position
- the second column write start position is the address 2 position
- the writing start position of the second column is the position where the address is 3
- the writing start position of the fourth column is the position where the address is 3.
- the memory 31 is arranged in the row direction according to FIG. It has 8 columns that store 4 ⁇ 2 bits, and stores 16200 / (4 ⁇ 2) bits in the column direction.
- the first column write start position is the address 0 position
- the second column write start position is the address 0 position
- the first column write start position is the address 0
- the fourth column write start position is the address 1 position
- the fifth column write start position is the address 7.
- the position and the start position of writing the sixth column are the position where the address is 20, the start position of the seventh column is the position where the address is 20, and the start position of the eighth column is Addresses are made with 21 positions, respectively.
- the memory 31 is arranged in the row direction according to FIG. It has 6 columns for storing 6 ⁇ 1 bits, and stores 16200 / (6 ⁇ 1) bits in the column direction.
- the first column write start position is the address 0 position
- the second column write start position is the address 0 position
- the start position of the second column is the position where the address is 2
- the start position of the fourth column is the position where the address is 3
- the start position of the fifth column is the position where the address is 7.
- the position and the position at the beginning of writing in the sixth column are set to the position where the address is 7, respectively.
- the memory 31 is arranged in the row direction according to FIG. It has 12 columns for storing 6 ⁇ 2 bits, and stores 16200 / (6 ⁇ 2) bits in the column direction.
- the first column write start position is the address 0 position
- the second column write start position is the address 0 position
- 3 The start position of the second column is the position where the address is 0
- the start position of the fourth column is the position where the address is 2
- the start position of the fifth column is the position where the address is 2.
- the position of the start position of the 6th column is the position where the address is 2
- the start position of the 7th column is the position of the address 3
- the start position of the 8th column is The position where the address is 3 and the start position of the 9th column are the position where the address is 3 and the start position of the 10th column is the position where the address is 6 and the start position of the 11th column
- the position of is the position of address 7 and the 12th color Position of the writing start is set to the position whose address is 7, are respectively.
- the memory 31 is arranged in the row direction according to FIG. It has 8 columns for storing 8 ⁇ 1 bits, and stores 16200 / (8 ⁇ 1) bits in the column direction.
- the first column write start position is the address 0 position
- the second column write start position is the address 0 position
- the first column write start position is the address 0
- the fourth column write start position is the address 1 position
- the fifth column write start position is the address 7.
- the position and the start position of writing the sixth column are the position where the address is 20, the start position of the seventh column is the position where the address is 20, and the start position of the eighth column is Addresses are made with 21 positions, respectively.
- the memory 31 is arranged in the row direction according to FIG. It has 10 columns for storing 10 ⁇ 1 bits, and stores 16200 / (10 ⁇ 1) bits in the column direction.
- the first column write start position is the address 0 position
- the second column write start position is the address 1 position
- the start position of the second column is the position where the address is 2
- the start position of the fourth column is the position where the address is 2
- the start position of the fifth column is the position where the address is 3.
- the position and the start position of the 6th column are the position where the address is 3
- the start position of the 7th column is the position where the address is 4
- the start position of the 8th column is The address 4 position
- the 9th column write start position are the address 5 position
- the 10th column write start position are the address 7 position.
- the memory 31 is arranged in the row direction according to FIG. It has 20 columns for storing 10 ⁇ 2 bits, and stores 16200 / (10 ⁇ 2) bits in the column direction.
- the first column write start position is the address 0 position
- the second column write start position is the address 0 position
- the start position of the second column is the position where the address is 0
- the start position of the fourth column is the position where the address is 2
- the start position of the fifth column is the position where the address is 2.
- the position and the start position of writing in the sixth column are the position where the address is 2
- the start position of writing in the seventh column is the position of address 2
- the starting position of the eighth column is
- the position where the address is 2 and the start position of writing the ninth column are the position where the address is 5,
- the start position of writing the tenth column is the position where the address is 5 and the start of writing the eleventh column.
- the position of is the position of address 5 and the 12th color
- the writing start position is the position where the address is 5
- the writing start position of the 13th column is the position where the address is 5
- the writing start position of the 14th column is the position where the address is 7
- the write start position of the 15th column is the position where the address is 7
- the write start position of the 16th column is the position of address 7
- the write start position of the 17th column is address 7
- the position of the 18th column and the start position of the 18th column are the position where the address is 8
- the start position of the 19th column is the position of the address 8 and the start position of the 20th column is ,
- the address is 10 positions, respectively.
- the memory 31 is arranged in the row direction according to FIG. It has 12 columns for storing 12 ⁇ 1 bits, and stores 16200 / (12 ⁇ 1) bits in the column direction.
- the first column write start position is the address 0 position
- the second column write start position is the address 0 position
- 3 The start position of the second column is the position where the address is 0
- the start position of the fourth column is the position where the address is 2
- the start position of the fifth column is the position where the address is 2.
- the position of the start position of the 6th column is the position where the address is 2
- the start position of the 7th column is the position of the address 3
- the start position of the 8th column is The position where the address is 3 and the start position of the 9th column are the position where the address is 3 and the start position of the 10th column is the position where the address is 6 and the start position of the 11th column
- the position of is the position of address 7 and the 12th color Position of the writing start is set to the position whose address is 7, are respectively.
- the memory 31 is arranged in the row direction according to FIG. It has 24 columns for storing 12 ⁇ 2 bits, and stores 16200 / (12 ⁇ 2) bits in the column direction.
- the first column write start position is the address 0 position
- the second column write start position is the address 0 position
- the start position of the second column is the position where the address is 0
- the start position of the fourth column is the position where the address is 0
- the start position of the fifth column is the position where the address is 0.
- the position of the start position of the 6th column is the position where the address is 0
- the start position of the 7th column is the position where the address is 0,
- the start position of the 8th column is
- the position where the address is 1 and the start position of writing the ninth column are the position where the address is 1, and the start position of writing the tenth column is the position where the address is 1 and the start of writing the eleventh column.
- the position of is the position of address 2 and the 12th color
- the write start position is the position where the address is 2
- the write start position of the 13th column is the position where the address is 2
- the write start position of the 14th column is the position where the address is 3
- the write start position of the 15th column is the position where the address is 7
- the write start position of the 16th column is the position of address 9
- the write start position of the 17th column is the address 9
- the 18th column write start position are the address 9 position
- the 19th column write start position are the address 10 position
- the 20th column write start position are
- the first position is the position where the address is 10.
- the writing starting position for the 24th column is set to the position whose address is 11, are respectively.
- FIG. 31 is a flowchart for explaining processing performed by the LDPC encoder 115, the bit interleaver 116, and the QAM encoder 117 of FIG.
- the LDPC encoder 115 waits for the LDPC target data to be supplied from the BCH encoder 114, encodes the LDPC target data into an LDPC code in step S101, and supplies the LDPC code to the bit interleaver 116. The process proceeds to step S102.
- step S102 the bit interleaver 116 performs bit interleaving on the LDPC code from the LDPC encoder 115, supplies a symbol obtained by symbolizing the LDPC code after the bit interleaving to the QAM encoder 117, and performs processing.
- the process proceeds to step S103.
- the parity interleaver 23 performs parity interleaving for the LDPC code from the LDPC encoder 115, and converts the LDPC code after the parity interleaving into the column twist interleave. Supplied to Lever 24.
- the column twist interleaver 24 performs column twist interleaving on the LDPC code from the parity interleaver 23 and supplies it to the demultiplexer 25.
- the demultiplexer 25 replaces the code bits of the LDPC code after the column twist interleaving by the column twist interleaver 24, and performs a replacement process using the replaced code bits as symbol bits (symbol bits) of the symbols.
- the replacement process by the demultiplexer 25 can be performed in accordance with the first to fourth replacement methods shown in FIGS. 22 and 23, and the code bit of the LDPC code is assigned to the symbol bit representing the symbol. This can be done in accordance with a predetermined allocation rule.
- the symbol obtained by the replacement process by the demultiplexer 25 is supplied from the demultiplexer 25 to the QAM encoder 117.
- step S103 the QAM encoder 117 maps the symbol from the demultiplexer 25 to a signal point determined by the modulation method of the orthogonal modulation performed by the QAM encoder 117 and performs orthogonal modulation, and the resulting data is converted into a time interleaver. 118.
- the parity interleaver 23 that is a block that performs parity interleaving and the column twist interleaver 24 that is a block that performs column twist interleaving are configured separately.
- the parity interleaver 23 and the column twist interleaver 24 can be integrally configured.
- both parity interleaving and column twist interleaving can be performed by writing and reading code bits to and from the memory, and an address (write address) for writing code bits is an address for reading code bits. It can be represented by a matrix to be converted into (read address).
- parity interleaving is performed by converting the sign bit by the matrix, and further, the parity.
- the result of column twist interleaving of the interleaved LDPC code can be obtained.
- the demultiplexer 25 can also be configured integrally.
- the replacement process performed by the demultiplexer 25 can also be represented by a matrix that converts the write address of the memory 31 that stores the LDPC code into a read address.
- parity interleaving, column twist interleaving, and replacement processing are performed according to the matrix. Can be performed collectively.
- parity interleaving and column twist interleaving can be performed, or neither can be performed.
- the communication path 13 (FIG. 7) is a satellite line other than AWGN that does not require much consideration of burst errors, flutter, etc.
- parity interleaving and column twisting Interleaving can be avoided.
- the simulation was performed using a communication path with flutter with a D / U of 0 dB.
- FIG. 32 shows a model of the communication path adopted in the simulation.
- a in FIG. 32 shows a flutter model employed in the simulation.
- 32B shows a model of a communication path with flutter represented by the model of A in FIG.
- H represents the flutter model of FIG. 32B
- N represents ICI (Inter Carrier Interference).
- E [N 2 ] of the power is approximated by AWGN.
- FIG. 33 shows the relationship between the error rate and the Doppler frequency f d when the modulation method is 16QAM, the coding rate (r) is (3/4), and the replacement method is the first replacement method.
- FIG. 34 shows the relationship between the error rate and the Doppler frequency f d when the modulation method is 64QAM, the coding rate (r) is (5/6), and the replacement method is the first replacement method. Show.
- the thick line indicates the relationship between the error rate and the Doppler frequency f d when parity interleaving, column twist interleaving, and replacement processing are all performed
- the thin line indicates the parity. interleave, column twist interleave and of the replacement process, in the case of performing only the replacement process, shows the relationship between the error rate and the Doppler frequency f d.
- the error rate is improved (smaller) when all of parity interleaving, column twist interleaving, and replacement processing are performed than when only replacement processing is performed. I understand that.
- FIG. 35 is a block diagram illustrating a configuration example of the LDPC encoder 115 of FIG.
- LDPC encoder 122 of FIG. 8 is similarly configured.
- N LDPC codes 64800 bits and 16200 bits are defined.
- LDPC codes having a code length N of 64,800 bits eleven coding rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4 / 5, 5/6, 8/9, and 9/10 are defined, and for LDPC codes with a code length N of 16200 bits, 10 coding rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, and 8/9 are defined (FIGS. 12 and 13).
- the LDPC encoder 115 performs encoding (error correction coding) using an LDPC code having a code length N of 64,800 bits or 16200 bits for each code length N and each code rate. This can be performed according to the prepared check matrix H.
- the LDPC encoder 115 includes an encoding processing unit 601 and a storage unit 602.
- the encoding processing unit 601 includes an encoding rate setting unit 611, an initial value table reading unit 612, a parity check matrix generation unit 613, an information bit reading unit 614, an encoded parity calculation unit 615, and a control unit 616, and an LDPC encoder
- the LDPC encoding of the LDPC target data supplied to 115 is performed, and the resulting LDPC code is supplied to the bit interleaver 116 (FIG. 8).
- the coding rate setting unit 611 sets the code length N and coding rate of the LDPC code in accordance with, for example, an operator's operation.
- the initial value table reading unit 612 reads a parity check matrix initial value table, which will be described later, corresponding to the code length N and the coding rate set by the coding rate setting unit 611 from the storage unit 602.
- the information bit reading unit 614 reads (extracts) information bits for the information length K from the LDPC target data supplied to the LDPC encoder 115.
- the encoded parity calculation unit 615 reads the parity check matrix H generated by the parity check matrix generation unit 613 from the storage unit 602, and uses the parity check matrix H to calculate a parity bit for the information bits read by the information bit reading unit 614, A codeword (LDPC code) is generated by calculating based on the formula.
- LDPC code LDPC code
- the control unit 616 controls each block constituting the encoding processing unit 601.
- the storage unit 602 stores, for example, a plurality of parity check matrix initial value tables corresponding to a plurality of coding rates and the like shown in FIGS. 12 and 13 for code lengths N such as 64800 bits and 16200 bits, respectively. Has been.
- the storage unit 602 temporarily stores data necessary for the processing of the encoding processing unit 601.
- FIG. 36 is a flowchart for explaining processing of the LDPC encoder 115 of FIG.
- step S201 the coding rate setting unit 611 determines (sets) a code length N and a coding rate r for performing LDPC coding.
- step S202 the initial value table reading unit 612 reads, from the storage unit 602, a predetermined parity check matrix initial value table corresponding to the code length N and the coding rate r determined by the coding rate setting unit 611. .
- the parity check matrix generation unit 613 uses the parity check matrix initial value table read from the storage unit 602 by the initial value table reading unit 612, and the code length N and the coding rate determined by the coding rate setting unit 611.
- the parity check matrix H of the LDPC code of r is obtained (generated), supplied to the storage unit 602 and stored.
- step S205 the encoded parity calculation unit 615 sequentially calculates the parity bits of the codeword c satisfying Expression (8) using the information bits from the information bit reading unit 614 and the check matrix H.
- c represents a row vector as a code word (LDPC code), and c T represents transposition of the row vector c.
- the information bit portion is represented by the row vector A and the parity bit portion is represented by the row vector T.
- step S206 the control unit 616 determines whether or not to end LDPC encoding. If it is determined in step S206 that the LDPC encoding is not terminated, that is, for example, if there is still LDPC target data to be LDPC encoded, the process returns to step S201 (or step S204). The processing from S201 (or step S204) to S206 is repeated.
- step S206 If it is determined in step S206 that the LDPC encoding is to be ended, that is, for example, if there is no LDPC target data to be LDPC encoded, the LDPC encoder 115 ends the processing.
- a parity check matrix initial value table corresponding to each code length N and each coding rate r is prepared, and the LDPC encoder 115 has a predetermined code length N and a predetermined coding rate r.
- LDPC encoding is performed using a parity check matrix H generated from a parity check matrix initial value table corresponding to the predetermined code length N and the predetermined coding rate r.
- the parity check matrix initial value table includes an information matrix H A corresponding to the code length N of the LDPC code (LDPC code defined by the parity check matrix H) and the information length K of the parity check matrix H (FIG. 10). ) Is a table that represents the position of one element for each 360 columns (number of columns P of cyclic structure units), and is created in advance for each check matrix H of each code length N and each coding rate r.
- FIG. 37 is a diagram illustrating an example of a parity check matrix initial value table.
- FIG. 37 shows that the code length N is 16200 bits and the coding rate (coding rate in the notation of DVB-T.2) r is 1/4 as defined in the DVB-T.2 standard.
- the parity check matrix initial value table with respect to the parity check matrix H is shown.
- the parity check matrix generator 613 obtains the parity check matrix H using the parity check matrix initial value table as follows.
- FIG. 38 shows a method for obtaining the parity check matrix H from the parity check matrix initial value table.
- parity check matrix initial value table in FIG. 38 is the parity check matrix initial value for the parity check matrix H defined in the DVB-T.2 standard and having a code length N of 16200 bits and a code rate r of 2/3. Shows the table.
- the parity check matrix initial value table indicates the position of one element of the information matrix H A (FIG. 10) corresponding to the information length K corresponding to the code length N of the LDPC code and the coding rate r, as 360 columns.
- This is a table expressed for each (number of columns P of the unit of the cyclic structure), and in the i-th row, the row number of the 1 element of the 1 + 360 ⁇ (i ⁇ 1) -th column of the check matrix H (check matrix H (The row number where the row number of the first row is 0) is arranged by the number of column weights of the 1 + 360 ⁇ (i ⁇ 1) th column.
- parity matrix H T (FIG. 10) corresponding to parity length M of parity check matrix H is determined as shown in FIG. 25, according to parity check matrix initial value table, An information matrix H A (FIG. 10) corresponding to the information length K is obtained.
- the number of rows k + 1 in the parity check matrix initial value table differs depending on the information length K.
- Equation (9) The relationship of Equation (9) is established between the information length K and the number k + 1 of rows in the parity check matrix initial value table.
- 360 in Expression (9) is the number of columns P of the unit of the cyclic structure described in FIG.
- the column weight of the parity check matrix H obtained from the parity check matrix initial value table of FIG. 38 is 13, from the first column to the 1 + 360 ⁇ (3-1) ⁇ 1 column, and 1 + 360 ⁇ (3-1) It is 3 from the column to the Kth column.
- the first row of the parity check matrix initial value table of FIG. 38 is 0,2084,1613,1548,1286,1460,3196,4297,2481,3369,3451,4620,2622, which is the parity check matrix H
- the row number is 0,2084,1613,1548,1286,1460,3196,4297,2481,3369,3451,4620,2622
- the element of the row is 1 (and other elements) Is 0).
- the second row of the parity check matrix initial value table in FIG. 38 is 1,122,1516,3448,2880,1407,1847,3799,3529,373,971,4358,3108, which is 361 of the parity check matrix H.
- the row number is 1,122,1516,3448,2880,1407,1847,3799,3529,373,971,4358,3108, indicating that the element is 1 ing.
- the parity check matrix initial value table represents the position of one element of the information matrix HA of the parity check matrix H for every 360 columns.
- the numerical value of the i-th row (i-th from the top) and j-th column (j-th from the left) of the parity check matrix initial value table is represented as h i, j and j items in the w-th column of the parity check matrix H. If the row number of the first element is represented as H wj , the row number H of the first element in the w column, which is a column other than the 1 + 360 ⁇ (i ⁇ 1) column of the parity check matrix H wj can be obtained by Expression (10).
- mod (x, y) means the remainder of dividing x by y.
- P is the number of columns of the cyclic structure unit described above, and is 360, for example, in the DVB-S.2, DVB-T.2, and DVB-C.2 standards, as described above.
- the parity check matrix generation unit 613 (FIG. 35) specifies the row number of the 1 element in the 1 + 360 ⁇ (i ⁇ 1) column of the parity check matrix H by using the parity check matrix initial value table.
- the parity check matrix generation unit 613 calculates the row number H wj of the first element of the w column that is a column other than the 1 + 360 ⁇ (i ⁇ 1) column of the parity check matrix H by the formula ( 10) to generate a parity check matrix H in which the element of the row number obtained as described above is 1.
- DVB-Sx DVB-S.2
- the second requirement is to prepare 22 ModCods in the 12 dB range from 12 dB to 24 dB
- the third requirement is C / N from -3 dB to 5 dB. It is required to prepare 12 ModCods in the 8 dB range, and as a fourth requirement, to prepare 5 ModCods in the 7 dB range where C / N is from -10 dB to -3 dB. Yes.
- the ModCod FER Fra Error Rate
- the priority of the first request is the highest “1”, but the priority of the second to fourth requests is “2” which is lower than the priority of the first request. It has become.
- an LDPC code (a check matrix) that can satisfy the first requirement having the highest priority at least in CfT is provided as a new LDPC code.
- FIG. 39 shows a BER / FER curve when QPSK is adopted as a modulation method for 11 LDPC codes with a code length N of 64k bits defined in DVB-S.2. .
- the horizontal axis represents E s / N 0 (signal power to noise power ratio per symbol) corresponding to C / N, and the vertical axis represents FER / BER.
- the solid line represents FER and the dotted line represents BER (Bit Error Rate).
- QPSK is adopted as a modulation method for 11 coding rate LDPC codes with a code length N of 64k bits as defined in DVB-S.2 in a range where E s / N 0 is 10 dB. There is a FER (BER) curve.
- the average interval of the FER curves between ModCod (hereinafter also referred to as the average interval) Is about 1 dB ( ⁇ 10 dB / (10-1)).
- the LDPC code with 11 coding rates can obtain ModCod with an average interval of about 1 dB compared to the case of DVB-S.2.
- the number is about three times the coding rate of 11 ( ⁇ 1 dB / 0.3 dB), that is, 30
- An LDPC code with a coding rate of about a level is sufficient.
- this technology is an LDPC code having a coding rate that is easy to set a coding rate of about 30.
- the coding rate is i / 30 (i is a positive integer less than 30) and the code length is 64k.
- the parity matrix of the parity check matrix H is the same as the LDPC code defined in DVB-S.2.
- H T is a stepped structure (FIG. 11).
- the information matrix HA of the check matrix H has a cyclic structure, and the number of columns P of the cyclic structure unit is also 360. To do.
- 40 to 106 are diagrams illustrating examples of the parity check matrix initial value table of the new LDPC code having the code length N of 64k bits and the encoding rate of i / 30 as described above.
- the new LDPC code is an LDPC code whose coding rate is represented by i / 30, the maximum is 1/30, 2/30, 3/30,..., 28/30, and There are 29 coding rate LDPC codes of 29/30.
- LDPC codes with a coding rate of 1/30 may be restricted in terms of efficiency.
- the use of LDPC codes with a coding rate of 29/30 may be restricted in terms of error rate (BER / FER).
- the LDPC code with a coding rate of 1/30 and the LDPC code with a coding rate of 29/30 may not be treated as a new LDPC code.
- LDPC codes with the coding rates 2/30 to 29/30 are referred to as new LDPC codes.
- the parity check matrix initial value table for the parity check matrix H of the LDPC code is shown.
- FIG. 40 shows a parity check matrix initial value table for a parity check matrix H of an LDPC code having a code length N of 64k bits and a code rate r of 2/30.
- FIG. 41 shows a parity check matrix initial value table for a parity check matrix H of an LDPC code having a code length N of 64k bits and an encoding rate r of 3/30.
- FIG. 42 shows a parity check matrix initial value table for a parity check matrix H of an LDPC code having a code length N of 64k bits and a code rate r of 4/30.
- 43 shows a parity check matrix initial value table for a parity check matrix H of an LDPC code having a code length N of 64k bits and a code rate r of 5/30.
- FIG. 45 shows a parity check matrix initial value table for a parity check matrix H of an LDPC code having a code length N of 64k bits and a coding rate r of 7/30.
- 46 and 47 show a parity check matrix initial value table for a parity check matrix H of an LDPC code having a code length N of 64k bits and a code rate r of 8/30.
- 50 and 51 show a parity check matrix initial value table for a parity check matrix H of an LDPC code having a code length N of 64k bits and a code rate r of 10/30.
- 52 and 53 show a parity check matrix initial value table for a parity check matrix H of an LDPC code having a code length N of 64k bits and a code rate r of 11/30.
- 54 and 55 illustrate a parity check matrix initial value table for a parity check matrix H of an LDPC code having a code length N of 64k bits and a code rate r of 12/30.
- 58 and 59 show a parity check matrix initial value table for a parity check matrix H of an LDPC code having a code length N of 64k bits and a code rate r of 14/30.
- 60 and 61 illustrate a parity check matrix initial value table for a parity check matrix H of an LDPC code having a code length N of 64k bits and a code rate r of 15/30.
- 62, 63, and 64 illustrate a parity check matrix initial value table for a parity check matrix H of an LDPC code having a code length N of 64k bits and a code rate r of 16/30.
- 65, 66, and 67 illustrate a parity check matrix initial value table for a parity check matrix H of an LDPC code having a code length N of 64k bits and a code rate r of 17/30.
- 68, 69, and 70 illustrate a parity check matrix initial value table for a parity check matrix H of an LDPC code having a code length N of 64k bits and a code rate r of 18/30.
- 71, 72, and 73 illustrate a parity check matrix initial value table for a parity check matrix H of an LDPC code having a code length N of 64k bits and a code rate r of 19/30.
- 74, 75, and 76 illustrate a parity check matrix initial value table for a parity check matrix H of an LDPC code having a code length N of 64k bits and a code rate r of 20/30.
- 77, 78, and 79 illustrate a parity check matrix initial value table for a parity check matrix H of an LDPC code having a code length N of 64k bits and a code rate r of 21/30.
- 80, 81, and 82 illustrate a parity check matrix initial value table for a parity check matrix H of an LDPC code having a code length N of 64k bits and a code rate r of 22/30.
- 83, 84, and 85 illustrate a parity check matrix initial value table for a parity check matrix H of an LDPC code having a code length N of 64k bits and a code rate r of 23/30.
- 86, 87, and 88 show a parity check matrix initial value table for a parity check matrix H of an LDPC code having a code length N of 64k bits and a code rate r of 24/30.
- 89, 90, and 91 illustrate a parity check matrix initial value table for a parity check matrix H of an LDPC code having a code length N of 64k bits and a code rate r of 25/30.
- 92, 93, and 94 show a parity check matrix initial value table for a parity check matrix H of an LDPC code having a code length N of 64k bits and a code rate r of 26/30.
- 95, 96, 97, and 98 show a parity check matrix initial value table for a parity check matrix H of an LDPC code having a code length N of 64k bits and a code rate r of 27/30.
- 99, 100, 101, and 102 show a parity check matrix initial value table for a parity check matrix H of an LDPC code having a code length N of 64k bits and a code rate r of 28/30.
- 103, 104, 105, and 106 show a parity check matrix initial value table for a parity check matrix H of an LDPC code having a code length N of 64k bits and a coding rate r of 29/30.
- the LDPC encoder 115 uses the parity check matrix H obtained from the parity check matrix initial value tables shown in FIGS. 40 to 106, and has a code length N of 64k bits and an encoding rate r of 2 /. Coding into any (new) LDPC code of 28 types from 30 to 29/30 can be performed.
- the parity check matrix initial value table shown in FIGS. 40 to 106 is stored in the storage unit 602 of the LDPC encoder 115 (FIG. 8).
- all 28 types of LDPC codes with coding rates r of 2/30 to 29/30 need not necessarily be adopted as new LDPCs. Absent. That is, for the 28 types of LDPC codes with coding rates r of 2/30 to 29/30 in FIGS. 40 to 106, LDPC codes with any one or more coding rates are used as new LDPC codes. Can be adopted.
- the LDPC code obtained by using the parity check matrix H obtained from the parity check matrix initial value table in FIG. 40 to FIG. 106 is a high-performance LDPC code.
- a high-performance LDPC code is an LDPC code obtained from an appropriate check matrix H.
- the appropriate check matrix H is that when an LDPC code obtained from the check matrix H is transmitted at a low E s / N 0 or E b / N o (signal power to noise power ratio per bit).
- BER (and FER) is a check matrix that satisfies a predetermined condition.
- An appropriate parity check matrix H can be obtained, for example, by performing a simulation for measuring the BER when LDPC codes obtained from various parity check matrices satisfying a predetermined condition are transmitted at low E s / N o .
- the predetermined conditions that the appropriate check matrix H should satisfy are, for example, that the analysis result obtained by the code performance analysis method called “Density Evolution” is good, There are no loops, etc.
- the predetermined condition to be satisfied by the appropriate parity check matrix H can be determined as appropriate from the viewpoints of improving the decoding performance of the LDPC code, facilitating (simplifying) the decoding process of the LDPC code, and the like.
- FIG. 107 and FIG. 108 are diagrams for explaining density evolution in which an analysis result is obtained as a predetermined condition to be satisfied by an appropriate check matrix H.
- Density evolution is a code analysis method that calculates the expected value of the error probability for the entire LDPC code (ensemble) with a code length N of ⁇ characterized by a degree sequence described later. It is.
- the noise variance when the noise variance is increased from 0, the expected value of the error probability of a certain ensemble is initially 0, but the noise variance is greater than a certain threshold. Then, it is not 0.
- the expected value of the error probability is not zero, and the threshold of noise variance (hereinafter also referred to as performance threshold) is compared to determine whether the ensemble performance (appropriateness of the check matrix) is good or bad. Can be decided.
- performance threshold the threshold of noise variance
- a high-performance LDPC code can be found among the LDPC codes belonging to the ensemble.
- the above-described degree sequence represents the ratio of variable nodes and check nodes having weights of each value to the code length N of the LDPC code.
- a regular (3,6) LDPC code with a coding rate of 1/2 is a degree in which the weights (column weights) of all variable nodes are 3 and the weights (row weights) of all check nodes are 6. Belongs to an ensemble characterized by a sequence.
- FIG. 107 shows a Tanner graph of such an ensemble.
- Each variable node is connected with three edges equal to the column weight, and therefore there are only 3N branches connected to the N variable nodes.
- each check node is connected with 6 branches equal to the row weight, and therefore there are only 3N branches connected to N / 2 check nodes.
- the interleaver randomly reorders 3N branches connected to N variable nodes, and reorders each of the rearranged branches into 3N branches connected to N / 2 check nodes. Connect to one of them.
- the interleaver through which the branch connected to the variable node and the branch connected to the check node pass is divided into multiple (multi edge), which makes it possible to further characterize the ensemble. Strictly done.
- FIG. 108 shows an example of a Tanner graph of a multi-edge type ensemble.
- Tanner graph of FIG. 108 there is one branch connected to the first interleaver, 0 branches connected to the second interleaver, only v1 variable, and one branch connected to the first interleaver.
- the Tanner graph of FIG. 108 there are two branches connected to the first interleaver, c1 check nodes with 0 branches connected to the second interleaver, and two branches connected to the first interleaver.
- the number of branches connected to the second interleaver is c2 check nodes, the number of branches connected to the first interleaver is 0, and the number of branches connected to the second interleaver is c3.
- Exists there are two branches connected to the first interleaver, c1 check nodes with 0 branches connected to the second interleaver, and two branches connected to the first interleaver.
- the BER starts to decrease (becomes smaller) due to multi-edge type density evolution E b / N 0 (Signal power to noise power ratio per bit) LDPC code that finds an ensemble whose performance threshold is less than or equal to a predetermined value and reduces the BER in multiple modulation schemes used in DVB-S.2 etc., such as QPSK, among the LDPC codes belonging to that ensemble was selected as a high-performance LDPC code.
- E b / N 0 Signal to noise power ratio per bit
- the above-mentioned parity check matrix initial value table of the new LDPC code is a parity check matrix initial value table of an LDPC code having a code length N of 64k bits, which is obtained by the above simulation.
- FIG. 109 is a parity check matrix H obtained from the parity check matrix initial value table of 28 new LDPC codes with code length N of 64k bits and code rates of 2/30 to 29/30 in FIGS. It is a figure which shows the minimum cycle length and performance threshold value.
- the minimum cycle length (girth) means the minimum value of the loop length (loop length) composed of 1 elements in the check matrix H.
- Cycle 4 (a loop of one element with a loop length of 4) does not exist in the parity check matrix H obtained from the parity check matrix initial value table of the new LDPC code.
- the performance threshold tends to improve (decrease) as the encoding rate r decreases.
- FIG. 110 is a diagram for explaining a parity check matrix H (which is also referred to as a parity check matrix H of a new LDPC code) (shown from the parity check matrix initial value table) in FIGS. 40 to 106.
- a parity check matrix H which is also referred to as a parity check matrix H of a new LDPC code
- the column weight is X
- the subsequent KY1 column is the column weight Y1
- the subsequent KY2 column is the column weight Y2.
- the subsequent column M-1 has a column weight of 2
- the last column has a column weight of 1.
- FIG. 111 is a diagram showing the number of columns KX, KY1, KY2, and M of FIG. 110 and the column weights X, Y1, and Y2 for each coding rate r of the new LDPC code.
- the column weight on the head side (left side) tends to be larger as in the case of the parity check matrix described in FIG. 12 and FIG.
- the first code bit of the new LDPC code tends to be more resistant to errors (resistant to errors).
- the coding rate is 2/30, 3/30, 4/30, 5/30, 6/30, 7/30, 8/30, 9/30, 10/30, 11/30, 12/30, 13/30, 14/30, 15/30, 16/30, 17/30, 18/30, 19/30, 20/30, 21/30, 22/30, 23/30, 24/30, 25 /
- the shift amounts for the 30, 26/30, 27/30, 28/30, 29/30 new LDPC codes are 168, 162, 156, 150, 144, 138, 132, 126, 120, 114, 108, 102, 96, 90, 84, 78, 72, 66, 60, 54, 48, 42, respectively. 36,30,24,18,12,6.
- FIG. 112, 113, and 114 are diagrams showing BER / FER simulation results of the new LDPC codes of FIGS. 40 to 106.
- FIG. 112, 113, and 114 are diagrams showing BER / FER simulation results of the new LDPC codes of FIGS. 40 to 106.
- FIG. 112, 113, and 114 are diagrams showing BER / FER simulation results of the new LDPC codes of FIGS. 40 to 106.
- the horizontal axis represents E s / N 0 and the vertical axis represents BER / FER.
- the solid line represents BER and the dotted line represents FER.
- the simulation in the 15 dB range from E s / N 0 to -10 dB to 5 dB, it is possible to set 28 ModCods with a FER of 10 -5 or less, so other than BPSK used in the simulation, for example, , QPSK, 8PSK, 16APSK, 32APSK, 16QAM, 32QAM, 64QAM, and other 20 ModCods with a FER of 10-5 or less in a 7dB range from 5dB to 12dB It is fully anticipated that this can be set.
- the FER (BER) curve of the new LDPC code is relatively smaller for each of the low, medium, and high coding rate groups at intervals smaller than 1 dB. They are lined up at intervals. Therefore, for a broadcaster who broadcasts a program using the transmission device 11, the new LDPC code has an advantage that it is easy to select a coding rate used for broadcasting according to the channel (communication channel 13) status and the like.
- the information is BCH encoded and the resulting BCH code is LDPC encoded.
- FIG. 115 is a diagram for explaining the BCH encoding used in the simulation.
- a in FIG. 115 is a diagram illustrating parameters of BCH encoding performed before LDPC encoding to a 64k LDPC code defined in DVB-S.2.
- DVB-S.2 adds 12-bit, 10-bit, or 8-bit error correction by adding 192-bit, 160-bit, or 128-bit redundant bits according to the coding rate of the LDPC code. BCH encoding is possible.
- FIG. 115 is a diagram illustrating parameters of BCH encoding used in the simulation.
- FIG. 116 is a block diagram illustrating a configuration example of the receiving device 12 of FIG.
- An OFDM processor 151 receives an OFDM signal from the transmission device 11 (FIG. 7) and performs signal processing on the OFDM signal. Data (symbols) obtained by performing signal processing by the OFDM processing unit 151 is supplied to a frame management unit 152.
- the frame management unit 152 performs processing (frame interpretation) of a frame including symbols supplied from the OFDM processing unit 151, and converts the symbol of the target data and the control data symbol obtained as a result thereof into a frequency deinterleaver. (Frequency Deinterleaver) 161 and 153, respectively.
- the frequency deinterleaver 153 performs frequency deinterleaving for each symbol from the frame management unit 152 and supplies the symbol to the QAM decoder 154.
- the QAM decoder 154 performs demapping (signal point constellation decoding) on the symbol (symbol arranged at the signal point) from the frequency deinterleaver 153 to perform orthogonal demodulation, and the resulting data (LDPC code) is converted into the LDPC decoder.
- demapping signal point constellation decoding
- LDPC decoder LDPC decoder
- the LDPC decoder 155 performs LDPC decoding of the LDPC code from the QAM decoder 154, and supplies LDPC target data (in this case, BCH code) obtained as a result thereof to a BCH decoder (BCH decoder) 156.
- LDPC target data in this case, BCH code
- the BCH decoder 156 performs BCH decoding of the LDPC target data from the LDPC decoder 155 and outputs control data (signaling) obtained as a result.
- the frequency deinterleaver 161 performs frequency deinterleaving for each symbol from the frame management unit 152 and supplies the symbol to the MISO / MIMO decoder 162.
- the MISO / MIMO decoder 162 performs space-time decoding of data (symbols) from the frequency deinterleaver 161 and supplies it to a time deinterleaver 163.
- the time deinterleaver 163 performs time deinterleaving on the data (symbol) from the MISO / MIMO decoder 162 in units of symbols, and supplies the data to the QAM decoder (QAM decoder) 164.
- QAM decoder QAM decoder
- the QAM decoder 164 performs demapping (signal point arrangement decoding) on the symbol (symbol arranged at the signal point) from the time deinterleaver 163 to perform orthogonal demodulation, and the resulting data (symbol) is subjected to bit deinterlacing. This is supplied to a Lieber (Bit Deinterleaver) 165.
- the bit deinterleaver 165 performs bit deinterleaving on the data (symbol) from the QAM decoder 164 and supplies the resulting LDPC code to the LDPC decoder 166.
- the LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 and supplies the LDPC target data (in this case, BCH code) obtained as a result to the BCH decoder 167.
- the BCH decoder 167 performs BCH decoding of the LDPC target data from the LDPC decoder 155 and supplies data obtained as a result to a BB descrambler BB.
- the BB descrambler 168 performs BB descrambling on the data from the BCH decoder 167 and supplies the data obtained as a result to a null deletion unit (Null Deletion) 169.
- the null deletion unit 169 deletes the null inserted by the padder 112 in FIG. 8 from the data from the BB descrambler 168 and supplies the null to the demultiplexer 170.
- the demultiplexer 170 separates each of one or more streams (target data) multiplexed in the data from the null deletion unit 169, performs necessary processing, and outputs the result as an output stream (Output stream).
- the receiving device 12 can be configured without providing a part of the blocks shown in FIG. That is, for example, when the transmitter 11 (FIG. 8) is configured without the time interleaver 118, the MISO / MIMO encoder 119, the frequency interleaver 120, and the frequency interleaver 124, the receiver 12 A time deinterleaver 163, a MISO / MIMO decoder 162, and a frequency deinterleaver 161, which are blocks corresponding to the time interleaver 118, the MISO / MIMO encoder 119, the frequency interleaver 120, and the frequency interleaver 124 of the transmission apparatus 11, respectively. And it can comprise without providing the frequency deinterleaver 153.
- FIG. 117 is a block diagram showing a configuration example of the bit deinterleaver 165 of FIG.
- the bit deinterleaver 165 includes a multiplexer (MUX) 54 and a column twist deinterleaver 55, and performs symbol bit deinterleaving of symbols from the QAM decoder 164 (FIG. 116).
- MUX multiplexer
- MUX column twist deinterleaver
- the multiplexer 54 replaces the symbol bit of the symbol from the QAM decoder 164 by the reverse replacement process (reverse process of the replacement process) corresponding to the replacement process performed by the demultiplexer 25 of FIG.
- a reverse permutation process is performed to return the position of the code bit (symbol bit) of the LDPC code to the original position, and the resulting LDPC code is supplied to the column twist deinterleaver 55.
- the column twist deinterleaver 55 targets the LDPC code from the multiplexer 54, and corresponds to the column twist deinterleave as the rearrangement process performed by the column twist interleaver 24 in FIG. Processing), that is, column twist deinterleaving, for example, as reverse rearrangement processing for returning the code bits of LDPC codes whose rearrangement has been changed by column twist interleaving as rearrangement processing.
- the column twist deinterleaver 55 writes the code bit of the LDPC code to the memory for deinterleaving configured similarly to the memory 31 shown in FIG. Perform column twist deinterleaving.
- writing of the sign bit is performed in the row direction of the memory for deinterleaving, using the read address when reading the sign bit from the memory 31 as the write address.
- the sign bit is read out in the column direction of the deinterleave memory using the write address at the time of writing the sign bit to the memory 31 as the read address.
- the LDPC code obtained as a result of the column twist deinterleaving is supplied from the column twist deinterleaver 55 to the LDPC decoder 166.
- the bit deinterleaver 165 supports parity interleaving.
- Parity deinterleaving reverse processing of parity interleaving, that is, parity deinterleaving for returning the code bits of the LDPC code whose arrangement has been changed by parity interleaving
- reverse permutation processing corresponding to permutation processing
- column twist All of column twist deinterleaving corresponding to interleaving can be performed.
- bit deinterleaver 165 of FIG. 117 is provided with a multiplexer 54 that performs reverse permutation processing corresponding to the permutation processing, and a column twist deinterleaver 55 that performs column twist deinterleaving corresponding to column twist interleaving.
- a multiplexer 54 that performs reverse permutation processing corresponding to the permutation processing
- a column twist deinterleaver 55 that performs column twist deinterleaving corresponding to column twist interleaving.
- no block for performing parity deinterleaving corresponding to parity interleaving is provided, and parity deinterleaving is not performed.
- bit deinterleaver 165 the column twist deinterleaver 55
- LDPC decoder 166 the reverse permutation process and the column twist deinterleave are performed, and the LDPC code not subjected to the parity deinterleave Is supplied.
- the LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165, and at least performs column replacement corresponding to parity interleaving on the parity check matrix H used by the LDPC encoder 115 in FIG. 8 for LDPC encoding.
- the conversion check matrix obtained is used, and the resulting data is output as the decoding result of the LDPC target data.
- 118 is a flowchart for explaining processing performed by the QAM decoder 164, the bit deinterleaver 165, and the LDPC decoder 166 of FIG.
- step S111 the QAM decoder 164 demaps and orthogonally demodulates symbols (symbols mapped to signal points) from the time deinterleaver 163, and supplies them to the bit deinterleaver 165. Proceed to
- step S112 the bit deinterleaver 165 performs deinterleaving (bit deinterleaving) of the symbol bits of the symbols from the QAM decoder 164, and the process proceeds to step S113.
- step S112 in the bit deinterleaver 165, the multiplexer 54 performs a reverse permutation process on the symbol bits of the symbols from the QAM decoder 164, and converts the code bits of the LDPC code obtained as a result of This is supplied to the interleaver 55.
- the column twist deinterleaver 55 performs column twist deinterleaving on the LDPC code from the multiplexer 54 and supplies the resulting LDPC code to the LDPC decoder 166.
- step S113 the LDPC decoder 166 performs LDPC decoding of the LDPC code from the column twist deinterleaver 55 using the parity check matrix H used for LDPC encoding by the LDPC encoder 115 of FIG.
- a conversion check matrix obtained by performing at least column replacement corresponding to parity interleaving is used, and data obtained as a result is output to the BCH decoder 167 as a decoding result of LDPC target data.
- the multiplexer 54 that performs reverse permutation processing and the column twist deinterleaver 55 that performs column twist deinterleaving are configured separately.
- the multiplexer 54 and the column twist deinterleaver 55 can be configured integrally.
- the column twist deinterleaver 55 need not be provided in the bit deinterleaver 165 in FIG.
- Decoding is performed using a transform parity check matrix obtained by performing at least column replacement corresponding to parity interleaving on parity check matrix H for parity check matrix H used by LDPC encoder 115 in FIG.
- FIG. 119 shows an example of a parity check matrix H of an LDPC code having a code length N of 90 and a coding rate of 2/3.
- 0 is represented by a period (.).
- the parity matrix has a staircase structure.
- FIG. 120 shows a parity check matrix H ′ obtained by subjecting the parity check matrix H of FIG. 119 to row replacement of equation (11) and column replacement of equation (12).
- s, t, x, and y are integers in the range of 0 ⁇ s ⁇ 5, 0 ⁇ t ⁇ 6, 0 ⁇ x ⁇ 5, 0 ⁇ t ⁇ 6, respectively. It is.
- the first, seventh, thirteenth, nineteenth and twenty-fifth rows which are divided by six and the remainder is 1, the first, second, third, fourth, and fifth rows respectively.
- the second, eighth, eighth, ninth, and tenth lines that are divided by the remainder of 2 are replaced with the sixth, seventh, eighth, ninth, and tenth lines, respectively.
- the 61st column, the 61st column (parity matrix) and the 61st column, the 67th column, the 73rd column, the 79th column, and the 85th column whose remainder is 1 are divided by 61, respectively.
- 62, 63, 64, and 65, the 62, 68, 74, 80, and 86 columns, which are divided by 6 and have a remainder of 2 are called 66, 67, 68, 69, and 70 columns, respectively.
- the replacement is performed accordingly.
- a matrix obtained by performing row and column replacement on the parity check matrix H in FIG. 119 is the parity check matrix H ′ in FIG.
- the parity check matrix H ′ in FIG. 120 corresponds to the K + qx + y + 1-th column of the parity check matrix H in FIG. 119 (hereinafter referred to as the original parity check matrix as appropriate) as the K + Py + x + 1-th column.
- This is a conversion check matrix obtained by performing at least column replacement to be replaced with this column.
- the transformed check matrix H ′ in FIG. 120 is multiplied by a zero vector. That is, if the row vector obtained by performing column substitution of Expression (12) on the row vector c as the LDPC code (one codeword) of the original check matrix H is expressed as c ′, the property of the check matrix , Hc T is a 0 vector, and H'c ' T is naturally a 0 vector.
- the conversion parity check matrix H ′ in FIG. 120 is a parity check matrix of the LDPC code c ′ obtained by performing the column replacement of Expression (12) on the LDPC code c of the original parity check matrix H.
- Equation (12) the column replacement of Equation (12) is performed on the LDPC code c of the original parity check matrix H, and the LDPC code c ′ after the column replacement is decoded using the transform parity check matrix H ′ of FIG. 120 (LDPC decoding). Then, the decoding result similar to the case of decoding the LDPC code of the original parity check matrix H using the parity check matrix H is obtained by performing the inverse permutation of the column permutation of the equation (12) on the decoding result. Can do.
- FIG. 121 shows the conversion parity check matrix H ′ of FIG. 120 with an interval in units of 5 ⁇ 5 matrices.
- these 5 ⁇ 5 matrices (unit matrix, quasi-unit matrix, shift matrix, sum matrix, 0 matrix) constituting the conversion check matrix H ′ are hereinafter appropriately referred to as constituent matrices.
- FIG. 122 is a block diagram illustrating a configuration example of a decoding device that performs such decoding.
- FIG. 122 performs decoding of an LDPC code using at least the transformed parity check matrix H ′ of FIG. 121 obtained by performing column replacement of Expression (12) on the original parity check matrix H of FIG. 2 shows a configuration example of a decoding device.
- Decoding device in FIG. 122 six FIFO 300 1 to the edge data storage memory 300 consisting of 300 6, FIFO 300 1 to the selector 301 for selecting 300 6, a check node calculation section 302,2 one cyclic shift circuit 303 and 308, 18 FIFOs 304 1 to 304 18 the edge data storage memory 304 consisting of, FIFOs 304 1 to 304 18 to select the selector 305, the reception data memory 306 for storing received data, a variable node calculation section 307, a decoded word calculation section 309
- the storage area of the first stage of the FIFO 300 1 includes (1, 1) to (5, 5) of the conversion parity check matrix H ′. Data corresponding to the position of 1 in the 5 ⁇ 5 unit matrix is stored.
- the shift check matrix H '(1,21) to (5,25) shift matrix (shift matrix obtained by cyclically shifting three 5 ⁇ 5 unit matrices to the right by 3)
- the data corresponding to the 1 position is stored.
- the third to eighth storage areas store data in association with the conversion parity check matrix H ′.
- 1 in the first row of the 5 ⁇ 5 unit matrix is replaced with 0 in the shift matrix from (1,86) to (5,90) of the conversion check matrix H ′. Data corresponding to one position of the shift matrix that has been shifted by one to the left.
- the storage area of the first stage of the FIFO 300 2 has a sum matrix of (6,1) to (10,5) of the conversion check matrix H ′ (5 ⁇ 5 unit matrix cyclically shifted by one to the right)
- the data corresponding to the position of 1 of the first shift matrix constituting the first shift matrix and the sum matrix which is the sum of the second shift matrix cyclically shifted by two to the right is stored.
- the second storage area stores data corresponding to position 1 of the second shift matrix constituting the sum matrix of (6,1) to (10,5) of the conversion check matrix H ′.
- the constituent matrix is a P ⁇ P unit matrix having a weight of 1, a quasi-unit matrix in which one or more of the elements of the unit matrix are 0, or Data corresponding to the unit matrix, quasi-unit matrix, or 1 position of the shift matrix when the unit matrix or quasi-unit matrix is expressed in the form of a plurality of shift matrices obtained by cyclically shifting the unit matrix or quasi-unit matrix (Messages corresponding to branches belonging to the unit matrix, quasi-unit matrix, or shift matrix) are stored in the same address (the same FIFO among the FIFOs 300 1 to 300 6 ).
- the third to ninth storage areas are also stored in association with the conversion check matrix H ′.
- the FIFOs 300 3 to 300 6 store data in association with the conversion check matrix H ′.
- the branch data storage memory 304 is composed of 18 FIFOs 304 1 to 304 18 obtained by dividing the number of columns 90 of the conversion check matrix H ′ by 5 which is the number of columns of the constituent matrix (the number of columns P of the unit of the cyclic structure). Has been.
- FIFO304 The 1, data (messages u j from the check nodes) corresponding to the first position from the first row of the conversion parity check matrix H of FIG. 121 'to the fifth column, packed vertically in each column both Stored in the form (ignoring 0). That is, data corresponding to the position of 1 in the 5 ⁇ 5 unit matrix of (1, 1) to (5, 5) of the conversion parity check matrix H ′ is stored in the first-stage storage area of the FIFO 304 1 . .
- the sum matrix of (6,1) to (10,5) of the conversion check matrix H ′ (the first shift obtained by cyclically shifting one 5 ⁇ 5 unit matrix to the right by one)
- the data corresponding to the position of 1 of the first shift matrix constituting the matrix and the sum matrix that is the sum of the matrix and the second shift matrix cyclically shifted by two to the right is stored.
- the third storage area stores data corresponding to position 1 of the second shift matrix constituting the sum matrix of (6,1) to (10,5) of the conversion check matrix H ′.
- the constituent matrix is a P ⁇ P unit matrix having a weight of 1, a quasi-unit matrix in which one or more of the elements of the unit matrix are 0, or Data corresponding to the unit matrix, quasi-unit matrix, or 1 position of the shift matrix when the unit matrix or quasi-unit matrix is expressed in the form of a plurality of shift matrices obtained by cyclically shifting the unit matrix or quasi-unit matrix (identity matrix, the message corresponding to the branch belonging to quasi unit matrix or shift matrix) are stored in the same address (same FIFO from among the FIFOs 304 1 to 304 18).
- data is also stored in the storage areas of the fourth and fifth stages in association with the conversion parity check matrix H ′.
- the number of stages in the storage area of the FIFO 304 1 is 5, which is the maximum number of 1s (Hamming weights) in the row direction in the first to fifth columns of the conversion parity check matrix H ′.
- the FIFOs 304 2 and 304 3 store data in association with the conversion parity check matrix H ′, and each has a length (number of stages) of 5.
- the FIFOs 304 4 to 304 12 store data in association with the conversion check matrix H ′, and each has a length of 3.
- the FIFOs 304 13 to 304 18 store data in association with the conversion check matrix H ′, and each has a length of 2.
- the branch data storage memory 300 includes six FIFOs 300 1 to 300 6 , and to which row of the conversion check matrix H ′ of FIG. 121 the five messages D 311 supplied from the preceding cyclic shift circuit 308 belong. according to the information (Matrix data) D312, a FIFO to store the data, select from among the FIFO300 1 to 300 6, will be stored in the order together five messages D311 to the selected FIFO. Also, the edge data storage memory 300, when reading data, sequentially reads five messages D300 1 from FIFO 300 1, supplied to the next stage of the selector 301. The branch data storage memory 300 reads the messages in order from the FIFOs 300 2 to 300 6 after reading the messages from the FIFO 300 1 and supplies them to the selector 301.
- the selector 301 selects five messages from the FIFO from which the current data is read out of the FIFOs 300 1 to 300 6 according to the select signal D301, and supplies the selected message to the check node calculation unit 302 as a message D302.
- Check node calculation section 302, 302 1 five check node calculator to consist 302 5, messages D302 (D302 1 to D302 5) supplied through the selector 301 using (messages v i of the expression (7)), A check node operation is performed according to Equation (7), and five messages D303 (D303 1 to D303 5 ) (message u j in Equation (7)) obtained as a result of the check node operation are supplied to the cyclic shift circuit 303.
- the cyclic shift circuit 303 circulates the five messages D303 1 to D303 5 obtained by the check node calculation unit 302 using unit matrices (or quasi-unit matrices) whose corresponding branches are the original in the conversion check matrix H ′.
- a cyclic shift is performed based on the information (Matrix data) D305 indicating whether the data has been click-shifted, and the result is supplied to the branch data storage memory 304 as a message D304.
- the branch data storage memory 304 includes 18 FIFOs 304 1 to 304 18 , and is in accordance with information D 305 indicating which row of the conversion check matrix H ′ the five messages D 304 supplied from the preceding cyclic shift circuit 303 belong to.
- the FIFO for storing data is selected from the FIFOs 304 1 to 304 18 , and the five messages D 304 are collectively stored in the selected FIFO in order.
- the edge data storage memory 304 when reading data, sequentially reads five messages D306 1 from FIFOs 304 1, supplied to the next stage of the selector 305.
- Edge data storage memory 304 after completion of the data read from the FIFOs 304 1, from FIFOs 304 2 to 304 18, sequentially reads out a message, to the selector 305.
- the selector 305 selects five messages from the FIFO from which the current data is read out of the FIFOs 304 1 to 304 18 in accordance with the select signal D307, and as the message D308, the variable node calculation unit 307 and the decoded word calculation unit 309.
- the received data rearrangement unit 310 rearranges the LDPC code D313 corresponding to the parity check matrix H of FIG. 119 received through the communication path 13 by performing column replacement of Expression (12), and receives the received data D314 as The data is supplied to the reception data memory 306.
- the reception data memory 306 calculates and stores reception LLRs (log likelihood ratios) from the reception data D314 supplied from the reception data rearrangement unit 310, and collects the reception LLRs by five as reception values D309.
- the variable node calculation unit 307 and the decoded word calculation unit 309 are supplied.
- the variable node calculation unit 307 includes five variable node calculators 307 1 to 307 5 , a message D308 (D308 1 to D308 5 ) (message u j in Expression (1)) supplied through the selector 305, and received data. using five reception values supplied from use memory 306 D309 (formula (reception values u 0i 1)), the variable node operation according to equation (1), to the message D310 (D310 1 not obtained as a result of the calculation D310 5 ) (message v i in equation (1)) is supplied to the cyclic shift circuit 308.
- the cyclic shift circuit 308 cyclically shifts the message D310 1 to D310 5 calculated by the variable node calculation unit 307 by a number of unit matrices (or quasi-unit matrices) whose corresponding branches are the original in the transformation check matrix H ′. A cyclic shift is performed based on the information as to whether or not the data has been obtained, and the result is supplied to the branch data storage memory 300 as a message D311.
- the LDPC code can be decoded once (variable node calculation and check node calculation) by performing the above operation once. 122 decodes the LDPC code a predetermined number of times, and then obtains and outputs the final decoding result in the decoded word calculation unit 309 and the decoded data rearrangement unit 311.
- the decoded word calculation unit 309 includes five decoded word calculators 309 1 to 309 5 , and five messages D308 (D308 1 to D308 5 ) (message u j in Expression (5)) output from the selector 305 and Using the five reception values D309 (the reception value u 0i in equation (5)) supplied from the reception data memory 306, the decoding result (decoding) based on equation (5) is used as the final stage of multiple times of decoding. And the decoded data D315 obtained as a result is supplied to the decoded data rearranging unit 311.
- the decoded data rearranging unit 311 rearranges the order of the decoded data D315 supplied from the decoded word calculation unit 309 by performing the column replacement in the formula (12), and obtains the final decoding result. Output as D316.
- one or both of row permutation and column permutation is applied to the parity check matrix (original parity check matrix), and one or more of the P ⁇ P unit matrix and one of its elements is set to 0.
- a quasi-unit matrix, a unit matrix or a shift matrix obtained by cyclically shifting a quasi-unit matrix, a unit matrix, a quasi-unit matrix, a sum matrix that is a sum of shift matrices, or a combination of P ⁇ P 0 matrices By converting to a parity check matrix (conversion parity check matrix) that can be represented by a combination of constituent matrices, decoding of LDPC code, check node operation and variable node operation, P smaller than the number of rows and columns of the parity check matrix It is possible to adopt an architecture that is performed simultaneously.
- the LDPC decoder 166 constituting the receiving device 12 performs LDPC decoding by simultaneously performing P check node operations and P variable node operations, for example, as in the decoding device of FIG.
- the parity check matrix of the LDPC code output from the LDPC encoder 115 that constitutes the transmission apparatus 11 of FIG. 8 is, for example, the parity matrix shown in FIG.
- the parity interleaver 23 of the transmission apparatus 11 interleaves the K + qx + y + 1-th code bit at the position of the K + Py + x + 1-th code bit.
- the information length K is set to 60
- the column number P of the cyclic structure unit is set to 5
- the column twist deinterleaver 55 performs the LDPC code on which the parity deinterleaving is not performed to the LDPC decoder 166, that is, the sequence of Expression (12).
- the LDPC code in a state where the replacement is performed is supplied, and the LDPC decoder 166 performs the same processing as that of the decoding device in FIG. 122 except that the column replacement of Expression (12) is not performed.
- FIG. 123 shows a configuration example of the LDPC decoder 166 of FIG.
- the LDPC decoder 166 is configured in the same manner as the decoding device of FIG. 122 except that the received data rearrangement unit 310 of FIG. 122 is not provided, and the column replacement of Expression (12) is performed. Except for this, the same processing as that of the decoding device of FIG.
- the scale can be reduced as compared with the decoding apparatus of FIG.
- the code length N of the LDPC code is 90
- the information length K is 60
- the number of columns of the unit of the cyclic structure (the number of rows and the number of columns of the constituent matrix).
- P is 5
- the LDPC code is a LDPC code in which the number P is 360 and the divisor q is M / P.
- the LDPC decoder 166 in FIG. 123 performs P check node operations and variable node operations for such LDPC codes. It is applicable when performing LDPC decoding by carrying out simultaneously.
- FIG. 124 is a diagram for explaining the processing of the multiplexer 54 constituting the bit deinterleaver 165 of FIG. 117.
- a in FIG. 124 shows a functional configuration example of the multiplexer 54.
- the multiplexer 54 includes a reverse switching unit 1001 and a memory 1002.
- the multiplexer 54 performs reverse replacement processing (reverse processing of replacement processing) corresponding to the replacement processing performed by the demultiplexer 25 of the transmission device 11 on the symbol bit of the symbol supplied from the preceding stage QAM decoder 164, that is, replacement.
- a reverse replacement process is performed to return the position of the code bit (symbol bit) of the LDPC code replaced by the process to the original position, and the resulting LDPC code is supplied to the subsequent column twist deinterleaver 55.
- the reverse switching unit 1001 includes the symbol bits y 0 , y 1 ,..., Y mb ⁇ 1 of the b symbols in units of (consecutive) b symbols. Is supplied.
- the reverse permutation unit 1001 replaces the mb symbol bits y 0 to y mb ⁇ 1 with the original mb bit code bits b 0 , b 1 ,. Reverse replacement is performed to return to the order of the sign bits b 0 to b mb ⁇ 1 before the replacement in the replacement unit 32 constituting the multiplexer 25, and the resulting mb bit code bits b 0 to b mb ⁇ 1 is output.
- the memory 1002 stores mb bits in the row (horizontal) direction and N / (mb in the column (vertical) direction, similarly to the memory 31 constituting the demultiplexer 25 on the transmission device 11 side. ) It has a storage capacity for storing bits. That is, the memory 1002 includes mb columns that store N / (mb) bits.
- the code bits of the LDPC code output from the reverse switching unit 1001 are written in the direction in which the code bits are read from the memory 31 of the demultiplexer 25 of the transmission device 11.
- the sign bit written in the memory 1002 is read in the direction in which the sign bit is written.
- the multiplexer 54 reads the code bits from the memory 1002 in the column direction and supplies them to the subsequent column twist deinterleaver 55.
- B in FIG. 124 is a diagram illustrating reading of the sign bit from the memory 1002.
- the multiplexer 54 reads the code bits of the LDPC code from the top to the bottom (column direction) of the columns constituting the memory 1002 from the left to the right columns.
- FIG. 125 is a diagram for explaining processing of the column twist deinterleaver 55 configuring the bit deinterleaver 165 of FIG. 117.
- FIG. 125 shows a configuration example of the memory 1002 of the multiplexer 54.
- the memory 1002 stores mb bits in the column (vertical) direction and has a storage capacity for storing N / (mb) bits in the row (horizontal) direction, and includes mb columns.
- the column twist deinterleaver 55 performs column twist deinterleaving by writing the code bit of the LDPC code in the row direction to the memory 1002 and controlling the read start position when reading in the column direction.
- the code bit sequence rearranged by the column twist interleave is appropriately changed by appropriately changing the read start position where the code bit read is started for each of the plurality of columns.
- a reverse rearrangement process for returning the sequence is performed.
- FIG. 125 shows a configuration example of the memory 1002 when the modulation method is 16APSK, 16QAM or the like and the multiple b is 1 as described in FIG.
- the bit number m of one symbol is 4 bits
- the column twist deinterleaver 55 sequentially writes the code bits of the LDPC code output from the reverse switching unit 1001 in the row direction, instead of the multiplexer 54, from the first row to the lower row of the memory 1002.
- the column twist deinterleaver 55 reads the code bits from the top to the bottom (column direction) from the top of the memory 1002 in the column from the left to the right. Do towards.
- the column twist deinterleaver 55 reads the code bit from the memory 1002 with the write start position where the column twist interleaver 24 on the transmission apparatus 11 side writes the code bit as the code bit read start position. .
- the modulation method is 16APSK or 16QAM
- multiple b Is 1 the column twist deinterleaver 55 sets the read start position for the leftmost column to the position where the address is 0, and (from the left) the read start position for the second column.
- the position is the position where the address is 2
- the read start position is the position of the address 4 for the third column
- the read start position is the position of the address 7 for the fourth column.
- FIG. 126 is a block diagram showing another configuration example of the bit deinterleaver 165 of FIG.
- bit deinterleaver 165 in FIG. 126 has the same configuration as that in FIG. 117 except that a parity deinterleaver 1011 is newly provided.
- the bit deinterleaver 165 includes a multiplexer (MUX) 54, a column twist deinterleaver 55, and a parity deinterleaver 1011.
- the bit deinterleaver 165 performs bit deinterleaving of the code bits of the LDPC code from the QAM decoder 164. Do.
- the multiplexer 54 replaces the LDPC code from the QAM decoder 164 by reverse replacement processing (reverse processing of the replacement processing) corresponding to the replacement processing performed by the demultiplexer 25 of the transmission device 11, that is, the replacement processing. Then, a reverse permutation process is performed to return the position of the code bit to the original position, and the resulting LDPC code is supplied to the column twist deinterleaver 55.
- reverse replacement processing reverse processing of the replacement processing
- the column twist deinterleaver 55 performs column twist deinterleave corresponding to the column twist interleave as the rearrangement process performed by the column twist interleaver 24 of the transmission device 11 for the LDPC code from the multiplexer 54.
- the LDPC code obtained as a result of the column twist deinterleave is supplied from the column twist deinterleaver 55 to the parity deinterleaver 1011.
- the parity deinterleaver 1011 targets the code bit after the column twist deinterleave in the column twist deinterleaver 55, and performs parity deinterleave corresponding to the parity interleave performed by the parity interleaver 23 of the transmission device 11 (inverse of parity interleave). In other words, parity deinterleaving is performed to return the code bits of the LDPC code whose arrangement has been changed by parity interleaving to the original order.
- the LDPC code obtained as a result of parity deinterleaving is supplied from the parity deinterleaver 1011 to the LDPC decoder 166.
- the LDPC decoder 166 includes the LDPC code subjected to the reverse permutation process, the column twist deinterleave, and the parity deinterleave, that is, the LDPC encoding according to the check matrix H.
- the LDPC code obtained by is supplied.
- the LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 using the parity check matrix H used by the LDPC encoder 115 of the transmission device 11 for LDPC encoding. That is, the LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 using the parity check matrix H itself used for the LDPC encoding by the LDPC encoder 115 of the transmission device 11 or to the parity check matrix H. On the other hand, the conversion check matrix obtained by performing at least column replacement corresponding to parity interleaving is used.
- the LDPC decoder 166 since the LDPC code obtained by the LDPC encoding according to the check matrix H is supplied from the bit deinterleaver 165 (its parity deinterleaver 1011) to the LDPC decoder 166, the LDPC When the LDPC decoding of the code is performed using the parity check matrix H itself used for the LDPC encoding by the LDPC encoder 115 of the transmission apparatus 11, the LDPC decoder 166, for example, a message (check node message, variable node message) Decoding device that performs LDPC decoding by full serial decoding (full serial decoding) method that sequentially performs operations of one node at a time, and full parallel decoding (full parallel) that performs message operations on all nodes simultaneously (in parallel) A decoding apparatus that performs LDPC decoding by a decoding method can be used.
- LDPC decoder 166 performs LDPC decoding of an LDPC code, and a transform check obtained by performing at least column replacement corresponding to parity interleaving on parity check matrix H used by LDPC encoder 115 of transmitting apparatus 11 for LDPC encoding
- the LDPC decoder 166 is an architecture decoding device that simultaneously performs P (or a divisor other than 1 of P) check node operations and variable node operations.
- the decoding apparatus (FIG. 122) having the received data rearrangement unit 310 that rearranges the code bits of the LDPC code by performing column replacement similar to the column replacement for obtaining the check matrix on the LDPC code. it can.
- a multiplexer 54 that performs reverse permutation processing, a column twist deinterleaver 55 that performs column twist deinterleaving, and a parity deinterleaver 1011 that performs parity deinterleaving are separately illustrated.
- the multiplexer 54, the column twist deinterleaver 55, and the parity deinterleaver 1011 are configured, the parity interleaver 23, the column twist interleaver 24, and the demultiplexer 25 of the transmission device 11 Similarly, it can be configured integrally.
- bit interleaver 116 (FIG. 8) of the transmission apparatus 11 is configured without the parity interleaver 23 and the column twist interleaver 24, the bit deinterleaver 165 in FIG. It is possible to configure without the twist deinterleaver 55 and the parity deinterleaver 1011.
- the LDPC decoder 166 includes a full serial decoding decoding apparatus that performs LDPC decoding using the check matrix H itself, a full parallel decoding decoding apparatus that performs LDPC decoding using the check matrix H itself,
- the transform parity check matrix H ′ can be used to configure the decoding apparatus (FIG. 122) having the received data rearrangement unit 310 that performs LDPC decoding by P simultaneous check node computations and variable node computations.
- FIG. 127 is a block diagram illustrating a first configuration example of a receiving system to which the receiving device 12 can be applied.
- the reception system includes an acquisition unit 1101, a transmission path decoding processing unit 1102, and an information source decoding processing unit 1103.
- the acquisition unit 1101 obtains a signal including an LDPC code obtained by LDPC encoding at least LDPC target data such as program image data and audio data, for example, terrestrial digital broadcasting, satellite digital broadcasting, CATV network, the Internet, and the like. Obtained via a transmission path (communication path) (not shown) such as a network of the network, and supplied to the transmission path decoding processing unit 1102.
- a transmission path communication path
- the acquisition unit 1101 when the signal acquired by the acquisition unit 1101 is broadcast from a broadcasting station via a terrestrial wave, a satellite wave, a CATV (Cable Television) network, or the like, the acquisition unit 1101 includes a tuner, It consists of STB (Set Top Box). Further, when the signal acquired by the acquisition unit 1101 is transmitted from a web server by multicast such as IPTV (Internet Protocol) Television, for example, the acquisition unit 1101 may be a NIC (Network Interface Card) or the like. Network I / F (Inter face).
- NIC Network Interface Card
- the transmission path decoding processing unit 1102 corresponds to the receiving device 12.
- the transmission path decoding processing unit 1102 performs a transmission path decoding process including at least processing for correcting an error occurring in the transmission path on the signal acquired by the acquisition unit 1101 via the transmission path, and obtains a signal obtained as a result thereof.
- the information is supplied to the information source decoding processing unit 1103.
- the signal acquired by the acquisition unit 1101 via the transmission path is a signal obtained by performing at least error correction coding for correcting an error occurring in the transmission path.
- the transmission path decoding processing unit 1102 Such a signal is subjected to transmission path decoding processing such as error correction processing, for example.
- examples of error correction coding include LDPC coding and BCH coding.
- at least LDPC encoding is performed as error correction encoding.
- the transmission path decoding process may include demodulation of the modulation signal.
- the information source decoding processing unit 1103 performs an information source decoding process including at least a process of expanding the compressed information into the original information on the signal subjected to the transmission path decoding process.
- the signal acquired by the acquisition unit 1101 via the transmission path may be subjected to compression coding for compressing information in order to reduce the amount of data such as images and sounds as information.
- the information source decoding processing unit 1103 performs information source decoding processing such as processing (decompression processing) for expanding the compressed information to the original information on the signal subjected to the transmission path decoding processing.
- the information source decoding processing unit 1103 performs a process of expanding the compressed information to the original information. I will not.
- examples of the decompression process include MPEG decoding.
- the transmission path decoding process may include descrambling and the like in addition to the decompression process.
- the acquisition unit 1101 for example, compression coding such as MPEG coding is performed on data such as images and sound, and further error correction codes such as LDPC coding are performed.
- the processed signal is acquired via the transmission path and supplied to the transmission path decoding processing unit 1102.
- the transmission path decoding processing unit 1102 for example, processing similar to that performed by the receiving device 12 is performed on the signal from the acquisition unit 1101 as transmission path decoding processing, and the resulting signal is used as an information source. This is supplied to the decryption processing unit 1103.
- the information source decoding processing unit 1103 performs information source decoding processing such as MPEG decoding on the signal from the transmission path decoding processing unit 1102 and outputs the resulting image or sound.
- the reception system of FIG. 127 as described above can be applied to, for example, a television tuner that receives a television broadcast as a digital broadcast.
- the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103 are each configured as one independent device (hardware (IC (IntegratedIntegrCircuit) or the like) or software module)). It is possible.
- the set of the unit 1103, the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103 can be configured as one independent device.
- 128 is a block diagram illustrating a second configuration example of a receiving system to which the receiving device 12 can be applied.
- the reception system of FIG. 128 includes an acquisition unit 1101, a transmission path decoding processing unit 1102, and an information source decoding processing unit 1103, and is common to the case of FIG. 127, in that an output unit 1111 is newly provided. This is different from the case of FIG.
- the output unit 1111 is, for example, a display device that displays an image or a speaker that outputs audio, and outputs an image, audio, or the like as a signal output from the information source decoding processor 1103. That is, the output unit 1111 displays an image or outputs sound.
- the reception system of FIG. 128 as described above can be applied to, for example, a TV (television receiver) that receives a television broadcast as a digital broadcast, a radio receiver that receives a radio broadcast, or the like.
- a TV television receiver
- a radio receiver that receives a radio broadcast
- the signal output from the transmission path decoding processing unit 1102 is supplied to the output unit 1111.
- FIG. 129 is a block diagram illustrating a third configuration example of the receiving system to which the receiving device 12 can be applied.
- the reception system of FIG. 129 is common to the case of FIG. 127 in that it includes an acquisition unit 1101 and a transmission path decoding processing unit 1102.
- the receiving system of FIG. 129 is different from the case of FIG. 127 in that the information source decoding processing unit 1103 is not provided and the recording unit 1121 is newly provided.
- the recording unit 1121 records a signal (for example, TS packet of MPEG TS) output from the transmission path decoding processing unit 1102 on a recording (storage) medium such as an optical disk, a hard disk (magnetic disk), or a flash memory (memory). )
- a recording (storage) medium such as an optical disk, a hard disk (magnetic disk), or a flash memory (memory).
- the reception system of FIG. 129 as described above can be applied to a recorder or the like for recording a television broadcast.
- the receiving system is configured by providing an information source decoding processing unit 1103, and the information source decoding processing unit 1103 performs a signal after the information source decoding processing, that is, an image obtained by decoding, Audio can be recorded by the recording unit 1121.
- FIG. 130 shows a configuration example of an embodiment of a computer in which a program for executing the series of processes described above is installed.
- the program can be recorded in advance in a hard disk 705 or a ROM 703 as a recording medium built in the computer.
- the program is stored temporarily on a removable recording medium 711 such as a flexible disk, a CD-ROM (Compact Disc Read Only Memory), an MO (Magneto Optical) disc, a DVD (Digital Versatile Disc), a magnetic disc, or a semiconductor memory. It can be stored permanently (recorded).
- a removable recording medium 711 can be provided as so-called package software.
- the program is installed in the computer from the removable recording medium 711 as described above, or transferred from the download site to the computer wirelessly via a digital satellite broadcasting artificial satellite, LAN (Local Area Network),
- the program can be transferred to a computer via a network such as the Internet.
- the computer can receive the program transferred in this way by the communication unit 708 and install it in the built-in hard disk 705.
- the computer has a CPU (Central Processing Unit) 702 built-in.
- An input / output interface 710 is connected to the CPU 702 via a bus 701, and the CPU 702 operates an input unit 707 including a keyboard, a mouse, a microphone, and the like by the user via the input / output interface 710.
- a program stored in a ROM (Read Only Memory) 703 is executed accordingly.
- the CPU 702 may be a program stored in the hard disk 705, a program transferred from a satellite or a network, received by the communication unit 708 and installed in the hard disk 705, or a removable recording medium 711 installed in the drive 709.
- the program read and installed in the hard disk 705 is loaded into a RAM (Random Access Memory) 704 and executed.
- the CPU 702 performs processing according to the above-described flowchart or processing performed by the configuration of the above-described block diagram.
- the CPU 702 outputs the processing result from the output unit 706 configured by an LCD (Liquid Crystal Display), a speaker, or the like, for example, via the input / output interface 710 or from the communication unit 708 as necessary. Transmission and further recording on the hard disk 705 are performed.
- processing steps for describing a program for causing a computer to perform various types of processing do not necessarily have to be processed in time series according to the order described in the flowchart, but in parallel or individually. This includes processing to be executed (for example, parallel processing or processing by an object).
- the program may be processed by one computer, or may be processed in a distributed manner by a plurality of computers. Furthermore, the program may be transferred to a remote computer and executed.
- the above-described new LDPC code (the check matrix initial value table) is used regardless of whether the communication path 13 (FIG. 7) is a satellite line, a terrestrial wave, a cable (wired line), or the like. Is possible. Furthermore, the new LDPC code can be used for data transmission other than digital broadcasting.
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Abstract
Description
1504 2103 2621 2840 3869 4594 5246 6314 7327 7364 10425 11934 12898 12954
27 1903 3923 4513 7812 8098 8428 9789 10519 11345 12032 12157 12573 12930
17 191 660 2451 2475 2976 3398 3616 5769 6724 8641 10046 11552 12842
13 1366 4993 6468 7689 8563 9131 10012 10914 11574 11837 12203 12715 12946
432 872 2603 3286 3306 3385 4137 5563 7540 9339 9948 12315 12656 12929
1113 1394 4104 4186 7240 8827 11522 11833 12359 12363 12629 12821 12904 12946
14 441 1432 1677 2432 8981 11478 11507 12599 12783 12793 12912 12922 12943
1579 1806 7971 8586 9845 10357 11600 12007 12020 12339 12576 12817 12830 12904
20 546 3672 5538 6944 8052 8781 9743 12269 12393 12418 12549 12555 12718
1 3540 4397 5011 6626 8617 9587 10360 10602 11402 11983 12068 12495 12838
30 1572 4908 7421 8041 8910 8963 11005 11930 12240 12340 12467 12892 12933
33 2060 3907 4215 5545 8306 8655 8743 8806 9315 9364 10685 11954 12959
1338 2596 4876 5207 9555 10421 10929 11648 11739 12375 12416 12643 12742 12754
9469 10544 10932 11250 11426 11582 11846 12139 12202 12210 12356 12378 12873 12929
2681 3337 3616 6113 7078 8167 8624 9697 10908 11781 11855 12095 12475 12659
28 4086 5432 6555 6848 7368 8794 11483 11572 12414 12816 12894 12936 12957
5 5044 5572 9023 9192 9589 9979 10009 10855 10991 11715 12314 12610 12945
17 272 602 5681 6530 9572 9886 11061 11495 12238 12265 12483 12885 12955
22 2245 4282 4469 5007 6650 6733 10151 10401 11571 12004 12261 12805 12844
23 3270 4468 8621 9662 11240 11934 12091 12444 12691 12717 12858 12888 12917
740 1519 4923 6191 7878 8350 9293 10779 11020 11287 11630 12792 12862 12920
12 28 3584 6072 7079 8075 10477 11130 11383 11780 12341 12667 12818 12927
14 118 5283 5382 8301 9097 9413 9664 10437 10701 11124 12685 12730 12734
32 1426 3078 4325 5353 7780 9042 9928 10077 10377 10679 11191 11750 12611
1 669 3831 3980 5381 5412 6552 8453 9435 10243 11546 11821 11987 12807
232 483 919 1232 2156 2396 2990 3774 8539 8704 8819 10810 11868 12634
2381 7309 9334
348 6494 12623
4872 6257 11090
7 11970 11985
6615 12788 12855
1173 5269 12647
1944 7738 8116
17 4828 9175
2329 6034 12642
1254 2366 5013
2984 5078 5664
7423 10265 11528
1656 8526 8716
22 287 2837
18 100 3079
299 3171 12169
33 5920 11144
1286 3650 9309
2283 8809 12588
3199 8242 9081
2507 6846 8113
5211 8722 12689
1064 2592 8659
6136 6925 12958
1256 12789 12932
4274 8045 8788
1824 3209 6926
11 8899 12669
6249 6338 8730
641 9679 12831
3459 9876 11185
3226 6148 8173
9078 12126 12771
10907 11278 12731
3392 4020 12838
2814 11588 12909
6063 9214 11519
6064 6827 12683
1610 2452 6582
903 6289 8074
4592 8138 12952
2587 6271 9945
2733 11844 11893
581 4601 10020
14 5597 6049
343 3582 5931
5263 6521 12846
1394 2457 5251
11 4627 12747
2650 10366 12390
6285 11893 12062
10143 12892 12956
8448 11917 12330
4209 11693 12356
1529 2360 9086
5389 8148 10224
64 4876 12862
9483 12659 12887
3587 6767 12478
3122 5245 9044
3267 10118 11466
1347 3857 6705
9384 9576 11971
1366 8708 10758
412 4249 12863
1676 10488 11850
17 1605 2455
14 111 6045
11368 12919 12953
10588 11530 12937
4549 5143 12218
3088 4185 11674
23 2554 7823
6615 9291 9863
2229 3629 10855
3818 5509 12764
2740 11525 12914
8297 8611 12948
3606 11104 12920
5097 10412 12759
6502 7266 12072
5425 5490 10728
22 73 8462
32 12439 12657
8483 9540 10430
7275 7377 7420
5748 9726 12356
5672 6150 9156
28 3527 5857
520 7099 11335
405 6173 12865
5847 12843 12934
4289 7679 10386
2950 8021 12938
8844 11214 12955
2130 10760 12665
734 4790 12940
8 6991 12772
19 8205 11289
12 1440 9077
8670 8837 12951
3531 9166 12937
15 8901 8929
838 10114 11740
2648 9959 10934
323 7499 12877
5505 5659 11395
6627 12709 12933
364 1976 12888
8213 9124 12793
9588 10088 11108
299 890 11634
7368 7598 11602
28 4669 12585
15 27 12474
1426 3614 4205
30 2087 11147
6226 6259 12941
であるデータ処理装置又はデータ処理方法である。
1504 2103 2621 2840 3869 4594 5246 6314 7327 7364 10425 11934 12898 12954
27 1903 3923 4513 7812 8098 8428 9789 10519 11345 12032 12157 12573 12930
17 191 660 2451 2475 2976 3398 3616 5769 6724 8641 10046 11552 12842
13 1366 4993 6468 7689 8563 9131 10012 10914 11574 11837 12203 12715 12946
432 872 2603 3286 3306 3385 4137 5563 7540 9339 9948 12315 12656 12929
1113 1394 4104 4186 7240 8827 11522 11833 12359 12363 12629 12821 12904 12946
14 441 1432 1677 2432 8981 11478 11507 12599 12783 12793 12912 12922 12943
1579 1806 7971 8586 9845 10357 11600 12007 12020 12339 12576 12817 12830 12904
20 546 3672 5538 6944 8052 8781 9743 12269 12393 12418 12549 12555 12718
1 3540 4397 5011 6626 8617 9587 10360 10602 11402 11983 12068 12495 12838
30 1572 4908 7421 8041 8910 8963 11005 11930 12240 12340 12467 12892 12933
33 2060 3907 4215 5545 8306 8655 8743 8806 9315 9364 10685 11954 12959
1338 2596 4876 5207 9555 10421 10929 11648 11739 12375 12416 12643 12742 12754
9469 10544 10932 11250 11426 11582 11846 12139 12202 12210 12356 12378 12873 12929
2681 3337 3616 6113 7078 8167 8624 9697 10908 11781 11855 12095 12475 12659
28 4086 5432 6555 6848 7368 8794 11483 11572 12414 12816 12894 12936 12957
5 5044 5572 9023 9192 9589 9979 10009 10855 10991 11715 12314 12610 12945
17 272 602 5681 6530 9572 9886 11061 11495 12238 12265 12483 12885 12955
22 2245 4282 4469 5007 6650 6733 10151 10401 11571 12004 12261 12805 12844
23 3270 4468 8621 9662 11240 11934 12091 12444 12691 12717 12858 12888 12917
740 1519 4923 6191 7878 8350 9293 10779 11020 11287 11630 12792 12862 12920
12 28 3584 6072 7079 8075 10477 11130 11383 11780 12341 12667 12818 12927
14 118 5283 5382 8301 9097 9413 9664 10437 10701 11124 12685 12730 12734
32 1426 3078 4325 5353 7780 9042 9928 10077 10377 10679 11191 11750 12611
1 669 3831 3980 5381 5412 6552 8453 9435 10243 11546 11821 11987 12807
232 483 919 1232 2156 2396 2990 3774 8539 8704 8819 10810 11868 12634
2381 7309 9334
348 6494 12623
4872 6257 11090
7 11970 11985
6615 12788 12855
1173 5269 12647
1944 7738 8116
17 4828 9175
2329 6034 12642
1254 2366 5013
2984 5078 5664
7423 10265 11528
1656 8526 8716
22 287 2837
18 100 3079
299 3171 12169
33 5920 11144
1286 3650 9309
2283 8809 12588
3199 8242 9081
2507 6846 8113
5211 8722 12689
1064 2592 8659
6136 6925 12958
1256 12789 12932
4274 8045 8788
1824 3209 6926
11 8899 12669
6249 6338 8730
641 9679 12831
3459 9876 11185
3226 6148 8173
9078 12126 12771
10907 11278 12731
3392 4020 12838
2814 11588 12909
6063 9214 11519
6064 6827 12683
1610 2452 6582
903 6289 8074
4592 8138 12952
2587 6271 9945
2733 11844 11893
581 4601 10020
14 5597 6049
343 3582 5931
5263 6521 12846
1394 2457 5251
11 4627 12747
2650 10366 12390
6285 11893 12062
10143 12892 12956
8448 11917 12330
4209 11693 12356
1529 2360 9086
5389 8148 10224
64 4876 12862
9483 12659 12887
3587 6767 12478
3122 5245 9044
3267 10118 11466
1347 3857 6705
9384 9576 11971
1366 8708 10758
412 4249 12863
1676 10488 11850
17 1605 2455
14 111 6045
11368 12919 12953
10588 11530 12937
4549 5143 12218
3088 4185 11674
23 2554 7823
6615 9291 9863
2229 3629 10855
3818 5509 12764
2740 11525 12914
8297 8611 12948
3606 11104 12920
5097 10412 12759
6502 7266 12072
5425 5490 10728
22 73 8462
32 12439 12657
8483 9540 10430
7275 7377 7420
5748 9726 12356
5672 6150 9156
28 3527 5857
520 7099 11335
405 6173 12865
5847 12843 12934
4289 7679 10386
2950 8021 12938
8844 11214 12955
2130 10760 12665
734 4790 12940
8 6991 12772
19 8205 11289
12 1440 9077
8670 8837 12951
3531 9166 12937
15 8901 8929
838 10114 11740
2648 9959 10934
323 7499 12877
5505 5659 11395
6627 12709 12933
364 1976 12888
8213 9124 12793
9588 10088 11108
299 890 11634
7368 7598 11602
28 4669 12585
15 27 12474
1426 3614 4205
30 2087 11147
6226 6259 12941
であるデータ処理装置又はデータ処理方法である。
1860 2354 3967 4292 4488 5243 5373 5766 8378 9111 10468 10505 10774
24 2266 2380 3282 4255 4779 8729 9140 9566 10102 10661 10711 10797
605 650 1108 1669 2251 3133 5847 6197 6902 7545 10521 10600 10773
1016 1428 1612 2335 3102 3810 4926 5953 9964 10246 10569 10734 10784
3195 6308 8029 9030 9397 9461 9833 10239 10499 10675 10736 10757 10773
2 27 3641 4566 7332 9318 9323 9916 10365 10438 10561 10581 10750
2405 2458 4820 6232 6254 6347 7139 7474 8623 8779 8798 10747 10794
3164 4736 6474 7162 7420 7517 7835 8238 8412 8489 9006 10113 10440
20 2372 5561 5649 6907 8393 8505 9181 9567 9595 10388 10483 10714
1071 2899 5135 5780 6616 7111 7773 8582 9015 9912 10139 10387 10768
292 2833 5490 6011 6136 6713 7517 9096 10128 10328 10407 10525 10736
1044 3711 4421 5140 5207 8118 8749 8884 9205 10359 10372 10746 10784
3241 5696 6440 7240 7419 8613 8878 9593 9959 9997 10401 10404 10754
3133 4647 5912 6065 6694 7208 7346 8227 9465 9739 10452 10516 10770
2254 6444 7449 8095 8120 8710 9030 9162 9643 9968 10101 10571 10678
918 1445 2217 4262 4623 5401 5749 7446 7907 9539 10125 10514 10726
6 1341 1788 3105 4359 5263 5470 7552 8249 8644 10609 10674 10733
1994 3000 3151 3173 7742 8335 8438 8741 9232 9296 9817 10023 10257
467 1674 3016 3950 4055 5399 6688 7113 7273 8658 8702 9642 10545
2007 2541 3125 7380 7550 8122 8501 8665 9882 10403 10519 10594 10696
334 587 709 1540 2023 2876 6216 8768 9328 9481 10424 10507 10779
2165 4185 4306 5019 6961 7386 8447 9082 9837 10091 10461 10559 10570
7 903 2948 6312 6654 7738 7980 8312 9104 9743 10070 10278 10406
3047 3154 4160 4378 5461 8711 8809 9040 9173 9252 9537 9995 10735
2018 2355 3828 3854 6201 6696 8313 8459 8550 8833 9586 10202 10224
1402 1908 4286 4660 6029 6115 6737 7538 9495 9517 10055 10509 10644
3442 3589 3868 5051 5322 5580 8725 9046 9170 10041 10613 10681 10689
2733 7826 10622
3597 4753 7086
1394 7297 10264
2848 7502 10304
1649 2405 10783
647 2911 9069
2572 4006 7508
1361 8887 10103
3681 4023 9090
1496 4962 6325
2016 5120 9747
3954 5260 8568
3364 8719 10035
4208 4806 9973
29 3361 3490
1835 2317 10436
7312 8177 9041
7728 8097 10761
2109 7902 9685
5424 8943 9436
4369 7643 9152
2240 10140 10528
3435 6124 10604
8962 9357 10040
26 1931 8629
8275 10455 10643
8 24 4952
3995 6456 10633
28 10300 10337
4894 9286 9429
5587 6721 9120
1859 9198 9762
6374 6453 7011
1319 4530 5442
1507 10711 10798
2115 3445 3641
6668 9139 10163
4038 8117 10295
1479 3403 8247
2522 2934 3562
1526 5073 9650
2136 9820 10636
4214 8464 9891
8018 10330 10610
8984 10209 10647
3414 7272 8599
4883 9077 9525
22 8173 8425
2941 6536 10126
29 6540 7361
5 3787 10468
4264 4818 6906
3903 7041 10412
6078 7661 10619
6922 9723 9890
5112 5416 6253
5925 9961 10447
9 10311 10598
8790 8814 10793
4768 5466 10664
10 10675 10766
6814 8705 10737
17 769 6692
1503 10696 10742
1285 4632 8976
4279 4973 7907
4650 4775 10785
28 729 10331
1914 5240 10723
3569 4921 9561
4 9442 10796
494 2328 9507
1717 8768 10750
9540 10599 10774
11 10075 10644
10246 10607 10753
5510 7088 9053
1347 3584 5523
7872 10596 10736
628 10592 10695
5632 5688 10627
2375 10009 10561
4169 4630 8871
2896 10038 10521
89 9695 9799
20 7563 9069
4534 10321 10697
8212 9868 10716
7485 9312 10327
234 536 6293
5515 7350 9251
283 3182 7167
2444 5378 6130
6183 8315 10726
43 4871 8347
2427 10219 10728
10 21 9448
1067 8312 8420
4793 9522 10105
4688 10536 10724
3825 7496 10709
682 8544 10449
2794 7110 10741
9279 10741 10767
2897 5442 8771
33 7957 10460
5 10393 10792
6225 10224 10798
23 9014 10786
7836 8339 8642
3476 5455 9788
1939 10251 10384
4008 7890 10450
926 2090 3804
1038 2497 10701
22 6220 8405
5153 5944 10367
7260 7726 9529
3039 8397 10665
7262 9644 10083
5531 6248 10795
7926 8248 8413
4649 8971 10182
であるデータ処理装置又はデータ処理方法である。
1860 2354 3967 4292 4488 5243 5373 5766 8378 9111 10468 10505 10774
24 2266 2380 3282 4255 4779 8729 9140 9566 10102 10661 10711 10797
605 650 1108 1669 2251 3133 5847 6197 6902 7545 10521 10600 10773
1016 1428 1612 2335 3102 3810 4926 5953 9964 10246 10569 10734 10784
3195 6308 8029 9030 9397 9461 9833 10239 10499 10675 10736 10757 10773
2 27 3641 4566 7332 9318 9323 9916 10365 10438 10561 10581 10750
2405 2458 4820 6232 6254 6347 7139 7474 8623 8779 8798 10747 10794
3164 4736 6474 7162 7420 7517 7835 8238 8412 8489 9006 10113 10440
20 2372 5561 5649 6907 8393 8505 9181 9567 9595 10388 10483 10714
1071 2899 5135 5780 6616 7111 7773 8582 9015 9912 10139 10387 10768
292 2833 5490 6011 6136 6713 7517 9096 10128 10328 10407 10525 10736
1044 3711 4421 5140 5207 8118 8749 8884 9205 10359 10372 10746 10784
3241 5696 6440 7240 7419 8613 8878 9593 9959 9997 10401 10404 10754
3133 4647 5912 6065 6694 7208 7346 8227 9465 9739 10452 10516 10770
2254 6444 7449 8095 8120 8710 9030 9162 9643 9968 10101 10571 10678
918 1445 2217 4262 4623 5401 5749 7446 7907 9539 10125 10514 10726
6 1341 1788 3105 4359 5263 5470 7552 8249 8644 10609 10674 10733
1994 3000 3151 3173 7742 8335 8438 8741 9232 9296 9817 10023 10257
467 1674 3016 3950 4055 5399 6688 7113 7273 8658 8702 9642 10545
2007 2541 3125 7380 7550 8122 8501 8665 9882 10403 10519 10594 10696
334 587 709 1540 2023 2876 6216 8768 9328 9481 10424 10507 10779
2165 4185 4306 5019 6961 7386 8447 9082 9837 10091 10461 10559 10570
7 903 2948 6312 6654 7738 7980 8312 9104 9743 10070 10278 10406
3047 3154 4160 4378 5461 8711 8809 9040 9173 9252 9537 9995 10735
2018 2355 3828 3854 6201 6696 8313 8459 8550 8833 9586 10202 10224
1402 1908 4286 4660 6029 6115 6737 7538 9495 9517 10055 10509 10644
3442 3589 3868 5051 5322 5580 8725 9046 9170 10041 10613 10681 10689
2733 7826 10622
3597 4753 7086
1394 7297 10264
2848 7502 10304
1649 2405 10783
647 2911 9069
2572 4006 7508
1361 8887 10103
3681 4023 9090
1496 4962 6325
2016 5120 9747
3954 5260 8568
3364 8719 10035
4208 4806 9973
29 3361 3490
1835 2317 10436
7312 8177 9041
7728 8097 10761
2109 7902 9685
5424 8943 9436
4369 7643 9152
2240 10140 10528
3435 6124 10604
8962 9357 10040
26 1931 8629
8275 10455 10643
8 24 4952
3995 6456 10633
28 10300 10337
4894 9286 9429
5587 6721 9120
1859 9198 9762
6374 6453 7011
1319 4530 5442
1507 10711 10798
2115 3445 3641
6668 9139 10163
4038 8117 10295
1479 3403 8247
2522 2934 3562
1526 5073 9650
2136 9820 10636
4214 8464 9891
8018 10330 10610
8984 10209 10647
3414 7272 8599
4883 9077 9525
22 8173 8425
2941 6536 10126
29 6540 7361
5 3787 10468
4264 4818 6906
3903 7041 10412
6078 7661 10619
6922 9723 9890
5112 5416 6253
5925 9961 10447
9 10311 10598
8790 8814 10793
4768 5466 10664
10 10675 10766
6814 8705 10737
17 769 6692
1503 10696 10742
1285 4632 8976
4279 4973 7907
4650 4775 10785
28 729 10331
1914 5240 10723
3569 4921 9561
4 9442 10796
494 2328 9507
1717 8768 10750
9540 10599 10774
11 10075 10644
10246 10607 10753
5510 7088 9053
1347 3584 5523
7872 10596 10736
628 10592 10695
5632 5688 10627
2375 10009 10561
4169 4630 8871
2896 10038 10521
89 9695 9799
20 7563 9069
4534 10321 10697
8212 9868 10716
7485 9312 10327
234 536 6293
5515 7350 9251
283 3182 7167
2444 5378 6130
6183 8315 10726
43 4871 8347
2427 10219 10728
10 21 9448
1067 8312 8420
4793 9522 10105
4688 10536 10724
3825 7496 10709
682 8544 10449
2794 7110 10741
9279 10741 10767
2897 5442 8771
33 7957 10460
5 10393 10792
6225 10224 10798
23 9014 10786
7836 8339 8642
3476 5455 9788
1939 10251 10384
4008 7890 10450
926 2090 3804
1038 2497 10701
22 6220 8405
5153 5944 10367
7260 7726 9529
3039 8397 10665
7262 9644 10083
5531 6248 10795
7926 8248 8413
4649 8971 10182
であるデータ処理装置又はデータ処理方法である。
142 2307 2598 2650 4028 4434 5781 5881 6016 6323 6681 6698 8125
2932 4928 5248 5256 5983 6773 6828 7789 8426 8494 8534 8539 8583
899 3295 3833 5399 6820 7400 7753 7890 8109 8451 8529 8564 8602
21 3060 4720 5429 5636 5927 6966 8110 8170 8247 8355 8365 8616
20 1745 2838 3799 4380 4418 4646 5059 7343 8161 8302 8456 8631
9 6274 6725 6792 7195 7333 8027 8186 8209 8273 8442 8548 8632
494 1365 2405 3799 5188 5291 7644 7926 8139 8458 8504 8594 8625
192 574 1179 4387 4695 5089 5831 7673 7789 8298 8301 8612 8632
11 20 1406 6111 6176 6256 6708 6834 7828 8232 8457 8495 8602
6 2654 3554 4483 4966 5866 6795 8069 8249 8301 8497 8509 8623
21 1144 2355 3124 6773 6805 6887 7742 7994 8358 8374 8580 8611
335 4473 4883 5528 6096 7543 7586 7921 8197 8319 8394 8489 8636
2919 4331 4419 4735 6366 6393 6844 7193 8165 8205 8544 8586 8617
12 19 742 930 3009 4330 6213 6224 7292 7430 7792 7922 8137
710 1439 1588 2434 3516 5239 6248 6827 8230 8448 8515 8581 8619
200 1075 1868 5581 7349 7642 7698 8037 8201 8210 8320 8391 8526
3 2501 4252 5256 5292 5567 6136 6321 6430 6486 7571 8521 8636
3062 4599 5885 6529 6616 7314 7319 7567 8024 8153 8302 8372 8598
105 381 1574 4351 5452 5603 5943 7467 7788 7933 8362 8513 8587
787 1857 3386 3659 6550 7131 7965 8015 8040 8312 8484 8525 8537
15 1118 4226 5197 5575 5761 6762 7038 8260 8338 8444 8512 8568
36 5216 5368 5616 6029 6591 8038 8067 8299 8351 8565 8578 8585
1 23 4300 4530 5426 5532 5817 6967 7124 7979 8022 8270 8437
629 2133 4828 5475 5875 5890 7194 8042 8345 8385 8518 8598 8612
11 1065 3782 4237 4993 7104 7863 7904 8104 8228 8321 8383 8565
2131 2274 3168 3215 3220 5597 6347 7812 8238 8354 8527 8557 8614
5600 6591 7491 7696
1766 8281 8626
1725 2280 5120
1650 3445 7652
4312 6911 8626
15 1013 5892
2263 2546 2979
1545 5873 7406
67 726 3697
2860 6443 8542
17 911 2820
1561 4580 6052
79 5269 7134
22 2410 2424
3501 5642 8627
808 6950 8571
4099 6389 7482
4023 5000 7833
5476 5765 7917
1008 3194 7207
20 495 5411
1703 8388 8635
6 4395 4921
200 2053 8206
1089 5126 5562
10 4193 7720
1967 2151 4608
22 738 3513
3385 5066 8152
440 1118 8537
3429 6058 7716
5213 7519 8382
5564 8365 8620
43 3219 8603
4 5409 5815
5 6376 7654
4091 5724 5953
5348 6754 8613
1634 6398 6632
72 2058 8605
3497 5811 7579
3846 6743 8559
15 5933 8629
2133 5859 7068
4151 4617 8566
2960 8270 8410
2059 3617 8210
544 1441 6895
4043 7482 8592
294 2180 8524
3058 8227 8373
364 5756 8617
5383 8555 8619
1704 2480 4181
7338 7929 7990
2615 3905 7981
4298 4548 8296
8262 8319 8630
892 1893 8028
5694 7237 8595
1487 5012 5810
4335 8593 8624
3509 4531 5273
10 22 830
4161 5208 6280
275 7063 8634
4 2725 3113
2279 7403 8174
1637 3328 3930
2810 4939 5624
3 1234 7687
2799 7740 8616
22 7701 8636
4302 7857 7993
7477 7794 8592
9 6111 8591
5 8606 8628
347 3497 4033
1747 2613 8636
1827 5600 7042
580 1822 6842
232 7134 7783
4629 5000 7231
951 2806 4947
571 3474 8577
2437 2496 7945
23 5873 8162
12 1168 7686
8315 8540 8596
1766 2506 4733
929 1516 3338
21 1216 6555
782 1452 8617
8 6083 6087
667 3240 4583
4030 4661 5790
559 7122 8553
3202 4388 4909
2533 3673 8594
1991 3954 6206
6835 7900 7980
189 5722 8573
2680 4928 4998
243 2579 7735
4281 8132 8566
7656 7671 8609
1116 2291 4166
21 388 8021
6 1123 8369
311 4918 8511
0 3248 6290
13 6762 7172
4209 5632 7563
49 127 8074
581 1735 4075
0 2235 5470
2178 5820 6179
16 3575 6054
1095 4564 6458
9 1581 5953
2537 6469 8552
14 3874 4844
0 3269 3551
2114 7372 7926
1875 2388 4057
3232 4042 6663
9 401 583
13 4100 6584
2299 4190 4410
21 3670 4979
であるデータ処理装置又はデータ処理方法である。
142 2307 2598 2650 4028 4434 5781 5881 6016 6323 6681 6698 8125
2932 4928 5248 5256 5983 6773 6828 7789 8426 8494 8534 8539 8583
899 3295 3833 5399 6820 7400 7753 7890 8109 8451 8529 8564 8602
21 3060 4720 5429 5636 5927 6966 8110 8170 8247 8355 8365 8616
20 1745 2838 3799 4380 4418 4646 5059 7343 8161 8302 8456 8631
9 6274 6725 6792 7195 7333 8027 8186 8209 8273 8442 8548 8632
494 1365 2405 3799 5188 5291 7644 7926 8139 8458 8504 8594 8625
192 574 1179 4387 4695 5089 5831 7673 7789 8298 8301 8612 8632
11 20 1406 6111 6176 6256 6708 6834 7828 8232 8457 8495 8602
6 2654 3554 4483 4966 5866 6795 8069 8249 8301 8497 8509 8623
21 1144 2355 3124 6773 6805 6887 7742 7994 8358 8374 8580 8611
335 4473 4883 5528 6096 7543 7586 7921 8197 8319 8394 8489 8636
2919 4331 4419 4735 6366 6393 6844 7193 8165 8205 8544 8586 8617
12 19 742 930 3009 4330 6213 6224 7292 7430 7792 7922 8137
710 1439 1588 2434 3516 5239 6248 6827 8230 8448 8515 8581 8619
200 1075 1868 5581 7349 7642 7698 8037 8201 8210 8320 8391 8526
3 2501 4252 5256 5292 5567 6136 6321 6430 6486 7571 8521 8636
3062 4599 5885 6529 6616 7314 7319 7567 8024 8153 8302 8372 8598
105 381 1574 4351 5452 5603 5943 7467 7788 7933 8362 8513 8587
787 1857 3386 3659 6550 7131 7965 8015 8040 8312 8484 8525 8537
15 1118 4226 5197 5575 5761 6762 7038 8260 8338 8444 8512 8568
36 5216 5368 5616 6029 6591 8038 8067 8299 8351 8565 8578 8585
1 23 4300 4530 5426 5532 5817 6967 7124 7979 8022 8270 8437
629 2133 4828 5475 5875 5890 7194 8042 8345 8385 8518 8598 8612
11 1065 3782 4237 4993 7104 7863 7904 8104 8228 8321 8383 8565
2131 2274 3168 3215 3220 5597 6347 7812 8238 8354 8527 8557 8614
5600 6591 7491 7696
1766 8281 8626
1725 2280 5120
1650 3445 7652
4312 6911 8626
15 1013 5892
2263 2546 2979
1545 5873 7406
67 726 3697
2860 6443 8542
17 911 2820
1561 4580 6052
79 5269 7134
22 2410 2424
3501 5642 8627
808 6950 8571
4099 6389 7482
4023 5000 7833
5476 5765 7917
1008 3194 7207
20 495 5411
1703 8388 8635
6 4395 4921
200 2053 8206
1089 5126 5562
10 4193 7720
1967 2151 4608
22 738 3513
3385 5066 8152
440 1118 8537
3429 6058 7716
5213 7519 8382
5564 8365 8620
43 3219 8603
4 5409 5815
5 6376 7654
4091 5724 5953
5348 6754 8613
1634 6398 6632
72 2058 8605
3497 5811 7579
3846 6743 8559
15 5933 8629
2133 5859 7068
4151 4617 8566
2960 8270 8410
2059 3617 8210
544 1441 6895
4043 7482 8592
294 2180 8524
3058 8227 8373
364 5756 8617
5383 8555 8619
1704 2480 4181
7338 7929 7990
2615 3905 7981
4298 4548 8296
8262 8319 8630
892 1893 8028
5694 7237 8595
1487 5012 5810
4335 8593 8624
3509 4531 5273
10 22 830
4161 5208 6280
275 7063 8634
4 2725 3113
2279 7403 8174
1637 3328 3930
2810 4939 5624
3 1234 7687
2799 7740 8616
22 7701 8636
4302 7857 7993
7477 7794 8592
9 6111 8591
5 8606 8628
347 3497 4033
1747 2613 8636
1827 5600 7042
580 1822 6842
232 7134 7783
4629 5000 7231
951 2806 4947
571 3474 8577
2437 2496 7945
23 5873 8162
12 1168 7686
8315 8540 8596
1766 2506 4733
929 1516 3338
21 1216 6555
782 1452 8617
8 6083 6087
667 3240 4583
4030 4661 5790
559 7122 8553
3202 4388 4909
2533 3673 8594
1991 3954 6206
6835 7900 7980
189 5722 8573
2680 4928 4998
243 2579 7735
4281 8132 8566
7656 7671 8609
1116 2291 4166
21 388 8021
6 1123 8369
311 4918 8511
0 3248 6290
13 6762 7172
4209 5632 7563
49 127 8074
581 1735 4075
0 2235 5470
2178 5820 6179
16 3575 6054
1095 4564 6458
9 1581 5953
2537 6469 8552
14 3874 4844
0 3269 3551
2114 7372 7926
1875 2388 4057
3232 4042 6663
9 401 583
13 4100 6584
2299 4190 4410
21 3670 4979
であるデータ処理装置又はデータ処理方法である。
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
658 706 898 1149 2577 2622 2772 3266 3329 5243 6079 6271
289 784 1682 3584 3995 4821 4856 5063 5974 6168 6437 6453
658 1426 2043 2065 2986 4118 4284 5394 5444 5477 5727 6018
641 928 1225 2841 4052 4840 4992 5268 5533 6249 6461 6475
2312 2917 3713 3849 4059 4241 4610 5440 5727 6101 6397 6444
1165 1592 1891 2154 3981 4817 5181 5748 5788 6012 6266 6350
13 2758 3069 4233 4697 5100 5279 5677 5919 5969 6280 6422
818 1500 2125 2340 3774 4707 4901 5170 5744 6008 6316 6353
857 3054 3409 3496 3704 4868 5326 6211 6292 6356 6367 6381
0 7 12 1709 2166 3418 3723 4887 5770 6043 6069 6431
2481 3379 4650 4900 4919 5060 5410 5425 6056 6173 6283 6386
15 814 854 1871 2934 3387 3915 5180 5303 5442 5581 5665
146 1882 3076 4458 4848 5252 5602 5778 5821 6213 6251 6401
2 947 1419 1566 3437 3646 4615 4634 4735 5819 5943 6280
1231 2309 2920 4158 4185 4298 4711 5082 5757 5762 6204 6209
257 297 337 2783 3230 4134 4480 4749 5295 5689 5921 6202
1436 2151 2629 3217 3930 4078 5386 5799 5906 6146 6226 6366
133 530 2448 4745 5000 5020 5224 5273 6211 6266 6431 6453
13 2644 3895 3898 4485 4722 5142 5462 5951 6031 6084 6351
6 3000 3873 3995 4680 5158 5504 5692 5755 6255 6338 6359
166 465 1658 2549 2941 4244 5071 5149 5452 5874 5939 6038
2309 2937 4282 4628 5113 5454 5731 5825 6021 6171 6402 6472
3 1077 2116 2426 2830 4853 5066 5571 5850 5916 6389 6421
817 1608 2229 2925 3281 4393 5042 5058 5377 5464 5588 6448
1848 3871 4381 4776 5366 5578 5648 6143 6389 6434 6465 6473
1263 1616 3150 3497 3759 4078 5530 5665 5694 5913 6397 6420
11 813 2185 2795 3349 4652 4678 5078 5504 6011 6286 6387
3060 3161 4584 4996 5143 5542 5697 5937 6141 6155 6342 6445
1638 2333 2632 3450 3505 3911 4399 4454 5499 5860 6044 6360
650 1744 4517
5772 6071 6471
3582 3622 5776
6153 6380 6446
3977 5932 6447
2071 4597 4891
11 1428 3776
1111 3874 5048
1410 2144 4445
4681 5481 6462
4044 5037 5497
2716 2891 6411
3299 4384 6224
1843 6087 6400
4664 5009 5856
1548 4383 5055
3172 4190 6373
5899 6443 6470
2572 3647 6240
1295 2158 6466
5604 6269 6368
3 5551 6454
3325 5797 6261
666 1397 5538
3069 4274 6410
4042 5992 6437
743 3075 3447
1344 2725 6386
283 2808 6303
2 4627 4632
26 1565 4000
4012 4946 6472
1629 6158 6467
6300 6351 6376
2969 4344 4440
2317 3115 4832
2099 5263 6285
2409 5868 5997
3752 4200 6350
3125 5841 6142
1 2249 6328
16 2525 6379
3198 5269 5960
4 1705 2069
990 4948 5520
1664 3836 4521
1765 4110 6454
9 1373 6387
1969 2405 6368
623 1428 3946
3111 6380 6436
1861 5611 5934
9 2444 3081
5 5508 6317
3184 4988 5995
1060 4803 6400
5021 5826 6289
1608 4754 5648
4702 6391 6421
3899 4811 6128
927 2286 5313
4123 6181 6453
2893 4150 5261
605 4332 5094
17 3518 6358
2858 6126 6478
15 1316 6465
2 2032 2983
5249 6340 6427
5 6003 6200
4478 6315 6420
5158 6390 6447
2598 3229 5399
3747 6424 6446
1412 2453 6332
5256 5715 6455
2137 3421 4368
15 3880 5245
17 3156 5638
3227 3798 6230
2094 3129 6458
1412 5573 5932
175 1182 6304
3555 6407 6463
583 1654 6339
14 6261 6449
3553 5383 5679
2092 2744 4153
0 4466 6472
11 3840 4354
17 5457 6222
1467 6083 6220
3449 3858 6337
3782 5318 6426
417 5038 5790
3571 5638 5873
6117 6241 6476
1898 5680 6219
3235 3817 6429
2095 4194 6224
2 4092 6448
5 6330 6383
285 5075 6334
10 505 2867
1183 5956 6466
839 4716 6471
984 3254 6432
1501 4790 6465
8 1457 1707
1660 1969 6438
4349 6182 6305
1423 3848 5490
1651 2969 6345
344 4164 6298
2397 6027 6274
2233 2778 6161
13 1778 2977
9 1916 3377
0 3 6190
395 4893 6394
3512 4098 6400
3490 6281 6473
12 1359 6465
4202 5179 6412
3007 3542 4271
2400 3350 6351
7 5490 5716
4695 5231 6266
777 6292 6402
919 4851 6367
6 644 3893
5386 6190 6434
17 169 4896
であるデータ処理装置又はデータ処理方法である。
658 706 898 1149 2577 2622 2772 3266 3329 5243 6079 6271
289 784 1682 3584 3995 4821 4856 5063 5974 6168 6437 6453
658 1426 2043 2065 2986 4118 4284 5394 5444 5477 5727 6018
641 928 1225 2841 4052 4840 4992 5268 5533 6249 6461 6475
2312 2917 3713 3849 4059 4241 4610 5440 5727 6101 6397 6444
1165 1592 1891 2154 3981 4817 5181 5748 5788 6012 6266 6350
13 2758 3069 4233 4697 5100 5279 5677 5919 5969 6280 6422
818 1500 2125 2340 3774 4707 4901 5170 5744 6008 6316 6353
857 3054 3409 3496 3704 4868 5326 6211 6292 6356 6367 6381
0 7 12 1709 2166 3418 3723 4887 5770 6043 6069 6431
2481 3379 4650 4900 4919 5060 5410 5425 6056 6173 6283 6386
15 814 854 1871 2934 3387 3915 5180 5303 5442 5581 5665
146 1882 3076 4458 4848 5252 5602 5778 5821 6213 6251 6401
2 947 1419 1566 3437 3646 4615 4634 4735 5819 5943 6280
1231 2309 2920 4158 4185 4298 4711 5082 5757 5762 6204 6209
257 297 337 2783 3230 4134 4480 4749 5295 5689 5921 6202
1436 2151 2629 3217 3930 4078 5386 5799 5906 6146 6226 6366
133 530 2448 4745 5000 5020 5224 5273 6211 6266 6431 6453
13 2644 3895 3898 4485 4722 5142 5462 5951 6031 6084 6351
6 3000 3873 3995 4680 5158 5504 5692 5755 6255 6338 6359
166 465 1658 2549 2941 4244 5071 5149 5452 5874 5939 6038
2309 2937 4282 4628 5113 5454 5731 5825 6021 6171 6402 6472
3 1077 2116 2426 2830 4853 5066 5571 5850 5916 6389 6421
817 1608 2229 2925 3281 4393 5042 5058 5377 5464 5588 6448
1848 3871 4381 4776 5366 5578 5648 6143 6389 6434 6465 6473
1263 1616 3150 3497 3759 4078 5530 5665 5694 5913 6397 6420
11 813 2185 2795 3349 4652 4678 5078 5504 6011 6286 6387
3060 3161 4584 4996 5143 5542 5697 5937 6141 6155 6342 6445
1638 2333 2632 3450 3505 3911 4399 4454 5499 5860 6044 6360
650 1744 4517
5772 6071 6471
3582 3622 5776
6153 6380 6446
3977 5932 6447
2071 4597 4891
11 1428 3776
1111 3874 5048
1410 2144 4445
4681 5481 6462
4044 5037 5497
2716 2891 6411
3299 4384 6224
1843 6087 6400
4664 5009 5856
1548 4383 5055
3172 4190 6373
5899 6443 6470
2572 3647 6240
1295 2158 6466
5604 6269 6368
3 5551 6454
3325 5797 6261
666 1397 5538
3069 4274 6410
4042 5992 6437
743 3075 3447
1344 2725 6386
283 2808 6303
2 4627 4632
26 1565 4000
4012 4946 6472
1629 6158 6467
6300 6351 6376
2969 4344 4440
2317 3115 4832
2099 5263 6285
2409 5868 5997
3752 4200 6350
3125 5841 6142
1 2249 6328
16 2525 6379
3198 5269 5960
4 1705 2069
990 4948 5520
1664 3836 4521
1765 4110 6454
9 1373 6387
1969 2405 6368
623 1428 3946
3111 6380 6436
1861 5611 5934
9 2444 3081
5 5508 6317
3184 4988 5995
1060 4803 6400
5021 5826 6289
1608 4754 5648
4702 6391 6421
3899 4811 6128
927 2286 5313
4123 6181 6453
2893 4150 5261
605 4332 5094
17 3518 6358
2858 6126 6478
15 1316 6465
2 2032 2983
5249 6340 6427
5 6003 6200
4478 6315 6420
5158 6390 6447
2598 3229 5399
3747 6424 6446
1412 2453 6332
5256 5715 6455
2137 3421 4368
15 3880 5245
17 3156 5638
3227 3798 6230
2094 3129 6458
1412 5573 5932
175 1182 6304
3555 6407 6463
583 1654 6339
14 6261 6449
3553 5383 5679
2092 2744 4153
0 4466 6472
11 3840 4354
17 5457 6222
1467 6083 6220
3449 3858 6337
3782 5318 6426
417 5038 5790
3571 5638 5873
6117 6241 6476
1898 5680 6219
3235 3817 6429
2095 4194 6224
2 4092 6448
5 6330 6383
285 5075 6334
10 505 2867
1183 5956 6466
839 4716 6471
984 3254 6432
1501 4790 6465
8 1457 1707
1660 1969 6438
4349 6182 6305
1423 3848 5490
1651 2969 6345
344 4164 6298
2397 6027 6274
2233 2778 6161
13 1778 2977
9 1916 3377
0 3 6190
395 4893 6394
3512 4098 6400
3490 6281 6473
12 1359 6465
4202 5179 6412
3007 3542 4271
2400 3350 6351
7 5490 5716
4695 5231 6266
777 6292 6402
919 4851 6367
6 644 3893
5386 6190 6434
17 169 4896
であるデータ処理装置又はデータ処理方法である。
85 314 1602 1728 1929 2295 2729 2924 3779 4054 4276
918 1378 1838 1903 2399 2524 2937 3615 3740 4140 4213
1361 1430 2639 2648 2910 3418 3511 3543 4177 4209 4248
472 1143 1318 1545 1830 2228 2249 2256 3626 3839 3991
226 1401 2154 2318 2851 3317 3468 3944 3983 4047 4093
490 1145 1247 1851 2671 2776 3152 3229 3345 3758 3786
522 1393 1473 2196 2707 3052 3398 3814 3827 4148 4301
417 1982 2176 2336 2459 2806 3005 3771 3870 4080 4243
112 1040 1596 1621 1685 2118 2571 3359 3945 4034 4171
646 1705 2181 2439 2808 2851 2987 3044 3494 4049 4312
6 11 115 245 663 1773 2624 3444 3601 3952 4246
11 541 1020 1326 2259 2347 2750 2861 3328 3428 4126
515 941 1233 1804 2295 2528 3265 3826 4002 4022 4224
46 484 679 1949 2342 2929 3555 3860 3918 4068 4113
1832 2023 2279 2376 2965 3278 3318 3549 3640 3843 3910
241 943 1222 1583 1637 2745 3338 4080 4086 4203 4300
11 1419 1841 2398 2920 3409 3703 3768 3878 4052 4254
878 2049 2123 2431 2657 2704 3135 3342 3728 4141 4162
16 837 1267 1410 2100 3026 3099 3107 4042 4129 4157
133 646 1367 1394 2118 2311 2676 2956 3195 3536 3657
698 1444 2129 2432 2494 2793 2947 3852 3985 4254 4319
11 1076 1618 1995 2332 2743 2934 3009 3565 4169 4188
14 20 808 2629 2681 3090 3491 3835 4017 4068 4083
433 1386 2416 2570 2950 3611 3869 3969 4248 4251 4316
384 1292 1534 2610 2617 3559 3638 3964 4131 4293 4313
271 564 1719 2288 2597 2674 3429 3455 3793 4074 4286
133 190 815 955 1485 2000 2860 3000 3734 4013 4287
559 771 1762 2537 2764 2816 3186 3806 3933 4224 4271
11 733 1198 1735 1856 2668 2754 3216 4070 4113 4311
4 806 1832 2047 2058 2724 3387 3793 3833 4005 4319
506 1456 2339 3069 3343 3442 3889 3939 4013 4212 4278
2038 3980 4313
64 2373 4080
800 1535 4166
1030 3759 4002
1687 3269 4225
1219 2632 3878
719 2916 4277
1261 1930 3459
777 1568 1914
4 397 3290
10 3451 4115
3629 3885 4155
2652 3668 4026
135 3172 4319
1426 1970 3657
199 1268 2064
570 845 2761
41 1067 3498
1588 2482 2750
1615 2013 2715
121 1812 2588
10 992 1082
1929 4225 4279
6 1967 3760
593 1812 4107
891 2146 4158
924 2282 3585
592 2971 4235
260 3493 4313
2423 3180 3449
2042 3118 3625
2877 3064 3882
7 2139 4316
4 7 2954
1398 3947 4272
3675 4253 4318
1561 1977 2432
2531 4192 4209
1032 1102 4268
75 1718 3438
925 1073 4171
2124 2762 4148
4 3455 4069
3 1279 3382
1277 1746 3969
2727 3127 4230
584 1108 3454
9 2057 3061
1608 4103 4310
2673 3164 3713
1379 4072 4318
950 3447 4146
2509 4255 4296
819 1352 3371
3562 3865 4041
940 1217 3607
114 2544 4310
4 2178 4213
2035 4246 4251
272 1236 2733
953 2762 4115
1853 3496 4309
1119 3740 4318
2051 4058 4317
0 3162 4207
2389 4034 4111
4 3395 4301
3716 4089 4198
6 4272 4311
1 4 1854
4238 4299 4305
7 10 3737
11 3764 4296
297 1912 4117
1087 1796 4056
2153 3882 4030
962 4043 4203
243 3841 4308
2183 3886 4216
943 1974 2897
278 3224 3933
3 4196 4245
3409 4301 4315
2 2176 3214
462 3203 4008
478 2178 4202
3593 3825 4216
115 2796 4225
3827 4196 4251
1375 4301 4306
296 407 2055
688 3913 4281
3446 3840 4314
1073 3444 4146
1556 2761 3391
2 3543 4264
1378 3347 4305
847 1952 2745
1 1743 4042
2087 3048 4254
1010 4073 4132
2610 4129 4152
4106 4120 4313
7 4282 4304
3885 4227 4319
1235 4105 4195
1700 2332 4224
9 3750 4282
1539 4013 4310
3734 3834 4011
1397 2758 3645
7 1000 2984
11 3433 4068
1139 1800 3352
8 546 2561
1 4209 4239
2366 4063 4282
279 2524 2533
657 1913 4006
2322 2623 2960
758 803 2304
9 13 4241
3887 4299 4318
2612 3830 4230
1300 1596 2155
3622 3671 4230
2491 3722 3977
735 3812 4201
3204 3796 4317
2727 4292 4305
1062 2676 4255
2777 3131 4286
2518 3352 3937
4225 4255 4317
3644 3822 4311
1853 3754 4094
599 2608 3276
であるデータ処理装置又はデータ処理方法である。
85 314 1602 1728 1929 2295 2729 2924 3779 4054 4276
918 1378 1838 1903 2399 2524 2937 3615 3740 4140 4213
1361 1430 2639 2648 2910 3418 3511 3543 4177 4209 4248
472 1143 1318 1545 1830 2228 2249 2256 3626 3839 3991
226 1401 2154 2318 2851 3317 3468 3944 3983 4047 4093
490 1145 1247 1851 2671 2776 3152 3229 3345 3758 3786
522 1393 1473 2196 2707 3052 3398 3814 3827 4148 4301
417 1982 2176 2336 2459 2806 3005 3771 3870 4080 4243
112 1040 1596 1621 1685 2118 2571 3359 3945 4034 4171
646 1705 2181 2439 2808 2851 2987 3044 3494 4049 4312
6 11 115 245 663 1773 2624 3444 3601 3952 4246
11 541 1020 1326 2259 2347 2750 2861 3328 3428 4126
515 941 1233 1804 2295 2528 3265 3826 4002 4022 4224
46 484 679 1949 2342 2929 3555 3860 3918 4068 4113
1832 2023 2279 2376 2965 3278 3318 3549 3640 3843 3910
241 943 1222 1583 1637 2745 3338 4080 4086 4203 4300
11 1419 1841 2398 2920 3409 3703 3768 3878 4052 4254
878 2049 2123 2431 2657 2704 3135 3342 3728 4141 4162
16 837 1267 1410 2100 3026 3099 3107 4042 4129 4157
133 646 1367 1394 2118 2311 2676 2956 3195 3536 3657
698 1444 2129 2432 2494 2793 2947 3852 3985 4254 4319
11 1076 1618 1995 2332 2743 2934 3009 3565 4169 4188
14 20 808 2629 2681 3090 3491 3835 4017 4068 4083
433 1386 2416 2570 2950 3611 3869 3969 4248 4251 4316
384 1292 1534 2610 2617 3559 3638 3964 4131 4293 4313
271 564 1719 2288 2597 2674 3429 3455 3793 4074 4286
133 190 815 955 1485 2000 2860 3000 3734 4013 4287
559 771 1762 2537 2764 2816 3186 3806 3933 4224 4271
11 733 1198 1735 1856 2668 2754 3216 4070 4113 4311
4 806 1832 2047 2058 2724 3387 3793 3833 4005 4319
506 1456 2339 3069 3343 3442 3889 3939 4013 4212 4278
2038 3980 4313
64 2373 4080
800 1535 4166
1030 3759 4002
1687 3269 4225
1219 2632 3878
719 2916 4277
1261 1930 3459
777 1568 1914
4 397 3290
10 3451 4115
3629 3885 4155
2652 3668 4026
135 3172 4319
1426 1970 3657
199 1268 2064
570 845 2761
41 1067 3498
1588 2482 2750
1615 2013 2715
121 1812 2588
10 992 1082
1929 4225 4279
6 1967 3760
593 1812 4107
891 2146 4158
924 2282 3585
592 2971 4235
260 3493 4313
2423 3180 3449
2042 3118 3625
2877 3064 3882
7 2139 4316
4 7 2954
1398 3947 4272
3675 4253 4318
1561 1977 2432
2531 4192 4209
1032 1102 4268
75 1718 3438
925 1073 4171
2124 2762 4148
4 3455 4069
3 1279 3382
1277 1746 3969
2727 3127 4230
584 1108 3454
9 2057 3061
1608 4103 4310
2673 3164 3713
1379 4072 4318
950 3447 4146
2509 4255 4296
819 1352 3371
3562 3865 4041
940 1217 3607
114 2544 4310
4 2178 4213
2035 4246 4251
272 1236 2733
953 2762 4115
1853 3496 4309
1119 3740 4318
2051 4058 4317
0 3162 4207
2389 4034 4111
4 3395 4301
3716 4089 4198
6 4272 4311
1 4 1854
4238 4299 4305
7 10 3737
11 3764 4296
297 1912 4117
1087 1796 4056
2153 3882 4030
962 4043 4203
243 3841 4308
2183 3886 4216
943 1974 2897
278 3224 3933
3 4196 4245
3409 4301 4315
2 2176 3214
462 3203 4008
478 2178 4202
3593 3825 4216
115 2796 4225
3827 4196 4251
1375 4301 4306
296 407 2055
688 3913 4281
3446 3840 4314
1073 3444 4146
1556 2761 3391
2 3543 4264
1378 3347 4305
847 1952 2745
1 1743 4042
2087 3048 4254
1010 4073 4132
2610 4129 4152
4106 4120 4313
7 4282 4304
3885 4227 4319
1235 4105 4195
1700 2332 4224
9 3750 4282
1539 4013 4310
3734 3834 4011
1397 2758 3645
7 1000 2984
11 3433 4068
1139 1800 3352
8 546 2561
1 4209 4239
2366 4063 4282
279 2524 2533
657 1913 4006
2322 2623 2960
758 803 2304
9 13 4241
3887 4299 4318
2612 3830 4230
1300 1596 2155
3622 3671 4230
2491 3722 3977
735 3812 4201
3204 3796 4317
2727 4292 4305
1062 2676 4255
2777 3131 4286
2518 3352 3937
4225 4255 4317
3644 3822 4311
1853 3754 4094
599 2608 3276
であるデータ処理装置又はデータ処理方法である。
212 499 911 940 1392
316 563 1527 2006 2077
2 1906 2043 2112 2123
537 901 1582 1812 1955
5 978 1280 1933 2145
5 2035 2044 2108 2121
5 939 1874 1974
4 1069 1758
694 2096 2106
1129 1511 1659
1564 2089 2159
2 1605 2004
474 1341 2003
103 2128 2150
1656 1993 2153
1881 2122 2138
1088 1968 2141
1 298 2073
1042 1724 2137
1253 1758 2145
1209 1566 2123
1466 2116 2155
43 2006 2049
592 1806 1865
3 143 2149
1158 1448 2002
1422 2152 2157
485 2119 2150
371 1831 2086
204 2042 2151
174 544 974
1469 1795 1995
13 708 1683
5 1144 2030
486 1309 1576
165 2030 2147
504 2073 2126
263 565 1798
239 861 1861
862 1610 1716
1346 1971 2128
5 804 1399
2139 2144 2155
4 2136 2159
1485 2059 2158
50 1091 1332
373 1730 2092
59 1086 1401
1166 1781 2065
213 2080 2154
492 1905 2110
1 1517 2126
722 1427 2146
885 991 1842
3 278 1806
967 1354 1907
1697 2047 2156
684 1924 2151
2077 2122 2157
978 2054 2135
435 2034 2150
136 1997 2125
1504 1850 2153
1404 1989 2119
109 1001 2152
780 1473 2150
198 1723 2062
927 2087 2138
1 666 2018
1293 1960 2141
1648 2033 2144
681 1578 1999
1342 2022 2157
949 1907 1994
138 1261 2135
3 608 982
1211 1501 2150
201 228 1186
1295 2089 2132
267 556 2142
801 2052 2122
1382 2135 2155
572 1503 1704
346 1183 2129
1926 2090 2149
1337 2133 2140
5 1806 2125
1383 1628 2068
1193 1626 2138
1999 2115 2146
217 274 2021
3 816 2024
1380 2138 2157
607 1385 2110
184 1195 2063
0 1767 2108
0 2081 2097
1135 2036 2128
1748 2001 2125
797 1552 1926
1046 1890 2128
291 1859 2131
1075 1214 1762
60 549 1943
581 1197 1232
1009 2026 2136
884 2002 2117
1 576 1449
519 1968 2114
5 1489 1630
1926 2037 2158
2 1249 2159
0 811 2114
2055 2152 2159
802 1911 2120
204 1033 2033
1840 2012 2037
1746 2111 2155
1098 1835 2157
2 1492 1831
353 1537 1830
375 1264 2036
2 1638 2035
1096 1971 2021
950 1809 1884
253 467 1600
5 379 1833
4 1698 1970
37 1637 2136
1174 1460 2157
612 1827 2134
1783 1802 1949
2029 2118 2151
1984 2030 2141
2 347 462
862 1693 2121
2 895 1401
4 1901 2100
1183 1674 2069
1575 1940 2158
5 1904 2097
1044 2029 2092
1441 1943 2150
0 3 1300
2 516 1735
503 1342 2019
1421 1914 2131
28 986 1467
1270 1851 1988
481 1265 2016
530 546 909
653 1909 2158
1805 2002 2149
2 1359 1518
1640 2104 2129
1656 2109 2155
1307 1762 2114
565 1647 2118
1690 2081 2156
1 300 1995
5 1681 2151
1602 2050 2156
1 1960 2153
2061 2070 2138
1581 1673 2142
1048 1142 2101
1867 1991 2055
856 1640 1878
251 561 966
343 1816 2114
3 966 2045
1885 1922 2158
57 556 2059
732 1724 2147
であるデータ処理装置又はデータ処理方法である。
212 499 911 940 1392
316 563 1527 2006 2077
2 1906 2043 2112 2123
537 901 1582 1812 1955
5 978 1280 1933 2145
5 2035 2044 2108 2121
5 939 1874 1974
4 1069 1758
694 2096 2106
1129 1511 1659
1564 2089 2159
2 1605 2004
474 1341 2003
103 2128 2150
1656 1993 2153
1881 2122 2138
1088 1968 2141
1 298 2073
1042 1724 2137
1253 1758 2145
1209 1566 2123
1466 2116 2155
43 2006 2049
592 1806 1865
3 143 2149
1158 1448 2002
1422 2152 2157
485 2119 2150
371 1831 2086
204 2042 2151
174 544 974
1469 1795 1995
13 708 1683
5 1144 2030
486 1309 1576
165 2030 2147
504 2073 2126
263 565 1798
239 861 1861
862 1610 1716
1346 1971 2128
5 804 1399
2139 2144 2155
4 2136 2159
1485 2059 2158
50 1091 1332
373 1730 2092
59 1086 1401
1166 1781 2065
213 2080 2154
492 1905 2110
1 1517 2126
722 1427 2146
885 991 1842
3 278 1806
967 1354 1907
1697 2047 2156
684 1924 2151
2077 2122 2157
978 2054 2135
435 2034 2150
136 1997 2125
1504 1850 2153
1404 1989 2119
109 1001 2152
780 1473 2150
198 1723 2062
927 2087 2138
1 666 2018
1293 1960 2141
1648 2033 2144
681 1578 1999
1342 2022 2157
949 1907 1994
138 1261 2135
3 608 982
1211 1501 2150
201 228 1186
1295 2089 2132
267 556 2142
801 2052 2122
1382 2135 2155
572 1503 1704
346 1183 2129
1926 2090 2149
1337 2133 2140
5 1806 2125
1383 1628 2068
1193 1626 2138
1999 2115 2146
217 274 2021
3 816 2024
1380 2138 2157
607 1385 2110
184 1195 2063
0 1767 2108
0 2081 2097
1135 2036 2128
1748 2001 2125
797 1552 1926
1046 1890 2128
291 1859 2131
1075 1214 1762
60 549 1943
581 1197 1232
1009 2026 2136
884 2002 2117
1 576 1449
519 1968 2114
5 1489 1630
1926 2037 2158
2 1249 2159
0 811 2114
2055 2152 2159
802 1911 2120
204 1033 2033
1840 2012 2037
1746 2111 2155
1098 1835 2157
2 1492 1831
353 1537 1830
375 1264 2036
2 1638 2035
1096 1971 2021
950 1809 1884
253 467 1600
5 379 1833
4 1698 1970
37 1637 2136
1174 1460 2157
612 1827 2134
1783 1802 1949
2029 2118 2151
1984 2030 2141
2 347 462
862 1693 2121
2 895 1401
4 1901 2100
1183 1674 2069
1575 1940 2158
5 1904 2097
1044 2029 2092
1441 1943 2150
0 3 1300
2 516 1735
503 1342 2019
1421 1914 2131
28 986 1467
1270 1851 1988
481 1265 2016
530 546 909
653 1909 2158
1805 2002 2149
2 1359 1518
1640 2104 2129
1656 2109 2155
1307 1762 2114
565 1647 2118
1690 2081 2156
1 300 1995
5 1681 2151
1602 2050 2156
1 1960 2153
2061 2070 2138
1581 1673 2142
1048 1142 2101
1867 1991 2055
856 1640 1878
251 561 966
343 1816 2114
3 966 2045
1885 1922 2158
57 556 2059
732 1724 2147
であるデータ処理装置又はデータ処理方法である。
1504 2103 2621 2840 3869 4594 5246 6314 7327 7364 10425 11934 12898 12954
27 1903 3923 4513 7812 8098 8428 9789 10519 11345 12032 12157 12573 12930
17 191 660 2451 2475 2976 3398 3616 5769 6724 8641 10046 11552 12842
13 1366 4993 6468 7689 8563 9131 10012 10914 11574 11837 12203 12715 12946
432 872 2603 3286 3306 3385 4137 5563 7540 9339 9948 12315 12656 12929
1113 1394 4104 4186 7240 8827 11522 11833 12359 12363 12629 12821 12904 12946
14 441 1432 1677 2432 8981 11478 11507 12599 12783 12793 12912 12922 12943
1579 1806 7971 8586 9845 10357 11600 12007 12020 12339 12576 12817 12830 12904
20 546 3672 5538 6944 8052 8781 9743 12269 12393 12418 12549 12555 12718
1 3540 4397 5011 6626 8617 9587 10360 10602 11402 11983 12068 12495 12838
30 1572 4908 7421 8041 8910 8963 11005 11930 12240 12340 12467 12892 12933
33 2060 3907 4215 5545 8306 8655 8743 8806 9315 9364 10685 11954 12959
1338 2596 4876 5207 9555 10421 10929 11648 11739 12375 12416 12643 12742 12754
9469 10544 10932 11250 11426 11582 11846 12139 12202 12210 12356 12378 12873 12929
2681 3337 3616 6113 7078 8167 8624 9697 10908 11781 11855 12095 12475 12659
28 4086 5432 6555 6848 7368 8794 11483 11572 12414 12816 12894 12936 12957
5 5044 5572 9023 9192 9589 9979 10009 10855 10991 11715 12314 12610 12945
17 272 602 5681 6530 9572 9886 11061 11495 12238 12265 12483 12885 12955
22 2245 4282 4469 5007 6650 6733 10151 10401 11571 12004 12261 12805 12844
23 3270 4468 8621 9662 11240 11934 12091 12444 12691 12717 12858 12888 12917
740 1519 4923 6191 7878 8350 9293 10779 11020 11287 11630 12792 12862 12920
12 28 3584 6072 7079 8075 10477 11130 11383 11780 12341 12667 12818 12927
14 118 5283 5382 8301 9097 9413 9664 10437 10701 11124 12685 12730 12734
32 1426 3078 4325 5353 7780 9042 9928 10077 10377 10679 11191 11750 12611
1 669 3831 3980 5381 5412 6552 8453 9435 10243 11546 11821 11987 12807
232 483 919 1232 2156 2396 2990 3774 8539 8704 8819 10810 11868 12634
2381 7309 9334
348 6494 12623
4872 6257 11090
7 11970 11985
6615 12788 12855
1173 5269 12647
1944 7738 8116
17 4828 9175
2329 6034 12642
1254 2366 5013
2984 5078 5664
7423 10265 11528
1656 8526 8716
22 287 2837
18 100 3079
299 3171 12169
33 5920 11144
1286 3650 9309
2283 8809 12588
3199 8242 9081
2507 6846 8113
5211 8722 12689
1064 2592 8659
6136 6925 12958
1256 12789 12932
4274 8045 8788
1824 3209 6926
11 8899 12669
6249 6338 8730
641 9679 12831
3459 9876 11185
3226 6148 8173
9078 12126 12771
10907 11278 12731
3392 4020 12838
2814 11588 12909
6063 9214 11519
6064 6827 12683
1610 2452 6582
903 6289 8074
4592 8138 12952
2587 6271 9945
2733 11844 11893
581 4601 10020
14 5597 6049
343 3582 5931
5263 6521 12846
1394 2457 5251
11 4627 12747
2650 10366 12390
6285 11893 12062
10143 12892 12956
8448 11917 12330
4209 11693 12356
1529 2360 9086
5389 8148 10224
64 4876 12862
9483 12659 12887
3587 6767 12478
3122 5245 9044
3267 10118 11466
1347 3857 6705
9384 9576 11971
1366 8708 10758
412 4249 12863
1676 10488 11850
17 1605 2455
14 111 6045
11368 12919 12953
10588 11530 12937
4549 5143 12218
3088 4185 11674
23 2554 7823
6615 9291 9863
2229 3629 10855
3818 5509 12764
2740 11525 12914
8297 8611 12948
3606 11104 12920
5097 10412 12759
6502 7266 12072
5425 5490 10728
22 73 8462
32 12439 12657
8483 9540 10430
7275 7377 7420
5748 9726 12356
5672 6150 9156
28 3527 5857
520 7099 11335
405 6173 12865
5847 12843 12934
4289 7679 10386
2950 8021 12938
8844 11214 12955
2130 10760 12665
734 4790 12940
8 6991 12772
19 8205 11289
12 1440 9077
8670 8837 12951
3531 9166 12937
15 8901 8929
838 10114 11740
2648 9959 10934
323 7499 12877
5505 5659 11395
6627 12709 12933
364 1976 12888
8213 9124 12793
9588 10088 11108
299 890 11634
7368 7598 11602
28 4669 12585
15 27 12474
1426 3614 4205
30 2087 11147
6226 6259 12941
になっている。
1860 2354 3967 4292 4488 5243 5373 5766 8378 9111 10468 10505 10774
24 2266 2380 3282 4255 4779 8729 9140 9566 10102 10661 10711 10797
605 650 1108 1669 2251 3133 5847 6197 6902 7545 10521 10600 10773
1016 1428 1612 2335 3102 3810 4926 5953 9964 10246 10569 10734 10784
3195 6308 8029 9030 9397 9461 9833 10239 10499 10675 10736 10757 10773
2 27 3641 4566 7332 9318 9323 9916 10365 10438 10561 10581 10750
2405 2458 4820 6232 6254 6347 7139 7474 8623 8779 8798 10747 10794
3164 4736 6474 7162 7420 7517 7835 8238 8412 8489 9006 10113 10440
20 2372 5561 5649 6907 8393 8505 9181 9567 9595 10388 10483 10714
1071 2899 5135 5780 6616 7111 7773 8582 9015 9912 10139 10387 10768
292 2833 5490 6011 6136 6713 7517 9096 10128 10328 10407 10525 10736
1044 3711 4421 5140 5207 8118 8749 8884 9205 10359 10372 10746 10784
3241 5696 6440 7240 7419 8613 8878 9593 9959 9997 10401 10404 10754
3133 4647 5912 6065 6694 7208 7346 8227 9465 9739 10452 10516 10770
2254 6444 7449 8095 8120 8710 9030 9162 9643 9968 10101 10571 10678
918 1445 2217 4262 4623 5401 5749 7446 7907 9539 10125 10514 10726
6 1341 1788 3105 4359 5263 5470 7552 8249 8644 10609 10674 10733
1994 3000 3151 3173 7742 8335 8438 8741 9232 9296 9817 10023 10257
467 1674 3016 3950 4055 5399 6688 7113 7273 8658 8702 9642 10545
2007 2541 3125 7380 7550 8122 8501 8665 9882 10403 10519 10594 10696
334 587 709 1540 2023 2876 6216 8768 9328 9481 10424 10507 10779
2165 4185 4306 5019 6961 7386 8447 9082 9837 10091 10461 10559 10570
7 903 2948 6312 6654 7738 7980 8312 9104 9743 10070 10278 10406
3047 3154 4160 4378 5461 8711 8809 9040 9173 9252 9537 9995 10735
2018 2355 3828 3854 6201 6696 8313 8459 8550 8833 9586 10202 10224
1402 1908 4286 4660 6029 6115 6737 7538 9495 9517 10055 10509 10644
3442 3589 3868 5051 5322 5580 8725 9046 9170 10041 10613 10681 10689
2733 7826 10622
3597 4753 7086
1394 7297 10264
2848 7502 10304
1649 2405 10783
647 2911 9069
2572 4006 7508
1361 8887 10103
3681 4023 9090
1496 4962 6325
2016 5120 9747
3954 5260 8568
3364 8719 10035
4208 4806 9973
29 3361 3490
1835 2317 10436
7312 8177 9041
7728 8097 10761
2109 7902 9685
5424 8943 9436
4369 7643 9152
2240 10140 10528
3435 6124 10604
8962 9357 10040
26 1931 8629
8275 10455 10643
8 24 4952
3995 6456 10633
28 10300 10337
4894 9286 9429
5587 6721 9120
1859 9198 9762
6374 6453 7011
1319 4530 5442
1507 10711 10798
2115 3445 3641
6668 9139 10163
4038 8117 10295
1479 3403 8247
2522 2934 3562
1526 5073 9650
2136 9820 10636
4214 8464 9891
8018 10330 10610
8984 10209 10647
3414 7272 8599
4883 9077 9525
22 8173 8425
2941 6536 10126
29 6540 7361
5 3787 10468
4264 4818 6906
3903 7041 10412
6078 7661 10619
6922 9723 9890
5112 5416 6253
5925 9961 10447
9 10311 10598
8790 8814 10793
4768 5466 10664
10 10675 10766
6814 8705 10737
17 769 6692
1503 10696 10742
1285 4632 8976
4279 4973 7907
4650 4775 10785
28 729 10331
1914 5240 10723
3569 4921 9561
4 9442 10796
494 2328 9507
1717 8768 10750
9540 10599 10774
11 10075 10644
10246 10607 10753
5510 7088 9053
1347 3584 5523
7872 10596 10736
628 10592 10695
5632 5688 10627
2375 10009 10561
4169 4630 8871
2896 10038 10521
89 9695 9799
20 7563 9069
4534 10321 10697
8212 9868 10716
7485 9312 10327
234 536 6293
5515 7350 9251
283 3182 7167
2444 5378 6130
6183 8315 10726
43 4871 8347
2427 10219 10728
10 21 9448
1067 8312 8420
4793 9522 10105
4688 10536 10724
3825 7496 10709
682 8544 10449
2794 7110 10741
9279 10741 10767
2897 5442 8771
33 7957 10460
5 10393 10792
6225 10224 10798
23 9014 10786
7836 8339 8642
3476 5455 9788
1939 10251 10384
4008 7890 10450
926 2090 3804
1038 2497 10701
22 6220 8405
5153 5944 10367
7260 7726 9529
3039 8397 10665
7262 9644 10083
5531 6248 10795
7926 8248 8413
4649 8971 10182
になっている。
142 2307 2598 2650 4028 4434 5781 5881 6016 6323 6681 6698 8125
2932 4928 5248 5256 5983 6773 6828 7789 8426 8494 8534 8539 8583
899 3295 3833 5399 6820 7400 7753 7890 8109 8451 8529 8564 8602
21 3060 4720 5429 5636 5927 6966 8110 8170 8247 8355 8365 8616
20 1745 2838 3799 4380 4418 4646 5059 7343 8161 8302 8456 8631
9 6274 6725 6792 7195 7333 8027 8186 8209 8273 8442 8548 8632
494 1365 2405 3799 5188 5291 7644 7926 8139 8458 8504 8594 8625
192 574 1179 4387 4695 5089 5831 7673 7789 8298 8301 8612 8632
11 20 1406 6111 6176 6256 6708 6834 7828 8232 8457 8495 8602
6 2654 3554 4483 4966 5866 6795 8069 8249 8301 8497 8509 8623
21 1144 2355 3124 6773 6805 6887 7742 7994 8358 8374 8580 8611
335 4473 4883 5528 6096 7543 7586 7921 8197 8319 8394 8489 8636
2919 4331 4419 4735 6366 6393 6844 7193 8165 8205 8544 8586 8617
12 19 742 930 3009 4330 6213 6224 7292 7430 7792 7922 8137
710 1439 1588 2434 3516 5239 6248 6827 8230 8448 8515 8581 8619
200 1075 1868 5581 7349 7642 7698 8037 8201 8210 8320 8391 8526
3 2501 4252 5256 5292 5567 6136 6321 6430 6486 7571 8521 8636
3062 4599 5885 6529 6616 7314 7319 7567 8024 8153 8302 8372 8598
105 381 1574 4351 5452 5603 5943 7467 7788 7933 8362 8513 8587
787 1857 3386 3659 6550 7131 7965 8015 8040 8312 8484 8525 8537
15 1118 4226 5197 5575 5761 6762 7038 8260 8338 8444 8512 8568
36 5216 5368 5616 6029 6591 8038 8067 8299 8351 8565 8578 8585
1 23 4300 4530 5426 5532 5817 6967 7124 7979 8022 8270 8437
629 2133 4828 5475 5875 5890 7194 8042 8345 8385 8518 8598 8612
11 1065 3782 4237 4993 7104 7863 7904 8104 8228 8321 8383 8565
2131 2274 3168 3215 3220 5597 6347 7812 8238 8354 8527 8557 8614
5600 6591 7491 7696
1766 8281 8626
1725 2280 5120
1650 3445 7652
4312 6911 8626
15 1013 5892
2263 2546 2979
1545 5873 7406
67 726 3697
2860 6443 8542
17 911 2820
1561 4580 6052
79 5269 7134
22 2410 2424
3501 5642 8627
808 6950 8571
4099 6389 7482
4023 5000 7833
5476 5765 7917
1008 3194 7207
20 495 5411
1703 8388 8635
6 4395 4921
200 2053 8206
1089 5126 5562
10 4193 7720
1967 2151 4608
22 738 3513
3385 5066 8152
440 1118 8537
3429 6058 7716
5213 7519 8382
5564 8365 8620
43 3219 8603
4 5409 5815
5 6376 7654
4091 5724 5953
5348 6754 8613
1634 6398 6632
72 2058 8605
3497 5811 7579
3846 6743 8559
15 5933 8629
2133 5859 7068
4151 4617 8566
2960 8270 8410
2059 3617 8210
544 1441 6895
4043 7482 8592
294 2180 8524
3058 8227 8373
364 5756 8617
5383 8555 8619
1704 2480 4181
7338 7929 7990
2615 3905 7981
4298 4548 8296
8262 8319 8630
892 1893 8028
5694 7237 8595
1487 5012 5810
4335 8593 8624
3509 4531 5273
10 22 830
4161 5208 6280
275 7063 8634
4 2725 3113
2279 7403 8174
1637 3328 3930
2810 4939 5624
3 1234 7687
2799 7740 8616
22 7701 8636
4302 7857 7993
7477 7794 8592
9 6111 8591
5 8606 8628
347 3497 4033
1747 2613 8636
1827 5600 7042
580 1822 6842
232 7134 7783
4629 5000 7231
951 2806 4947
571 3474 8577
2437 2496 7945
23 5873 8162
12 1168 7686
8315 8540 8596
1766 2506 4733
929 1516 3338
21 1216 6555
782 1452 8617
8 6083 6087
667 3240 4583
4030 4661 5790
559 7122 8553
3202 4388 4909
2533 3673 8594
1991 3954 6206
6835 7900 7980
189 5722 8573
2680 4928 4998
243 2579 7735
4281 8132 8566
7656 7671 8609
1116 2291 4166
21 388 8021
6 1123 8369
311 4918 8511
0 3248 6290
13 6762 7172
4209 5632 7563
49 127 8074
581 1735 4075
0 2235 5470
2178 5820 6179
16 3575 6054
1095 4564 6458
9 1581 5953
2537 6469 8552
14 3874 4844
0 3269 3551
2114 7372 7926
1875 2388 4057
3232 4042 6663
9 401 583
13 4100 6584
2299 4190 4410
21 3670 4979
になっている。
658 706 898 1149 2577 2622 2772 3266 3329 5243 6079 6271
289 784 1682 3584 3995 4821 4856 5063 5974 6168 6437 6453
658 1426 2043 2065 2986 4118 4284 5394 5444 5477 5727 6018
641 928 1225 2841 4052 4840 4992 5268 5533 6249 6461 6475
2312 2917 3713 3849 4059 4241 4610 5440 5727 6101 6397 6444
1165 1592 1891 2154 3981 4817 5181 5748 5788 6012 6266 6350
13 2758 3069 4233 4697 5100 5279 5677 5919 5969 6280 6422
818 1500 2125 2340 3774 4707 4901 5170 5744 6008 6316 6353
857 3054 3409 3496 3704 4868 5326 6211 6292 6356 6367 6381
0 7 12 1709 2166 3418 3723 4887 5770 6043 6069 6431
2481 3379 4650 4900 4919 5060 5410 5425 6056 6173 6283 6386
15 814 854 1871 2934 3387 3915 5180 5303 5442 5581 5665
146 1882 3076 4458 4848 5252 5602 5778 5821 6213 6251 6401
2 947 1419 1566 3437 3646 4615 4634 4735 5819 5943 6280
1231 2309 2920 4158 4185 4298 4711 5082 5757 5762 6204 6209
257 297 337 2783 3230 4134 4480 4749 5295 5689 5921 6202
1436 2151 2629 3217 3930 4078 5386 5799 5906 6146 6226 6366
133 530 2448 4745 5000 5020 5224 5273 6211 6266 6431 6453
13 2644 3895 3898 4485 4722 5142 5462 5951 6031 6084 6351
6 3000 3873 3995 4680 5158 5504 5692 5755 6255 6338 6359
166 465 1658 2549 2941 4244 5071 5149 5452 5874 5939 6038
2309 2937 4282 4628 5113 5454 5731 5825 6021 6171 6402 6472
3 1077 2116 2426 2830 4853 5066 5571 5850 5916 6389 6421
817 1608 2229 2925 3281 4393 5042 5058 5377 5464 5588 6448
1848 3871 4381 4776 5366 5578 5648 6143 6389 6434 6465 6473
1263 1616 3150 3497 3759 4078 5530 5665 5694 5913 6397 6420
11 813 2185 2795 3349 4652 4678 5078 5504 6011 6286 6387
3060 3161 4584 4996 5143 5542 5697 5937 6141 6155 6342 6445
1638 2333 2632 3450 3505 3911 4399 4454 5499 5860 6044 6360
650 1744 4517
5772 6071 6471
3582 3622 5776
6153 6380 6446
3977 5932 6447
2071 4597 4891
11 1428 3776
1111 3874 5048
1410 2144 4445
4681 5481 6462
4044 5037 5497
2716 2891 6411
3299 4384 6224
1843 6087 6400
4664 5009 5856
1548 4383 5055
3172 4190 6373
5899 6443 6470
2572 3647 6240
1295 2158 6466
5604 6269 6368
3 5551 6454
3325 5797 6261
666 1397 5538
3069 4274 6410
4042 5992 6437
743 3075 3447
1344 2725 6386
283 2808 6303
2 4627 4632
26 1565 4000
4012 4946 6472
1629 6158 6467
6300 6351 6376
2969 4344 4440
2317 3115 4832
2099 5263 6285
2409 5868 5997
3752 4200 6350
3125 5841 6142
1 2249 6328
16 2525 6379
3198 5269 5960
4 1705 2069
990 4948 5520
1664 3836 4521
1765 4110 6454
9 1373 6387
1969 2405 6368
623 1428 3946
3111 6380 6436
1861 5611 5934
9 2444 3081
5 5508 6317
3184 4988 5995
1060 4803 6400
5021 5826 6289
1608 4754 5648
4702 6391 6421
3899 4811 6128
927 2286 5313
4123 6181 6453
2893 4150 5261
605 4332 5094
17 3518 6358
2858 6126 6478
15 1316 6465
2 2032 2983
5249 6340 6427
5 6003 6200
4478 6315 6420
5158 6390 6447
2598 3229 5399
3747 6424 6446
1412 2453 6332
5256 5715 6455
2137 3421 4368
15 3880 5245
17 3156 5638
3227 3798 6230
2094 3129 6458
1412 5573 5932
175 1182 6304
3555 6407 6463
583 1654 6339
14 6261 6449
3553 5383 5679
2092 2744 4153
0 4466 6472
11 3840 4354
17 5457 6222
1467 6083 6220
3449 3858 6337
3782 5318 6426
417 5038 5790
3571 5638 5873
6117 6241 6476
1898 5680 6219
3235 3817 6429
2095 4194 6224
2 4092 6448
5 6330 6383
285 5075 6334
10 505 2867
1183 5956 6466
839 4716 6471
984 3254 6432
1501 4790 6465
8 1457 1707
1660 1969 6438
4349 6182 6305
1423 3848 5490
1651 2969 6345
344 4164 6298
2397 6027 6274
2233 2778 6161
13 1778 2977
9 1916 3377
0 3 6190
395 4893 6394
3512 4098 6400
3490 6281 6473
12 1359 6465
4202 5179 6412
3007 3542 4271
2400 3350 6351
7 5490 5716
4695 5231 6266
777 6292 6402
919 4851 6367
6 644 3893
5386 6190 6434
17 169 4896
になっている。
85 314 1602 1728 1929 2295 2729 2924 3779 4054 4276
918 1378 1838 1903 2399 2524 2937 3615 3740 4140 4213
1361 1430 2639 2648 2910 3418 3511 3543 4177 4209 4248
472 1143 1318 1545 1830 2228 2249 2256 3626 3839 3991
226 1401 2154 2318 2851 3317 3468 3944 3983 4047 4093
490 1145 1247 1851 2671 2776 3152 3229 3345 3758 3786
522 1393 1473 2196 2707 3052 3398 3814 3827 4148 4301
417 1982 2176 2336 2459 2806 3005 3771 3870 4080 4243
112 1040 1596 1621 1685 2118 2571 3359 3945 4034 4171
646 1705 2181 2439 2808 2851 2987 3044 3494 4049 4312
6 11 115 245 663 1773 2624 3444 3601 3952 4246
11 541 1020 1326 2259 2347 2750 2861 3328 3428 4126
515 941 1233 1804 2295 2528 3265 3826 4002 4022 4224
46 484 679 1949 2342 2929 3555 3860 3918 4068 4113
1832 2023 2279 2376 2965 3278 3318 3549 3640 3843 3910
241 943 1222 1583 1637 2745 3338 4080 4086 4203 4300
11 1419 1841 2398 2920 3409 3703 3768 3878 4052 4254
878 2049 2123 2431 2657 2704 3135 3342 3728 4141 4162
16 837 1267 1410 2100 3026 3099 3107 4042 4129 4157
133 646 1367 1394 2118 2311 2676 2956 3195 3536 3657
698 1444 2129 2432 2494 2793 2947 3852 3985 4254 4319
11 1076 1618 1995 2332 2743 2934 3009 3565 4169 4188
14 20 808 2629 2681 3090 3491 3835 4017 4068 4083
433 1386 2416 2570 2950 3611 3869 3969 4248 4251 4316
384 1292 1534 2610 2617 3559 3638 3964 4131 4293 4313
271 564 1719 2288 2597 2674 3429 3455 3793 4074 4286
133 190 815 955 1485 2000 2860 3000 3734 4013 4287
559 771 1762 2537 2764 2816 3186 3806 3933 4224 4271
11 733 1198 1735 1856 2668 2754 3216 4070 4113 4311
4 806 1832 2047 2058 2724 3387 3793 3833 4005 4319
506 1456 2339 3069 3343 3442 3889 3939 4013 4212 4278
2038 3980 4313
64 2373 4080
800 1535 4166
1030 3759 4002
1687 3269 4225
1219 2632 3878
719 2916 4277
1261 1930 3459
777 1568 1914
4 397 3290
10 3451 4115
3629 3885 4155
2652 3668 4026
135 3172 4319
1426 1970 3657
199 1268 2064
570 845 2761
41 1067 3498
1588 2482 2750
1615 2013 2715
121 1812 2588
10 992 1082
1929 4225 4279
6 1967 3760
593 1812 4107
891 2146 4158
924 2282 3585
592 2971 4235
260 3493 4313
2423 3180 3449
2042 3118 3625
2877 3064 3882
7 2139 4316
4 7 2954
1398 3947 4272
3675 4253 4318
1561 1977 2432
2531 4192 4209
1032 1102 4268
75 1718 3438
925 1073 4171
2124 2762 4148
4 3455 4069
3 1279 3382
1277 1746 3969
2727 3127 4230
584 1108 3454
9 2057 3061
1608 4103 4310
2673 3164 3713
1379 4072 4318
950 3447 4146
2509 4255 4296
819 1352 3371
3562 3865 4041
940 1217 3607
114 2544 4310
4 2178 4213
2035 4246 4251
272 1236 2733
953 2762 4115
1853 3496 4309
1119 3740 4318
2051 4058 4317
0 3162 4207
2389 4034 4111
4 3395 4301
3716 4089 4198
6 4272 4311
1 4 1854
4238 4299 4305
7 10 3737
11 3764 4296
297 1912 4117
1087 1796 4056
2153 3882 4030
962 4043 4203
243 3841 4308
2183 3886 4216
943 1974 2897
278 3224 3933
3 4196 4245
3409 4301 4315
2 2176 3214
462 3203 4008
478 2178 4202
3593 3825 4216
115 2796 4225
3827 4196 4251
1375 4301 4306
296 407 2055
688 3913 4281
3446 3840 4314
1073 3444 4146
1556 2761 3391
2 3543 4264
1378 3347 4305
847 1952 2745
1 1743 4042
2087 3048 4254
1010 4073 4132
2610 4129 4152
4106 4120 4313
7 4282 4304
3885 4227 4319
1235 4105 4195
1700 2332 4224
9 3750 4282
1539 4013 4310
3734 3834 4011
1397 2758 3645
7 1000 2984
11 3433 4068
1139 1800 3352
8 546 2561
1 4209 4239
2366 4063 4282
279 2524 2533
657 1913 4006
2322 2623 2960
758 803 2304
9 13 4241
3887 4299 4318
2612 3830 4230
1300 1596 2155
3622 3671 4230
2491 3722 3977
735 3812 4201
3204 3796 4317
2727 4292 4305
1062 2676 4255
2777 3131 4286
2518 3352 3937
4225 4255 4317
3644 3822 4311
1853 3754 4094
599 2608 3276
になっている。
212 499 911 940 1392
316 563 1527 2006 2077
2 1906 2043 2112 2123
537 901 1582 1812 1955
5 978 1280 1933 2145
5 2035 2044 2108 2121
5 939 1874 1974
4 1069 1758
694 2096 2106
1129 1511 1659
1564 2089 2159
2 1605 2004
474 1341 2003
103 2128 2150
1656 1993 2153
1881 2122 2138
1088 1968 2141
1 298 2073
1042 1724 2137
1253 1758 2145
1209 1566 2123
1466 2116 2155
43 2006 2049
592 1806 1865
3 143 2149
1158 1448 2002
1422 2152 2157
485 2119 2150
371 1831 2086
204 2042 2151
174 544 974
1469 1795 1995
13 708 1683
5 1144 2030
486 1309 1576
165 2030 2147
504 2073 2126
263 565 1798
239 861 1861
862 1610 1716
1346 1971 2128
5 804 1399
2139 2144 2155
4 2136 2159
1485 2059 2158
50 1091 1332
373 1730 2092
59 1086 1401
1166 1781 2065
213 2080 2154
492 1905 2110
1 1517 2126
722 1427 2146
885 991 1842
3 278 1806
967 1354 1907
1697 2047 2156
684 1924 2151
2077 2122 2157
978 2054 2135
435 2034 2150
136 1997 2125
1504 1850 2153
1404 1989 2119
109 1001 2152
780 1473 2150
198 1723 2062
927 2087 2138
1 666 2018
1293 1960 2141
1648 2033 2144
681 1578 1999
1342 2022 2157
949 1907 1994
138 1261 2135
3 608 982
1211 1501 2150
201 228 1186
1295 2089 2132
267 556 2142
801 2052 2122
1382 2135 2155
572 1503 1704
346 1183 2129
1926 2090 2149
1337 2133 2140
5 1806 2125
1383 1628 2068
1193 1626 2138
1999 2115 2146
217 274 2021
3 816 2024
1380 2138 2157
607 1385 2110
184 1195 2063
0 1767 2108
0 2081 2097
1135 2036 2128
1748 2001 2125
797 1552 1926
1046 1890 2128
291 1859 2131
1075 1214 1762
60 549 1943
581 1197 1232
1009 2026 2136
884 2002 2117
1 576 1449
519 1968 2114
5 1489 1630
1926 2037 2158
2 1249 2159
0 811 2114
2055 2152 2159
802 1911 2120
204 1033 2033
1840 2012 2037
1746 2111 2155
1098 1835 2157
2 1492 1831
353 1537 1830
375 1264 2036
2 1638 2035
1096 1971 2021
950 1809 1884
253 467 1600
5 379 1833
4 1698 1970
37 1637 2136
1174 1460 2157
612 1827 2134
1783 1802 1949
2029 2118 2151
1984 2030 2141
2 347 462
862 1693 2121
2 895 1401
4 1901 2100
1183 1674 2069
1575 1940 2158
5 1904 2097
1044 2029 2092
1441 1943 2150
0 3 1300
2 516 1735
503 1342 2019
1421 1914 2131
28 986 1467
1270 1851 1988
481 1265 2016
530 546 909
653 1909 2158
1805 2002 2149
2 1359 1518
1640 2104 2129
1656 2109 2155
1307 1762 2114
565 1647 2118
1690 2081 2156
1 300 1995
5 1681 2151
1602 2050 2156
1 1960 2153
2061 2070 2138
1581 1673 2142
1048 1142 2101
1867 1991 2055
856 1640 1878
251 561 966
343 1816 2114
3 966 2045
1885 1922 2158
57 556 2059
732 1724 2147
になっている。
・・・(8)
・・・(9)
・・・(10)
・・・(11)
・・・(12)
Claims (58)
- LDPC(Low Density Parity Check)符号の検査行列に基づき、情報ビットを、符号長が64800ビットで符号化率が24/30のLDPC符号に符号化する符号化部を備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部と前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
1504 2103 2621 2840 3869 4594 5246 6314 7327 7364 10425 11934 12898 12954
27 1903 3923 4513 7812 8098 8428 9789 10519 11345 12032 12157 12573 12930
17 191 660 2451 2475 2976 3398 3616 5769 6724 8641 10046 11552 12842
13 1366 4993 6468 7689 8563 9131 10012 10914 11574 11837 12203 12715 12946
432 872 2603 3286 3306 3385 4137 5563 7540 9339 9948 12315 12656 12929
1113 1394 4104 4186 7240 8827 11522 11833 12359 12363 12629 12821 12904 12946
14 441 1432 1677 2432 8981 11478 11507 12599 12783 12793 12912 12922 12943
1579 1806 7971 8586 9845 10357 11600 12007 12020 12339 12576 12817 12830 12904
20 546 3672 5538 6944 8052 8781 9743 12269 12393 12418 12549 12555 12718
1 3540 4397 5011 6626 8617 9587 10360 10602 11402 11983 12068 12495 12838
30 1572 4908 7421 8041 8910 8963 11005 11930 12240 12340 12467 12892 12933
33 2060 3907 4215 5545 8306 8655 8743 8806 9315 9364 10685 11954 12959
1338 2596 4876 5207 9555 10421 10929 11648 11739 12375 12416 12643 12742 12754
9469 10544 10932 11250 11426 11582 11846 12139 12202 12210 12356 12378 12873 12929
2681 3337 3616 6113 7078 8167 8624 9697 10908 11781 11855 12095 12475 12659
28 4086 5432 6555 6848 7368 8794 11483 11572 12414 12816 12894 12936 12957
5 5044 5572 9023 9192 9589 9979 10009 10855 10991 11715 12314 12610 12945
17 272 602 5681 6530 9572 9886 11061 11495 12238 12265 12483 12885 12955
22 2245 4282 4469 5007 6650 6733 10151 10401 11571 12004 12261 12805 12844
23 3270 4468 8621 9662 11240 11934 12091 12444 12691 12717 12858 12888 12917
740 1519 4923 6191 7878 8350 9293 10779 11020 11287 11630 12792 12862 12920
12 28 3584 6072 7079 8075 10477 11130 11383 11780 12341 12667 12818 12927
14 118 5283 5382 8301 9097 9413 9664 10437 10701 11124 12685 12730 12734
32 1426 3078 4325 5353 7780 9042 9928 10077 10377 10679 11191 11750 12611
1 669 3831 3980 5381 5412 6552 8453 9435 10243 11546 11821 11987 12807
232 483 919 1232 2156 2396 2990 3774 8539 8704 8819 10810 11868 12634
2381 7309 9334
348 6494 12623
4872 6257 11090
7 11970 11985
6615 12788 12855
1173 5269 12647
1944 7738 8116
17 4828 9175
2329 6034 12642
1254 2366 5013
2984 5078 5664
7423 10265 11528
1656 8526 8716
22 287 2837
18 100 3079
299 3171 12169
33 5920 11144
1286 3650 9309
2283 8809 12588
3199 8242 9081
2507 6846 8113
5211 8722 12689
1064 2592 8659
6136 6925 12958
1256 12789 12932
4274 8045 8788
1824 3209 6926
11 8899 12669
6249 6338 8730
641 9679 12831
3459 9876 11185
3226 6148 8173
9078 12126 12771
10907 11278 12731
3392 4020 12838
2814 11588 12909
6063 9214 11519
6064 6827 12683
1610 2452 6582
903 6289 8074
4592 8138 12952
2587 6271 9945
2733 11844 11893
581 4601 10020
14 5597 6049
343 3582 5931
5263 6521 12846
1394 2457 5251
11 4627 12747
2650 10366 12390
6285 11893 12062
10143 12892 12956
8448 11917 12330
4209 11693 12356
1529 2360 9086
5389 8148 10224
64 4876 12862
9483 12659 12887
3587 6767 12478
3122 5245 9044
3267 10118 11466
1347 3857 6705
9384 9576 11971
1366 8708 10758
412 4249 12863
1676 10488 11850
17 1605 2455
14 111 6045
11368 12919 12953
10588 11530 12937
4549 5143 12218
3088 4185 11674
23 2554 7823
6615 9291 9863
2229 3629 10855
3818 5509 12764
2740 11525 12914
8297 8611 12948
3606 11104 12920
5097 10412 12759
6502 7266 12072
5425 5490 10728
22 73 8462
32 12439 12657
8483 9540 10430
7275 7377 7420
5748 9726 12356
5672 6150 9156
28 3527 5857
520 7099 11335
405 6173 12865
5847 12843 12934
4289 7679 10386
2950 8021 12938
8844 11214 12955
2130 10760 12665
734 4790 12940
8 6991 12772
19 8205 11289
12 1440 9077
8670 8837 12951
3531 9166 12937
15 8901 8929
838 10114 11740
2648 9959 10934
323 7499 12877
5505 5659 11395
6627 12709 12933
364 1976 12888
8213 9124 12793
9588 10088 11108
299 890 11634
7368 7598 11602
28 4669 12585
15 27 12474
1426 3614 4205
30 2087 11147
6226 6259 12941
である
データ処理装置。 - 前記検査行列初期値テーブルの行をiと表すとともに、前記LDPC符号のパリティ長をMと表すとき、
前記検査行列の2+360×(i-1)列目は、前記検査行列初期値テーブルで1の要素の位置が表される前記検査行列の1+360×(i-1)列目を、q=M/360だけ下方向にサイクリックシフトした列である
請求項1に記載のデータ処理装置。 - 前記検査行列の1+360×(i-1)列については、
前記検査行列初期値テーブルのi行目が、前記検査行列の1+360×(i-1)列目の1の要素の行番号を表し、
前記検査行列の1+360×(i-1)列目以外の列である2+360×(i-1)列目から360×i列目までの各列については、
前記検査行列初期値テーブルのi行目のj列目の数値をhi,jと表すとともに、前記検査行列Hのw列目の、j個目の1の要素の行番号をHw-jと表すとき、
前記検査行列の1+360×(i-1)列目以外の列であるw列目の、1の要素の行番号Hw-jは、式Hw-j=mod{hi,j+mod((w-1),360)×M/360,M)で表される
請求項2に記載のデータ処理装置。 - 前記qは、36である
請求項2に記載のデータ処理装置。 - 前記LDPC符号の符号ビットのパリティビットのみをインターリーブするパリティインターリーブ部をさらに備える
請求項1に記載のデータ処理装置。 - 前記LDPC符号の符号ビットを、カラム方向にずらして記憶することによりカラムツイストインターリーブを行うカラムツイストインターリーブ部をさらに備える
請求項1に記載のデータ処理装置。 - 前記LDPC符号の符号ビットを、所定のディジタル変調方式で定める所定数の信号点のうちのいずれかに対応するシンボルのシンボルビットに入れ替える入れ替え部をさらに備える
請求項1に記載のデータ処理装置。 - 前記入れ替え部は、カラム方向に記憶されてロウ方向に読み出される前記符号ビットを入れ替える
請求項7に記載のデータ処理装置。 - 前記検査行列は、サイクル4が存在しない検査行列である
請求項1に記載のデータ処理装置。 - 前記検査行列は、マルチエッジタイプのデンシティエボリューションによって検出される、BERが落ち始めるEb/N0である性能閾値が所定値以下になるLDPC符号のアンサンブルに属するLDPC符号の検査行列である
請求項1に記載のデータ処理装置。 - LDPC(Low Density Parity Check)符号の検査行列に基づき、情報ビットを、符号長が64800ビットで符号化率が24/30のLDPC符号に符号化する符号化ステップを備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部と前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
1504 2103 2621 2840 3869 4594 5246 6314 7327 7364 10425 11934 12898 12954
27 1903 3923 4513 7812 8098 8428 9789 10519 11345 12032 12157 12573 12930
17 191 660 2451 2475 2976 3398 3616 5769 6724 8641 10046 11552 12842
13 1366 4993 6468 7689 8563 9131 10012 10914 11574 11837 12203 12715 12946
432 872 2603 3286 3306 3385 4137 5563 7540 9339 9948 12315 12656 12929
1113 1394 4104 4186 7240 8827 11522 11833 12359 12363 12629 12821 12904 12946
14 441 1432 1677 2432 8981 11478 11507 12599 12783 12793 12912 12922 12943
1579 1806 7971 8586 9845 10357 11600 12007 12020 12339 12576 12817 12830 12904
20 546 3672 5538 6944 8052 8781 9743 12269 12393 12418 12549 12555 12718
1 3540 4397 5011 6626 8617 9587 10360 10602 11402 11983 12068 12495 12838
30 1572 4908 7421 8041 8910 8963 11005 11930 12240 12340 12467 12892 12933
33 2060 3907 4215 5545 8306 8655 8743 8806 9315 9364 10685 11954 12959
1338 2596 4876 5207 9555 10421 10929 11648 11739 12375 12416 12643 12742 12754
9469 10544 10932 11250 11426 11582 11846 12139 12202 12210 12356 12378 12873 12929
2681 3337 3616 6113 7078 8167 8624 9697 10908 11781 11855 12095 12475 12659
28 4086 5432 6555 6848 7368 8794 11483 11572 12414 12816 12894 12936 12957
5 5044 5572 9023 9192 9589 9979 10009 10855 10991 11715 12314 12610 12945
17 272 602 5681 6530 9572 9886 11061 11495 12238 12265 12483 12885 12955
22 2245 4282 4469 5007 6650 6733 10151 10401 11571 12004 12261 12805 12844
23 3270 4468 8621 9662 11240 11934 12091 12444 12691 12717 12858 12888 12917
740 1519 4923 6191 7878 8350 9293 10779 11020 11287 11630 12792 12862 12920
12 28 3584 6072 7079 8075 10477 11130 11383 11780 12341 12667 12818 12927
14 118 5283 5382 8301 9097 9413 9664 10437 10701 11124 12685 12730 12734
32 1426 3078 4325 5353 7780 9042 9928 10077 10377 10679 11191 11750 12611
1 669 3831 3980 5381 5412 6552 8453 9435 10243 11546 11821 11987 12807
232 483 919 1232 2156 2396 2990 3774 8539 8704 8819 10810 11868 12634
2381 7309 9334
348 6494 12623
4872 6257 11090
7 11970 11985
6615 12788 12855
1173 5269 12647
1944 7738 8116
17 4828 9175
2329 6034 12642
1254 2366 5013
2984 5078 5664
7423 10265 11528
1656 8526 8716
22 287 2837
18 100 3079
299 3171 12169
33 5920 11144
1286 3650 9309
2283 8809 12588
3199 8242 9081
2507 6846 8113
5211 8722 12689
1064 2592 8659
6136 6925 12958
1256 12789 12932
4274 8045 8788
1824 3209 6926
11 8899 12669
6249 6338 8730
641 9679 12831
3459 9876 11185
3226 6148 8173
9078 12126 12771
10907 11278 12731
3392 4020 12838
2814 11588 12909
6063 9214 11519
6064 6827 12683
1610 2452 6582
903 6289 8074
4592 8138 12952
2587 6271 9945
2733 11844 11893
581 4601 10020
14 5597 6049
343 3582 5931
5263 6521 12846
1394 2457 5251
11 4627 12747
2650 10366 12390
6285 11893 12062
10143 12892 12956
8448 11917 12330
4209 11693 12356
1529 2360 9086
5389 8148 10224
64 4876 12862
9483 12659 12887
3587 6767 12478
3122 5245 9044
3267 10118 11466
1347 3857 6705
9384 9576 11971
1366 8708 10758
412 4249 12863
1676 10488 11850
17 1605 2455
14 111 6045
11368 12919 12953
10588 11530 12937
4549 5143 12218
3088 4185 11674
23 2554 7823
6615 9291 9863
2229 3629 10855
3818 5509 12764
2740 11525 12914
8297 8611 12948
3606 11104 12920
5097 10412 12759
6502 7266 12072
5425 5490 10728
22 73 8462
32 12439 12657
8483 9540 10430
7275 7377 7420
5748 9726 12356
5672 6150 9156
28 3527 5857
520 7099 11335
405 6173 12865
5847 12843 12934
4289 7679 10386
2950 8021 12938
8844 11214 12955
2130 10760 12665
734 4790 12940
8 6991 12772
19 8205 11289
12 1440 9077
8670 8837 12951
3531 9166 12937
15 8901 8929
838 10114 11740
2648 9959 10934
323 7499 12877
5505 5659 11395
6627 12709 12933
364 1976 12888
8213 9124 12793
9588 10088 11108
299 890 11634
7368 7598 11602
28 4669 12585
15 27 12474
1426 3614 4205
30 2087 11147
6226 6259 12941
である
データ処理方法。 - 前記検査行列初期値テーブルの行をiと表すとともに、前記LDPC符号のパリティ長をMと表すとき、
前記検査行列の2+360×(i-1)列目は、前記検査行列初期値テーブルで1の要素の位置が表される前記検査行列の1+360×(i-1)列目を、q=M/360だけ下方向にサイクリックシフトした列である
請求項11に記載のデータ処理方法。 - 前記検査行列の1+360×(i-1)列については、
前記検査行列初期値テーブルのi行目が、前記検査行列の1+360×(i-1)列目の1の要素の行番号を表し、
前記検査行列の1+360×(i-1)列目以外の列である2+360×(i-1)列目から360×i列目までの各列については、
前記検査行列初期値テーブルのi行目のj列目の数値をhi,jと表すとともに、前記検査行列Hのw列目の、j個目の1の要素の行番号をHw-jと表すとき、
前記検査行列の1+360×(i-1)列目以外の列であるw列目の、1の要素の行番号Hw-jは、式Hw-j=mod{hi,j+mod((w-1),360)×M/360,M)で表される
請求項12に記載のデータ処理方法。 - 前記qは、36である
請求項12に記載のデータ処理方法。 - 前記LDPC符号の符号ビットのパリティビットのみをインターリーブする
請求項11に記載のデータ処理方法。 - 前記LDPC符号の符号ビットを、カラム方向にずらして記憶することによりカラムツイストインターリーブを行う
請求項11に記載のデータ処理方法。 - 前記LDPC符号の符号ビットを、所定のディジタル変調方式で定める所定数の信号点のうちのいずれかに対応するシンボルのシンボルビットに入れ替える
請求項11に記載のデータ処理方法。 - 前記符号ビットの入れ替えでは、カラム方向に記憶されてロウ方向に読み出される前記符号ビットを入れ替える
請求項17に記載のデータ処理方法。 - 前記検査行列は、サイクル4が存在しない検査行列である
請求項11に記載のデータ処理方法。 - 前記検査行列は、マルチエッジタイプのデンシティエボリューションによって検出される、BERが落ち始めるEb/N0である性能閾値が所定値以下になるLDPC符号のアンサンブルに属するLDPC符号の検査行列である
請求項11に記載のデータ処理方法。 - LDPC(Low Density Parity Check)符号の検査行列に基づき、符号長が64800ビットで符号化率が24/30のLDPC符号を復号する復号部を備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部と前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
1504 2103 2621 2840 3869 4594 5246 6314 7327 7364 10425 11934 12898 12954
27 1903 3923 4513 7812 8098 8428 9789 10519 11345 12032 12157 12573 12930
17 191 660 2451 2475 2976 3398 3616 5769 6724 8641 10046 11552 12842
13 1366 4993 6468 7689 8563 9131 10012 10914 11574 11837 12203 12715 12946
432 872 2603 3286 3306 3385 4137 5563 7540 9339 9948 12315 12656 12929
1113 1394 4104 4186 7240 8827 11522 11833 12359 12363 12629 12821 12904 12946
14 441 1432 1677 2432 8981 11478 11507 12599 12783 12793 12912 12922 12943
1579 1806 7971 8586 9845 10357 11600 12007 12020 12339 12576 12817 12830 12904
20 546 3672 5538 6944 8052 8781 9743 12269 12393 12418 12549 12555 12718
1 3540 4397 5011 6626 8617 9587 10360 10602 11402 11983 12068 12495 12838
30 1572 4908 7421 8041 8910 8963 11005 11930 12240 12340 12467 12892 12933
33 2060 3907 4215 5545 8306 8655 8743 8806 9315 9364 10685 11954 12959
1338 2596 4876 5207 9555 10421 10929 11648 11739 12375 12416 12643 12742 12754
9469 10544 10932 11250 11426 11582 11846 12139 12202 12210 12356 12378 12873 12929
2681 3337 3616 6113 7078 8167 8624 9697 10908 11781 11855 12095 12475 12659
28 4086 5432 6555 6848 7368 8794 11483 11572 12414 12816 12894 12936 12957
5 5044 5572 9023 9192 9589 9979 10009 10855 10991 11715 12314 12610 12945
17 272 602 5681 6530 9572 9886 11061 11495 12238 12265 12483 12885 12955
22 2245 4282 4469 5007 6650 6733 10151 10401 11571 12004 12261 12805 12844
23 3270 4468 8621 9662 11240 11934 12091 12444 12691 12717 12858 12888 12917
740 1519 4923 6191 7878 8350 9293 10779 11020 11287 11630 12792 12862 12920
12 28 3584 6072 7079 8075 10477 11130 11383 11780 12341 12667 12818 12927
14 118 5283 5382 8301 9097 9413 9664 10437 10701 11124 12685 12730 12734
32 1426 3078 4325 5353 7780 9042 9928 10077 10377 10679 11191 11750 12611
1 669 3831 3980 5381 5412 6552 8453 9435 10243 11546 11821 11987 12807
232 483 919 1232 2156 2396 2990 3774 8539 8704 8819 10810 11868 12634
2381 7309 9334
348 6494 12623
4872 6257 11090
7 11970 11985
6615 12788 12855
1173 5269 12647
1944 7738 8116
17 4828 9175
2329 6034 12642
1254 2366 5013
2984 5078 5664
7423 10265 11528
1656 8526 8716
22 287 2837
18 100 3079
299 3171 12169
33 5920 11144
1286 3650 9309
2283 8809 12588
3199 8242 9081
2507 6846 8113
5211 8722 12689
1064 2592 8659
6136 6925 12958
1256 12789 12932
4274 8045 8788
1824 3209 6926
11 8899 12669
6249 6338 8730
641 9679 12831
3459 9876 11185
3226 6148 8173
9078 12126 12771
10907 11278 12731
3392 4020 12838
2814 11588 12909
6063 9214 11519
6064 6827 12683
1610 2452 6582
903 6289 8074
4592 8138 12952
2587 6271 9945
2733 11844 11893
581 4601 10020
14 5597 6049
343 3582 5931
5263 6521 12846
1394 2457 5251
11 4627 12747
2650 10366 12390
6285 11893 12062
10143 12892 12956
8448 11917 12330
4209 11693 12356
1529 2360 9086
5389 8148 10224
64 4876 12862
9483 12659 12887
3587 6767 12478
3122 5245 9044
3267 10118 11466
1347 3857 6705
9384 9576 11971
1366 8708 10758
412 4249 12863
1676 10488 11850
17 1605 2455
14 111 6045
11368 12919 12953
10588 11530 12937
4549 5143 12218
3088 4185 11674
23 2554 7823
6615 9291 9863
2229 3629 10855
3818 5509 12764
2740 11525 12914
8297 8611 12948
3606 11104 12920
5097 10412 12759
6502 7266 12072
5425 5490 10728
22 73 8462
32 12439 12657
8483 9540 10430
7275 7377 7420
5748 9726 12356
5672 6150 9156
28 3527 5857
520 7099 11335
405 6173 12865
5847 12843 12934
4289 7679 10386
2950 8021 12938
8844 11214 12955
2130 10760 12665
734 4790 12940
8 6991 12772
19 8205 11289
12 1440 9077
8670 8837 12951
3531 9166 12937
15 8901 8929
838 10114 11740
2648 9959 10934
323 7499 12877
5505 5659 11395
6627 12709 12933
364 1976 12888
8213 9124 12793
9588 10088 11108
299 890 11634
7368 7598 11602
28 4669 12585
15 27 12474
1426 3614 4205
30 2087 11147
6226 6259 12941
である
データ処理装置。 - 前記検査行列初期値テーブルの行をiと表すとともに、前記LDPC符号のパリティ長をMと表すとき、
前記検査行列の2+360×(i-1)列目は、前記検査行列初期値テーブルで1の要素の位置が表される前記検査行列の1+360×(i-1)列目を、q=M/360だけ下方向にサイクリックシフトした列である
請求項21に記載のデータ処理装置。 - 前記検査行列の1+360×(i-1)列については、
前記検査行列初期値テーブルのi行目が、前記検査行列の1+360×(i-1)列目の1の要素の行番号を表し、
前記検査行列の1+360×(i-1)列目以外の列である2+360×(i-1)列目から360×i列目までの各列については、
前記検査行列初期値テーブルのi行目のj列目の数値をhi,jと表すとともに、前記検査行列Hのw列目の、j個目の1の要素の行番号をHw-jと表すとき、
前記検査行列の1+360×(i-1)列目以外の列であるw列目の、1の要素の行番号Hw-jは、式Hw-j=mod{hi,j+mod((w-1),360)×M/360,M)で表される
請求項22に記載のデータ処理装置。 - 前記qは、36である
請求項22に記載のデータ処理装置。 - 前記LDPC符号の符号ビットを、カラム方向にずらして記憶することによりカラムツイストインターリーブが行われている場合に、前記LDPC符号の符号ビットを元の並びに戻すカラムツイストデインターリーブを行うカラムツイストデインターリーブ部をさらに備える
請求項21に記載のデータ処理装置。 - 前記LDPC符号の符号ビットを、所定のディジタル変調方式で定める所定数の信号点のうちのいずれかに対応するシンボルのシンボルビットに入れ替える入れ替え処理が行われている場合に、前記シンボルビットとして位置が入れ替えられた前記符号ビットを、元の位置に戻す逆入れ替え処理を行う逆入れ替え部をさらに備える
請求項21に記載のデータ処理装置。 - 前記逆入れ替え部は、ロウ方向に記憶されてカラム方向に読み出される前記符号ビットを元の位置に戻す逆入れ替え処理を行う
請求項26に記載のデータ処理装置。 - 前記検査行列は、サイクル4が存在しない検査行列である
請求項21に記載のデータ処理装置。 - 前記検査行列は、マルチエッジタイプのデンシティエボリューションによって検出される、BERが落ち始めるEb/N0である性能閾値が所定値以下になるLDPC符号のアンサンブルに属するLDPC符号の検査行列である
請求項21に記載のデータ処理装置。 - LDPC(Low Density Parity Check)符号の検査行列に基づき、符号長が64800ビットで符号化率が24/30のLDPC符号を復号する復号ステップを備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部と前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
1504 2103 2621 2840 3869 4594 5246 6314 7327 7364 10425 11934 12898 12954
27 1903 3923 4513 7812 8098 8428 9789 10519 11345 12032 12157 12573 12930
17 191 660 2451 2475 2976 3398 3616 5769 6724 8641 10046 11552 12842
13 1366 4993 6468 7689 8563 9131 10012 10914 11574 11837 12203 12715 12946
432 872 2603 3286 3306 3385 4137 5563 7540 9339 9948 12315 12656 12929
1113 1394 4104 4186 7240 8827 11522 11833 12359 12363 12629 12821 12904 12946
14 441 1432 1677 2432 8981 11478 11507 12599 12783 12793 12912 12922 12943
1579 1806 7971 8586 9845 10357 11600 12007 12020 12339 12576 12817 12830 12904
20 546 3672 5538 6944 8052 8781 9743 12269 12393 12418 12549 12555 12718
1 3540 4397 5011 6626 8617 9587 10360 10602 11402 11983 12068 12495 12838
30 1572 4908 7421 8041 8910 8963 11005 11930 12240 12340 12467 12892 12933
33 2060 3907 4215 5545 8306 8655 8743 8806 9315 9364 10685 11954 12959
1338 2596 4876 5207 9555 10421 10929 11648 11739 12375 12416 12643 12742 12754
9469 10544 10932 11250 11426 11582 11846 12139 12202 12210 12356 12378 12873 12929
2681 3337 3616 6113 7078 8167 8624 9697 10908 11781 11855 12095 12475 12659
28 4086 5432 6555 6848 7368 8794 11483 11572 12414 12816 12894 12936 12957
5 5044 5572 9023 9192 9589 9979 10009 10855 10991 11715 12314 12610 12945
17 272 602 5681 6530 9572 9886 11061 11495 12238 12265 12483 12885 12955
22 2245 4282 4469 5007 6650 6733 10151 10401 11571 12004 12261 12805 12844
23 3270 4468 8621 9662 11240 11934 12091 12444 12691 12717 12858 12888 12917
740 1519 4923 6191 7878 8350 9293 10779 11020 11287 11630 12792 12862 12920
12 28 3584 6072 7079 8075 10477 11130 11383 11780 12341 12667 12818 12927
14 118 5283 5382 8301 9097 9413 9664 10437 10701 11124 12685 12730 12734
32 1426 3078 4325 5353 7780 9042 9928 10077 10377 10679 11191 11750 12611
1 669 3831 3980 5381 5412 6552 8453 9435 10243 11546 11821 11987 12807
232 483 919 1232 2156 2396 2990 3774 8539 8704 8819 10810 11868 12634
2381 7309 9334
348 6494 12623
4872 6257 11090
7 11970 11985
6615 12788 12855
1173 5269 12647
1944 7738 8116
17 4828 9175
2329 6034 12642
1254 2366 5013
2984 5078 5664
7423 10265 11528
1656 8526 8716
22 287 2837
18 100 3079
299 3171 12169
33 5920 11144
1286 3650 9309
2283 8809 12588
3199 8242 9081
2507 6846 8113
5211 8722 12689
1064 2592 8659
6136 6925 12958
1256 12789 12932
4274 8045 8788
1824 3209 6926
11 8899 12669
6249 6338 8730
641 9679 12831
3459 9876 11185
3226 6148 8173
9078 12126 12771
10907 11278 12731
3392 4020 12838
2814 11588 12909
6063 9214 11519
6064 6827 12683
1610 2452 6582
903 6289 8074
4592 8138 12952
2587 6271 9945
2733 11844 11893
581 4601 10020
14 5597 6049
343 3582 5931
5263 6521 12846
1394 2457 5251
11 4627 12747
2650 10366 12390
6285 11893 12062
10143 12892 12956
8448 11917 12330
4209 11693 12356
1529 2360 9086
5389 8148 10224
64 4876 12862
9483 12659 12887
3587 6767 12478
3122 5245 9044
3267 10118 11466
1347 3857 6705
9384 9576 11971
1366 8708 10758
412 4249 12863
1676 10488 11850
17 1605 2455
14 111 6045
11368 12919 12953
10588 11530 12937
4549 5143 12218
3088 4185 11674
23 2554 7823
6615 9291 9863
2229 3629 10855
3818 5509 12764
2740 11525 12914
8297 8611 12948
3606 11104 12920
5097 10412 12759
6502 7266 12072
5425 5490 10728
22 73 8462
32 12439 12657
8483 9540 10430
7275 7377 7420
5748 9726 12356
5672 6150 9156
28 3527 5857
520 7099 11335
405 6173 12865
5847 12843 12934
4289 7679 10386
2950 8021 12938
8844 11214 12955
2130 10760 12665
734 4790 12940
8 6991 12772
19 8205 11289
12 1440 9077
8670 8837 12951
3531 9166 12937
15 8901 8929
838 10114 11740
2648 9959 10934
323 7499 12877
5505 5659 11395
6627 12709 12933
364 1976 12888
8213 9124 12793
9588 10088 11108
299 890 11634
7368 7598 11602
28 4669 12585
15 27 12474
1426 3614 4205
30 2087 11147
6226 6259 12941
である
データ処理方法。 - 前記検査行列初期値テーブルの行をiと表すとともに、前記LDPC符号のパリティ長をMと表すとき、
前記検査行列の2+360×(i-1)列目は、前記検査行列初期値テーブルで1の要素の位置が表される前記検査行列の1+360×(i-1)列目を、q=M/360だけ下方向にサイクリックシフトした列である
請求項30に記載のデータ処理方法。 - 前記検査行列の1+360×(i-1)列については、
前記検査行列初期値テーブルのi行目が、前記検査行列の1+360×(i-1)列目の1の要素の行番号を表し、
前記検査行列の1+360×(i-1)列目以外の列である2+360×(i-1)列目から360×i列目までの各列については、
前記検査行列初期値テーブルのi行目のj列目の数値をhi,jと表すとともに、前記検査行列Hのw列目の、j個目の1の要素の行番号をHw-jと表すとき、
前記検査行列の1+360×(i-1)列目以外の列であるw列目の、1の要素の行番号Hw-jは、式Hw-j=mod{hi,j+mod((w-1),360)×M/360,M)で表される
請求項31に記載のデータ処理方法。 - 前記qは、36である
請求項31に記載のデータ処理方法。 - 前記LDPC符号の符号ビットを、カラム方向にずらして記憶することによりカラムツイストインターリーブが行われている場合に、前記LDPC符号の符号ビットを元の並びに戻すカラムツイストデインターリーブを行う
請求項30に記載のデータ処理方法。 - 前記LDPC符号の符号ビットを、所定のディジタル変調方式で定める所定数の信号点のうちのいずれかに対応するシンボルのシンボルビットに入れ替える入れ替え処理が行われている場合に、前記シンボルビットとして位置が入れ替えられた前記符号ビットを、元の位置に戻す逆入れ替え処理を行う
請求項30に記載のデータ処理方法。 - 前記逆入れ替え部処理では、ロウ方向に記憶されてカラム方向に読み出される前記符号ビットを元の位置に戻す
請求項35に記載のデータ処理方法。 - 前記検査行列は、サイクル4が存在しない検査行列である
請求項30に記載のデータ処理方法。 - 前記検査行列は、マルチエッジタイプのデンシティエボリューションによって検出される、BERが落ち始めるEb/N0である性能閾値が所定値以下になるLDPC符号のアンサンブルに属するLDPC符号の検査行列である
請求項30に記載のデータ処理方法。 - LDPC(Low Density Parity Check)符号の検査行列に基づき、情報ビットを、符号長が64800ビットで符号化率が25/30のLDPC符号に符号化する符号化部を備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部と前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
1860 2354 3967 4292 4488 5243 5373 5766 8378 9111 10468 10505 10774
24 2266 2380 3282 4255 4779 8729 9140 9566 10102 10661 10711 10797
605 650 1108 1669 2251 3133 5847 6197 6902 7545 10521 10600 10773
1016 1428 1612 2335 3102 3810 4926 5953 9964 10246 10569 10734 10784
3195 6308 8029 9030 9397 9461 9833 10239 10499 10675 10736 10757 10773
2 27 3641 4566 7332 9318 9323 9916 10365 10438 10561 10581 10750
2405 2458 4820 6232 6254 6347 7139 7474 8623 8779 8798 10747 10794
3164 4736 6474 7162 7420 7517 7835 8238 8412 8489 9006 10113 10440
20 2372 5561 5649 6907 8393 8505 9181 9567 9595 10388 10483 10714
1071 2899 5135 5780 6616 7111 7773 8582 9015 9912 10139 10387 10768
292 2833 5490 6011 6136 6713 7517 9096 10128 10328 10407 10525 10736
1044 3711 4421 5140 5207 8118 8749 8884 9205 10359 10372 10746 10784
3241 5696 6440 7240 7419 8613 8878 9593 9959 9997 10401 10404 10754
3133 4647 5912 6065 6694 7208 7346 8227 9465 9739 10452 10516 10770
2254 6444 7449 8095 8120 8710 9030 9162 9643 9968 10101 10571 10678
918 1445 2217 4262 4623 5401 5749 7446 7907 9539 10125 10514 10726
6 1341 1788 3105 4359 5263 5470 7552 8249 8644 10609 10674 10733
1994 3000 3151 3173 7742 8335 8438 8741 9232 9296 9817 10023 10257
467 1674 3016 3950 4055 5399 6688 7113 7273 8658 8702 9642 10545
2007 2541 3125 7380 7550 8122 8501 8665 9882 10403 10519 10594 10696
334 587 709 1540 2023 2876 6216 8768 9328 9481 10424 10507 10779
2165 4185 4306 5019 6961 7386 8447 9082 9837 10091 10461 10559 10570
7 903 2948 6312 6654 7738 7980 8312 9104 9743 10070 10278 10406
3047 3154 4160 4378 5461 8711 8809 9040 9173 9252 9537 9995 10735
2018 2355 3828 3854 6201 6696 8313 8459 8550 8833 9586 10202 10224
1402 1908 4286 4660 6029 6115 6737 7538 9495 9517 10055 10509 10644
3442 3589 3868 5051 5322 5580 8725 9046 9170 10041 10613 10681 10689
2733 7826 10622
3597 4753 7086
1394 7297 10264
2848 7502 10304
1649 2405 10783
647 2911 9069
2572 4006 7508
1361 8887 10103
3681 4023 9090
1496 4962 6325
2016 5120 9747
3954 5260 8568
3364 8719 10035
4208 4806 9973
29 3361 3490
1835 2317 10436
7312 8177 9041
7728 8097 10761
2109 7902 9685
5424 8943 9436
4369 7643 9152
2240 10140 10528
3435 6124 10604
8962 9357 10040
26 1931 8629
8275 10455 10643
8 24 4952
3995 6456 10633
28 10300 10337
4894 9286 9429
5587 6721 9120
1859 9198 9762
6374 6453 7011
1319 4530 5442
1507 10711 10798
2115 3445 3641
6668 9139 10163
4038 8117 10295
1479 3403 8247
2522 2934 3562
1526 5073 9650
2136 9820 10636
4214 8464 9891
8018 10330 10610
8984 10209 10647
3414 7272 8599
4883 9077 9525
22 8173 8425
2941 6536 10126
29 6540 7361
5 3787 10468
4264 4818 6906
3903 7041 10412
6078 7661 10619
6922 9723 9890
5112 5416 6253
5925 9961 10447
9 10311 10598
8790 8814 10793
4768 5466 10664
10 10675 10766
6814 8705 10737
17 769 6692
1503 10696 10742
1285 4632 8976
4279 4973 7907
4650 4775 10785
28 729 10331
1914 5240 10723
3569 4921 9561
4 9442 10796
494 2328 9507
1717 8768 10750
9540 10599 10774
11 10075 10644
10246 10607 10753
5510 7088 9053
1347 3584 5523
7872 10596 10736
628 10592 10695
5632 5688 10627
2375 10009 10561
4169 4630 8871
2896 10038 10521
89 9695 9799
20 7563 9069
4534 10321 10697
8212 9868 10716
7485 9312 10327
234 536 6293
5515 7350 9251
283 3182 7167
2444 5378 6130
6183 8315 10726
43 4871 8347
2427 10219 10728
10 21 9448
1067 8312 8420
4793 9522 10105
4688 10536 10724
3825 7496 10709
682 8544 10449
2794 7110 10741
9279 10741 10767
2897 5442 8771
33 7957 10460
5 10393 10792
6225 10224 10798
23 9014 10786
7836 8339 8642
3476 5455 9788
1939 10251 10384
4008 7890 10450
926 2090 3804
1038 2497 10701
22 6220 8405
5153 5944 10367
7260 7726 9529
3039 8397 10665
7262 9644 10083
5531 6248 10795
7926 8248 8413
4649 8971 10182
である
データ処理装置。 - LDPC(Low Density Parity Check)符号の検査行列に基づき、情報ビットを、符号長が64800ビットで符号化率が25/30のLDPC符号に符号化する符号化ステップを備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部と前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
1860 2354 3967 4292 4488 5243 5373 5766 8378 9111 10468 10505 10774
24 2266 2380 3282 4255 4779 8729 9140 9566 10102 10661 10711 10797
605 650 1108 1669 2251 3133 5847 6197 6902 7545 10521 10600 10773
1016 1428 1612 2335 3102 3810 4926 5953 9964 10246 10569 10734 10784
3195 6308 8029 9030 9397 9461 9833 10239 10499 10675 10736 10757 10773
2 27 3641 4566 7332 9318 9323 9916 10365 10438 10561 10581 10750
2405 2458 4820 6232 6254 6347 7139 7474 8623 8779 8798 10747 10794
3164 4736 6474 7162 7420 7517 7835 8238 8412 8489 9006 10113 10440
20 2372 5561 5649 6907 8393 8505 9181 9567 9595 10388 10483 10714
1071 2899 5135 5780 6616 7111 7773 8582 9015 9912 10139 10387 10768
292 2833 5490 6011 6136 6713 7517 9096 10128 10328 10407 10525 10736
1044 3711 4421 5140 5207 8118 8749 8884 9205 10359 10372 10746 10784
3241 5696 6440 7240 7419 8613 8878 9593 9959 9997 10401 10404 10754
3133 4647 5912 6065 6694 7208 7346 8227 9465 9739 10452 10516 10770
2254 6444 7449 8095 8120 8710 9030 9162 9643 9968 10101 10571 10678
918 1445 2217 4262 4623 5401 5749 7446 7907 9539 10125 10514 10726
6 1341 1788 3105 4359 5263 5470 7552 8249 8644 10609 10674 10733
1994 3000 3151 3173 7742 8335 8438 8741 9232 9296 9817 10023 10257
467 1674 3016 3950 4055 5399 6688 7113 7273 8658 8702 9642 10545
2007 2541 3125 7380 7550 8122 8501 8665 9882 10403 10519 10594 10696
334 587 709 1540 2023 2876 6216 8768 9328 9481 10424 10507 10779
2165 4185 4306 5019 6961 7386 8447 9082 9837 10091 10461 10559 10570
7 903 2948 6312 6654 7738 7980 8312 9104 9743 10070 10278 10406
3047 3154 4160 4378 5461 8711 8809 9040 9173 9252 9537 9995 10735
2018 2355 3828 3854 6201 6696 8313 8459 8550 8833 9586 10202 10224
1402 1908 4286 4660 6029 6115 6737 7538 9495 9517 10055 10509 10644
3442 3589 3868 5051 5322 5580 8725 9046 9170 10041 10613 10681 10689
2733 7826 10622
3597 4753 7086
1394 7297 10264
2848 7502 10304
1649 2405 10783
647 2911 9069
2572 4006 7508
1361 8887 10103
3681 4023 9090
1496 4962 6325
2016 5120 9747
3954 5260 8568
3364 8719 10035
4208 4806 9973
29 3361 3490
1835 2317 10436
7312 8177 9041
7728 8097 10761
2109 7902 9685
5424 8943 9436
4369 7643 9152
2240 10140 10528
3435 6124 10604
8962 9357 10040
26 1931 8629
8275 10455 10643
8 24 4952
3995 6456 10633
28 10300 10337
4894 9286 9429
5587 6721 9120
1859 9198 9762
6374 6453 7011
1319 4530 5442
1507 10711 10798
2115 3445 3641
6668 9139 10163
4038 8117 10295
1479 3403 8247
2522 2934 3562
1526 5073 9650
2136 9820 10636
4214 8464 9891
8018 10330 10610
8984 10209 10647
3414 7272 8599
4883 9077 9525
22 8173 8425
2941 6536 10126
29 6540 7361
5 3787 10468
4264 4818 6906
3903 7041 10412
6078 7661 10619
6922 9723 9890
5112 5416 6253
5925 9961 10447
9 10311 10598
8790 8814 10793
4768 5466 10664
10 10675 10766
6814 8705 10737
17 769 6692
1503 10696 10742
1285 4632 8976
4279 4973 7907
4650 4775 10785
28 729 10331
1914 5240 10723
3569 4921 9561
4 9442 10796
494 2328 9507
1717 8768 10750
9540 10599 10774
11 10075 10644
10246 10607 10753
5510 7088 9053
1347 3584 5523
7872 10596 10736
628 10592 10695
5632 5688 10627
2375 10009 10561
4169 4630 8871
2896 10038 10521
89 9695 9799
20 7563 9069
4534 10321 10697
8212 9868 10716
7485 9312 10327
234 536 6293
5515 7350 9251
283 3182 7167
2444 5378 6130
6183 8315 10726
43 4871 8347
2427 10219 10728
10 21 9448
1067 8312 8420
4793 9522 10105
4688 10536 10724
3825 7496 10709
682 8544 10449
2794 7110 10741
9279 10741 10767
2897 5442 8771
33 7957 10460
5 10393 10792
6225 10224 10798
23 9014 10786
7836 8339 8642
3476 5455 9788
1939 10251 10384
4008 7890 10450
926 2090 3804
1038 2497 10701
22 6220 8405
5153 5944 10367
7260 7726 9529
3039 8397 10665
7262 9644 10083
5531 6248 10795
7926 8248 8413
4649 8971 10182
である
データ処理方法。 - LDPC(Low Density Parity Check)符号の検査行列に基づき、符号長が64800ビットで符号化率が25/30のLDPC符号を復号する復号部を備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部と前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
1860 2354 3967 4292 4488 5243 5373 5766 8378 9111 10468 10505 10774
24 2266 2380 3282 4255 4779 8729 9140 9566 10102 10661 10711 10797
605 650 1108 1669 2251 3133 5847 6197 6902 7545 10521 10600 10773
1016 1428 1612 2335 3102 3810 4926 5953 9964 10246 10569 10734 10784
3195 6308 8029 9030 9397 9461 9833 10239 10499 10675 10736 10757 10773
2 27 3641 4566 7332 9318 9323 9916 10365 10438 10561 10581 10750
2405 2458 4820 6232 6254 6347 7139 7474 8623 8779 8798 10747 10794
3164 4736 6474 7162 7420 7517 7835 8238 8412 8489 9006 10113 10440
20 2372 5561 5649 6907 8393 8505 9181 9567 9595 10388 10483 10714
1071 2899 5135 5780 6616 7111 7773 8582 9015 9912 10139 10387 10768
292 2833 5490 6011 6136 6713 7517 9096 10128 10328 10407 10525 10736
1044 3711 4421 5140 5207 8118 8749 8884 9205 10359 10372 10746 10784
3241 5696 6440 7240 7419 8613 8878 9593 9959 9997 10401 10404 10754
3133 4647 5912 6065 6694 7208 7346 8227 9465 9739 10452 10516 10770
2254 6444 7449 8095 8120 8710 9030 9162 9643 9968 10101 10571 10678
918 1445 2217 4262 4623 5401 5749 7446 7907 9539 10125 10514 10726
6 1341 1788 3105 4359 5263 5470 7552 8249 8644 10609 10674 10733
1994 3000 3151 3173 7742 8335 8438 8741 9232 9296 9817 10023 10257
467 1674 3016 3950 4055 5399 6688 7113 7273 8658 8702 9642 10545
2007 2541 3125 7380 7550 8122 8501 8665 9882 10403 10519 10594 10696
334 587 709 1540 2023 2876 6216 8768 9328 9481 10424 10507 10779
2165 4185 4306 5019 6961 7386 8447 9082 9837 10091 10461 10559 10570
7 903 2948 6312 6654 7738 7980 8312 9104 9743 10070 10278 10406
3047 3154 4160 4378 5461 8711 8809 9040 9173 9252 9537 9995 10735
2018 2355 3828 3854 6201 6696 8313 8459 8550 8833 9586 10202 10224
1402 1908 4286 4660 6029 6115 6737 7538 9495 9517 10055 10509 10644
3442 3589 3868 5051 5322 5580 8725 9046 9170 10041 10613 10681 10689
2733 7826 10622
3597 4753 7086
1394 7297 10264
2848 7502 10304
1649 2405 10783
647 2911 9069
2572 4006 7508
1361 8887 10103
3681 4023 9090
1496 4962 6325
2016 5120 9747
3954 5260 8568
3364 8719 10035
4208 4806 9973
29 3361 3490
1835 2317 10436
7312 8177 9041
7728 8097 10761
2109 7902 9685
5424 8943 9436
4369 7643 9152
2240 10140 10528
3435 6124 10604
8962 9357 10040
26 1931 8629
8275 10455 10643
8 24 4952
3995 6456 10633
28 10300 10337
4894 9286 9429
5587 6721 9120
1859 9198 9762
6374 6453 7011
1319 4530 5442
1507 10711 10798
2115 3445 3641
6668 9139 10163
4038 8117 10295
1479 3403 8247
2522 2934 3562
1526 5073 9650
2136 9820 10636
4214 8464 9891
8018 10330 10610
8984 10209 10647
3414 7272 8599
4883 9077 9525
22 8173 8425
2941 6536 10126
29 6540 7361
5 3787 10468
4264 4818 6906
3903 7041 10412
6078 7661 10619
6922 9723 9890
5112 5416 6253
5925 9961 10447
9 10311 10598
8790 8814 10793
4768 5466 10664
10 10675 10766
6814 8705 10737
17 769 6692
1503 10696 10742
1285 4632 8976
4279 4973 7907
4650 4775 10785
28 729 10331
1914 5240 10723
3569 4921 9561
4 9442 10796
494 2328 9507
1717 8768 10750
9540 10599 10774
11 10075 10644
10246 10607 10753
5510 7088 9053
1347 3584 5523
7872 10596 10736
628 10592 10695
5632 5688 10627
2375 10009 10561
4169 4630 8871
2896 10038 10521
89 9695 9799
20 7563 9069
4534 10321 10697
8212 9868 10716
7485 9312 10327
234 536 6293
5515 7350 9251
283 3182 7167
2444 5378 6130
6183 8315 10726
43 4871 8347
2427 10219 10728
10 21 9448
1067 8312 8420
4793 9522 10105
4688 10536 10724
3825 7496 10709
682 8544 10449
2794 7110 10741
9279 10741 10767
2897 5442 8771
33 7957 10460
5 10393 10792
6225 10224 10798
23 9014 10786
7836 8339 8642
3476 5455 9788
1939 10251 10384
4008 7890 10450
926 2090 3804
1038 2497 10701
22 6220 8405
5153 5944 10367
7260 7726 9529
3039 8397 10665
7262 9644 10083
5531 6248 10795
7926 8248 8413
4649 8971 10182
である
データ処理装置。 - LDPC(Low Density Parity Check)符号の検査行列に基づき、符号長が64800ビットで符号化率が25/30のLDPC符号を復号する復号ステップを備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部と前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
1860 2354 3967 4292 4488 5243 5373 5766 8378 9111 10468 10505 10774
24 2266 2380 3282 4255 4779 8729 9140 9566 10102 10661 10711 10797
605 650 1108 1669 2251 3133 5847 6197 6902 7545 10521 10600 10773
1016 1428 1612 2335 3102 3810 4926 5953 9964 10246 10569 10734 10784
3195 6308 8029 9030 9397 9461 9833 10239 10499 10675 10736 10757 10773
2 27 3641 4566 7332 9318 9323 9916 10365 10438 10561 10581 10750
2405 2458 4820 6232 6254 6347 7139 7474 8623 8779 8798 10747 10794
3164 4736 6474 7162 7420 7517 7835 8238 8412 8489 9006 10113 10440
20 2372 5561 5649 6907 8393 8505 9181 9567 9595 10388 10483 10714
1071 2899 5135 5780 6616 7111 7773 8582 9015 9912 10139 10387 10768
292 2833 5490 6011 6136 6713 7517 9096 10128 10328 10407 10525 10736
1044 3711 4421 5140 5207 8118 8749 8884 9205 10359 10372 10746 10784
3241 5696 6440 7240 7419 8613 8878 9593 9959 9997 10401 10404 10754
3133 4647 5912 6065 6694 7208 7346 8227 9465 9739 10452 10516 10770
2254 6444 7449 8095 8120 8710 9030 9162 9643 9968 10101 10571 10678
918 1445 2217 4262 4623 5401 5749 7446 7907 9539 10125 10514 10726
6 1341 1788 3105 4359 5263 5470 7552 8249 8644 10609 10674 10733
1994 3000 3151 3173 7742 8335 8438 8741 9232 9296 9817 10023 10257
467 1674 3016 3950 4055 5399 6688 7113 7273 8658 8702 9642 10545
2007 2541 3125 7380 7550 8122 8501 8665 9882 10403 10519 10594 10696
334 587 709 1540 2023 2876 6216 8768 9328 9481 10424 10507 10779
2165 4185 4306 5019 6961 7386 8447 9082 9837 10091 10461 10559 10570
7 903 2948 6312 6654 7738 7980 8312 9104 9743 10070 10278 10406
3047 3154 4160 4378 5461 8711 8809 9040 9173 9252 9537 9995 10735
2018 2355 3828 3854 6201 6696 8313 8459 8550 8833 9586 10202 10224
1402 1908 4286 4660 6029 6115 6737 7538 9495 9517 10055 10509 10644
3442 3589 3868 5051 5322 5580 8725 9046 9170 10041 10613 10681 10689
2733 7826 10622
3597 4753 7086
1394 7297 10264
2848 7502 10304
1649 2405 10783
647 2911 9069
2572 4006 7508
1361 8887 10103
3681 4023 9090
1496 4962 6325
2016 5120 9747
3954 5260 8568
3364 8719 10035
4208 4806 9973
29 3361 3490
1835 2317 10436
7312 8177 9041
7728 8097 10761
2109 7902 9685
5424 8943 9436
4369 7643 9152
2240 10140 10528
3435 6124 10604
8962 9357 10040
26 1931 8629
8275 10455 10643
8 24 4952
3995 6456 10633
28 10300 10337
4894 9286 9429
5587 6721 9120
1859 9198 9762
6374 6453 7011
1319 4530 5442
1507 10711 10798
2115 3445 3641
6668 9139 10163
4038 8117 10295
1479 3403 8247
2522 2934 3562
1526 5073 9650
2136 9820 10636
4214 8464 9891
8018 10330 10610
8984 10209 10647
3414 7272 8599
4883 9077 9525
22 8173 8425
2941 6536 10126
29 6540 7361
5 3787 10468
4264 4818 6906
3903 7041 10412
6078 7661 10619
6922 9723 9890
5112 5416 6253
5925 9961 10447
9 10311 10598
8790 8814 10793
4768 5466 10664
10 10675 10766
6814 8705 10737
17 769 6692
1503 10696 10742
1285 4632 8976
4279 4973 7907
4650 4775 10785
28 729 10331
1914 5240 10723
3569 4921 9561
4 9442 10796
494 2328 9507
1717 8768 10750
9540 10599 10774
11 10075 10644
10246 10607 10753
5510 7088 9053
1347 3584 5523
7872 10596 10736
628 10592 10695
5632 5688 10627
2375 10009 10561
4169 4630 8871
2896 10038 10521
89 9695 9799
20 7563 9069
4534 10321 10697
8212 9868 10716
7485 9312 10327
234 536 6293
5515 7350 9251
283 3182 7167
2444 5378 6130
6183 8315 10726
43 4871 8347
2427 10219 10728
10 21 9448
1067 8312 8420
4793 9522 10105
4688 10536 10724
3825 7496 10709
682 8544 10449
2794 7110 10741
9279 10741 10767
2897 5442 8771
33 7957 10460
5 10393 10792
6225 10224 10798
23 9014 10786
7836 8339 8642
3476 5455 9788
1939 10251 10384
4008 7890 10450
926 2090 3804
1038 2497 10701
22 6220 8405
5153 5944 10367
7260 7726 9529
3039 8397 10665
7262 9644 10083
5531 6248 10795
7926 8248 8413
4649 8971 10182
である
データ処理方法。 - LDPC(Low Density Parity Check)符号の検査行列に基づき、情報ビットを、符号長が64800ビットで符号化率が26/30のLDPC符号に符号化する符号化部を備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部と前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
142 2307 2598 2650 4028 4434 5781 5881 6016 6323 6681 6698 8125
2932 4928 5248 5256 5983 6773 6828 7789 8426 8494 8534 8539 8583
899 3295 3833 5399 6820 7400 7753 7890 8109 8451 8529 8564 8602
21 3060 4720 5429 5636 5927 6966 8110 8170 8247 8355 8365 8616
20 1745 2838 3799 4380 4418 4646 5059 7343 8161 8302 8456 8631
9 6274 6725 6792 7195 7333 8027 8186 8209 8273 8442 8548 8632
494 1365 2405 3799 5188 5291 7644 7926 8139 8458 8504 8594 8625
192 574 1179 4387 4695 5089 5831 7673 7789 8298 8301 8612 8632
11 20 1406 6111 6176 6256 6708 6834 7828 8232 8457 8495 8602
6 2654 3554 4483 4966 5866 6795 8069 8249 8301 8497 8509 8623
21 1144 2355 3124 6773 6805 6887 7742 7994 8358 8374 8580 8611
335 4473 4883 5528 6096 7543 7586 7921 8197 8319 8394 8489 8636
2919 4331 4419 4735 6366 6393 6844 7193 8165 8205 8544 8586 8617
12 19 742 930 3009 4330 6213 6224 7292 7430 7792 7922 8137
710 1439 1588 2434 3516 5239 6248 6827 8230 8448 8515 8581 8619
200 1075 1868 5581 7349 7642 7698 8037 8201 8210 8320 8391 8526
3 2501 4252 5256 5292 5567 6136 6321 6430 6486 7571 8521 8636
3062 4599 5885 6529 6616 7314 7319 7567 8024 8153 8302 8372 8598
105 381 1574 4351 5452 5603 5943 7467 7788 7933 8362 8513 8587
787 1857 3386 3659 6550 7131 7965 8015 8040 8312 8484 8525 8537
15 1118 4226 5197 5575 5761 6762 7038 8260 8338 8444 8512 8568
36 5216 5368 5616 6029 6591 8038 8067 8299 8351 8565 8578 8585
1 23 4300 4530 5426 5532 5817 6967 7124 7979 8022 8270 8437
629 2133 4828 5475 5875 5890 7194 8042 8345 8385 8518 8598 8612
11 1065 3782 4237 4993 7104 7863 7904 8104 8228 8321 8383 8565
2131 2274 3168 3215 3220 5597 6347 7812 8238 8354 8527 8557 8614
5600 6591 7491 7696
1766 8281 8626
1725 2280 5120
1650 3445 7652
4312 6911 8626
15 1013 5892
2263 2546 2979
1545 5873 7406
67 726 3697
2860 6443 8542
17 911 2820
1561 4580 6052
79 5269 7134
22 2410 2424
3501 5642 8627
808 6950 8571
4099 6389 7482
4023 5000 7833
5476 5765 7917
1008 3194 7207
20 495 5411
1703 8388 8635
6 4395 4921
200 2053 8206
1089 5126 5562
10 4193 7720
1967 2151 4608
22 738 3513
3385 5066 8152
440 1118 8537
3429 6058 7716
5213 7519 8382
5564 8365 8620
43 3219 8603
4 5409 5815
5 6376 7654
4091 5724 5953
5348 6754 8613
1634 6398 6632
72 2058 8605
3497 5811 7579
3846 6743 8559
15 5933 8629
2133 5859 7068
4151 4617 8566
2960 8270 8410
2059 3617 8210
544 1441 6895
4043 7482 8592
294 2180 8524
3058 8227 8373
364 5756 8617
5383 8555 8619
1704 2480 4181
7338 7929 7990
2615 3905 7981
4298 4548 8296
8262 8319 8630
892 1893 8028
5694 7237 8595
1487 5012 5810
4335 8593 8624
3509 4531 5273
10 22 830
4161 5208 6280
275 7063 8634
4 2725 3113
2279 7403 8174
1637 3328 3930
2810 4939 5624
3 1234 7687
2799 7740 8616
22 7701 8636
4302 7857 7993
7477 7794 8592
9 6111 8591
5 8606 8628
347 3497 4033
1747 2613 8636
1827 5600 7042
580 1822 6842
232 7134 7783
4629 5000 7231
951 2806 4947
571 3474 8577
2437 2496 7945
23 5873 8162
12 1168 7686
8315 8540 8596
1766 2506 4733
929 1516 3338
21 1216 6555
782 1452 8617
8 6083 6087
667 3240 4583
4030 4661 5790
559 7122 8553
3202 4388 4909
2533 3673 8594
1991 3954 6206
6835 7900 7980
189 5722 8573
2680 4928 4998
243 2579 7735
4281 8132 8566
7656 7671 8609
1116 2291 4166
21 388 8021
6 1123 8369
311 4918 8511
0 3248 6290
13 6762 7172
4209 5632 7563
49 127 8074
581 1735 4075
0 2235 5470
2178 5820 6179
16 3575 6054
1095 4564 6458
9 1581 5953
2537 6469 8552
14 3874 4844
0 3269 3551
2114 7372 7926
1875 2388 4057
3232 4042 6663
9 401 583
13 4100 6584
2299 4190 4410
21 3670 4979
である
データ処理装置。 - LDPC(Low Density Parity Check)符号の検査行列に基づき、情報ビットを、符号長が64800ビットで符号化率が26/30のLDPC符号に符号化する符号化ステップを備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部と前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
142 2307 2598 2650 4028 4434 5781 5881 6016 6323 6681 6698 8125
2932 4928 5248 5256 5983 6773 6828 7789 8426 8494 8534 8539 8583
899 3295 3833 5399 6820 7400 7753 7890 8109 8451 8529 8564 8602
21 3060 4720 5429 5636 5927 6966 8110 8170 8247 8355 8365 8616
20 1745 2838 3799 4380 4418 4646 5059 7343 8161 8302 8456 8631
9 6274 6725 6792 7195 7333 8027 8186 8209 8273 8442 8548 8632
494 1365 2405 3799 5188 5291 7644 7926 8139 8458 8504 8594 8625
192 574 1179 4387 4695 5089 5831 7673 7789 8298 8301 8612 8632
11 20 1406 6111 6176 6256 6708 6834 7828 8232 8457 8495 8602
6 2654 3554 4483 4966 5866 6795 8069 8249 8301 8497 8509 8623
21 1144 2355 3124 6773 6805 6887 7742 7994 8358 8374 8580 8611
335 4473 4883 5528 6096 7543 7586 7921 8197 8319 8394 8489 8636
2919 4331 4419 4735 6366 6393 6844 7193 8165 8205 8544 8586 8617
12 19 742 930 3009 4330 6213 6224 7292 7430 7792 7922 8137
710 1439 1588 2434 3516 5239 6248 6827 8230 8448 8515 8581 8619
200 1075 1868 5581 7349 7642 7698 8037 8201 8210 8320 8391 8526
3 2501 4252 5256 5292 5567 6136 6321 6430 6486 7571 8521 8636
3062 4599 5885 6529 6616 7314 7319 7567 8024 8153 8302 8372 8598
105 381 1574 4351 5452 5603 5943 7467 7788 7933 8362 8513 8587
787 1857 3386 3659 6550 7131 7965 8015 8040 8312 8484 8525 8537
15 1118 4226 5197 5575 5761 6762 7038 8260 8338 8444 8512 8568
36 5216 5368 5616 6029 6591 8038 8067 8299 8351 8565 8578 8585
1 23 4300 4530 5426 5532 5817 6967 7124 7979 8022 8270 8437
629 2133 4828 5475 5875 5890 7194 8042 8345 8385 8518 8598 8612
11 1065 3782 4237 4993 7104 7863 7904 8104 8228 8321 8383 8565
2131 2274 3168 3215 3220 5597 6347 7812 8238 8354 8527 8557 8614
5600 6591 7491 7696
1766 8281 8626
1725 2280 5120
1650 3445 7652
4312 6911 8626
15 1013 5892
2263 2546 2979
1545 5873 7406
67 726 3697
2860 6443 8542
17 911 2820
1561 4580 6052
79 5269 7134
22 2410 2424
3501 5642 8627
808 6950 8571
4099 6389 7482
4023 5000 7833
5476 5765 7917
1008 3194 7207
20 495 5411
1703 8388 8635
6 4395 4921
200 2053 8206
1089 5126 5562
10 4193 7720
1967 2151 4608
22 738 3513
3385 5066 8152
440 1118 8537
3429 6058 7716
5213 7519 8382
5564 8365 8620
43 3219 8603
4 5409 5815
5 6376 7654
4091 5724 5953
5348 6754 8613
1634 6398 6632
72 2058 8605
3497 5811 7579
3846 6743 8559
15 5933 8629
2133 5859 7068
4151 4617 8566
2960 8270 8410
2059 3617 8210
544 1441 6895
4043 7482 8592
294 2180 8524
3058 8227 8373
364 5756 8617
5383 8555 8619
1704 2480 4181
7338 7929 7990
2615 3905 7981
4298 4548 8296
8262 8319 8630
892 1893 8028
5694 7237 8595
1487 5012 5810
4335 8593 8624
3509 4531 5273
10 22 830
4161 5208 6280
275 7063 8634
4 2725 3113
2279 7403 8174
1637 3328 3930
2810 4939 5624
3 1234 7687
2799 7740 8616
22 7701 8636
4302 7857 7993
7477 7794 8592
9 6111 8591
5 8606 8628
347 3497 4033
1747 2613 8636
1827 5600 7042
580 1822 6842
232 7134 7783
4629 5000 7231
951 2806 4947
571 3474 8577
2437 2496 7945
23 5873 8162
12 1168 7686
8315 8540 8596
1766 2506 4733
929 1516 3338
21 1216 6555
782 1452 8617
8 6083 6087
667 3240 4583
4030 4661 5790
559 7122 8553
3202 4388 4909
2533 3673 8594
1991 3954 6206
6835 7900 7980
189 5722 8573
2680 4928 4998
243 2579 7735
4281 8132 8566
7656 7671 8609
1116 2291 4166
21 388 8021
6 1123 8369
311 4918 8511
0 3248 6290
13 6762 7172
4209 5632 7563
49 127 8074
581 1735 4075
0 2235 5470
2178 5820 6179
16 3575 6054
1095 4564 6458
9 1581 5953
2537 6469 8552
14 3874 4844
0 3269 3551
2114 7372 7926
1875 2388 4057
3232 4042 6663
9 401 583
13 4100 6584
2299 4190 4410
21 3670 4979
である
データ処理方法。 - LDPC(Low Density Parity Check)符号の検査行列に基づき、符号長が64800ビットで符号化率が26/30のLDPC符号を復号する復号部を備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部と前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
142 2307 2598 2650 4028 4434 5781 5881 6016 6323 6681 6698 8125
2932 4928 5248 5256 5983 6773 6828 7789 8426 8494 8534 8539 8583
899 3295 3833 5399 6820 7400 7753 7890 8109 8451 8529 8564 8602
21 3060 4720 5429 5636 5927 6966 8110 8170 8247 8355 8365 8616
20 1745 2838 3799 4380 4418 4646 5059 7343 8161 8302 8456 8631
9 6274 6725 6792 7195 7333 8027 8186 8209 8273 8442 8548 8632
494 1365 2405 3799 5188 5291 7644 7926 8139 8458 8504 8594 8625
192 574 1179 4387 4695 5089 5831 7673 7789 8298 8301 8612 8632
11 20 1406 6111 6176 6256 6708 6834 7828 8232 8457 8495 8602
6 2654 3554 4483 4966 5866 6795 8069 8249 8301 8497 8509 8623
21 1144 2355 3124 6773 6805 6887 7742 7994 8358 8374 8580 8611
335 4473 4883 5528 6096 7543 7586 7921 8197 8319 8394 8489 8636
2919 4331 4419 4735 6366 6393 6844 7193 8165 8205 8544 8586 8617
12 19 742 930 3009 4330 6213 6224 7292 7430 7792 7922 8137
710 1439 1588 2434 3516 5239 6248 6827 8230 8448 8515 8581 8619
200 1075 1868 5581 7349 7642 7698 8037 8201 8210 8320 8391 8526
3 2501 4252 5256 5292 5567 6136 6321 6430 6486 7571 8521 8636
3062 4599 5885 6529 6616 7314 7319 7567 8024 8153 8302 8372 8598
105 381 1574 4351 5452 5603 5943 7467 7788 7933 8362 8513 8587
787 1857 3386 3659 6550 7131 7965 8015 8040 8312 8484 8525 8537
15 1118 4226 5197 5575 5761 6762 7038 8260 8338 8444 8512 8568
36 5216 5368 5616 6029 6591 8038 8067 8299 8351 8565 8578 8585
1 23 4300 4530 5426 5532 5817 6967 7124 7979 8022 8270 8437
629 2133 4828 5475 5875 5890 7194 8042 8345 8385 8518 8598 8612
11 1065 3782 4237 4993 7104 7863 7904 8104 8228 8321 8383 8565
2131 2274 3168 3215 3220 5597 6347 7812 8238 8354 8527 8557 8614
5600 6591 7491 7696
1766 8281 8626
1725 2280 5120
1650 3445 7652
4312 6911 8626
15 1013 5892
2263 2546 2979
1545 5873 7406
67 726 3697
2860 6443 8542
17 911 2820
1561 4580 6052
79 5269 7134
22 2410 2424
3501 5642 8627
808 6950 8571
4099 6389 7482
4023 5000 7833
5476 5765 7917
1008 3194 7207
20 495 5411
1703 8388 8635
6 4395 4921
200 2053 8206
1089 5126 5562
10 4193 7720
1967 2151 4608
22 738 3513
3385 5066 8152
440 1118 8537
3429 6058 7716
5213 7519 8382
5564 8365 8620
43 3219 8603
4 5409 5815
5 6376 7654
4091 5724 5953
5348 6754 8613
1634 6398 6632
72 2058 8605
3497 5811 7579
3846 6743 8559
15 5933 8629
2133 5859 7068
4151 4617 8566
2960 8270 8410
2059 3617 8210
544 1441 6895
4043 7482 8592
294 2180 8524
3058 8227 8373
364 5756 8617
5383 8555 8619
1704 2480 4181
7338 7929 7990
2615 3905 7981
4298 4548 8296
8262 8319 8630
892 1893 8028
5694 7237 8595
1487 5012 5810
4335 8593 8624
3509 4531 5273
10 22 830
4161 5208 6280
275 7063 8634
4 2725 3113
2279 7403 8174
1637 3328 3930
2810 4939 5624
3 1234 7687
2799 7740 8616
22 7701 8636
4302 7857 7993
7477 7794 8592
9 6111 8591
5 8606 8628
347 3497 4033
1747 2613 8636
1827 5600 7042
580 1822 6842
232 7134 7783
4629 5000 7231
951 2806 4947
571 3474 8577
2437 2496 7945
23 5873 8162
12 1168 7686
8315 8540 8596
1766 2506 4733
929 1516 3338
21 1216 6555
782 1452 8617
8 6083 6087
667 3240 4583
4030 4661 5790
559 7122 8553
3202 4388 4909
2533 3673 8594
1991 3954 6206
6835 7900 7980
189 5722 8573
2680 4928 4998
243 2579 7735
4281 8132 8566
7656 7671 8609
1116 2291 4166
21 388 8021
6 1123 8369
311 4918 8511
0 3248 6290
13 6762 7172
4209 5632 7563
49 127 8074
581 1735 4075
0 2235 5470
2178 5820 6179
16 3575 6054
1095 4564 6458
9 1581 5953
2537 6469 8552
14 3874 4844
0 3269 3551
2114 7372 7926
1875 2388 4057
3232 4042 6663
9 401 583
13 4100 6584
2299 4190 4410
21 3670 4979
である
データ処理装置。 - LDPC(Low Density Parity Check)符号の検査行列に基づき、符号長が64800ビットで符号化率が26/30のLDPC符号を復号する復号ステップを備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部と前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
142 2307 2598 2650 4028 4434 5781 5881 6016 6323 6681 6698 8125
2932 4928 5248 5256 5983 6773 6828 7789 8426 8494 8534 8539 8583
899 3295 3833 5399 6820 7400 7753 7890 8109 8451 8529 8564 8602
21 3060 4720 5429 5636 5927 6966 8110 8170 8247 8355 8365 8616
20 1745 2838 3799 4380 4418 4646 5059 7343 8161 8302 8456 8631
9 6274 6725 6792 7195 7333 8027 8186 8209 8273 8442 8548 8632
494 1365 2405 3799 5188 5291 7644 7926 8139 8458 8504 8594 8625
192 574 1179 4387 4695 5089 5831 7673 7789 8298 8301 8612 8632
11 20 1406 6111 6176 6256 6708 6834 7828 8232 8457 8495 8602
6 2654 3554 4483 4966 5866 6795 8069 8249 8301 8497 8509 8623
21 1144 2355 3124 6773 6805 6887 7742 7994 8358 8374 8580 8611
335 4473 4883 5528 6096 7543 7586 7921 8197 8319 8394 8489 8636
2919 4331 4419 4735 6366 6393 6844 7193 8165 8205 8544 8586 8617
12 19 742 930 3009 4330 6213 6224 7292 7430 7792 7922 8137
710 1439 1588 2434 3516 5239 6248 6827 8230 8448 8515 8581 8619
200 1075 1868 5581 7349 7642 7698 8037 8201 8210 8320 8391 8526
3 2501 4252 5256 5292 5567 6136 6321 6430 6486 7571 8521 8636
3062 4599 5885 6529 6616 7314 7319 7567 8024 8153 8302 8372 8598
105 381 1574 4351 5452 5603 5943 7467 7788 7933 8362 8513 8587
787 1857 3386 3659 6550 7131 7965 8015 8040 8312 8484 8525 8537
15 1118 4226 5197 5575 5761 6762 7038 8260 8338 8444 8512 8568
36 5216 5368 5616 6029 6591 8038 8067 8299 8351 8565 8578 8585
1 23 4300 4530 5426 5532 5817 6967 7124 7979 8022 8270 8437
629 2133 4828 5475 5875 5890 7194 8042 8345 8385 8518 8598 8612
11 1065 3782 4237 4993 7104 7863 7904 8104 8228 8321 8383 8565
2131 2274 3168 3215 3220 5597 6347 7812 8238 8354 8527 8557 8614
5600 6591 7491 7696
1766 8281 8626
1725 2280 5120
1650 3445 7652
4312 6911 8626
15 1013 5892
2263 2546 2979
1545 5873 7406
67 726 3697
2860 6443 8542
17 911 2820
1561 4580 6052
79 5269 7134
22 2410 2424
3501 5642 8627
808 6950 8571
4099 6389 7482
4023 5000 7833
5476 5765 7917
1008 3194 7207
20 495 5411
1703 8388 8635
6 4395 4921
200 2053 8206
1089 5126 5562
10 4193 7720
1967 2151 4608
22 738 3513
3385 5066 8152
440 1118 8537
3429 6058 7716
5213 7519 8382
5564 8365 8620
43 3219 8603
4 5409 5815
5 6376 7654
4091 5724 5953
5348 6754 8613
1634 6398 6632
72 2058 8605
3497 5811 7579
3846 6743 8559
15 5933 8629
2133 5859 7068
4151 4617 8566
2960 8270 8410
2059 3617 8210
544 1441 6895
4043 7482 8592
294 2180 8524
3058 8227 8373
364 5756 8617
5383 8555 8619
1704 2480 4181
7338 7929 7990
2615 3905 7981
4298 4548 8296
8262 8319 8630
892 1893 8028
5694 7237 8595
1487 5012 5810
4335 8593 8624
3509 4531 5273
10 22 830
4161 5208 6280
275 7063 8634
4 2725 3113
2279 7403 8174
1637 3328 3930
2810 4939 5624
3 1234 7687
2799 7740 8616
22 7701 8636
4302 7857 7993
7477 7794 8592
9 6111 8591
5 8606 8628
347 3497 4033
1747 2613 8636
1827 5600 7042
580 1822 6842
232 7134 7783
4629 5000 7231
951 2806 4947
571 3474 8577
2437 2496 7945
23 5873 8162
12 1168 7686
8315 8540 8596
1766 2506 4733
929 1516 3338
21 1216 6555
782 1452 8617
8 6083 6087
667 3240 4583
4030 4661 5790
559 7122 8553
3202 4388 4909
2533 3673 8594
1991 3954 6206
6835 7900 7980
189 5722 8573
2680 4928 4998
243 2579 7735
4281 8132 8566
7656 7671 8609
1116 2291 4166
21 388 8021
6 1123 8369
311 4918 8511
0 3248 6290
13 6762 7172
4209 5632 7563
49 127 8074
581 1735 4075
0 2235 5470
2178 5820 6179
16 3575 6054
1095 4564 6458
9 1581 5953
2537 6469 8552
14 3874 4844
0 3269 3551
2114 7372 7926
1875 2388 4057
3232 4042 6663
9 401 583
13 4100 6584
2299 4190 4410
21 3670 4979
である
データ処理方法。 - LDPC(Low Density Parity Check)符号の検査行列に基づき、情報ビットを、符号長が64800ビットで符号化率が27/30のLDPC符号に符号化する符号化部を備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部と前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
658 706 898 1149 2577 2622 2772 3266 3329 5243 6079 6271
289 784 1682 3584 3995 4821 4856 5063 5974 6168 6437 6453
658 1426 2043 2065 2986 4118 4284 5394 5444 5477 5727 6018
641 928 1225 2841 4052 4840 4992 5268 5533 6249 6461 6475
2312 2917 3713 3849 4059 4241 4610 5440 5727 6101 6397 6444
1165 1592 1891 2154 3981 4817 5181 5748 5788 6012 6266 6350
13 2758 3069 4233 4697 5100 5279 5677 5919 5969 6280 6422
818 1500 2125 2340 3774 4707 4901 5170 5744 6008 6316 6353
857 3054 3409 3496 3704 4868 5326 6211 6292 6356 6367 6381
0 7 12 1709 2166 3418 3723 4887 5770 6043 6069 6431
2481 3379 4650 4900 4919 5060 5410 5425 6056 6173 6283 6386
15 814 854 1871 2934 3387 3915 5180 5303 5442 5581 5665
146 1882 3076 4458 4848 5252 5602 5778 5821 6213 6251 6401
2 947 1419 1566 3437 3646 4615 4634 4735 5819 5943 6280
1231 2309 2920 4158 4185 4298 4711 5082 5757 5762 6204 6209
257 297 337 2783 3230 4134 4480 4749 5295 5689 5921 6202
1436 2151 2629 3217 3930 4078 5386 5799 5906 6146 6226 6366
133 530 2448 4745 5000 5020 5224 5273 6211 6266 6431 6453
13 2644 3895 3898 4485 4722 5142 5462 5951 6031 6084 6351
6 3000 3873 3995 4680 5158 5504 5692 5755 6255 6338 6359
166 465 1658 2549 2941 4244 5071 5149 5452 5874 5939 6038
2309 2937 4282 4628 5113 5454 5731 5825 6021 6171 6402 6472
3 1077 2116 2426 2830 4853 5066 5571 5850 5916 6389 6421
817 1608 2229 2925 3281 4393 5042 5058 5377 5464 5588 6448
1848 3871 4381 4776 5366 5578 5648 6143 6389 6434 6465 6473
1263 1616 3150 3497 3759 4078 5530 5665 5694 5913 6397 6420
11 813 2185 2795 3349 4652 4678 5078 5504 6011 6286 6387
3060 3161 4584 4996 5143 5542 5697 5937 6141 6155 6342 6445
1638 2333 2632 3450 3505 3911 4399 4454 5499 5860 6044 6360
650 1744 4517
5772 6071 6471
3582 3622 5776
6153 6380 6446
3977 5932 6447
2071 4597 4891
11 1428 3776
1111 3874 5048
1410 2144 4445
4681 5481 6462
4044 5037 5497
2716 2891 6411
3299 4384 6224
1843 6087 6400
4664 5009 5856
1548 4383 5055
3172 4190 6373
5899 6443 6470
2572 3647 6240
1295 2158 6466
5604 6269 6368
3 5551 6454
3325 5797 6261
666 1397 5538
3069 4274 6410
4042 5992 6437
743 3075 3447
1344 2725 6386
283 2808 6303
2 4627 4632
26 1565 4000
4012 4946 6472
1629 6158 6467
6300 6351 6376
2969 4344 4440
2317 3115 4832
2099 5263 6285
2409 5868 5997
3752 4200 6350
3125 5841 6142
1 2249 6328
16 2525 6379
3198 5269 5960
4 1705 2069
990 4948 5520
1664 3836 4521
1765 4110 6454
9 1373 6387
1969 2405 6368
623 1428 3946
3111 6380 6436
1861 5611 5934
9 2444 3081
5 5508 6317
3184 4988 5995
1060 4803 6400
5021 5826 6289
1608 4754 5648
4702 6391 6421
3899 4811 6128
927 2286 5313
4123 6181 6453
2893 4150 5261
605 4332 5094
17 3518 6358
2858 6126 6478
15 1316 6465
2 2032 2983
5249 6340 6427
5 6003 6200
4478 6315 6420
5158 6390 6447
2598 3229 5399
3747 6424 6446
1412 2453 6332
5256 5715 6455
2137 3421 4368
15 3880 5245
17 3156 5638
3227 3798 6230
2094 3129 6458
1412 5573 5932
175 1182 6304
3555 6407 6463
583 1654 6339
14 6261 6449
3553 5383 5679
2092 2744 4153
0 4466 6472
11 3840 4354
17 5457 6222
1467 6083 6220
3449 3858 6337
3782 5318 6426
417 5038 5790
3571 5638 5873
6117 6241 6476
1898 5680 6219
3235 3817 6429
2095 4194 6224
2 4092 6448
5 6330 6383
285 5075 6334
10 505 2867
1183 5956 6466
839 4716 6471
984 3254 6432
1501 4790 6465
8 1457 1707
1660 1969 6438
4349 6182 6305
1423 3848 5490
1651 2969 6345
344 4164 6298
2397 6027 6274
2233 2778 6161
13 1778 2977
9 1916 3377
0 3 6190
395 4893 6394
3512 4098 6400
3490 6281 6473
12 1359 6465
4202 5179 6412
3007 3542 4271
2400 3350 6351
7 5490 5716
4695 5231 6266
777 6292 6402
919 4851 6367
6 644 3893
5386 6190 6434
17 169 4896
である
データ処理装置。 - LDPC(Low Density Parity Check)符号の検査行列に基づき、情報ビットを、符号長が64800ビットで符号化率が27/30のLDPC符号に符号化する符号化ステップを備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部と前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
658 706 898 1149 2577 2622 2772 3266 3329 5243 6079 6271
289 784 1682 3584 3995 4821 4856 5063 5974 6168 6437 6453
658 1426 2043 2065 2986 4118 4284 5394 5444 5477 5727 6018
641 928 1225 2841 4052 4840 4992 5268 5533 6249 6461 6475
2312 2917 3713 3849 4059 4241 4610 5440 5727 6101 6397 6444
1165 1592 1891 2154 3981 4817 5181 5748 5788 6012 6266 6350
13 2758 3069 4233 4697 5100 5279 5677 5919 5969 6280 6422
818 1500 2125 2340 3774 4707 4901 5170 5744 6008 6316 6353
857 3054 3409 3496 3704 4868 5326 6211 6292 6356 6367 6381
0 7 12 1709 2166 3418 3723 4887 5770 6043 6069 6431
2481 3379 4650 4900 4919 5060 5410 5425 6056 6173 6283 6386
15 814 854 1871 2934 3387 3915 5180 5303 5442 5581 5665
146 1882 3076 4458 4848 5252 5602 5778 5821 6213 6251 6401
2 947 1419 1566 3437 3646 4615 4634 4735 5819 5943 6280
1231 2309 2920 4158 4185 4298 4711 5082 5757 5762 6204 6209
257 297 337 2783 3230 4134 4480 4749 5295 5689 5921 6202
1436 2151 2629 3217 3930 4078 5386 5799 5906 6146 6226 6366
133 530 2448 4745 5000 5020 5224 5273 6211 6266 6431 6453
13 2644 3895 3898 4485 4722 5142 5462 5951 6031 6084 6351
6 3000 3873 3995 4680 5158 5504 5692 5755 6255 6338 6359
166 465 1658 2549 2941 4244 5071 5149 5452 5874 5939 6038
2309 2937 4282 4628 5113 5454 5731 5825 6021 6171 6402 6472
3 1077 2116 2426 2830 4853 5066 5571 5850 5916 6389 6421
817 1608 2229 2925 3281 4393 5042 5058 5377 5464 5588 6448
1848 3871 4381 4776 5366 5578 5648 6143 6389 6434 6465 6473
1263 1616 3150 3497 3759 4078 5530 5665 5694 5913 6397 6420
11 813 2185 2795 3349 4652 4678 5078 5504 6011 6286 6387
3060 3161 4584 4996 5143 5542 5697 5937 6141 6155 6342 6445
1638 2333 2632 3450 3505 3911 4399 4454 5499 5860 6044 6360
650 1744 4517
5772 6071 6471
3582 3622 5776
6153 6380 6446
3977 5932 6447
2071 4597 4891
11 1428 3776
1111 3874 5048
1410 2144 4445
4681 5481 6462
4044 5037 5497
2716 2891 6411
3299 4384 6224
1843 6087 6400
4664 5009 5856
1548 4383 5055
3172 4190 6373
5899 6443 6470
2572 3647 6240
1295 2158 6466
5604 6269 6368
3 5551 6454
3325 5797 6261
666 1397 5538
3069 4274 6410
4042 5992 6437
743 3075 3447
1344 2725 6386
283 2808 6303
2 4627 4632
26 1565 4000
4012 4946 6472
1629 6158 6467
6300 6351 6376
2969 4344 4440
2317 3115 4832
2099 5263 6285
2409 5868 5997
3752 4200 6350
3125 5841 6142
1 2249 6328
16 2525 6379
3198 5269 5960
4 1705 2069
990 4948 5520
1664 3836 4521
1765 4110 6454
9 1373 6387
1969 2405 6368
623 1428 3946
3111 6380 6436
1861 5611 5934
9 2444 3081
5 5508 6317
3184 4988 5995
1060 4803 6400
5021 5826 6289
1608 4754 5648
4702 6391 6421
3899 4811 6128
927 2286 5313
4123 6181 6453
2893 4150 5261
605 4332 5094
17 3518 6358
2858 6126 6478
15 1316 6465
2 2032 2983
5249 6340 6427
5 6003 6200
4478 6315 6420
5158 6390 6447
2598 3229 5399
3747 6424 6446
1412 2453 6332
5256 5715 6455
2137 3421 4368
15 3880 5245
17 3156 5638
3227 3798 6230
2094 3129 6458
1412 5573 5932
175 1182 6304
3555 6407 6463
583 1654 6339
14 6261 6449
3553 5383 5679
2092 2744 4153
0 4466 6472
11 3840 4354
17 5457 6222
1467 6083 6220
3449 3858 6337
3782 5318 6426
417 5038 5790
3571 5638 5873
6117 6241 6476
1898 5680 6219
3235 3817 6429
2095 4194 6224
2 4092 6448
5 6330 6383
285 5075 6334
10 505 2867
1183 5956 6466
839 4716 6471
984 3254 6432
1501 4790 6465
8 1457 1707
1660 1969 6438
4349 6182 6305
1423 3848 5490
1651 2969 6345
344 4164 6298
2397 6027 6274
2233 2778 6161
13 1778 2977
9 1916 3377
0 3 6190
395 4893 6394
3512 4098 6400
3490 6281 6473
12 1359 6465
4202 5179 6412
3007 3542 4271
2400 3350 6351
7 5490 5716
4695 5231 6266
777 6292 6402
919 4851 6367
6 644 3893
5386 6190 6434
17 169 4896
である
データ処理方法。 - LDPC(Low Density Parity Check)符号の検査行列に基づき、符号長が64800ビットで符号化率が27/30のLDPC符号を復号する復号部を備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部と前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
658 706 898 1149 2577 2622 2772 3266 3329 5243 6079 6271
289 784 1682 3584 3995 4821 4856 5063 5974 6168 6437 6453
658 1426 2043 2065 2986 4118 4284 5394 5444 5477 5727 6018
641 928 1225 2841 4052 4840 4992 5268 5533 6249 6461 6475
2312 2917 3713 3849 4059 4241 4610 5440 5727 6101 6397 6444
1165 1592 1891 2154 3981 4817 5181 5748 5788 6012 6266 6350
13 2758 3069 4233 4697 5100 5279 5677 5919 5969 6280 6422
818 1500 2125 2340 3774 4707 4901 5170 5744 6008 6316 6353
857 3054 3409 3496 3704 4868 5326 6211 6292 6356 6367 6381
0 7 12 1709 2166 3418 3723 4887 5770 6043 6069 6431
2481 3379 4650 4900 4919 5060 5410 5425 6056 6173 6283 6386
15 814 854 1871 2934 3387 3915 5180 5303 5442 5581 5665
146 1882 3076 4458 4848 5252 5602 5778 5821 6213 6251 6401
2 947 1419 1566 3437 3646 4615 4634 4735 5819 5943 6280
1231 2309 2920 4158 4185 4298 4711 5082 5757 5762 6204 6209
257 297 337 2783 3230 4134 4480 4749 5295 5689 5921 6202
1436 2151 2629 3217 3930 4078 5386 5799 5906 6146 6226 6366
133 530 2448 4745 5000 5020 5224 5273 6211 6266 6431 6453
13 2644 3895 3898 4485 4722 5142 5462 5951 6031 6084 6351
6 3000 3873 3995 4680 5158 5504 5692 5755 6255 6338 6359
166 465 1658 2549 2941 4244 5071 5149 5452 5874 5939 6038
2309 2937 4282 4628 5113 5454 5731 5825 6021 6171 6402 6472
3 1077 2116 2426 2830 4853 5066 5571 5850 5916 6389 6421
817 1608 2229 2925 3281 4393 5042 5058 5377 5464 5588 6448
1848 3871 4381 4776 5366 5578 5648 6143 6389 6434 6465 6473
1263 1616 3150 3497 3759 4078 5530 5665 5694 5913 6397 6420
11 813 2185 2795 3349 4652 4678 5078 5504 6011 6286 6387
3060 3161 4584 4996 5143 5542 5697 5937 6141 6155 6342 6445
1638 2333 2632 3450 3505 3911 4399 4454 5499 5860 6044 6360
650 1744 4517
5772 6071 6471
3582 3622 5776
6153 6380 6446
3977 5932 6447
2071 4597 4891
11 1428 3776
1111 3874 5048
1410 2144 4445
4681 5481 6462
4044 5037 5497
2716 2891 6411
3299 4384 6224
1843 6087 6400
4664 5009 5856
1548 4383 5055
3172 4190 6373
5899 6443 6470
2572 3647 6240
1295 2158 6466
5604 6269 6368
3 5551 6454
3325 5797 6261
666 1397 5538
3069 4274 6410
4042 5992 6437
743 3075 3447
1344 2725 6386
283 2808 6303
2 4627 4632
26 1565 4000
4012 4946 6472
1629 6158 6467
6300 6351 6376
2969 4344 4440
2317 3115 4832
2099 5263 6285
2409 5868 5997
3752 4200 6350
3125 5841 6142
1 2249 6328
16 2525 6379
3198 5269 5960
4 1705 2069
990 4948 5520
1664 3836 4521
1765 4110 6454
9 1373 6387
1969 2405 6368
623 1428 3946
3111 6380 6436
1861 5611 5934
9 2444 3081
5 5508 6317
3184 4988 5995
1060 4803 6400
5021 5826 6289
1608 4754 5648
4702 6391 6421
3899 4811 6128
927 2286 5313
4123 6181 6453
2893 4150 5261
605 4332 5094
17 3518 6358
2858 6126 6478
15 1316 6465
2 2032 2983
5249 6340 6427
5 6003 6200
4478 6315 6420
5158 6390 6447
2598 3229 5399
3747 6424 6446
1412 2453 6332
5256 5715 6455
2137 3421 4368
15 3880 5245
17 3156 5638
3227 3798 6230
2094 3129 6458
1412 5573 5932
175 1182 6304
3555 6407 6463
583 1654 6339
14 6261 6449
3553 5383 5679
2092 2744 4153
0 4466 6472
11 3840 4354
17 5457 6222
1467 6083 6220
3449 3858 6337
3782 5318 6426
417 5038 5790
3571 5638 5873
6117 6241 6476
1898 5680 6219
3235 3817 6429
2095 4194 6224
2 4092 6448
5 6330 6383
285 5075 6334
10 505 2867
1183 5956 6466
839 4716 6471
984 3254 6432
1501 4790 6465
8 1457 1707
1660 1969 6438
4349 6182 6305
1423 3848 5490
1651 2969 6345
344 4164 6298
2397 6027 6274
2233 2778 6161
13 1778 2977
9 1916 3377
0 3 6190
395 4893 6394
3512 4098 6400
3490 6281 6473
12 1359 6465
4202 5179 6412
3007 3542 4271
2400 3350 6351
7 5490 5716
4695 5231 6266
777 6292 6402
919 4851 6367
6 644 3893
5386 6190 6434
17 169 4896
である
データ処理装置。 - LDPC(Low Density Parity Check)符号の検査行列に基づき、符号長が64800ビットで符号化率が27/30のLDPC符号を復号する復号ステップを備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部と前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
658 706 898 1149 2577 2622 2772 3266 3329 5243 6079 6271
289 784 1682 3584 3995 4821 4856 5063 5974 6168 6437 6453
658 1426 2043 2065 2986 4118 4284 5394 5444 5477 5727 6018
641 928 1225 2841 4052 4840 4992 5268 5533 6249 6461 6475
2312 2917 3713 3849 4059 4241 4610 5440 5727 6101 6397 6444
1165 1592 1891 2154 3981 4817 5181 5748 5788 6012 6266 6350
13 2758 3069 4233 4697 5100 5279 5677 5919 5969 6280 6422
818 1500 2125 2340 3774 4707 4901 5170 5744 6008 6316 6353
857 3054 3409 3496 3704 4868 5326 6211 6292 6356 6367 6381
0 7 12 1709 2166 3418 3723 4887 5770 6043 6069 6431
2481 3379 4650 4900 4919 5060 5410 5425 6056 6173 6283 6386
15 814 854 1871 2934 3387 3915 5180 5303 5442 5581 5665
146 1882 3076 4458 4848 5252 5602 5778 5821 6213 6251 6401
2 947 1419 1566 3437 3646 4615 4634 4735 5819 5943 6280
1231 2309 2920 4158 4185 4298 4711 5082 5757 5762 6204 6209
257 297 337 2783 3230 4134 4480 4749 5295 5689 5921 6202
1436 2151 2629 3217 3930 4078 5386 5799 5906 6146 6226 6366
133 530 2448 4745 5000 5020 5224 5273 6211 6266 6431 6453
13 2644 3895 3898 4485 4722 5142 5462 5951 6031 6084 6351
6 3000 3873 3995 4680 5158 5504 5692 5755 6255 6338 6359
166 465 1658 2549 2941 4244 5071 5149 5452 5874 5939 6038
2309 2937 4282 4628 5113 5454 5731 5825 6021 6171 6402 6472
3 1077 2116 2426 2830 4853 5066 5571 5850 5916 6389 6421
817 1608 2229 2925 3281 4393 5042 5058 5377 5464 5588 6448
1848 3871 4381 4776 5366 5578 5648 6143 6389 6434 6465 6473
1263 1616 3150 3497 3759 4078 5530 5665 5694 5913 6397 6420
11 813 2185 2795 3349 4652 4678 5078 5504 6011 6286 6387
3060 3161 4584 4996 5143 5542 5697 5937 6141 6155 6342 6445
1638 2333 2632 3450 3505 3911 4399 4454 5499 5860 6044 6360
650 1744 4517
5772 6071 6471
3582 3622 5776
6153 6380 6446
3977 5932 6447
2071 4597 4891
11 1428 3776
1111 3874 5048
1410 2144 4445
4681 5481 6462
4044 5037 5497
2716 2891 6411
3299 4384 6224
1843 6087 6400
4664 5009 5856
1548 4383 5055
3172 4190 6373
5899 6443 6470
2572 3647 6240
1295 2158 6466
5604 6269 6368
3 5551 6454
3325 5797 6261
666 1397 5538
3069 4274 6410
4042 5992 6437
743 3075 3447
1344 2725 6386
283 2808 6303
2 4627 4632
26 1565 4000
4012 4946 6472
1629 6158 6467
6300 6351 6376
2969 4344 4440
2317 3115 4832
2099 5263 6285
2409 5868 5997
3752 4200 6350
3125 5841 6142
1 2249 6328
16 2525 6379
3198 5269 5960
4 1705 2069
990 4948 5520
1664 3836 4521
1765 4110 6454
9 1373 6387
1969 2405 6368
623 1428 3946
3111 6380 6436
1861 5611 5934
9 2444 3081
5 5508 6317
3184 4988 5995
1060 4803 6400
5021 5826 6289
1608 4754 5648
4702 6391 6421
3899 4811 6128
927 2286 5313
4123 6181 6453
2893 4150 5261
605 4332 5094
17 3518 6358
2858 6126 6478
15 1316 6465
2 2032 2983
5249 6340 6427
5 6003 6200
4478 6315 6420
5158 6390 6447
2598 3229 5399
3747 6424 6446
1412 2453 6332
5256 5715 6455
2137 3421 4368
15 3880 5245
17 3156 5638
3227 3798 6230
2094 3129 6458
1412 5573 5932
175 1182 6304
3555 6407 6463
583 1654 6339
14 6261 6449
3553 5383 5679
2092 2744 4153
0 4466 6472
11 3840 4354
17 5457 6222
1467 6083 6220
3449 3858 6337
3782 5318 6426
417 5038 5790
3571 5638 5873
6117 6241 6476
1898 5680 6219
3235 3817 6429
2095 4194 6224
2 4092 6448
5 6330 6383
285 5075 6334
10 505 2867
1183 5956 6466
839 4716 6471
984 3254 6432
1501 4790 6465
8 1457 1707
1660 1969 6438
4349 6182 6305
1423 3848 5490
1651 2969 6345
344 4164 6298
2397 6027 6274
2233 2778 6161
13 1778 2977
9 1916 3377
0 3 6190
395 4893 6394
3512 4098 6400
3490 6281 6473
12 1359 6465
4202 5179 6412
3007 3542 4271
2400 3350 6351
7 5490 5716
4695 5231 6266
777 6292 6402
919 4851 6367
6 644 3893
5386 6190 6434
17 169 4896
である
データ処理方法。 - LDPC(Low Density Parity Check)符号の検査行列に基づき、情報ビットを、符号長が64800ビットで符号化率が28/30のLDPC符号に符号化する符号化部を備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部と前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
85 314 1602 1728 1929 2295 2729 2924 3779 4054 4276
918 1378 1838 1903 2399 2524 2937 3615 3740 4140 4213
1361 1430 2639 2648 2910 3418 3511 3543 4177 4209 4248
472 1143 1318 1545 1830 2228 2249 2256 3626 3839 3991
226 1401 2154 2318 2851 3317 3468 3944 3983 4047 4093
490 1145 1247 1851 2671 2776 3152 3229 3345 3758 3786
522 1393 1473 2196 2707 3052 3398 3814 3827 4148 4301
417 1982 2176 2336 2459 2806 3005 3771 3870 4080 4243
112 1040 1596 1621 1685 2118 2571 3359 3945 4034 4171
646 1705 2181 2439 2808 2851 2987 3044 3494 4049 4312
6 11 115 245 663 1773 2624 3444 3601 3952 4246
11 541 1020 1326 2259 2347 2750 2861 3328 3428 4126
515 941 1233 1804 2295 2528 3265 3826 4002 4022 4224
46 484 679 1949 2342 2929 3555 3860 3918 4068 4113
1832 2023 2279 2376 2965 3278 3318 3549 3640 3843 3910
241 943 1222 1583 1637 2745 3338 4080 4086 4203 4300
11 1419 1841 2398 2920 3409 3703 3768 3878 4052 4254
878 2049 2123 2431 2657 2704 3135 3342 3728 4141 4162
16 837 1267 1410 2100 3026 3099 3107 4042 4129 4157
133 646 1367 1394 2118 2311 2676 2956 3195 3536 3657
698 1444 2129 2432 2494 2793 2947 3852 3985 4254 4319
11 1076 1618 1995 2332 2743 2934 3009 3565 4169 4188
14 20 808 2629 2681 3090 3491 3835 4017 4068 4083
433 1386 2416 2570 2950 3611 3869 3969 4248 4251 4316
384 1292 1534 2610 2617 3559 3638 3964 4131 4293 4313
271 564 1719 2288 2597 2674 3429 3455 3793 4074 4286
133 190 815 955 1485 2000 2860 3000 3734 4013 4287
559 771 1762 2537 2764 2816 3186 3806 3933 4224 4271
11 733 1198 1735 1856 2668 2754 3216 4070 4113 4311
4 806 1832 2047 2058 2724 3387 3793 3833 4005 4319
506 1456 2339 3069 3343 3442 3889 3939 4013 4212 4278
2038 3980 4313
64 2373 4080
800 1535 4166
1030 3759 4002
1687 3269 4225
1219 2632 3878
719 2916 4277
1261 1930 3459
777 1568 1914
4 397 3290
10 3451 4115
3629 3885 4155
2652 3668 4026
135 3172 4319
1426 1970 3657
199 1268 2064
570 845 2761
41 1067 3498
1588 2482 2750
1615 2013 2715
121 1812 2588
10 992 1082
1929 4225 4279
6 1967 3760
593 1812 4107
891 2146 4158
924 2282 3585
592 2971 4235
260 3493 4313
2423 3180 3449
2042 3118 3625
2877 3064 3882
7 2139 4316
4 7 2954
1398 3947 4272
3675 4253 4318
1561 1977 2432
2531 4192 4209
1032 1102 4268
75 1718 3438
925 1073 4171
2124 2762 4148
4 3455 4069
3 1279 3382
1277 1746 3969
2727 3127 4230
584 1108 3454
9 2057 3061
1608 4103 4310
2673 3164 3713
1379 4072 4318
950 3447 4146
2509 4255 4296
819 1352 3371
3562 3865 4041
940 1217 3607
114 2544 4310
4 2178 4213
2035 4246 4251
272 1236 2733
953 2762 4115
1853 3496 4309
1119 3740 4318
2051 4058 4317
0 3162 4207
2389 4034 4111
4 3395 4301
3716 4089 4198
6 4272 4311
1 4 1854
4238 4299 4305
7 10 3737
11 3764 4296
297 1912 4117
1087 1796 4056
2153 3882 4030
962 4043 4203
243 3841 4308
2183 3886 4216
943 1974 2897
278 3224 3933
3 4196 4245
3409 4301 4315
2 2176 3214
462 3203 4008
478 2178 4202
3593 3825 4216
115 2796 4225
3827 4196 4251
1375 4301 4306
296 407 2055
688 3913 4281
3446 3840 4314
1073 3444 4146
1556 2761 3391
2 3543 4264
1378 3347 4305
847 1952 2745
1 1743 4042
2087 3048 4254
1010 4073 4132
2610 4129 4152
4106 4120 4313
7 4282 4304
3885 4227 4319
1235 4105 4195
1700 2332 4224
9 3750 4282
1539 4013 4310
3734 3834 4011
1397 2758 3645
7 1000 2984
11 3433 4068
1139 1800 3352
8 546 2561
1 4209 4239
2366 4063 4282
279 2524 2533
657 1913 4006
2322 2623 2960
758 803 2304
9 13 4241
3887 4299 4318
2612 3830 4230
1300 1596 2155
3622 3671 4230
2491 3722 3977
735 3812 4201
3204 3796 4317
2727 4292 4305
1062 2676 4255
2777 3131 4286
2518 3352 3937
4225 4255 4317
3644 3822 4311
1853 3754 4094
599 2608 3276
である
データ処理装置。 - LDPC(Low Density Parity Check)符号の検査行列に基づき、情報ビットを、符号長が64800ビットで符号化率が28/30のLDPC符号に符号化する符号化ステップを備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部と前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
85 314 1602 1728 1929 2295 2729 2924 3779 4054 4276
918 1378 1838 1903 2399 2524 2937 3615 3740 4140 4213
1361 1430 2639 2648 2910 3418 3511 3543 4177 4209 4248
472 1143 1318 1545 1830 2228 2249 2256 3626 3839 3991
226 1401 2154 2318 2851 3317 3468 3944 3983 4047 4093
490 1145 1247 1851 2671 2776 3152 3229 3345 3758 3786
522 1393 1473 2196 2707 3052 3398 3814 3827 4148 4301
417 1982 2176 2336 2459 2806 3005 3771 3870 4080 4243
112 1040 1596 1621 1685 2118 2571 3359 3945 4034 4171
646 1705 2181 2439 2808 2851 2987 3044 3494 4049 4312
6 11 115 245 663 1773 2624 3444 3601 3952 4246
11 541 1020 1326 2259 2347 2750 2861 3328 3428 4126
515 941 1233 1804 2295 2528 3265 3826 4002 4022 4224
46 484 679 1949 2342 2929 3555 3860 3918 4068 4113
1832 2023 2279 2376 2965 3278 3318 3549 3640 3843 3910
241 943 1222 1583 1637 2745 3338 4080 4086 4203 4300
11 1419 1841 2398 2920 3409 3703 3768 3878 4052 4254
878 2049 2123 2431 2657 2704 3135 3342 3728 4141 4162
16 837 1267 1410 2100 3026 3099 3107 4042 4129 4157
133 646 1367 1394 2118 2311 2676 2956 3195 3536 3657
698 1444 2129 2432 2494 2793 2947 3852 3985 4254 4319
11 1076 1618 1995 2332 2743 2934 3009 3565 4169 4188
14 20 808 2629 2681 3090 3491 3835 4017 4068 4083
433 1386 2416 2570 2950 3611 3869 3969 4248 4251 4316
384 1292 1534 2610 2617 3559 3638 3964 4131 4293 4313
271 564 1719 2288 2597 2674 3429 3455 3793 4074 4286
133 190 815 955 1485 2000 2860 3000 3734 4013 4287
559 771 1762 2537 2764 2816 3186 3806 3933 4224 4271
11 733 1198 1735 1856 2668 2754 3216 4070 4113 4311
4 806 1832 2047 2058 2724 3387 3793 3833 4005 4319
506 1456 2339 3069 3343 3442 3889 3939 4013 4212 4278
2038 3980 4313
64 2373 4080
800 1535 4166
1030 3759 4002
1687 3269 4225
1219 2632 3878
719 2916 4277
1261 1930 3459
777 1568 1914
4 397 3290
10 3451 4115
3629 3885 4155
2652 3668 4026
135 3172 4319
1426 1970 3657
199 1268 2064
570 845 2761
41 1067 3498
1588 2482 2750
1615 2013 2715
121 1812 2588
10 992 1082
1929 4225 4279
6 1967 3760
593 1812 4107
891 2146 4158
924 2282 3585
592 2971 4235
260 3493 4313
2423 3180 3449
2042 3118 3625
2877 3064 3882
7 2139 4316
4 7 2954
1398 3947 4272
3675 4253 4318
1561 1977 2432
2531 4192 4209
1032 1102 4268
75 1718 3438
925 1073 4171
2124 2762 4148
4 3455 4069
3 1279 3382
1277 1746 3969
2727 3127 4230
584 1108 3454
9 2057 3061
1608 4103 4310
2673 3164 3713
1379 4072 4318
950 3447 4146
2509 4255 4296
819 1352 3371
3562 3865 4041
940 1217 3607
114 2544 4310
4 2178 4213
2035 4246 4251
272 1236 2733
953 2762 4115
1853 3496 4309
1119 3740 4318
2051 4058 4317
0 3162 4207
2389 4034 4111
4 3395 4301
3716 4089 4198
6 4272 4311
1 4 1854
4238 4299 4305
7 10 3737
11 3764 4296
297 1912 4117
1087 1796 4056
2153 3882 4030
962 4043 4203
243 3841 4308
2183 3886 4216
943 1974 2897
278 3224 3933
3 4196 4245
3409 4301 4315
2 2176 3214
462 3203 4008
478 2178 4202
3593 3825 4216
115 2796 4225
3827 4196 4251
1375 4301 4306
296 407 2055
688 3913 4281
3446 3840 4314
1073 3444 4146
1556 2761 3391
2 3543 4264
1378 3347 4305
847 1952 2745
1 1743 4042
2087 3048 4254
1010 4073 4132
2610 4129 4152
4106 4120 4313
7 4282 4304
3885 4227 4319
1235 4105 4195
1700 2332 4224
9 3750 4282
1539 4013 4310
3734 3834 4011
1397 2758 3645
7 1000 2984
11 3433 4068
1139 1800 3352
8 546 2561
1 4209 4239
2366 4063 4282
279 2524 2533
657 1913 4006
2322 2623 2960
758 803 2304
9 13 4241
3887 4299 4318
2612 3830 4230
1300 1596 2155
3622 3671 4230
2491 3722 3977
735 3812 4201
3204 3796 4317
2727 4292 4305
1062 2676 4255
2777 3131 4286
2518 3352 3937
4225 4255 4317
3644 3822 4311
1853 3754 4094
599 2608 3276
である
データ処理方法。 - LDPC(Low Density Parity Check)符号の検査行列に基づき、符号長が64800ビットで符号化率が28/30のLDPC符号を復号する復号部を備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部と前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
85 314 1602 1728 1929 2295 2729 2924 3779 4054 4276
918 1378 1838 1903 2399 2524 2937 3615 3740 4140 4213
1361 1430 2639 2648 2910 3418 3511 3543 4177 4209 4248
472 1143 1318 1545 1830 2228 2249 2256 3626 3839 3991
226 1401 2154 2318 2851 3317 3468 3944 3983 4047 4093
490 1145 1247 1851 2671 2776 3152 3229 3345 3758 3786
522 1393 1473 2196 2707 3052 3398 3814 3827 4148 4301
417 1982 2176 2336 2459 2806 3005 3771 3870 4080 4243
112 1040 1596 1621 1685 2118 2571 3359 3945 4034 4171
646 1705 2181 2439 2808 2851 2987 3044 3494 4049 4312
6 11 115 245 663 1773 2624 3444 3601 3952 4246
11 541 1020 1326 2259 2347 2750 2861 3328 3428 4126
515 941 1233 1804 2295 2528 3265 3826 4002 4022 4224
46 484 679 1949 2342 2929 3555 3860 3918 4068 4113
1832 2023 2279 2376 2965 3278 3318 3549 3640 3843 3910
241 943 1222 1583 1637 2745 3338 4080 4086 4203 4300
11 1419 1841 2398 2920 3409 3703 3768 3878 4052 4254
878 2049 2123 2431 2657 2704 3135 3342 3728 4141 4162
16 837 1267 1410 2100 3026 3099 3107 4042 4129 4157
133 646 1367 1394 2118 2311 2676 2956 3195 3536 3657
698 1444 2129 2432 2494 2793 2947 3852 3985 4254 4319
11 1076 1618 1995 2332 2743 2934 3009 3565 4169 4188
14 20 808 2629 2681 3090 3491 3835 4017 4068 4083
433 1386 2416 2570 2950 3611 3869 3969 4248 4251 4316
384 1292 1534 2610 2617 3559 3638 3964 4131 4293 4313
271 564 1719 2288 2597 2674 3429 3455 3793 4074 4286
133 190 815 955 1485 2000 2860 3000 3734 4013 4287
559 771 1762 2537 2764 2816 3186 3806 3933 4224 4271
11 733 1198 1735 1856 2668 2754 3216 4070 4113 4311
4 806 1832 2047 2058 2724 3387 3793 3833 4005 4319
506 1456 2339 3069 3343 3442 3889 3939 4013 4212 4278
2038 3980 4313
64 2373 4080
800 1535 4166
1030 3759 4002
1687 3269 4225
1219 2632 3878
719 2916 4277
1261 1930 3459
777 1568 1914
4 397 3290
10 3451 4115
3629 3885 4155
2652 3668 4026
135 3172 4319
1426 1970 3657
199 1268 2064
570 845 2761
41 1067 3498
1588 2482 2750
1615 2013 2715
121 1812 2588
10 992 1082
1929 4225 4279
6 1967 3760
593 1812 4107
891 2146 4158
924 2282 3585
592 2971 4235
260 3493 4313
2423 3180 3449
2042 3118 3625
2877 3064 3882
7 2139 4316
4 7 2954
1398 3947 4272
3675 4253 4318
1561 1977 2432
2531 4192 4209
1032 1102 4268
75 1718 3438
925 1073 4171
2124 2762 4148
4 3455 4069
3 1279 3382
1277 1746 3969
2727 3127 4230
584 1108 3454
9 2057 3061
1608 4103 4310
2673 3164 3713
1379 4072 4318
950 3447 4146
2509 4255 4296
819 1352 3371
3562 3865 4041
940 1217 3607
114 2544 4310
4 2178 4213
2035 4246 4251
272 1236 2733
953 2762 4115
1853 3496 4309
1119 3740 4318
2051 4058 4317
0 3162 4207
2389 4034 4111
4 3395 4301
3716 4089 4198
6 4272 4311
1 4 1854
4238 4299 4305
7 10 3737
11 3764 4296
297 1912 4117
1087 1796 4056
2153 3882 4030
962 4043 4203
243 3841 4308
2183 3886 4216
943 1974 2897
278 3224 3933
3 4196 4245
3409 4301 4315
2 2176 3214
462 3203 4008
478 2178 4202
3593 3825 4216
115 2796 4225
3827 4196 4251
1375 4301 4306
296 407 2055
688 3913 4281
3446 3840 4314
1073 3444 4146
1556 2761 3391
2 3543 4264
1378 3347 4305
847 1952 2745
1 1743 4042
2087 3048 4254
1010 4073 4132
2610 4129 4152
4106 4120 4313
7 4282 4304
3885 4227 4319
1235 4105 4195
1700 2332 4224
9 3750 4282
1539 4013 4310
3734 3834 4011
1397 2758 3645
7 1000 2984
11 3433 4068
1139 1800 3352
8 546 2561
1 4209 4239
2366 4063 4282
279 2524 2533
657 1913 4006
2322 2623 2960
758 803 2304
9 13 4241
3887 4299 4318
2612 3830 4230
1300 1596 2155
3622 3671 4230
2491 3722 3977
735 3812 4201
3204 3796 4317
2727 4292 4305
1062 2676 4255
2777 3131 4286
2518 3352 3937
4225 4255 4317
3644 3822 4311
1853 3754 4094
599 2608 3276
である
データ処理装置。 - LDPC(Low Density Parity Check)符号の検査行列に基づき、符号長が64800ビットで符号化率が28/30のLDPC符号を復号する復号ステップを備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部と前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
85 314 1602 1728 1929 2295 2729 2924 3779 4054 4276
918 1378 1838 1903 2399 2524 2937 3615 3740 4140 4213
1361 1430 2639 2648 2910 3418 3511 3543 4177 4209 4248
472 1143 1318 1545 1830 2228 2249 2256 3626 3839 3991
226 1401 2154 2318 2851 3317 3468 3944 3983 4047 4093
490 1145 1247 1851 2671 2776 3152 3229 3345 3758 3786
522 1393 1473 2196 2707 3052 3398 3814 3827 4148 4301
417 1982 2176 2336 2459 2806 3005 3771 3870 4080 4243
112 1040 1596 1621 1685 2118 2571 3359 3945 4034 4171
646 1705 2181 2439 2808 2851 2987 3044 3494 4049 4312
6 11 115 245 663 1773 2624 3444 3601 3952 4246
11 541 1020 1326 2259 2347 2750 2861 3328 3428 4126
515 941 1233 1804 2295 2528 3265 3826 4002 4022 4224
46 484 679 1949 2342 2929 3555 3860 3918 4068 4113
1832 2023 2279 2376 2965 3278 3318 3549 3640 3843 3910
241 943 1222 1583 1637 2745 3338 4080 4086 4203 4300
11 1419 1841 2398 2920 3409 3703 3768 3878 4052 4254
878 2049 2123 2431 2657 2704 3135 3342 3728 4141 4162
16 837 1267 1410 2100 3026 3099 3107 4042 4129 4157
133 646 1367 1394 2118 2311 2676 2956 3195 3536 3657
698 1444 2129 2432 2494 2793 2947 3852 3985 4254 4319
11 1076 1618 1995 2332 2743 2934 3009 3565 4169 4188
14 20 808 2629 2681 3090 3491 3835 4017 4068 4083
433 1386 2416 2570 2950 3611 3869 3969 4248 4251 4316
384 1292 1534 2610 2617 3559 3638 3964 4131 4293 4313
271 564 1719 2288 2597 2674 3429 3455 3793 4074 4286
133 190 815 955 1485 2000 2860 3000 3734 4013 4287
559 771 1762 2537 2764 2816 3186 3806 3933 4224 4271
11 733 1198 1735 1856 2668 2754 3216 4070 4113 4311
4 806 1832 2047 2058 2724 3387 3793 3833 4005 4319
506 1456 2339 3069 3343 3442 3889 3939 4013 4212 4278
2038 3980 4313
64 2373 4080
800 1535 4166
1030 3759 4002
1687 3269 4225
1219 2632 3878
719 2916 4277
1261 1930 3459
777 1568 1914
4 397 3290
10 3451 4115
3629 3885 4155
2652 3668 4026
135 3172 4319
1426 1970 3657
199 1268 2064
570 845 2761
41 1067 3498
1588 2482 2750
1615 2013 2715
121 1812 2588
10 992 1082
1929 4225 4279
6 1967 3760
593 1812 4107
891 2146 4158
924 2282 3585
592 2971 4235
260 3493 4313
2423 3180 3449
2042 3118 3625
2877 3064 3882
7 2139 4316
4 7 2954
1398 3947 4272
3675 4253 4318
1561 1977 2432
2531 4192 4209
1032 1102 4268
75 1718 3438
925 1073 4171
2124 2762 4148
4 3455 4069
3 1279 3382
1277 1746 3969
2727 3127 4230
584 1108 3454
9 2057 3061
1608 4103 4310
2673 3164 3713
1379 4072 4318
950 3447 4146
2509 4255 4296
819 1352 3371
3562 3865 4041
940 1217 3607
114 2544 4310
4 2178 4213
2035 4246 4251
272 1236 2733
953 2762 4115
1853 3496 4309
1119 3740 4318
2051 4058 4317
0 3162 4207
2389 4034 4111
4 3395 4301
3716 4089 4198
6 4272 4311
1 4 1854
4238 4299 4305
7 10 3737
11 3764 4296
297 1912 4117
1087 1796 4056
2153 3882 4030
962 4043 4203
243 3841 4308
2183 3886 4216
943 1974 2897
278 3224 3933
3 4196 4245
3409 4301 4315
2 2176 3214
462 3203 4008
478 2178 4202
3593 3825 4216
115 2796 4225
3827 4196 4251
1375 4301 4306
296 407 2055
688 3913 4281
3446 3840 4314
1073 3444 4146
1556 2761 3391
2 3543 4264
1378 3347 4305
847 1952 2745
1 1743 4042
2087 3048 4254
1010 4073 4132
2610 4129 4152
4106 4120 4313
7 4282 4304
3885 4227 4319
1235 4105 4195
1700 2332 4224
9 3750 4282
1539 4013 4310
3734 3834 4011
1397 2758 3645
7 1000 2984
11 3433 4068
1139 1800 3352
8 546 2561
1 4209 4239
2366 4063 4282
279 2524 2533
657 1913 4006
2322 2623 2960
758 803 2304
9 13 4241
3887 4299 4318
2612 3830 4230
1300 1596 2155
3622 3671 4230
2491 3722 3977
735 3812 4201
3204 3796 4317
2727 4292 4305
1062 2676 4255
2777 3131 4286
2518 3352 3937
4225 4255 4317
3644 3822 4311
1853 3754 4094
599 2608 3276
である
データ処理方法。 - LDPC(Low Density Parity Check)符号の検査行列に基づき、情報ビットを、符号長が64800ビットで符号化率が29/30のLDPC符号に符号化する符号化部を備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部と前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
212 499 911 940 1392
316 563 1527 2006 2077
2 1906 2043 2112 2123
537 901 1582 1812 1955
5 978 1280 1933 2145
5 2035 2044 2108 2121
5 939 1874 1974
4 1069 1758
694 2096 2106
1129 1511 1659
1564 2089 2159
2 1605 2004
474 1341 2003
103 2128 2150
1656 1993 2153
1881 2122 2138
1088 1968 2141
1 298 2073
1042 1724 2137
1253 1758 2145
1209 1566 2123
1466 2116 2155
43 2006 2049
592 1806 1865
3 143 2149
1158 1448 2002
1422 2152 2157
485 2119 2150
371 1831 2086
204 2042 2151
174 544 974
1469 1795 1995
13 708 1683
5 1144 2030
486 1309 1576
165 2030 2147
504 2073 2126
263 565 1798
239 861 1861
862 1610 1716
1346 1971 2128
5 804 1399
2139 2144 2155
4 2136 2159
1485 2059 2158
50 1091 1332
373 1730 2092
59 1086 1401
1166 1781 2065
213 2080 2154
492 1905 2110
1 1517 2126
722 1427 2146
885 991 1842
3 278 1806
967 1354 1907
1697 2047 2156
684 1924 2151
2077 2122 2157
978 2054 2135
435 2034 2150
136 1997 2125
1504 1850 2153
1404 1989 2119
109 1001 2152
780 1473 2150
198 1723 2062
927 2087 2138
1 666 2018
1293 1960 2141
1648 2033 2144
681 1578 1999
1342 2022 2157
949 1907 1994
138 1261 2135
3 608 982
1211 1501 2150
201 228 1186
1295 2089 2132
267 556 2142
801 2052 2122
1382 2135 2155
572 1503 1704
346 1183 2129
1926 2090 2149
1337 2133 2140
5 1806 2125
1383 1628 2068
1193 1626 2138
1999 2115 2146
217 274 2021
3 816 2024
1380 2138 2157
607 1385 2110
184 1195 2063
0 1767 2108
0 2081 2097
1135 2036 2128
1748 2001 2125
797 1552 1926
1046 1890 2128
291 1859 2131
1075 1214 1762
60 549 1943
581 1197 1232
1009 2026 2136
884 2002 2117
1 576 1449
519 1968 2114
5 1489 1630
1926 2037 2158
2 1249 2159
0 811 2114
2055 2152 2159
802 1911 2120
204 1033 2033
1840 2012 2037
1746 2111 2155
1098 1835 2157
2 1492 1831
353 1537 1830
375 1264 2036
2 1638 2035
1096 1971 2021
950 1809 1884
253 467 1600
5 379 1833
4 1698 1970
37 1637 2136
1174 1460 2157
612 1827 2134
1783 1802 1949
2029 2118 2151
1984 2030 2141
2 347 462
862 1693 2121
2 895 1401
4 1901 2100
1183 1674 2069
1575 1940 2158
5 1904 2097
1044 2029 2092
1441 1943 2150
0 3 1300
2 516 1735
503 1342 2019
1421 1914 2131
28 986 1467
1270 1851 1988
481 1265 2016
530 546 909
653 1909 2158
1805 2002 2149
2 1359 1518
1640 2104 2129
1656 2109 2155
1307 1762 2114
565 1647 2118
1690 2081 2156
1 300 1995
5 1681 2151
1602 2050 2156
1 1960 2153
2061 2070 2138
1581 1673 2142
1048 1142 2101
1867 1991 2055
856 1640 1878
251 561 966
343 1816 2114
3 966 2045
1885 1922 2158
57 556 2059
732 1724 2147
である
データ処理装置。 - LDPC(Low Density Parity Check)符号の検査行列に基づき、情報ビットを、符号長が64800ビットで符号化率が29/30のLDPC符号に符号化する符号化ステップを備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部と前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
212 499 911 940 1392
316 563 1527 2006 2077
2 1906 2043 2112 2123
537 901 1582 1812 1955
5 978 1280 1933 2145
5 2035 2044 2108 2121
5 939 1874 1974
4 1069 1758
694 2096 2106
1129 1511 1659
1564 2089 2159
2 1605 2004
474 1341 2003
103 2128 2150
1656 1993 2153
1881 2122 2138
1088 1968 2141
1 298 2073
1042 1724 2137
1253 1758 2145
1209 1566 2123
1466 2116 2155
43 2006 2049
592 1806 1865
3 143 2149
1158 1448 2002
1422 2152 2157
485 2119 2150
371 1831 2086
204 2042 2151
174 544 974
1469 1795 1995
13 708 1683
5 1144 2030
486 1309 1576
165 2030 2147
504 2073 2126
263 565 1798
239 861 1861
862 1610 1716
1346 1971 2128
5 804 1399
2139 2144 2155
4 2136 2159
1485 2059 2158
50 1091 1332
373 1730 2092
59 1086 1401
1166 1781 2065
213 2080 2154
492 1905 2110
1 1517 2126
722 1427 2146
885 991 1842
3 278 1806
967 1354 1907
1697 2047 2156
684 1924 2151
2077 2122 2157
978 2054 2135
435 2034 2150
136 1997 2125
1504 1850 2153
1404 1989 2119
109 1001 2152
780 1473 2150
198 1723 2062
927 2087 2138
1 666 2018
1293 1960 2141
1648 2033 2144
681 1578 1999
1342 2022 2157
949 1907 1994
138 1261 2135
3 608 982
1211 1501 2150
201 228 1186
1295 2089 2132
267 556 2142
801 2052 2122
1382 2135 2155
572 1503 1704
346 1183 2129
1926 2090 2149
1337 2133 2140
5 1806 2125
1383 1628 2068
1193 1626 2138
1999 2115 2146
217 274 2021
3 816 2024
1380 2138 2157
607 1385 2110
184 1195 2063
0 1767 2108
0 2081 2097
1135 2036 2128
1748 2001 2125
797 1552 1926
1046 1890 2128
291 1859 2131
1075 1214 1762
60 549 1943
581 1197 1232
1009 2026 2136
884 2002 2117
1 576 1449
519 1968 2114
5 1489 1630
1926 2037 2158
2 1249 2159
0 811 2114
2055 2152 2159
802 1911 2120
204 1033 2033
1840 2012 2037
1746 2111 2155
1098 1835 2157
2 1492 1831
353 1537 1830
375 1264 2036
2 1638 2035
1096 1971 2021
950 1809 1884
253 467 1600
5 379 1833
4 1698 1970
37 1637 2136
1174 1460 2157
612 1827 2134
1783 1802 1949
2029 2118 2151
1984 2030 2141
2 347 462
862 1693 2121
2 895 1401
4 1901 2100
1183 1674 2069
1575 1940 2158
5 1904 2097
1044 2029 2092
1441 1943 2150
0 3 1300
2 516 1735
503 1342 2019
1421 1914 2131
28 986 1467
1270 1851 1988
481 1265 2016
530 546 909
653 1909 2158
1805 2002 2149
2 1359 1518
1640 2104 2129
1656 2109 2155
1307 1762 2114
565 1647 2118
1690 2081 2156
1 300 1995
5 1681 2151
1602 2050 2156
1 1960 2153
2061 2070 2138
1581 1673 2142
1048 1142 2101
1867 1991 2055
856 1640 1878
251 561 966
343 1816 2114
3 966 2045
1885 1922 2158
57 556 2059
732 1724 2147
である
データ処理方法。 - LDPC(Low Density Parity Check)符号の検査行列に基づき、符号長が64800ビットで符号化率が29/30のLDPC符号を復号する復号部を備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部と前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
212 499 911 940 1392
316 563 1527 2006 2077
2 1906 2043 2112 2123
537 901 1582 1812 1955
5 978 1280 1933 2145
5 2035 2044 2108 2121
5 939 1874 1974
4 1069 1758
694 2096 2106
1129 1511 1659
1564 2089 2159
2 1605 2004
474 1341 2003
103 2128 2150
1656 1993 2153
1881 2122 2138
1088 1968 2141
1 298 2073
1042 1724 2137
1253 1758 2145
1209 1566 2123
1466 2116 2155
43 2006 2049
592 1806 1865
3 143 2149
1158 1448 2002
1422 2152 2157
485 2119 2150
371 1831 2086
204 2042 2151
174 544 974
1469 1795 1995
13 708 1683
5 1144 2030
486 1309 1576
165 2030 2147
504 2073 2126
263 565 1798
239 861 1861
862 1610 1716
1346 1971 2128
5 804 1399
2139 2144 2155
4 2136 2159
1485 2059 2158
50 1091 1332
373 1730 2092
59 1086 1401
1166 1781 2065
213 2080 2154
492 1905 2110
1 1517 2126
722 1427 2146
885 991 1842
3 278 1806
967 1354 1907
1697 2047 2156
684 1924 2151
2077 2122 2157
978 2054 2135
435 2034 2150
136 1997 2125
1504 1850 2153
1404 1989 2119
109 1001 2152
780 1473 2150
198 1723 2062
927 2087 2138
1 666 2018
1293 1960 2141
1648 2033 2144
681 1578 1999
1342 2022 2157
949 1907 1994
138 1261 2135
3 608 982
1211 1501 2150
201 228 1186
1295 2089 2132
267 556 2142
801 2052 2122
1382 2135 2155
572 1503 1704
346 1183 2129
1926 2090 2149
1337 2133 2140
5 1806 2125
1383 1628 2068
1193 1626 2138
1999 2115 2146
217 274 2021
3 816 2024
1380 2138 2157
607 1385 2110
184 1195 2063
0 1767 2108
0 2081 2097
1135 2036 2128
1748 2001 2125
797 1552 1926
1046 1890 2128
291 1859 2131
1075 1214 1762
60 549 1943
581 1197 1232
1009 2026 2136
884 2002 2117
1 576 1449
519 1968 2114
5 1489 1630
1926 2037 2158
2 1249 2159
0 811 2114
2055 2152 2159
802 1911 2120
204 1033 2033
1840 2012 2037
1746 2111 2155
1098 1835 2157
2 1492 1831
353 1537 1830
375 1264 2036
2 1638 2035
1096 1971 2021
950 1809 1884
253 467 1600
5 379 1833
4 1698 1970
37 1637 2136
1174 1460 2157
612 1827 2134
1783 1802 1949
2029 2118 2151
1984 2030 2141
2 347 462
862 1693 2121
2 895 1401
4 1901 2100
1183 1674 2069
1575 1940 2158
5 1904 2097
1044 2029 2092
1441 1943 2150
0 3 1300
2 516 1735
503 1342 2019
1421 1914 2131
28 986 1467
1270 1851 1988
481 1265 2016
530 546 909
653 1909 2158
1805 2002 2149
2 1359 1518
1640 2104 2129
1656 2109 2155
1307 1762 2114
565 1647 2118
1690 2081 2156
1 300 1995
5 1681 2151
1602 2050 2156
1 1960 2153
2061 2070 2138
1581 1673 2142
1048 1142 2101
1867 1991 2055
856 1640 1878
251 561 966
343 1816 2114
3 966 2045
1885 1922 2158
57 556 2059
732 1724 2147
である
データ処理装置。 - LDPC(Low Density Parity Check)符号の検査行列に基づき、符号長が64800ビットで符号化率が29/30のLDPC符号を復号する復号ステップを備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部と前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
212 499 911 940 1392
316 563 1527 2006 2077
2 1906 2043 2112 2123
537 901 1582 1812 1955
5 978 1280 1933 2145
5 2035 2044 2108 2121
5 939 1874 1974
4 1069 1758
694 2096 2106
1129 1511 1659
1564 2089 2159
2 1605 2004
474 1341 2003
103 2128 2150
1656 1993 2153
1881 2122 2138
1088 1968 2141
1 298 2073
1042 1724 2137
1253 1758 2145
1209 1566 2123
1466 2116 2155
43 2006 2049
592 1806 1865
3 143 2149
1158 1448 2002
1422 2152 2157
485 2119 2150
371 1831 2086
204 2042 2151
174 544 974
1469 1795 1995
13 708 1683
5 1144 2030
486 1309 1576
165 2030 2147
504 2073 2126
263 565 1798
239 861 1861
862 1610 1716
1346 1971 2128
5 804 1399
2139 2144 2155
4 2136 2159
1485 2059 2158
50 1091 1332
373 1730 2092
59 1086 1401
1166 1781 2065
213 2080 2154
492 1905 2110
1 1517 2126
722 1427 2146
885 991 1842
3 278 1806
967 1354 1907
1697 2047 2156
684 1924 2151
2077 2122 2157
978 2054 2135
435 2034 2150
136 1997 2125
1504 1850 2153
1404 1989 2119
109 1001 2152
780 1473 2150
198 1723 2062
927 2087 2138
1 666 2018
1293 1960 2141
1648 2033 2144
681 1578 1999
1342 2022 2157
949 1907 1994
138 1261 2135
3 608 982
1211 1501 2150
201 228 1186
1295 2089 2132
267 556 2142
801 2052 2122
1382 2135 2155
572 1503 1704
346 1183 2129
1926 2090 2149
1337 2133 2140
5 1806 2125
1383 1628 2068
1193 1626 2138
1999 2115 2146
217 274 2021
3 816 2024
1380 2138 2157
607 1385 2110
184 1195 2063
0 1767 2108
0 2081 2097
1135 2036 2128
1748 2001 2125
797 1552 1926
1046 1890 2128
291 1859 2131
1075 1214 1762
60 549 1943
581 1197 1232
1009 2026 2136
884 2002 2117
1 576 1449
519 1968 2114
5 1489 1630
1926 2037 2158
2 1249 2159
0 811 2114
2055 2152 2159
802 1911 2120
204 1033 2033
1840 2012 2037
1746 2111 2155
1098 1835 2157
2 1492 1831
353 1537 1830
375 1264 2036
2 1638 2035
1096 1971 2021
950 1809 1884
253 467 1600
5 379 1833
4 1698 1970
37 1637 2136
1174 1460 2157
612 1827 2134
1783 1802 1949
2029 2118 2151
1984 2030 2141
2 347 462
862 1693 2121
2 895 1401
4 1901 2100
1183 1674 2069
1575 1940 2158
5 1904 2097
1044 2029 2092
1441 1943 2150
0 3 1300
2 516 1735
503 1342 2019
1421 1914 2131
28 986 1467
1270 1851 1988
481 1265 2016
530 546 909
653 1909 2158
1805 2002 2149
2 1359 1518
1640 2104 2129
1656 2109 2155
1307 1762 2114
565 1647 2118
1690 2081 2156
1 300 1995
5 1681 2151
1602 2050 2156
1 1960 2153
2061 2070 2138
1581 1673 2142
1048 1142 2101
1867 1991 2055
856 1640 1878
251 561 966
343 1816 2114
3 966 2045
1885 1922 2158
57 556 2059
732 1724 2147
である
データ処理方法。
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US14/386,830 US20150046765A1 (en) | 2013-02-08 | 2014-01-27 | Data processing apparatus and data processing method |
CN201480000958.9A CN104221292B (zh) | 2013-02-08 | 2014-01-27 | 数据处理装置和数据处理方法 |
MX2014011863A MX2014011863A (es) | 2013-02-08 | 2014-01-27 | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. |
JP2014542036A JPWO2014123018A1 (ja) | 2013-02-08 | 2014-01-27 | データ処理装置、及びデータ処理方法 |
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KR1020147027155A KR102091888B1 (ko) | 2013-02-08 | 2014-01-27 | 데이터 처리 장치, 및 데이터 처리 방법 |
CA2868419A CA2868419C (en) | 2013-02-08 | 2014-01-27 | Data processing apparatus and data processing method |
US15/962,992 US10804934B2 (en) | 2013-02-08 | 2018-04-25 | Data processing apparatus and data processing method |
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KR102287621B1 (ko) * | 2015-02-16 | 2021-08-10 | 한국전자통신연구원 | 길이가 64800이며, 부호율이 3/15인 ldpc 부호어 및 256-심볼 맵핑을 위한 비트 인터리버 및 이를 이용한 비트 인터리빙 방법 |
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KR102091888B1 (ko) | 2020-04-14 |
US20150046765A1 (en) | 2015-02-12 |
CN104221292B (zh) | 2019-07-02 |
MY191686A (en) | 2022-07-07 |
US11218170B2 (en) | 2022-01-04 |
CA2868419A1 (en) | 2014-08-14 |
US20190007061A1 (en) | 2019-01-03 |
CA2868419C (en) | 2023-03-14 |
US10804934B2 (en) | 2020-10-13 |
KR20150116378A (ko) | 2015-10-15 |
MX2014011863A (es) | 2014-11-03 |
CN104221292A (zh) | 2014-12-17 |
US20200403637A1 (en) | 2020-12-24 |
EP2955855A1 (en) | 2015-12-16 |
EP2955855A4 (en) | 2016-08-17 |
JPWO2014123018A1 (ja) | 2017-02-02 |
SG11201406379RA (en) | 2014-11-27 |
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