WO2014118985A1 - Module bus et système bus - Google Patents

Module bus et système bus Download PDF

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Publication number
WO2014118985A1
WO2014118985A1 PCT/JP2013/052472 JP2013052472W WO2014118985A1 WO 2014118985 A1 WO2014118985 A1 WO 2014118985A1 JP 2013052472 W JP2013052472 W JP 2013052472W WO 2014118985 A1 WO2014118985 A1 WO 2014118985A1
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WO
WIPO (PCT)
Prior art keywords
bus
detection result
abnormality detection
module
data
Prior art date
Application number
PCT/JP2013/052472
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English (en)
Japanese (ja)
Inventor
清水　利彦
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2013/052472 priority Critical patent/WO2014118985A1/fr
Publication of WO2014118985A1 publication Critical patent/WO2014118985A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0745—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in an input/output transactions management context
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766—Error or fault reporting or storing
    • G06F11/0772—Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/183—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components

Definitions

  • the present invention relates to a bus module and a bus system that can identify an abnormal location when an abnormality occurs in a bus and a bus module in a bus system that transmits and receives data signals between bus modules via a bus. Is.
  • a bus signal consists of an address, data, and control signal.
  • the bus module to be accessed is distinguished by the address signal, and data is transferred by the control signal. Is done.
  • the bus buffer function unit when a function unit of a bus master accesses a bus, the bus buffer function unit enables a data buffer of the bus slave function unit of the address related to the access. Whether the functional part of the bus slave that fetches the signal to the bus arbitration unit via the signal line other than the bus and outputs the bus buffer control signal matches the functional unit specified by the address signal sent to the bus.
  • the bus arbitration unit determines whether or not the function unit of the mismatched bus slave is identified as a failure location. Thereby, not only the error detection of the bus signal but also the failure location can be specified.
  • the present invention has been made in order to solve the above-described problems, and makes it possible to easily detect an abnormal part in a bus system, thereby easily identifying an abnormal part and a detailed part in the bus module.
  • the purpose is to improve performance and analysis.
  • a bus module includes, in a plurality of bus modules connected to a bus, an access control unit that controls access to the bus, and the bus signal based on the bus signal.
  • an abnormality detection unit that detects an abnormality of the bus and the bus module
  • an abnormality detection result storage unit that stores the abnormality detection result data output from the abnormality detection unit
  • the abnormality detection result storage unit of the bus module The abnormality detection result determination unit that compares the abnormality detection result data that has been performed and the abnormality detection result data transmitted from another bus module to determine whether or not they are the same, and the abnormality determination by the abnormality detection result determination unit Based on the result, the abnormality detection communication control for instructing the access control unit to transmit the abnormality detection result data to the other bus module.
  • the bus module and the bus module having an abnormal part are specified based on the abnormality determination result of each of the bus modules, and notified to the other bus modules. Is.
  • the bus system according to claim 6 of the present invention is characterized by comprising the above bus module and a bus.
  • the bus module and the bus system of the present invention it is possible to detect an abnormality of the bus system even in a bus module other than the master bus module and the slave bus module that are performing communication, and the plurality of bus modules By collating the abnormality detection result data, there is an effect that it is possible to improve the accuracy of specifying the abnormal part.
  • FIG. 1 is a block diagram illustrating a configuration of a bus module and an entire bus system according to a first embodiment.
  • FIG. 6 is a diagram illustrating a bus signal pattern in a normal state of the first embodiment.
  • FIG. 3 is a diagram showing a pattern of bus signals when an abnormality occurs in the first embodiment.
  • FIG. 10 is a diagram showing another pattern of bus signals when an abnormality occurs in the first embodiment.
  • FIG. 11 is a diagram showing a bus signal pattern in a normal state in another embodiment of the first embodiment. It is a figure which shows the pattern of the signal of the bus
  • FIG. FIG. 4 is a block diagram illustrating a configuration of a bus module and an entire bus system according to a second embodiment.
  • FIG. 1 is a block diagram showing the configuration of the entire bus module and bus system according to the first embodiment.
  • FIG. 2 is a diagram illustrating a bus signal pattern in a normal state
  • FIG. 3 is a diagram illustrating a bus signal pattern in an abnormality occurrence.
  • FIG. 4 is a diagram showing another pattern of bus signals when an abnormality occurs.
  • the bus system 200 includes bus modules 1, 2, 3,..., N, a bus 20, and a bus arbitration unit 10 that arbitrates competition for bus use and gives a bus use right.
  • the bus module 1 includes an access control unit 30 that controls access to the bus 20, an abnormality detection unit 40 that detects abnormality of the bus modules 1, 2, 3,.
  • the abnormality detection result storage unit 70 in which data is stored, the abnormality detection result data transmitted from the other bus modules 2, 3,..., N output from the abnormality detection unit 40, and the abnormality detection result of the bus module 1
  • the abnormality detection result determination unit 50 that compares the abnormality detection result data stored in the storage unit 70 to determine whether or not they are the same, and the abnormality detection result data based on the determination result in the abnormality detection result determination unit 50 Among the signals, other predetermined bits of the data line for transmitting the data signal (if the data signal is transmitted in parallel, there are data lines corresponding to the number of bits of the data signal) are used.
  • Bus module 2,3, .., the abnormality detecting the communication control unit 60 instructs the access control unit 30 to transmit to n, in is configured.
  • the signals used in the bus module 1 are a bus use right request signal 80 in which a request for using the bus 20 is sent from the access control unit 30 to the bus arbitration unit 10, and an access control unit 30 from the bus arbitration unit 10.
  • the other bus modules 2, 3,..., N have the same configuration and will not be described.
  • the abnormal part of the bus system 200 is identified from the abnormality detection result data of each of the bus modules 1, 2, 3,. , 3,..., N, and has the function of sharing the abnormal location information among all the bus modules 1, 2, 3,.
  • a bus use right request signal 80 is sent to the bus arbitration unit 10. Since the bus use right request signal 80 is output from the bus module 1, the bus arbitration unit 10 communicates with the bus use right request signal 80 from any of the other bus modules 2, 3,. When arbitration is performed and the bus use right is granted to the bus module 1, a bus use right grant signal 81 is transmitted. When the bus use right permission signal 81 is received, the bus module 1 sends an address signal to any of the bus modules 2, 3,..., N serving as slaves via the bus 20, and reads (reads). Or, write (write) access is performed.
  • the abnormality detection unit 40 checks whether there is an abnormality in the address, the write data, and the read data by a parity check. When an abnormality is detected, the abnormality detection result data is output and stored in the abnormality detection result storage unit 70.
  • the abnormality detection communication control unit 60 When the abnormality result data is output from the abnormality detection result determination unit 50, the abnormality detection communication control unit 60 notifies the access control unit 30 that there is an abnormality, and notifies the access control unit 30 of the bus use right request signal 90. And requests the bus arbitration unit 10 to request the right to use the bus.
  • the access control unit 30 sends a bus use right request signal 80 to the bus arbitration unit 10. At this time, when normal access is performed by the access control unit 30, normal access is prioritized.
  • the access control unit 30 transmits the bus use right permission to the abnormality detection communication control unit 60.
  • the abnormality detection communication control unit 60 passes through the access control unit 30 and uses a predetermined bit of the data line of the bus 20 (bit 15 of the data line in FIG. 3), The abnormality detection result data from the abnormality detection result determination unit 50 is transmitted to the bus module 2.
  • the abnormality detection result determination unit 50 detects the abnormality of the bus module 2 itself. Comparison with the abnormality detection result data stored in the detection result storage unit 70 is performed to determine whether or not the abnormality detection result data is the same.
  • the abnormality detection communication control unit 60 uses the predetermined bit of the data line of the bus 20 (bit 15 of the data line) for the abnormality detection result data based on the determination result in the abnormality detection result determination unit 50 to another bus. A command is sent to the access control unit 30 to transmit to modules 2, 3,..., N.
  • the abnormality detection result data received from the bus module 1 is added, and if different, the abnormality detection result data detected by the bus module 2 itself is added to the received abnormality detection result data. Then, the data is transmitted to the bus module 3 by a predetermined bit of the data line (bit 15 of the data line). This processing is executed up to the bus module n, and finally the bus module n transmits to the module 1.
  • the bus module 1 identifies the bus module that has been determined to be abnormal by a number of bus modules from the abnormality detection result data transmitted last, as the bus module in which the abnormality has occurred. However, if the results of all the bus modules 1, 2, 3,..., N do not match, an abnormality occurs due to a majority decision from the abnormality detection result data of all the bus modules 1, 2, 3,. , And notifies the other bus modules 2, 3,..., N. Thereby, all the bus modules 1, 2, 3,..., N can share the abnormal part information.
  • FIG. 2 shows a normal bus signal pattern.
  • FIG. 3 shows a signal pattern of the bus when an abnormality occurs.
  • the abnormality detection result data is notified using a predetermined bit (in FIG. 3, the case where the bit 15 of the data line is used) of the data line for transmitting the data signal among the bus signals. .
  • the master bus module 1 (in this example, the bus module 1 is assumed to be a master bus module) outputs a destination address to be a slave bus module to the address line, and at the same time, the address line is valid.
  • the address strobe line indicating the presence is made significant.
  • Each of the bus modules 2, 3,..., N determines whether the transmission destination address is addressed to its own bus module and performs a parity check to check whether the address on the bus 20 is correct. As a result of the parity check, if it is not abnormal and the address is addressed to its own bus module, it is determined as a slave module. In the case of writing, the data output to the data line is subsequently stored in its own bus module. At the same time, the parity check is performed in the same manner as the address. On the other hand, even when the access is not addressed to its own bus module, a parity check is performed in the same manner to determine whether or not the access is normal.
  • the master bus module 1 uses the bit 15 of the data line to transmit the abnormality detection result data to the bus module 2.
  • the abnormality detection result data is transmitted using only bit 15 of the data line in serial transfer.
  • the serial transfer data includes a start bit indicating the start of transfer, a transmission destination address, and abnormality detection result data.
  • the anomaly detection result data length is an arbitrary length, and when the anomaly detection result data differs between bus modules, it can be added and transmitted as appropriate.
  • the abnormality detection result data detected by itself is compared with the abnormality detection result data transmitted from the bus module 1, and if it is determined to be the same, it is transmitted from the bus module 1.
  • the content is transmitted to the bus module 3 as it is, and when it is determined that the contents are different, the abnormality detection result data detected by itself is added and transmitted to the bus module 3.
  • This processing is sequentially executed up to the bus module n.
  • the bus module n transmits to the bus module 1, and the transmission processing of the abnormality detection result data is completed.
  • FIG. 4 shows the operation timing of the signal pattern of the bus in another embodiment.
  • a predetermined bit for example, the data in FIG. 3 of the data line used for transmitting the abnormality detection result data is shown.
  • the abnormality detection result data is used as the bit of the data line used here in FIGS.
  • notification is performed using another bit (in FIG. 4, the case where the bit 14 of the data line is used) different from the bit 15) of the data line.
  • the other operations are the same as those in FIGS. 2 and 3 and will not be described.
  • the abnormality detection result data is transmitted using not only the predetermined bits of the data line of the bus 20 but also other bits of the data line of the bus 20 when an abnormality occurs. Therefore, the redundancy and analysis at the time of occurrence of an abnormality can be improved.
  • FIG. 5 and FIG. 6 further show the operation timing of the bus signal pattern in another embodiment, and the abnormality detection result data is normally transmitted with the bit of the data signal currently in use. If this is not possible, another bit different from the bit of the data line used for transmitting the abnormality detection result data in the above embodiment (in the case of using bit 0 of the data line in FIGS. 5 and 6) It is configured so that it can be transmitted using. An abnormality detection result communication disabled pattern is formed and transmitted to another bus module, indicating that the abnormality detection result data cannot be transmitted with the bit of the data line currently in use. As a result, when the abnormality detection result data cannot be normally transmitted with the bit of the data line currently in use, the abnormality detection result data cannot be transmitted with another bit of the data line of the bus 20. Therefore, it is possible to specify a portion that cannot be normally transmitted by the abnormality detection result data.
  • the bus system can detect an abnormality in the bus module other than the master bus module and the slave bus module that are performing communication. Check the abnormality detection result data between modules and identify the abnormality location, or improve the accuracy of identifying the abnormality location by taking a majority vote when the abnormality detection result data between multiple bus modules do not match There is an effect that can be.
  • FIG. FIG. 7 is a block diagram illustrating the configuration of the bus module and the entire bus system according to the second embodiment.
  • the access control unit 30 and the bus 20 are further connected to the bus modules 1, 2, 3,.
  • An embodiment is provided except that a switch (for example, a semiconductor switch) 110 is provided in between, and the bus module can be disconnected from the bus 20 by the switch 110 when an abnormal point exists in the bus module. Since it is the same as 1, description of other components is omitted.
  • a switch for example, a semiconductor switch
  • the bus module 1 is configured to be electrically disconnected from the bus 20 by making the switch output valid signal 120 involuntary and turning off the switch 110 (open).
  • the bus module determined to be abnormal can be isolated from the bus, so that the bus module determined to be abnormal can be isolated even when a failure occurs that causes abnormal output to the bus. This makes it possible to ensure stable operation of the bus system.
  • the bus module and the bus system according to the second embodiment have the same effects as those of the first embodiment, and further, by providing the bus module with a switch between the access control unit and the bus, When the location is in the bus module, the bus module can be disconnected from the bus by a switch, and the stability and reliability of the bus system can be improved.
  • the present invention can be freely combined with each other, or can be appropriately modified or omitted.
  • bus module 10 bus arbitration unit, 20 buses, 30 access control units, 40 anomaly detection units, 50 abnormality detection result determination unit, 60 abnormality detection communication control unit, 70 anomaly detection result storage unit, 80, 90 bus use right request signal, 81,91 Bus use right permission signal, 110 switch, 120 Switch output valid signal, 200, 210 Bus system.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Bus Control (AREA)

Abstract

Un module bus (1) selon l'invention est configuré avec : une unité de contrôle d'accès (30) qui réalise un contrôle d'accès à un bus (20); une unité de détection d'anomalie (40) qui détecte une anomalie d'un module bus sur la base d'un signal provenant du bus (20); une unité de stockage de résultat de détection d'anomalie (70) qui stocke les données de résultat de détection d'anomalie; une unité de contrôle de communication de détection d'anomalie (60) qui produit en sortie une instruction pour transmettre les données de résultat de détection d'anomalie à d'autres modules bus (2, 3, …, et n) en utilisant les bits prédéterminés d'une ligne de données; et une unité d'évaluation de résultat de détection d'anomalie (50) qui compare les données de résultat de détection d'anomalie transmises depuis les autres modules bus (2, 3, …, et n) avec les données de résultat de détection d'anomalie stockées dans l'unité de stockage de résultat de détection d'anomalie (70) du module bus (1) pour évaluer si les deux sont identiques ou pas. En conséquence, il est possible de parvenir à une simplification de l'identification d'emplacements anomaux et de composantes détaillées au sein du module bus, ainsi qu'à une amélioration de son analyse.
PCT/JP2013/052472 2013-02-04 2013-02-04 Module bus et système bus WO2014118985A1 (fr)

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PCT/JP2013/052472 WO2014118985A1 (fr) 2013-02-04 2013-02-04 Module bus et système bus

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110458654A (zh) * 2019-07-23 2019-11-15 深圳市云充吧科技有限公司 一种移动电源及其租赁方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07182254A (ja) * 1993-12-21 1995-07-21 Nec Corp バス障害試験方式
JPH07334433A (ja) * 1994-06-08 1995-12-22 Nec Corp バス制御装置
JPH0991163A (ja) * 1995-07-13 1997-04-04 Fujitsu Ltd 情報処理装置
JPH09179835A (ja) * 1995-12-21 1997-07-11 Fuji Electric Co Ltd 並列プロセッサシステム
JP2005070822A (ja) * 2003-08-21 2005-03-17 Fujitsu Ltd 情報処理装置
JP2012113481A (ja) * 2010-11-24 2012-06-14 Mitsubishi Electric Corp バスモジュール及びバスシステム

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07182254A (ja) * 1993-12-21 1995-07-21 Nec Corp バス障害試験方式
JPH07334433A (ja) * 1994-06-08 1995-12-22 Nec Corp バス制御装置
JPH0991163A (ja) * 1995-07-13 1997-04-04 Fujitsu Ltd 情報処理装置
JPH09179835A (ja) * 1995-12-21 1997-07-11 Fuji Electric Co Ltd 並列プロセッサシステム
JP2005070822A (ja) * 2003-08-21 2005-03-17 Fujitsu Ltd 情報処理装置
JP2012113481A (ja) * 2010-11-24 2012-06-14 Mitsubishi Electric Corp バスモジュール及びバスシステム

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110458654A (zh) * 2019-07-23 2019-11-15 深圳市云充吧科技有限公司 一种移动电源及其租赁方法

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