WO2014115287A1 - Dispositif conducteur, et procédé de fabrication de celui-ci - Google Patents

Dispositif conducteur, et procédé de fabrication de celui-ci Download PDF

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Publication number
WO2014115287A1
WO2014115287A1 PCT/JP2013/051485 JP2013051485W WO2014115287A1 WO 2014115287 A1 WO2014115287 A1 WO 2014115287A1 JP 2013051485 W JP2013051485 W JP 2013051485W WO 2014115287 A1 WO2014115287 A1 WO 2014115287A1
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Prior art keywords
semiconductor layer
insulating film
columnar
metal
layer
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PCT/JP2013/051485
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English (en)
Japanese (ja)
Inventor
舛岡　富士雄
広記 中村
Original Assignee
ユニサンティス エレクトロニクス シンガポール プライベート リミテッド
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Priority to JP2014517295A priority Critical patent/JP5646116B1/ja
Priority to PCT/JP2013/051485 priority patent/WO2014115287A1/fr
Publication of WO2014115287A1 publication Critical patent/WO2014115287A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon

Definitions

  • the present invention relates to a semiconductor device manufacturing method and a semiconductor device.
  • SGT Surrounding Gate Transistor
  • a silicon pillar having a nitride hard mask formed in a columnar shape is formed, a diffusion layer under the silicon pillar is formed, a gate material is deposited, and then the gate material is planarized and etched.
  • the insulating film sidewall is formed on the sidewalls of the silicon pillar and the nitride film hard mask.
  • a resist pattern for a gate wiring is formed, the gate material is etched, the nitride film hard mask is removed, and a diffusion layer is formed on the silicon semiconductor pillar (see, for example, Patent Document 4).
  • a nitride film sidewall is formed on the silicon pillar side wall, ion implantation is performed, a diffusion layer is formed on the silicon pillar, a nitride film is deposited as a contact stopper, an oxide film is formed as an interlayer film, and contact etching is performed. ing.
  • the upper side wall of the silicon pillar is covered with the nitride film side wall, and the contact is in contact with the upper surface of the silicon pillar.
  • the silicon pillar diameter is reduced, the contact surface between the contact and the upper part of the silicon pillar is narrowed, and the resistance is increased.
  • the contact hole in the upper part of the silicon pillar is etched too much, it may reach the gate electrode, and if the etching is insufficient, the contact between the upper part of the silicon pillar and the contact may be insulated.
  • the contact hole on the planar silicon layer under the silicon pillar is deep, it is difficult to fill the contact hole. Moreover, it is difficult to form a deep contact hole.
  • the density of silicon is 5 ⁇ 10 22 pieces / cm 3 , so that it becomes difficult for impurities to be present in the silicon pillar.
  • the sidewall of the LDD region is formed of polycrystalline silicon having the same conductivity type as that of the low concentration layer, and the surface carrier of the LDD region is induced by the work function difference, so that the oxide film sidewall LDD type MOS It has been shown that the impedance of the LDD region can be reduced as compared with a transistor (see, for example, Patent Document 6).
  • the polycrystalline silicon sidewall is shown to be electrically insulated from the gate electrode. In the figure, it is shown that the polysilicon side wall and the source / drain are insulated by an interlayer insulating film.
  • JP-A-2-71556 Japanese Patent Laid-Open No. 2-188966 Japanese Patent Laid-Open No. 3-145761 JP 2009-182317 A JP 2012-004244 A JP-A-11-297984
  • an object of the present invention is to provide a structure of an SGT having a structure for reducing the resistance of the upper part of the columnar semiconductor layer and a method for manufacturing the SGT.
  • a fin-shaped semiconductor layer is formed on a semiconductor substrate, a first insulating film is formed around the fin-shaped semiconductor layer, and a columnar semiconductor layer is formed on the fin-shaped semiconductor layer.
  • a second step forming a first first conductivity type diffusion layer above the columnar semiconductor layer, and a second first conductivity type diffusion below the columnar semiconductor layer and above the fin-like semiconductor layer;
  • a second interlayer insulating film is deposited, the second interlayer insulating film is planarized, etched back, the upper part of the columnar semiconductor layer is exposed, and the first contact is formed.
  • a fifth resist for forming is formed, a contact hole is formed by etching the second interlayer insulating film and the first interlayer insulating film, and a second metal is deposited by depositing a second metal. Forming a first contact on the first conductivity type diffusion layer, forming a sixth resist for forming a metal wiring, and performing a fifth step of forming the first metal wiring by etching; It is characterized by having.
  • the semiconductor device of the present invention includes a fin-shaped semiconductor layer formed on a semiconductor substrate, a columnar semiconductor layer formed on the fin-shaped semiconductor layer, a gate insulating film formed around the columnar semiconductor layer, A gate electrode formed around the gate insulating film; a gate wiring connected to the gate electrode; a first first conductivity type diffusion layer formed above the columnar semiconductor layer; and the columnar semiconductor layer. And a first side wall made of a first metal formed around the upper side wall of the columnar semiconductor layer. And having.
  • the semiconductor device of the present invention further includes an upper portion of the columnar semiconductor layer and a first metal wiring formed on the first sidewall.
  • the semiconductor device of the present invention is characterized in that the semiconductor layer is a silicon layer.
  • the first conductivity type diffusion layer is n-type, and the work function of the metal of the first sidewall is between 4.0 eV and 4.2 eV.
  • the first conductivity type diffusion layer is p-type, and the work function of the metal of the first sidewall is between 5.0 eV and 5.2 eV.
  • the first contact is formed on the second first conductivity type diffusion layer, and the depth of the first contact is equal to or less than the height of the columnar semiconductor layer.
  • the semiconductor device of the present invention is characterized in that the width of the columnar semiconductor layer is the same as the width of the fin-shaped semiconductor layer.
  • an SGT structure having a structure for reducing the resistance of the upper part of the columnar semiconductor layer and a method for manufacturing the SGT.
  • the contact area between the metal and the upper portion of the columnar semiconductor layer is increased, so that the resistance of the upper portion of the columnar semiconductor layer can be reduced.
  • the work function of the metal of the first sidewall is between 4.0 eV and 4.2 eV, and is in the vicinity of the work function of n-type silicon of 4.05 eV. Since the surface carriers are induced by the work function difference, the resistance of the upper part of the columnar silicon layer can be reduced. For example, when the impurity concentration of the columnar silicon layer is low, the transistor formed of the first sidewall and the columnar silicon layer is turned on when the voltage applied to the first sidewall via the metal wiring is 0V. Will be.
  • the work function of the metal of the first sidewall is between 5.0 eV and 5.2 eV, and is in the vicinity of the work function of p-type silicon of 5.15 eV. Since the surface carriers are induced by the work function difference, the resistance of the upper part of the columnar silicon layer can be reduced. For example, when the impurity concentration of the columnar silicon layer is low, the transistor formed of the first sidewall and the columnar silicon layer is turned on when the voltage applied to the first sidewall via the metal wiring is 0V. Will be.
  • the contact hole depth for the first contact can be reduced, so that the contact hole can be easily formed, and the contact hole is made of metal. Easy to fill.
  • the fin-like semiconductor layer, the first insulating film, and the columnar semiconductor layer can be easily formed because they are based on a conventional method for manufacturing a FINFET.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • (A) is a top view of the semiconductor device based on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • a first step is shown in which a fin-shaped semiconductor layer is formed on a semiconductor substrate, a first insulating film is formed around the fin-shaped semiconductor layer, and a columnar semiconductor layer is formed on the fin-shaped semiconductor layer.
  • a first resist 102 for forming a fin-like semiconductor layer is formed on a semiconductor substrate 101.
  • the semiconductor substrate 101 is etched to form a fin-like semiconductor layer 103.
  • the fin-like semiconductor layer is formed using a resist as a mask this time, a hard mask such as an oxide film or a nitride film may be used.
  • the first resist 102 is removed.
  • a first insulating film 104 is deposited around the fin-like semiconductor layer 103.
  • An oxide film formed by high-density plasma or an oxide film formed by low-pressure chemical vapor deposition may be used as the first insulating film.
  • the first insulating film 104 is etched back to expose the upper portion of the fin-like semiconductor layer 103.
  • the manufacturing method is the same as that of the conventional fin-shaped semiconductor layer.
  • a second resist 105 is formed so as to be orthogonal to the fin-like semiconductor layer 103.
  • a portion where the fin-shaped semiconductor layer 103 and the resist 105 are orthogonal to each other is a portion that becomes a columnar semiconductor layer. Since a line-shaped resist can be used, the possibility that the resist falls after patterning is low, and the process is stable.
  • the fin-like semiconductor layer 103 is etched.
  • a portion where the fin-shaped semiconductor layer 103 and the second resist 105 are orthogonal to each other becomes a columnar semiconductor layer 106. Therefore, the width of the columnar semiconductor layer 106 is the same as the width of the fin-shaped semiconductor layer.
  • a columnar semiconductor layer 106 is formed on the fin-shaped semiconductor layer 103, and a first insulating film 104 is formed around the fin-shaped semiconductor layer 103.
  • the fin-like semiconductor layer, the first insulating film, and the columnar semiconductor layer can be easily formed because they are based on the conventional FINFET manufacturing method.
  • the second resist 105 is removed.
  • the first step of forming the fin-shaped semiconductor layer on the semiconductor substrate, forming the first insulating film around the fin-shaped semiconductor layer, and forming the columnar semiconductor layer on the fin-shaped semiconductor layer is performed. Indicated.
  • a second step of forming a gate insulating film formed around the columnar semiconductor layer, a gate electrode formed around the gate insulating film, and a gate wiring connected to the gate electrode is performed. Show.
  • a gate insulating film 107 is formed around the columnar semiconductor layer 106, and a metal film 108 and a polysilicon film 109 are formed around the gate insulating film 107. At this time, a thin polysilicon film 109 is used. Therefore, voids can be prevented from being formed in the polysilicon film.
  • the metal film 108 may be any metal that is used in a semiconductor process and sets a threshold voltage of a transistor. For example, titanium nitride can be used. .
  • the gate insulating film 107 may be any film used in a semiconductor process. For example, an oxide film, an oxynitride film, or a high dielectric film can be used.
  • a third resist 110 for forming the gate wiring 111b is formed.
  • the resist height is described as being higher than that of the columnar semiconductor layer. As the gate wiring width becomes narrower, the polysilicon above the columnar semiconductor layer becomes easier to be exposed. The resist height may be lower than the columnar semiconductor layer.
  • the polysilicon film 109 and the metal film 108 are etched.
  • a gate electrode 111a and a gate wiring 111b are formed.
  • the upper part of the columnar semiconductor layer may be etched during the etching.
  • the height may be set to the sum of a desired columnar semiconductor layer height and a height that is later removed during etching of the gate wiring. Therefore, the manufacturing process of the present invention is a self-alignment process.
  • the third resist 110 is removed.
  • a fourth resist 112 is deposited to expose the polysilicon film 109 on the upper side wall of the columnar semiconductor layer 106. It is preferable to use resist etchback. Further, a coating film such as spin-on glass may be used.
  • the exposed polysilicon film 109 is removed by etching. Isotropic etching is preferred.
  • the fourth resist 112 is removed.
  • the metal film 108 is removed by etching, and the metal film 108 is left on the side wall of the columnar semiconductor layer 106. Isotropic etching is preferred. A gate electrode 111 a is formed by the metal film 108 on the sidewall of the columnar semiconductor layer 106 and the polysilicon film 109. Therefore, it becomes a self-alignment process.
  • the second step of forming the gate insulating film formed around the columnar semiconductor layer, the gate electrode formed around the gate insulating film, and the gate wiring connected to the gate electrode is performed. Indicated.
  • a first first conductivity type diffusion layer is formed above the columnar semiconductor layer, and a second first conductivity type diffusion layer is formed below the columnar semiconductor layer and above the fin-like semiconductor layer.
  • a third step is shown.
  • arsenic is implanted to form a first first conductivity type diffusion layer 114 and a second first conductivity type diffusion layer 113.
  • boron or boron fluoride is implanted.
  • an oxide film 115 is deposited and heat treatment is performed.
  • a nitride film may be used.
  • the first first conductivity type diffusion layer is formed above the columnar semiconductor layer, and the second first conductivity type diffusion layer is formed below the columnar semiconductor layer and above the fin-like semiconductor layer.
  • a third step is shown.
  • the oxide film 115 is etched to form oxide film side walls 116a and 116b.
  • metal is deposited, heat-treated, and unreacted metal is removed, so that the first first conductivity type diffusion layer 114 and the second first conductivity type diffusion layer 113 are removed.
  • a first silicide 118, a second silicide 117, and a silicide 119 are formed on the top and the gate wiring 111b.
  • the silicide 120 is formed on the upper portion of the gate electrode 111a.
  • the gate wiring 111b tends to have a laminated structure of the metal film 108 and the silicide 119. Since the silicide 119 and the metal film 108 are in direct contact with each other, the resistance can be reduced.
  • the manufacturing method for forming the first silicide 118 and the second silicide 117 on the first first conductivity type diffusion layer 114, the second first conductivity type diffusion layer 113, and the gate wiring 111b is shown. It was.
  • a fourth step of forming a first side wall made of metal around the upper side wall of the columnar semiconductor layer by depositing and etching the metal is shown.
  • a first interlayer insulating film 121 is deposited and planarized.
  • etch back is performed to expose the upper side wall of the columnar semiconductor layer 106.
  • the first metal 122 is deposited.
  • the work function of the first metal is preferably between 4.0 eV and 4.2 eV. Since the work function of n-type silicon is in the vicinity of 4.05 eV, surface carriers are induced by the work function difference, so that the resistance at the top of the columnar silicon layer can be reduced.
  • the transistor formed of the first sidewall and the columnar silicon layer is turned on when the voltage applied to the first sidewall via the metal wiring is 0V. Will be.
  • a compound of tantalum and titanium (TaTi) or tantalum nitride (TaN) is preferable.
  • the work function of the first metal is preferably between 5.0 eV and 5.2 eV. Since the work function of p-type silicon is in the vicinity of 5.15 eV, surface carriers are induced by the work function difference, so that the resistance at the top of the columnar silicon layer can be reduced.
  • the transistor formed of the first sidewall and the columnar silicon layer is turned on when the voltage applied to the first sidewall via the metal wiring is 0V. Will be.
  • ruthenium (Ru) or titanium nitride (TiN) is preferable.
  • the first metal 122 is etched to form the first side wall 122 made of metal around the upper side wall of the columnar semiconductor layer 106. Since the metal is in contact with the periphery of the upper sidewall of the columnar semiconductor layer, the contact area between the metal and the upper portion of the columnar semiconductor layer is increased, so that the resistance of the upper portion of the columnar semiconductor layer can be reduced.
  • a fourth step of forming a first side wall made of metal around the upper side wall of the columnar semiconductor layer by depositing and etching the metal was shown.
  • a second interlayer insulating film is deposited, the second interlayer insulating film is flattened, etched back, an upper portion of the columnar semiconductor layer is exposed, and a fifth contact is formed to form a first contact.
  • a resist is formed, a contact hole is formed by etching the second interlayer insulating film and the first interlayer insulating film, and a second metal is deposited on the second first conductivity type diffusion layer.
  • 5 shows a fifth step of forming a first metal wiring by forming a first contact, forming a sixth resist for forming a metal wiring, and performing etching.
  • a second interlayer insulating film 123 is deposited, the second interlayer insulating film 123 is flattened, etched back, and the upper portion of the columnar semiconductor layer 106 is exposed.
  • a fifth resist 124 for forming contact holes 125 and 126 is formed.
  • the second interlayer insulating film 123 and the first interlayer insulating film 121 are etched to form contact holes 125 and 126.
  • the fifth resist 124 is removed.
  • a second metal 127 is deposited to form first contacts 128 and 129. Since the first metal wiring is directly connected to the upper part of the columnar semiconductor layer, a step of forming a contact on the upper part of the columnar semiconductor layer is unnecessary. Further, since the depth of the contact hole for the first contact can be reduced, it is easy to form the contact hole, and it is easy to fill the contact hole with metal. Further, since the upper portion of the columnar semiconductor layer 106, the upper portion of the first sidewall 122, and the second metal are in contact with each other, the resistance of the upper portion of the columnar semiconductor layer can be reduced.
  • sixth resists 130, 131, and 132 for forming the first metal wiring are formed.
  • the second metal 127 is etched to form first metal wirings 133, 134, and 135.
  • the sixth resists 130, 131, 132 are removed.
  • the second interlayer insulating film is deposited, the second interlayer insulating film is planarized, etched back, the upper portion of the columnar semiconductor layer is exposed, and the fifth contact for forming the first contact is formed.
  • a resist is formed, a contact hole is formed by etching the second interlayer insulating film and the first interlayer insulating film, and a second metal is deposited on the second first conductivity type diffusion layer.
  • a fifth step of forming a first metal wiring by forming a first contact, forming a sixth resist for forming a metal wiring, and performing etching is shown.
  • the semiconductor device obtained by the above method includes a fin-shaped semiconductor layer 103 formed on a semiconductor substrate 101, a columnar semiconductor layer 106 formed on the fin-shaped semiconductor layer 103, and a columnar semiconductor layer. 106, a gate insulating film 107 formed around the gate insulating film 107, a gate electrode 111a formed around the gate insulating film 107, a gate wiring 111b connected to the gate electrode 111a, and an upper portion of the columnar semiconductor layer 106.
  • the semiconductor device also includes an upper portion of the columnar semiconductor layer 106 and a first metal wiring formed on the first sidewall 122.
  • the first sidewall 122 may have a stacked structure of the gate insulator 107 and the first metal 122. Since the surface carriers are induced by the work function difference, the resistance of the upper part of the columnar semiconductor layer can be reduced.
  • the work function of the first metal is preferably between 4.0 eV and 4.2 eV. Since the work function of n-type silicon is in the vicinity of 4.05 eV, surface carriers are induced by the work function difference, so that the resistance at the top of the columnar silicon layer can be reduced.
  • the transistor formed of the first sidewall and the columnar silicon layer is turned on when the voltage applied to the first sidewall via the metal wiring is 0V.
  • a compound of tantalum and titanium (TaTi) or tantalum nitride (TaN) is preferable.
  • the work function of the first metal is preferably between 5.0 eV and 5.2 eV. Since the work function of p-type silicon is in the vicinity of 5.15 eV, surface carriers are induced by the work function difference, so that the resistance at the top of the columnar silicon layer can be reduced.
  • the transistor formed of the first sidewall and the columnar silicon layer is turned on when the voltage applied to the first sidewall via the metal wiring is 0V. Will be.
  • ruthenium (Ru) or titanium nitride (TiN) is preferable.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention a pour objectif de fournir un procédé de fabrication d'une structure de transistor à grille enveloppante (SGT) ainsi que d'un transistor à grille enveloppante possédant une structure destinée à réduire la résistance d'une partie supérieure de couche de semi-conducteur colonnaire. Le procédé de l'invention présente : une première étape au cours de laquelle une couche de semi-conducteur en forme d'ailette est formée, un premier film isolant est formé autour de ladite couche de semi-conducteur en forme d'ailette, et une couche de semi-conducteur colonnaire est formée sur la partie supérieure de ladite couche de semi-conducteur en forme d'ailette; une seconde étape au cours de laquelle sont formés un film isolant de grille formé autour de ladite couche de semi-conducteur colonnaire, une électrode de grille formée autour dudit film isolant de grille, et un câblage de grille connecté à ladite électrode de grille; une troisième étape au cours de laquelle sont formées une première couche de diffusion d'un premier type de conductivité sur la partie supérieure de ladite couche de semi-conducteur colonnaire, et une seconde couche de diffusion d'un premier type de conductivité sur la partie inférieure de ladite couche de semi-conducteur colonnaire et sur la partie supérieure de ladite couche de semi-conducteur en forme d'ailette; et une quatrième étape au cours de laquelle un premier film isolant intercouche est déposé et aplani, une gravure est effectuée, ladite partie supérieure de couche de semi-conducteur colonnaire est exposée, après quoi un premier métal est déposé, et un premier mur latéral constitué de métal est formé par gravure autour d'une paroi latérale de partie supérieure de ladite couche de semi-conducteur colonnaire.
PCT/JP2013/051485 2013-01-24 2013-01-24 Dispositif conducteur, et procédé de fabrication de celui-ci WO2014115287A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015008325A (ja) * 2014-09-02 2015-01-15 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置の製造方法、及び、半導体装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010251678A (ja) * 2009-04-20 2010-11-04 Unisantis Electronics Japan Ltd 半導体装置の製造方法
JP2010258345A (ja) * 2009-04-28 2010-11-11 Unisantis Electronics Japan Ltd Ｍｏｓトランジスタ及びｍｏｓトランジスタを備えた半導体装置の製造方法
JP2011040682A (ja) * 2009-08-18 2011-02-24 Unisantis Electronics Japan Ltd 半導体装置とその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010251678A (ja) * 2009-04-20 2010-11-04 Unisantis Electronics Japan Ltd 半導体装置の製造方法
JP2010258345A (ja) * 2009-04-28 2010-11-11 Unisantis Electronics Japan Ltd Ｍｏｓトランジスタ及びｍｏｓトランジスタを備えた半導体装置の製造方法
JP2011040682A (ja) * 2009-08-18 2011-02-24 Unisantis Electronics Japan Ltd 半導体装置とその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015008325A (ja) * 2014-09-02 2015-01-15 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置の製造方法、及び、半導体装置

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