WO2014079082A1 - 开关管的制作方法及开关管的蚀刻设备 - Google Patents

开关管的制作方法及开关管的蚀刻设备 Download PDF

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WO2014079082A1
WO2014079082A1 PCT/CN2012/085393 CN2012085393W WO2014079082A1 WO 2014079082 A1 WO2014079082 A1 WO 2014079082A1 CN 2012085393 W CN2012085393 W CN 2012085393W WO 2014079082 A1 WO2014079082 A1 WO 2014079082A1
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Prior art keywords
amorphous silicon
etching
silicon layer
plasma
layer
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English (en)
French (fr)
Inventor
阙祥灯
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US13/704,990 priority Critical patent/US8951818B2/en
Publication of WO2014079082A1 publication Critical patent/WO2014079082A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H10P50/268—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a method for fabricating a switch tube and an apparatus for etching a switch tube.
  • the five-time lithography process has a shorter production cycle and higher yield than that of the seven lithography processes, and can effectively reduce the number of exposures formed by the TFT array, and therefore, in modern times
  • a photolithography process is usually used to complete the fabrication of the TFT.
  • 5 lithography processes are generally classified into back channel etch type (Back Channel Etching TFT) and back channel blocking type (Etch Stop TFT), while the back channel etching type is relatively simpler than the back channel blocking type, and is more suitable for mass production.
  • a gate electrode 2 As shown in FIG. 1, in the process of fabricating a TFT by a back channel etching type process, a gate electrode 2, an insulating layer 3, an a-Si layer 4, and an n+ of a TFT are sequentially formed on a glass substrate 1. After the a-Si layer 5 and the source and drain electrodes 6, the a-Si layer 4 and the n+ a-Si layer 5 are etched to form the channel 7 of the TFT.
  • the one-step etching method is mainly used, and the same gas flow rate, the same power and the same pressure are used to etch the a-Si layer 4 and n+.
  • a-Si layer 5 which is completed in one step for a-Si layer 4 and n+
  • the etching of the a-Si layer 5 is also performed by the same parameters during over-etching, so that the energy of etching is stronger during the etching process of the entire channel 7, and the channel 7 is bombarded by the dry etching plasma.
  • the a-Si layer 4 is easily damaged, thereby causing poor TFT electrical properties.
  • the channel 7 is exposed to the outermost surface, and a protective silicon nitride CVD is formed.
  • a protective silicon nitride CVD is formed.
  • the channel 7 is subjected to bombardment from the CVD plasma due to the exposure of the channel 7, further resulting in worse electrical performance of the TFT.
  • the technical problem to be solved by the present invention is to provide a method for manufacturing a switch tube and an etching device for the switch tube, which can reduce damage to the switch tube and improve electrical performance of the switch tube.
  • a technical solution adopted by the present invention is to provide a method for manufacturing a switch tube, comprising: sequentially forming a control electrode, an insulating layer, an active layer, and a source/drain metal layer of a switch tube on a glass substrate; Patterning the source/drain metal layer to expose the active layer, and correspondingly forming an input electrode and an output electrode of the switching transistor; etching the exposed active layer in a manner of gradually decreasing the etching speed to form a channel of the switching transistor; The etching is plasma dry etching, and the switching transistor is a thin film transistor.
  • the control electrode of the switching transistor corresponds to the gate of the thin film transistor, and the input electrode and the output electrode of the switching transistor respectively correspond to the source and the drain of the thin film transistor.
  • the active layer includes an amorphous silicon layer adjacent to the insulating layer and an n+ amorphous silicon layer formed over the amorphous silicon layer; and the step of patterning the source/drain metal layer to expose the active layer includes: The drain metal layer is patterned to expose the n+ amorphous silicon layer.
  • the step of etching the exposed active layer in a manner of gradually decreasing the etching rate comprises: etching the exposed n+ amorphous silicon layer using a plasma having a first energy to expose the amorphous silicon layer; using the second energy The exposed amorphous silicon layer is plasma etched to remove a portion of the amorphous silicon layer, and the second energy is less than the first energy, thereby gradually reducing the etching rate.
  • the step of etching the exposed amorphous silicon layer using plasma having the second energy comprises: reducing power required to generate the plasma to etch the exposed amorphous silicon layer using plasma having the second energy.
  • the step of etching the exposed active layer in a manner of gradually decreasing the etching rate comprises: etching the exposed n+ amorphous silicon layer using a plasma having a first concentration to expose the amorphous silicon layer; using the second concentration The exposed amorphous silicon layer is plasma etched to remove a portion of the amorphous silicon layer, and the second concentration is less than the first concentration, thereby gradually reducing the etching rate.
  • the step of etching the exposed amorphous silicon layer with a second concentration of plasma to remove a portion of the amorphous silicon layer includes: reducing a gas flow rate of the plasma-generating etching gas to be exposed using a plasma etching having a second concentration Amorphous silicon layer.
  • another technical solution adopted by the present invention is to provide a method for manufacturing a switch tube, comprising: sequentially forming a control electrode, an insulating layer, an active layer, and a source/drain metal layer of a switch tube on a glass substrate. And patterning the source/drain metal layer to expose the active layer, and correspondingly forming an input electrode and an output electrode of the switching transistor; etching the exposed active layer in a manner of gradually decreasing the etching speed to form a channel of the switching transistor .
  • the active layer includes an amorphous silicon layer adjacent to the insulating layer and an n+ amorphous silicon layer formed over the amorphous silicon layer; and the step of patterning the source/drain metal layer to expose the active layer includes: The drain metal layer is patterned to expose the n+ amorphous silicon layer.
  • the step of etching the exposed active layer in a manner of gradually decreasing the etching rate comprises: etching the exposed n+ amorphous silicon layer using a plasma having a first energy to expose the amorphous silicon layer; using the second energy The exposed amorphous silicon layer is plasma etched to remove a portion of the amorphous silicon layer, and the second energy is less than the first energy, thereby gradually reducing the etching rate.
  • the step of etching the exposed amorphous silicon layer using plasma having the second energy comprises: reducing power required to generate the plasma to etch the exposed amorphous silicon layer using plasma having the second energy.
  • the step of etching the exposed active layer in a manner of gradually decreasing the etching rate comprises: etching the exposed n+ amorphous silicon layer using a plasma having a first concentration to expose the amorphous silicon layer; using the second concentration The exposed amorphous silicon layer is plasma etched to remove a portion of the amorphous silicon layer, and the second concentration is less than the first concentration, thereby gradually reducing the etching rate.
  • the step of etching the exposed amorphous silicon layer with a second concentration of plasma to remove a portion of the amorphous silicon layer includes: reducing a gas flow rate of the plasma-generating etching gas to be exposed using a plasma etching having a second concentration Amorphous silicon layer.
  • another technical solution adopted by the present invention is to provide an etching device for a switch tube, wherein the etching device is used for etching an active layer of the switch tube during the manufacturing process of the switch tube, wherein: An etching device for etching an active layer of the switching transistor to form a channel of the switching tube; and a control device for controlling an etching speed of the etching device to cause the etching device to perform the active layer in a manner of gradually decreasing the etching rate Etching.
  • the active layer comprises an amorphous silicon layer and an n+ amorphous silicon layer formed on the amorphous silicon layer; and the control device is specifically configured to control the etching device to generate the plasma having the first energy to use the first energy Plasma etching the n+ amorphous silicon layer to expose the amorphous silicon layer; after exposing the amorphous silicon layer, the control device is specifically configured to control the etching device to generate a plasma having the second energy to use the plasma having the second energy Etching the exposed amorphous silicon layer to remove a portion of the amorphous silicon layer, the second energy being less than the first energy, thereby gradually reducing the etching rate
  • control device comprises a first control module for controlling the power required by the etching device to generate plasma, so that the etching device generates plasma of different energies.
  • the active layer comprises an amorphous silicon layer and an n+ amorphous silicon layer formed on the amorphous silicon layer; and the control device is specifically configured to control the etching device to generate the plasma having the first concentration to use the first concentration Plasma etching the n+ amorphous silicon layer to expose the amorphous silicon layer; after exposing the amorphous silicon layer, the control device is specifically configured to control the etching device to generate the plasma having the second concentration to use the plasma having the second concentration
  • the exposed amorphous silicon layer is etched to remove a portion of the amorphous silicon layer, and the second concentration is less than the first concentration, thereby gradually reducing the etching rate.
  • the beneficial effects of the present invention are: in the manufacturing method of the switch tube of the present invention, in the process of forming the channel of the switch tube, the active layer is etched in a manner of gradually reducing the etching speed, instead of completing the etching process in one step, in a stepwise manner In the process of reducing the etching speed, the etching strength to the active layer is also gradually reduced, whereby damage to the channel can be reduced, and electrical performance and reliability of the switching transistor can be improved.
  • FIG. 1 is a schematic structural view of a TFT thin film transistor fabricated by a one-step etching method in the prior art
  • FIG. 2 is a flow chart of an embodiment of a method of fabricating a switch tube according to the present invention
  • FIG. 3 is a schematic view showing an embodiment of a manufacturing process of the switch tube of the present invention.
  • FIG. 4 is a flow diagram of an embodiment of the etching of the exposed active layer in a manner that progressively reduces the etch rate in FIG. 2;
  • FIG. 5 is a schematic diagram of an embodiment of etching an exposed active layer in a manner of gradually reducing an etching rate during fabrication of the switch tube of the present invention
  • FIG. 6 is a flow diagram of another embodiment of the etching of the exposed active layer in a manner that progressively reduces the etch rate in FIG. 2;
  • FIG. 7 is a flow chart of still another embodiment of the etching of the exposed active layer in a manner that gradually reduces the etch rate in FIG. 2;
  • FIG. 8 is a schematic view showing another embodiment of etching the exposed active layer in a manner of gradually reducing the etching rate during the fabrication process of the switch tube of the present invention
  • Fig. 9 is a schematic structural view showing an embodiment of an etching apparatus for a switch tube of the present invention.
  • the method includes the following steps:
  • Step 101 The control electrode 11, the insulating layer 12, the active layer 13, and the source/drain metal layer 14 of the switching transistor are sequentially formed on the glass substrate 10.
  • the switch tube is a three-terminal control switch.
  • a schematic diagram of the manufacturing process shown in FIG. 3 will be described.
  • the sub-step S11 after the glass substrate 10 is first cleaned and dried, a metal layer is sputtered on the glass substrate 10, and the metal is patterned to form the control electrode 11 of the switching tube. Thereafter, the insulating layer 12, the active layer 13, and the source/drain metal layer 14 are sequentially formed on the control electrode 11.
  • the insulating layer 12 is generally made of silicon nitride for blocking the active layer 13 and the control electrode 11, so that the switching tube has a high input resistance; the active layer 13 is mainly used to realize the energization conduction of the switching tube.
  • the control function of the electrical disconnection; the source and drain metal layer 14 is used to form the input electrode and the output electrode of the switch tube, which is generally made of aluminum alloy, metal aluminum or metal chromium.
  • Step S102 The source/drain metal layer 14 is patterned to expose the active layer 13, and the input electrode 141 and the output electrode 142 of the switching transistor are formed correspondingly.
  • the active layer 13 of the present embodiment specifically includes an amorphous silicon layer (a-Si layer) 131 adjacent to the insulating layer 12 and an n+ amorphous silicon layer (n+a-Si layer) formed over the amorphous silicon layer 131.
  • the amorphous silicon layer 131 is a core layer of the switch tube, the electrical characteristics and functions of the switch tube are mainly determined by the quality of the layer, and the n+ amorphous silicon layer 132 is for improving and improving the amorphous silicon layer 131 and the input.
  • a semiconductor doped layer formed by ohmic bonding between the electrode 141 and the output electrode 142. After the input electrode 141 and the output electrode 142 of the switching transistor are formed, the corresponding portion of the n+ amorphous silicon layer 132 is exposed.
  • the switch tube of the present embodiment may be a thin film transistor, and the control electrode 11 of the switch tube corresponds to the gate of the thin film transistor, and the input electrode 141 and the output electrode 142 of the switch tube correspond to the source and the drain of the thin film transistor.
  • the switch tube can also be other three-terminal control switches, such as a triode, etc., which are not limited herein.
  • Step S103 etching the exposed active layer 13 in such a manner as to gradually lower the etching rate to form the channel 15 of the switching transistor.
  • the active layer 13 is dry etched by gradually decreasing the etching rate to form the channel 15 of the switching transistor.
  • the active layer 13 is etched by plasma dry etching.
  • Plasma dry etching is a process mainly involving physical sputtering and a chemical reaction. The main purpose is to generate a chemically active plasma by using a chemically reactive gas, so that a high-energy plasma accelerated by an electric field bombards the material to be etched. Remove unwanted material.
  • the present embodiment performs dry etching of the active layer 13 in two steps, and gradually reduces the etching speed by gradually reducing the energy of the plasma.
  • the exposed active layer 13 is referred to.
  • Specific steps for etching in a manner that gradually reduces the etching rate include:
  • Step S201 etching the exposed n+ amorphous silicon layer 132 using a plasma having a first energy to expose the amorphous silicon layer 131.
  • step S102 After the source/drain metal layer 14 is patterned in step S102, the n+ amorphous silicon layer 132 in the active layer 13 is exposed.
  • this step S201 is the first etching of the active layer 13, and the exposed n+ amorphous silicon layer 132 is subjected to plasma bombardment to remove part of the n+ amorphous silicon layer 132, thereby exposing An amorphous silicon layer 131 under the corresponding removed n+ amorphous silicon layer 132 is formed.
  • the plasma from which the n+ amorphous silicon layer 132 is removed has the first energy.
  • the plasma can be subjected to corresponding bombardment energy to etch the active layer 13, and the power density corresponding to the first energy can be:
  • Upper RF source (Source RF) power density range is between 0.07 ⁇ 0.1W/cm2, for example 0.08W/cm2, and the lower RF source (Bias)
  • the power density range is between 0.05 and 0.08 W/cm 2 , for example, 0.07 W/cm 2 , and can be adjusted according to actual needs, and is not limited herein.
  • Step S202 etching the exposed amorphous silicon layer 131 using a plasma having a second energy to remove a portion of the amorphous silicon layer 131, the second energy being less than the first energy, thereby gradually reducing the etching speed.
  • the amorphous silicon layer 131 under the n+ amorphous silicon layer 132 is exposed, and the second etching of the active layer 13 is started.
  • the plasma for etching is subjected to a second energy by adjusting the power density parameter required to generate the plasma to perform a second etching on the exposed amorphous silicon layer 131 to remove a portion of the non- The silicon layer 131 is formed to form the channel 15 of the switching transistor.
  • the power density corresponding to the second energy may be in the range of: the upper RF source power density ranges from 0.05 to 0.07 W/cm 2 , for example, may be 0.05 W/cm 2 , and the lower RF source power density ranges from 0.03 to Between 0.05 W/cm 2 , for example, it may be 0.04 W/cm 2 , and specifically, it may be adjusted according to actual needs.
  • the second energy is smaller than the first energy at the first etching, thereby gradually reducing the etching speed of the active layer 13 to avoid damage to the amorphous silicon layer 131 due to excessive plasma energy during the second etching. For a plasma having a second energy, it can be obtained by reducing the power required by the plasma generating apparatus to generate plasma.
  • the exposed n+ amorphous silicon layer 132 has a thickness of 400 angstroms and the amorphous silicon layer 131 has a thickness of 1300 angstroms.
  • the plasma generating device is a dual RF source plasma etching device.
  • the active layer 13 When the active layer 13 is first etched, the exposed n + amorphous silicon layer 132 is etched, the upper RF source power of the plasma generating device generates plasma is 4000 W, and the lower RF source power is 3000 W, thereby The plasma is subjected to a corresponding first energy, and the etching time is set to 20 seconds to ensure that the n+ amorphous silicon layer 132 is etched clean and remains as little as possible on the amorphous silicon layer 131. After the first etching is completed, the second etching of the active layer 13 is performed, that is, the exposed amorphous silicon layer 131 is etched.
  • the power of the upper RF source generated by the plasma generating device is adjusted to 3000 W, and the power of the lower RF source is adjusted to 2500 W, which is reduced relative to the power during the first etching, thereby making the second plasma generated.
  • the energy is less than the first energy, such that the second etching speed is less than the first etching speed.
  • the time of the second etching was set to 15 seconds, and after the second etching was completed, the channel 15 of the switching tube was formed, and the thickness of the remaining amorphous silicon layer 131 was also changed to about 950 angstroms.
  • the plasma energy can be controlled by adjusting other parameters that affect the energy of the plasma such that the second energy of the plasma is less than the first energy.
  • the specific can be selected according to the actual situation.
  • the etching of the active layer 13 is performed in two steps instead of one step, and in the two-step etching, the plasma energy of the second etching is made smaller than that by the stepwise reduction of the power required to generate the plasma.
  • the plasma energy of the second etching reduces the energy of the plasma bombarding the amorphous silicon layer 131 during the second etching, and can reduce the damage of the amorphous silicon layer 131 caused by the excessive energy of the plasma, thereby improving the switching tube. Electrical performance and reliability.
  • the concentration of the plasma also affects the speed of plasma etching.
  • specific steps of etching the exposed active layer 13 in a manner of gradually decreasing the etching rate include:
  • Step S301 etching the exposed n+ amorphous silicon layer using plasma having a first concentration to expose the amorphous silicon layer.
  • This step is the first etching of the active layer 13, and the concentration of the plasma for etching is the first concentration to etch the exposed n+ amorphous silicon layer 132.
  • Step S302 etching the exposed amorphous silicon layer using a plasma having a second concentration to remove a portion of the amorphous silicon layer, the second concentration being less than the first concentration, thereby gradually decreasing the etching rate.
  • the active layer 13 is etched a second time.
  • the concentration of the plasma is lowered to etch the exposed amorphous silicon layer 131 using a plasma concentration smaller than the first concentration.
  • the concentration of the plasma is lowered by reducing the gas flow rate of the etching gas that generates plasma in the plasma generating apparatus.
  • the concentration of the plasma is lowered, and when the second etching of the active layer 13 is performed, the etching rate is made smaller than the etching rate of the first etching.
  • the embodiment can also reduce the plasma concentration by reducing the pressure of the chamber in which the plasma is generated, so that the second concentration is smaller than the first concentration, and the specific concentration is not performed here. limit.
  • the concentration of the plasma is decreased by reducing the gas flow rate of the etching gas, so that the second concentration is lower than the first concentration to gradually reduce the speed of etching the active layer 13.
  • the damage to the amorphous silicon layer 131 can be reduced, and the electrical performance of the switching tube can be improved.
  • the dry etching of the active layer 13 is performed in two steps.
  • the second etching ie, the second etching of the active layer 13
  • the stepwise reduction of the etching rate by lowering the energy of the plasma or lowering the concentration of the plasma can also be achieved by simultaneously reducing the energy of the plasma and the concentration of the plasma, which is not particularly limited.
  • the etching can also be performed in three steps. Specifically, referring to FIG. 7 and FIG. 8, in the process of etching the exposed active layer 23 in a manner of gradually decreasing the etching rate, the steps are as follows:
  • Step S401 etching the exposed n+ amorphous silicon layer 232 using a plasma having a first energy to expose the amorphous silicon layer 231.
  • This step is the first etching of the active layer 23, corresponding to the sub-step S31 of FIG. 7, mainly removing the n+ amorphous silicon layer 232, thereby exposing the amorphous silicon layer 231.
  • Step S402 etching the exposed amorphous silicon layer 231 using a plasma having a second energy to remove a portion of the amorphous silicon layer 231, the second energy being less than the first energy.
  • the amorphous silicon layer 231 is etched by the plasma generating apparatus to obtain a plasma having the second energy to remove a portion of the amorphous silicon layer 231, as shown in substep S32 in FIG. Moreover, the relevant parameters of the plasma generating apparatus are adjusted to reduce the power required to generate the plasma so that the second energy is smaller than the first energy to reduce the etching speed.
  • Step S403 etching a portion of the remaining amorphous silicon layer 231 using a plasma having a third energy to remove the remaining portion of the amorphous silicon layer 231, the third energy being less than the second energy, thereby gradually reducing the etching rate.
  • This step is a third etching of the active layer 23, corresponding to sub-step S33 of FIG. 7, that is, overetching the remaining amorphous silicon layer 231 to remove the remaining portion of the amorphous silicon layer 231, thereby forming a channel of the switching transistor. twenty four.
  • the power required for plasma generation by the plasma generating device is reduced again to obtain a plasma having a third energy, so that the third energy is less than the second energy.
  • the energy which in turn reduces the energy of the plasma bombarding the remaining amorphous silicon layer 231, thereby reducing damage to the amorphous silicon layer 231 and improving the reliability of the switching transistor.
  • the etching rate can also be gradually reduced by gradually decreasing the plasma concentration, the plasma concentration used in each step is different, and the plasma concentration in the latter step is smaller than in the previous step.
  • the specific implementation of the plasma concentration can be referred to the above embodiments, and will not be further described herein.
  • the plasma energy and the plasma concentration may be simultaneously reduced to gradually reduce the etching rate, and there is no particular limitation thereto.
  • the present invention further provides an embodiment of an etching apparatus for a switch tube, wherein the switch tube of the embodiment is the switch tube described in each of the above embodiments, and the etching device is used for the switch during the manufacturing process of the switch tube.
  • the active layer of the tube is etched.
  • the etching apparatus includes an etching device 41 and a control device 42.
  • the etching device 41 is for etching the active layer 13 of the switching tube to form the channel 16 of the switching tube
  • the control device 42 is for controlling the etching speed of the etching device 41 so that the etching device 41 is gradually reduced in etching speed.
  • the active layer 13 is etched.
  • the active layer 13 includes an amorphous silicon layer 131 and an n+ amorphous silicon layer 132.
  • the control device 42 is specifically configured to control the etching device 41 to generate a plasma having a first energy to etch the n+ amorphous silicon layer 132 using a plasma having a first energy, thereby exposing the amorphous silicon layer 131.
  • the control device 42 is specifically configured to control the etching device 41 to generate a plasma having a second energy to etch the exposed amorphous silicon layer 131 using a plasma having a second energy to remove a portion of the non- Crystalline silicon layer.
  • the second energy is made smaller than the first energy, and the etching speed is gradually decreased.
  • control device 42 includes a first control module 421 for controlling the power required by the etching device 41 to generate plasma. After etching the n+ amorphous silicon layer 132, the first control module 421 controls the etching device 41 to reduce the power required to generate the plasma, so that the etching device 41 generates a plasma having the second energy, and causes the second energy to be less than The first energy, thereby reducing the etching rate.
  • the control device 42 further includes a second control module 422 for controlling the concentration of plasma generated by the etching device 41.
  • the second control module 422 controls the etching device 41 to reduce the concentration of the plasma, so that the etching device 41 generates the plasma having the second concentration, and makes the second concentration smaller than the first concentration. , thereby reducing the etching speed.
  • the etching apparatus of the switch tube of the present embodiment etches the active layer 13 of the switch tube in a manner of gradually decreasing the etching speed, thereby reducing the damage to the amorphous silicon layer 131, thereby improving the electrical performance of the switch tube. And reliability.

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Abstract

一种开关管的制作方法，包括在玻璃基板上依次形成开关管的控制电极（11）、绝缘层（12）、有源层（13）以及源漏金属层（14），对源漏金属层（14）进行图案化处理后暴露有源层（13），之后对暴露的有源层（13）以逐步降低蚀刻速度的方式进行蚀刻以形成开关管的沟道。一种开关管的蚀刻设备，通过上述方式，能够减小对开关管沟道的损伤，提高开关管的可靠性。

Description

开关管的制作方法及开关管的蚀刻设备
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种开关管的制作方法及开关管的蚀刻设备。
【背景技术】
在TFT（Thin Film Transistor，薄膜晶体管）的制作工艺中，5次光刻工艺相对于7次光刻工艺而言，其生产周期更短，成品率更高，能够有效减少TFT阵列形成的曝光次数，因此，在现代TFT-LCD的生产过程中，通常采用5次光刻工艺来完成TFT的制作。5次光刻工艺一般分为背沟道蚀刻型（Back channel Etching TFT）和背沟道阻挡型（Etch Stop TFT），而背沟道蚀刻型相对背沟道阻挡型其制程更简单，更适合大批量生产。
如图1所示，采用背沟道蚀刻型工艺制作TFT的过程中，在玻璃基板1上依次形成TFT的栅极2、绝缘层3、a-Si层4、n+ a-Si层5以及源漏极6之后，对a-Si层4和n+ a-Si层5进行蚀刻以形成TFT的沟道7。
其中，在TFT的沟道7的蚀刻过程中，主要采用一步蚀刻的方法，使用同样的气体流量，同样的功率和同样的压力去蚀刻a-Si层4和n+ a-Si层5，即一步完成对a-Si层4和n+ a-Si层5的蚀刻，并且在过蚀刻时也采用同样的参数进行蚀刻，使得在整个沟道7的蚀刻过程中蚀刻的能量都较强劲，沟道7会受到干法蚀刻等离子体的轰击，a-Si层4容易受到破坏，进而导致TFT电性不良；其次，在形成沟道7后，沟道7是裸露在最外面的，在形成保护氮化硅CVD（Chemical Vapor Deposition，化学气相沉积）的过程中，由于沟道7的裸露，使得沟道7会受到来自CVD等离子体的轰击，进一步导致TFT电性性能更差。
【发明内容】
本发明主要解决的技术问题是提供一种开关管的制作方法及开关管的蚀刻设备，能够减小对开关管的损伤，提高开关管的电性性能。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种开关管的制作方法，包括：在玻璃基板上依次形成开关管的控制电极、绝缘层、有源层以及源漏金属层；将源漏金属层进行图案化处理以暴露有源层，并相应形成开关管的输入电极和输出电极；对暴露的有源层以逐步降低蚀刻速度的方式进行蚀刻以形成开关管的沟道；其中，蚀刻为等离子体干蚀刻，开关管为薄膜晶体管，开关管的控制电极对应为薄膜晶体管的栅极，开关管的输入电极和输出电极分别对应为薄膜晶体管的源极和漏极。
其中，有源层包括邻近绝缘层的非晶硅层以及形成于非晶硅层之上的n+非晶硅层；将源漏金属层进行图案化处理以暴露有源层的步骤包括：将源漏金属层进行图案化处理以暴露n+非晶硅层。
其中，对暴露的有源层以逐步降低蚀刻速度的方式进行蚀刻的步骤包括：使用具有第一能量的等离子体蚀刻暴露的n+非晶硅层以暴露非晶硅层；使用具有第二能量的等离子体蚀刻暴露的非晶硅层以除去部分非晶硅层，第二能量小于第一能量，进而逐步降低蚀刻速度。
其中，使用具有第二能量的等离子体蚀刻暴露的非晶硅层的步骤包括：减小产生等离子体所需的功率以使用具有第二能量的等离子体蚀刻暴露的非晶硅层。
其中，对暴露的有源层以逐步降低蚀刻速度的方式进行蚀刻的步骤包括：使用具有第一浓度的等离子体蚀刻暴露的n+非晶硅层以暴露非晶硅层；使用具有第二浓度的等离子体蚀刻暴露的非晶硅层以除去部分非晶硅层，第二浓度小于第一浓度，进而逐步降低蚀刻速度。
其中，使用具有第二浓度的等离子体蚀刻暴露的非晶硅层以除去部分非晶硅层的步骤包括：降低产生等离子体的蚀刻气体的气体流量以使用具有第二浓度的等离子体蚀刻暴露的非晶硅层。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种开关管的制作方法，包括：在玻璃基板上依次形成开关管的控制电极、绝缘层、有源层以及源漏金属层；将源漏金属层进行图案化处理以暴露有源层，并相应形成开关管的输入电极和输出电极；对暴露的有源层以逐步降低蚀刻速度的方式进行蚀刻以形成开关管的沟道。
其中，有源层包括邻近绝缘层的非晶硅层以及形成于非晶硅层之上的n+非晶硅层；将源漏金属层进行图案化处理以暴露有源层的步骤包括：将源漏金属层进行图案化处理以暴露n+非晶硅层。
其中，对暴露的有源层以逐步降低蚀刻速度的方式进行蚀刻的步骤包括：使用具有第一能量的等离子体蚀刻暴露的n+非晶硅层以暴露非晶硅层；使用具有第二能量的等离子体蚀刻暴露的非晶硅层以除去部分非晶硅层，第二能量小于第一能量，进而逐步降低蚀刻速度。
其中，使用具有第二能量的等离子体蚀刻暴露的非晶硅层的步骤包括：减小产生等离子体所需的功率以使用具有第二能量的等离子体蚀刻暴露的非晶硅层。
其中，对暴露的有源层以逐步降低蚀刻速度的方式进行蚀刻的步骤包括：使用具有第一浓度的等离子体蚀刻暴露的n+非晶硅层以暴露非晶硅层；使用具有第二浓度的等离子体蚀刻暴露的非晶硅层以除去部分非晶硅层，第二浓度小于第一浓度，进而逐步降低蚀刻速度。
其中，使用具有第二浓度的等离子体蚀刻暴露的非晶硅层以除去部分非晶硅层的步骤包括：降低产生等离子体的蚀刻气体的气体流量以使用具有第二浓度的等离子体蚀刻暴露的非晶硅层。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种开关管的蚀刻设备，蚀刻设备用于在开关管的制作过程中对开关管的有源层进行蚀刻，其中，包括：蚀刻装置，用于对开关管的有源层进行蚀刻以形成开关管的沟道；控制装置，用于控制蚀刻装置的蚀刻速度，以使蚀刻装置以逐步降低蚀刻速度的方式对有源层进行蚀刻。
其中，有源层包括非晶硅层以及形成于非晶硅层之上的n+非晶硅层；控制装置具体用于控制蚀刻装置产生具有第一能量的等离子体，以使用具有第一能量的等离子体蚀刻n+非晶硅层，以暴露非晶硅层；在暴露非晶硅层之后，控制装置具体用于控制蚀刻装置产生具有第二能量的等离子体，以使用具有第二能量的等离子体蚀刻暴露的非晶硅层，以除去部分非晶硅层，第二能量小于第一能量，进而逐步降低蚀刻速度
其中，控制装置包括第一控制模块，第一控制模块用于控制蚀刻装置产生等离子体所需的功率，以使得蚀刻装置产生不同能量的等离子体。
其中，有源层包括非晶硅层以及形成于非晶硅层之上的n+非晶硅层；控制装置具体用于控制蚀刻装置产生具有第一浓度的等离子体，以使用具有第一浓度的等离子体蚀刻n+非晶硅层，以暴露非晶硅层；在暴露非晶硅层之后，控制装置具体用于控制蚀刻装置产生具有第二浓度的等离子体，以使用具有第二浓度的等离子体蚀刻暴露的非晶硅层，以除去部分非晶硅层，第二浓度小于第一浓度，进而逐步降低蚀刻速度。
本发明的有益效果是：本发明开关管的制作方法中，在形成开关管的沟道的过程中，以逐步降低蚀刻速度的方式对有源层进行蚀刻，而不是一步完成蚀刻过程，在逐步减小蚀刻速度的过程中，使得对有源层的蚀刻强度也在逐渐变小，由此能够降低对沟道的损伤，提高开关管的电性性能和可靠性。
【附图说明】
图1是现有技术中采用一步蚀刻的方法制作的TFT薄膜晶体管的结构示意图；
图2是本发明开关管的制作方法的一实施方式的流程图；
图3是本发明开关管的制作过程的一实施方式的示意图；
图4是图2中对暴露的有源层以逐步降低蚀刻速度的方式进行蚀刻的一实施方式的流程图；
图5是本发明开关管的制作过程中对暴露的有源层以逐步降低蚀刻速度的方式进行蚀刻的一实施方式的示意图；
图6是图2中对暴露的有源层以逐步降低蚀刻速度的方式进行蚀刻的另一实施方式的流程图；
图7是图2中对暴露的有源层以逐步降低蚀刻速度的方式进行蚀刻的又一实施方式的流程图；
图8是本发明开关管的制作过程中对暴露的有源层以逐步降低蚀刻速度的方式进行蚀刻的另一实施方式的示意图；
图9是本发明开关管的蚀刻设备的一实施方式的结构示意图。
【具体实施方式】
下面将结合附图和实施方式对本发明进行详细描述。
参阅图2和图3，本发明开关管的制作方法的一实施方式中，包括步骤：
步骤101：在玻璃基板10上依次形成开关管的控制电极11、绝缘层12、有源层13以及源漏金属层14。
开关管为三端式控制开关，为了清楚表述本发明开关管的制作过程，结合图3所示的制作过程示意图进行说明。如图3所示，子步骤S11中，首先将玻璃基板10清洗干净并烘干后，在玻璃基板10上溅射一金属层，将该金属进行图案化处理以形成开关管的控制电极11。之后，在控制电极11上依次形成绝缘层12、有源层13以及源漏金属层14。其中，绝缘层12一般采用氮化硅，用于阻隔有源层13和控制电极11，使得开关管具有较高的输入电阻；有源层13主要是用于实现开关管的通电导通而断电断开的控制作用；源漏金属层14用于形成开关管的输入电极和输出电极，其一般采用铝合金、金属铝或金属铬制作。
步骤S102：将源漏金属层14进行图案化处理以暴露有源层13，并相应形成开关管的输入电极141和输出电极142。
对应图3的子步骤S12中，对源漏金属层14进行涂布光刻胶、曝光、蚀刻、剥离光刻胶等图案化工艺制程后，以相应形成开关管的输入电极141和输出电极142，并暴露出部分有源层13。本实施方式的有源层13具体包括邻近绝缘层12的非晶硅层（a-Si层）131和形成于非晶硅层131之上的n+非晶硅层（n+a-Si层）132，其中，非晶硅层131是开关管的核心层，开关管的电学特性和功能主要由这一层的质量决定，n+非晶硅层132是为了提高和改善非晶硅层131与输入电极141、输出电极142之间的欧姆结合而制作的半导体掺杂层。形成开关管的输入电极141和输出电极142后暴露相应的部分n+非晶硅层132。
其中，本实施方式的开关管可以是薄膜晶体管，开关管的控制电极11对应为薄膜晶体管的栅极，开关管的输入电极141和输出电极142对应为薄膜晶体管的源极和漏极。当然，开关管还可以是其他的三端式控制开关，如三极管等，此处不进行限定。
步骤S103：对暴露的有源层13以逐步降低蚀刻速度的方式进行蚀刻以形成开关管的沟道15。
对应于图3的子步骤S13，采用逐步降低蚀刻速度的方式对有源层13进行干法蚀刻，以形成开关管的沟道15。本实施方式中，采用等离子体干蚀刻方式对有源层13进行蚀刻。等离子体干蚀刻是以物理溅射为主并兼有化学反应的过程，其主要是利用有化学反应性气体产生具有化学活性的等离子体，使经过电场加速的高能等离子体轰击被蚀刻材料，以除去不需要的材料。
具体地，本实施方式对有源层13的干法蚀刻分两步进行，并且通过逐步降低等离子体的能量的方式来逐步降低蚀刻速度，参阅图4和图5，对暴露的有源层13以逐步降低蚀刻速度的方式进行蚀刻的具体步骤包括：
步骤S201：使用具有第一能量的等离子体蚀刻暴露的n+非晶硅层132以暴露非晶硅层131。
在步骤S102中对源漏金属层14进行图案化处理后暴露了有源层13中的n+非晶硅层132。对应于图5中的子步骤S21，本步骤S201为有源层13的第一次蚀刻，对暴露的n+非晶硅层132进行等离子体轰击以除去部分的n+非晶硅层132，从而暴露出位于对应除去的n+非晶硅层132之下的非晶硅层131。其中，除去n+非晶硅层132的等离子体具有第一能量。通过调整等离子体发生设备的相关参数，例如调整产生等离子体的功率密度参数，可使等离子体得到相应的轰击能量以蚀刻有源层13，而第一能量所对应的功率密度的范围可以为：上射频源（Source RF）功率密度范围在0.07~0.1W/cm2之间，例如可以是0.08W/cm2，而下射频源（Bias RF）功率密度范围在0.05~0.08W/cm2之间，例如可以是0.07W/cm2，具体地可根据实际需要进行调整，此处不进行限制。
步骤S202：使用具有第二能量的等离子体蚀刻暴露的非晶硅层131以除去部分非晶硅层131，第二能量小于第一能量，进而逐步降低蚀刻速度。
在步骤S201中完成对有源层13的第一次蚀刻之后，暴露出位于n+非晶硅层132之下的非晶硅层131，开始进行有源层13的第二次蚀刻。参阅图5中的子步骤S22，通过调整产生等离子体所需的功率密度参数，使蚀刻用的等离子体得到第二能量以对暴露的非晶硅层131进行第二次蚀刻，以除去部分非晶硅层131，从而形成开关管的沟道15。具体地，第二能量所对应的功率密度的范围可以为：上射频源功率密度范围在0.05~0.07W/cm2之间，例如可以是0.05W/cm2，而下射频源功率密度范围在0.03~0.05W/cm2之间，例如可以是0.04W/cm2，具体地可根据实际需要进行调整。其中，第二能量小于第一次蚀刻时的第一能量，从而逐步降低对有源层13的蚀刻速度，以避免第二次蚀刻时等离子体能量过高而对非晶硅层131造成损坏。而对于具有第二能量的等离子体，可通过减小等离子体发生设备在产生等离子体时所需的功率来获取。
举例而言，在对暴露的有源层13进行蚀刻之前，暴露的n+非晶硅层132的厚度为400埃，非晶硅层131的厚度为1300埃。等离子体发生设备为双射频源等离子体蚀刻设备。对有源层13进行第一次蚀刻时，即对暴露的n+非晶硅层132进行蚀刻，等离子体发生设备产生等离子体的上射频源功率为4000W，下射频源功率为3000W，从而使得产生的等离子体得到相应的第一能量，蚀刻时间设置为20秒，以保证n+非晶硅层132蚀刻干净，尽可能少的残留在非晶硅层131上。完成第一次蚀刻后，进行有源层13的第二次蚀刻，即蚀刻暴露的非晶硅层131。此时将等离子体发生设备产生等离子体的上射频源功率调整为3000W，下射频源功率调整为2500W，相对于第一次蚀刻时的功率有所减小，从而使得产生的等离子体的第二能量小于第一能量，进而使得第二次蚀刻的速度小于第一次蚀刻的速度。将第二次蚀刻的时间设置为15秒，在完成第二次蚀刻后，形成了开关管的沟道15，而残留的非晶硅层131的厚度也变为950埃左右。
当然，除了调整产生等离子体所需的功率参数以控制等离子体的能量外，还可以通过调整影响等离子体的能量的其他参数来控制等离子体能量，使等离子体的第二能量小于第一能量，具体的可根据实际情况进行选择。
通过上述方式，将有源层13的蚀刻分为两步进行，而不是一步完成，并且两步蚀刻中通过逐步减小产生等离子体所需的功率使第二次蚀刻的等离子体能量小于第一次蚀刻的等离子体能量，从而减小了第二次蚀刻时等离子体轰击非晶硅层131的能量，能够减少等离子体的能量过高而对非晶硅层131造成的损伤，提高了开关管的电性性能和可靠性。
此外，等离子体的浓度大小也会影响等离子体蚀刻的速度，对于逐步降低蚀刻速度，也可以采用逐步降低等离子体浓度的方式进行。具体为，参阅图6，并结合图5，对暴露的有源层13以逐步降低蚀刻速度的方式进行蚀刻的具体步骤包括：
步骤S301：使用具有第一浓度的等离子体蚀刻暴露的n+非晶硅层以暴露非晶硅层。
此步骤为对有源层13进行的第一次蚀刻，蚀刻用的等离子体的浓度为第一浓度，以对暴露的n+非晶硅层132进行蚀刻。
步骤S302：使用具有第二浓度的等离子体蚀刻暴露的非晶硅层以除去部分非晶硅层，第二浓度小于第一浓度，进而逐步降低所述蚀刻速度。
对有源层13进行第二次蚀刻，本实施方式中，降低等离子体的浓度，以使用比第一浓度更小的等离子体浓度蚀刻暴露的非晶硅层131。具体地，通过降低等离子体发生设备中产生等离子体的蚀刻气体的气体流量以此降低等离子体的浓度。等离子体的浓度降低，在进行有源层13的第二次蚀刻时，使得蚀刻速度比第一次蚀刻的蚀刻速度小。
除了采用降低蚀刻气体的气体流量来降低等离子体浓度外，本实施方式还可以通过降低产生等离子体的腔体压力来降低等离子体的浓度，使第二浓度小于第一浓度，此处不进行具体限制。
本实施方式在对有源层13进行两步蚀刻的过程中，通过降低蚀刻气体的气体流量来降低等离子体的浓度，使第二浓度小于第一浓度，以逐步降低蚀刻有源层13的速度，能够减小对非晶硅层131的损伤，提高开关管的电性性能。
在上述实施方式中，对有源层13的干法蚀刻分两步进行，在这两步蚀刻步骤的过程中，在进行第二步蚀刻（即对有源层13的第二次蚀刻）可以通过降低等离子体的能量或降低等离子体的浓度来实现逐步降低蚀刻速度，也可以通过同时降低等离子体的能量和等离子体的浓度来实现，对此不进行具体限制。在另一实施方式中，也可以分三步步骤进行蚀刻。具体地，参阅图7和图8，在对暴露的有源层23以逐步降低蚀刻速度的方式进行蚀刻的过程中，包括步骤：
步骤S401：使用具有第一能量的等离子体蚀刻暴露的n+非晶硅层232以暴露非晶硅层231。
此步骤为有源层23的第一次蚀刻，对应于图7的子步骤S31，主要是除去n+非晶硅层232，从而暴露出非晶硅层231。
步骤S402：使用具有第二能量的等离子体蚀刻暴露的非晶硅层231以除去部分非晶硅层231，第二能量小于第一能量。
完成第一次蚀刻后，通过等离子体发生设备获得具有第二能量的等离子体对非晶硅层231进行蚀刻以除去部分的非晶硅层231，如图7中的子步骤S32所示一样。并且，调整等离子体发生设备的相关参数，减小产生等离子体所需的功率，使第二能量小于第一能量，以减小蚀刻速度。
步骤S403：使用具有第三能量的等离子体蚀刻部分剩余的非晶硅层231以除去剩余的部分非晶硅层231，第三能量小于第二能量，进而逐步降低蚀刻速度。
本步骤为对有源层23的第三蚀刻，对应于图7的子步骤S33，即过蚀刻剩余的非晶硅层231以除去剩余的部分非晶硅层231，从而形成开关管的沟道24。其中，本实施方式中，在完成步骤S302的第二次蚀刻之后，再次减小等离子体发生设备产生等离子体所需的功率，以获得具有第三能量的等离子体，使得第三能量小于第二能量，进而减小等离子体轰击剩余的非晶硅层231的能量，由此能够减小对非晶硅层231的损伤，提高开关管的可靠性。
当然，在上述三个步骤中，也可以通过逐步降低等离子体的浓度以逐步降低蚀刻速度，每个步骤中采用的等离子体浓度不相同，且后一步骤中的等离子体浓度小于前一步骤中的等离子体浓度，具体的实现方式可参考上述实施方式进行，在此不进行一一赘述。
此外，上述三个步骤中，也可以同时降低等离子体能量和等离子体浓度来逐步降低蚀刻速度，，对此也不进行具体限制。
参阅图9，本发明还提供开关管的蚀刻设备的一实施方式，其中，本实施方式的开关管为上述各实施方式所述的开关管，蚀刻设备用于在开关管的制作过程中对开关管的有源层进行蚀刻。
具体地，结合图3所示的开关管，蚀刻设备包括蚀刻装置41和控制装置42。蚀刻装置41用于对开关管的有源层13进行蚀刻以形成开关管的沟道16，控制装置42用于控制蚀刻装置41的蚀刻速度，以使得蚀刻装置41以逐步降低蚀刻速度的方式对有源层13进行蚀刻。其中，有源层13包括非晶硅层131和n+非晶硅层132。控制装置42具体用于控制蚀刻装置41产生具有第一能量的等离子体，以使用具有第一能量的等离子体蚀刻n+非晶硅层132，从而暴露非晶硅层131。在暴露非晶硅层131之后，控制装置42具体用于控制蚀刻装置41产生具有第二能量的等离子体，以使用具有第二能量的等离子体蚀刻暴露的非晶硅层131，以除去部分非晶硅层。并且，使第二能量小于第一能量，进而逐步降低蚀刻速度。
进一步地，控制装置42包括第一控制模块421，第一控制模块421用于控制蚀刻装置41产生等离子体所需的功率。在蚀刻完n+非晶硅层132之后，第一控制模块421控制蚀刻装置41减小产生等离子体所需的功率，以使得蚀刻装置41产生具有第二能量的等离子体，并使得第二能量小于第一能量，从而降低蚀刻速度。
当然，还可以通过控制蚀刻装置41所产生的等离子体的浓度来逐步降低蚀刻速度。此时，控制装置42还包括第二控制模块422，第二控制模块422用于控制蚀刻装置41产生的等离子体的浓度。在蚀刻完n+非晶硅层132之后，第二控制模块422控制蚀刻装置41减小等离子体的浓度，以使得蚀刻装置41产生具有第二浓度的等离子体，并使得第二浓度小于第一浓度，从而降低蚀刻速度。
通过上述方式，本实施方式的开关管的蚀刻设备对开关管的有源层13以逐步降低蚀刻速度的方式进行蚀刻，能够降低对非晶硅层131的损伤，进而提高开关管的电性性能和可靠性。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (16)

  1. 一种开关管的制作方法，其中，包括：
    在玻璃基板上依次形成开关管的控制电极、绝缘层、有源层以及源漏金属层；
    将所述源漏金属层进行图案化处理以暴露有源层，并相应形成所述开关管的输入电极和输出电极；
    对暴露的有源层以逐步降低蚀刻速度的方式进行蚀刻以形成开关管的沟道；
    其中，所述蚀刻为等离子体干蚀刻，所述开关管为薄膜晶体管，所述开关管的控制电极对应为薄膜晶体管的栅极，所述开关管的输入电极和输出电极分别对应为薄膜晶体管的源极和漏极。
  2. 根据权利要求1所述的方法，其中，
    所述有源层包括邻近所述绝缘层的非晶硅层以及形成于所述非晶硅层之上的n+非晶硅层；
    所述将所述源漏金属层进行图案化处理以暴露有源层的步骤包括：
    将所述源漏金属层进行图案化处理以暴露所述n+非晶硅层。
  3. 根据权利要求2所述的方法，其中，
    所述对暴露的有源层以逐步降低蚀刻速度的方式进行蚀刻的步骤包括：
    使用具有第一能量的等离子体蚀刻暴露的n+非晶硅层以暴露非晶硅层；
    使用具有第二能量的等离子体蚀刻暴露的非晶硅层以除去部分所述非晶硅层，所述第二能量小于第一能量，进而逐步降低所述蚀刻速度。
  4. 根据权利要求3所述的方法，其中，
    所述使用具有第二能量的等离子体蚀刻暴露的非晶硅层的步骤包括：
    减小产生等离子体所需的功率以使用具有第二能量的等离子体蚀刻暴露的非晶硅层。
  5. 根据权利要求2所述的方法，其中，
    所述对暴露的有源层以逐步降低蚀刻速度的方式进行蚀刻的步骤包括：
    使用具有第一浓度的等离子体蚀刻暴露的n+非晶硅层以暴露非晶硅层；
    使用具有第二浓度的等离子体蚀刻暴露的非晶硅层以除去部分所述非晶硅层，所述第二浓度小于第一浓度，进而逐步降低所述蚀刻速度。
  6. 根据权利要求5所述的方法，其中，
    所述使用具有第二浓度的等离子体蚀刻暴露的非晶硅层以除去部分所述非晶硅层的步骤包括：
    降低产生等离子体的蚀刻气体的气体流量以使用具有第二浓度的等离子体蚀刻暴露的非晶硅层。
  7. 一种开关管的制作方法，其中，包括：
    在玻璃基板上依次形成开关管的控制电极、绝缘层、有源层以及源漏金属层；
    将所述源漏金属层进行图案化处理以暴露有源层，并相应形成所述开关管的输入电极和输出电极；
    对暴露的有源层以逐步降低蚀刻速度的方式进行蚀刻以形成开关管的沟道。
  8. 根据权利要求7所述的方法，其中，
    所述有源层包括邻近所述绝缘层的非晶硅层以及形成于所述非晶硅层之上的n+非晶硅层；
    所述将所述源漏金属层进行图案化处理以暴露有源层的步骤包括：
    将所述源漏金属层进行图案化处理以暴露所述n+非晶硅层。
  9. 根据权利要求8所述的方法，其中，
    所述对暴露的有源层以逐步降低蚀刻速度的方式进行蚀刻的步骤包括：
    使用具有第一能量的等离子体蚀刻暴露的n+非晶硅层以暴露非晶硅层；
    使用具有第二能量的等离子体蚀刻暴露的非晶硅层以除去部分所述非晶硅层，所述第二能量小于第一能量，进而逐步降低所述蚀刻速度。
  10. 根据权利要求9所述的方法，其中，
    所述使用具有第二能量的等离子体蚀刻暴露的非晶硅层的步骤包括：
    减小产生等离子体所需的功率以使用具有第二能量的等离子体蚀刻暴露的非晶硅层。
  11. 根据权利要求8所述的方法，其中，
    所述对暴露的有源层以逐步降低蚀刻速度的方式进行蚀刻的步骤包括：
    使用具有第一浓度的等离子体蚀刻暴露的n+非晶硅层以暴露非晶硅层；
    使用具有第二浓度的等离子体蚀刻暴露的非晶硅层以除去部分所述非晶硅层，所述第二浓度小于第一浓度，进而逐步降低所述蚀刻速度。
  12. 根据权利要求11所述的方法，其中，
    所述使用具有第二浓度的等离子体蚀刻暴露的非晶硅层以除去部分所述非晶硅层的步骤包括：
    降低产生等离子体的蚀刻气体的气体流量以使用具有第二浓度的等离子体蚀刻暴露的非晶硅层。
  13. 一种开关管的蚀刻设备，所述蚀刻设备用于在开关管的制作过程中对开关管的有源层进行蚀刻，其中，包括：
    蚀刻装置，用于对开关管的有源层进行蚀刻以形成所述开关管的沟道；
    控制装置，用于控制所述蚀刻装置的蚀刻速度，以使所述蚀刻装置以逐步降低蚀刻速度的方式对有源层进行蚀刻。
  14. 根据权利要求13所述的设备，其中，
    所述有源层包括非晶硅层以及形成于所述非晶硅层之上的n+非晶硅层；
    所述控制装置具体用于控制所述蚀刻装置产生具有第一能量的等离子体，以使用所述具有第一能量的等离子体蚀刻n+非晶硅层，以暴露所述非晶硅层；
    在暴露所述非晶硅层之后，所述控制装置具体用于控制所述蚀刻装置产生具有第二能量的等离子体，以使用所述具有第二能量的等离子体蚀刻所述暴露的非晶硅层，以除去部分非晶硅层，所述第二能量小于第一能量，进而逐步降低所述蚀刻速度。
  15. 根据权利要求14所述的设备，其中，
    所述控制装置包括第一控制模块，所述第一控制模块用于控制所述蚀刻装置产生等离子体所需的功率，以使得所述蚀刻装置产生不同能量的等离子体。
  16. 根据权利要求13所述的设备，其中，
    所述有源层包括非晶硅层以及形成于所述非晶硅层之上的n+非晶硅层；
    所述控制装置具体用于控制所述蚀刻装置产生具有第一浓度的等离子体，以使用所述具有第一浓度的等离子体蚀刻n+非晶硅层，以暴露所述非晶硅层；
    在暴露所述非晶硅层之后，所述控制装置具体用于控制所述蚀刻装置产生具有第二浓度的等离子体，以使用所述具有第二浓度的等离子体蚀刻所述暴露的非晶硅层，以除去部分非晶硅层，所述第二浓度小于第一浓度，进而逐步降低所述蚀刻速度。
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