WO2014067100A1 - 一种发射机、接收机及射频收发方法 - Google Patents

一种发射机、接收机及射频收发方法 Download PDF

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Publication number
WO2014067100A1
WO2014067100A1 PCT/CN2012/083855 CN2012083855W WO2014067100A1 WO 2014067100 A1 WO2014067100 A1 WO 2014067100A1 CN 2012083855 W CN2012083855 W CN 2012083855W WO 2014067100 A1 WO2014067100 A1 WO 2014067100A1
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WIPO (PCT)
Prior art keywords
signal
phase
amplitude
error
pulse signal
Prior art date
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PCT/CN2012/083855
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English (en)
French (fr)
Inventor
罗讯
马骏
Original Assignee
华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2012/083855 priority Critical patent/WO2014067100A1/zh
Priority to CN201280003511.8A priority patent/CN103430456B/zh
Priority to EP12887608.3A priority patent/EP2906000B1/en
Priority to ES12887608.3T priority patent/ES2597079T3/es
Publication of WO2014067100A1 publication Critical patent/WO2014067100A1/zh
Priority to US14/699,823 priority patent/US9264279B2/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/36—Modulator circuits; Transmitter circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/0002—Modulated-carrier systems analog front ends; means for connecting modulators, demodulators or transceivers to a transmission line
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/38—Demodulator circuits; Receiver circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B2001/0408—Circuits with power amplifiers

Definitions

  • the present invention relates to the field of wireless communication technologies, and in particular, to a transmitter, a receiver, and a radio frequency transceiver.
  • the radio frequency circuit is generally responsible for transmitting or receiving a radio frequency signal
  • the baseband chip is generally responsible for performing a series of processing on the radio frequency signal, for example: at the transmitter
  • the baseband chip can compile the audio signal into a radio frequency signal for transmission; at the receiver, the baseband chip can interpret the received radio frequency signal into an audio signal.
  • the baseband chip also has signal processing functions such as compiling/interpreting address information, text information, and picture information.
  • the baseband chip also has an important function: through a series of complex algorithms, carrier recovery, carrier generation, etc. are performed on the signals flowing through the RF circuit to correct the error of the signal, thereby ensuring the RF transmitted/received by the RF circuit.
  • the accuracy of the signal E.g:
  • a radio frequency circuit architecture in the prior art in which a receiver and a transmitter are integrated and connected to a same baseband chip, so that the baseband chip pair flows through the receiver and the transmitter.
  • the signal performs processing such as carrier recovery and carrier generation.
  • the basic processing flow of carrier recovery for the baseband chip wherein: the baseband chip obtains the phase error according to the error obtained by the phase detector, and then passes the loop filter and the digital oscillator. After the corresponding algorithm is processed, the phase signal with the error corrected is output.
  • the baseband chip In order to improve the efficiency of the transceiver, it is necessary to improve the spectral efficiency of the RF circuit, and improving the modulation mode is a main way to improve the spectrum efficiency.
  • the modulation mode for example: 3 ⁇ 4 port: Increased by 64QAM (Quadature Amplitude Modulation) to 1024QAM
  • the baseband chip also needs to add components to ensure that the functions of carrier recovery and carrier generation can work normally.
  • Mode to normal operation a viable option only integrate more elements on the baseband chip, for example: In the 64QAM scenario, the baseband chip requires 26 gates, and in 1024QAM scenario would require 2 1Q gates.
  • the number of required gate circuits is more exponentially increased, which is not achievable in industrial manufacturing.
  • the components that need to be added on a baseband chip are not only gate circuits, but also other components in the baseband chip, which need to be multiplied, cost hugely, and due to the increase of components.
  • the power consumption of the baseband chip during operation is also large.
  • Embodiments of the present invention provide a transmitter, a receiver, and a radio frequency transceiver method, which can perform carrier recovery and carrier generation at a front end of a radio frequency circuit, so that the baseband chip does not have to undertake the functions of carrier recovery and carrier generation, thereby reducing the baseband chip. Operating costs.
  • an embodiment of the present invention provides a receiver, including:
  • Receive antenna front-end frequency conversion module, amplitude detector, amplitude code generator, error matrix correction tool, wherein:
  • the front-end frequency conversion module obtains a radio frequency signal from the receiving antenna, and the front-end frequency conversion module converts the acquired radio frequency signal into an intermediate frequency analog signal, and then sends the intermediate frequency analog signal to the identifier, the front-end frequency conversion
  • the module includes: a low noise amplifier, a downconverting mixer, and a gain control amplifier;
  • the amplitude detector is connected to the front end frequency conversion module, and the amplitude detector generates a first signal amplitude pulse signal according to the intermediate frequency analog signal sent by the front end frequency conversion module, and then sends the first signal amplitude pulse signal to the Amplitude code generator
  • the amplitude code generator is coupled to the amplitude detector, the amplitude code generator converting the first signal amplitude pulse signal into a first signal amplitude digital code, and transmitting the first signal amplitude digital code to The error matrix error corrector;
  • the error matrix error corrector is connected to the amplitude detector, and the error matrix error corrector generates an amplitude error correction control signal according to the first signal amplitude digital code, and then sends the amplitude error correction control signal To the discriminator;
  • the amplitude detector performs error correction on the first signal amplitude pulse signal according to the amplitude error correction control signal to generate a second signal amplitude pulse signal;
  • the amplitude code generator converts the second signal amplitude pulse signal into a second signal amplitude digital code, such that the receiver digitally encodes the second signal amplitude as a signal after carrier recovery and carrier generation Amplitude digital coding.
  • the receiver further includes: a phase detector, a phase code generator, wherein: the phase detector is connected to the front end frequency conversion module, and the phase detector is configured according to the intermediate frequency analog signal sent by the front end frequency conversion module Generating a first signal phase pulse signal, and transmitting the first signal phase pulse signal to the phase code generator;
  • the phase code generator is coupled to the phase detector, the phase code generator converting the first signal phase pulse signal into a first signal phase digital code, and transmitting the first signal phase digital code to The error matrix error corrector;
  • the error matrix corrector is connected to the phase detector, and the error matrix error corrector generates a phase error correction control signal according to the first signal phase digital code, and then sends the phase error correction control signal To the phase detector;
  • the phase detector performs error correction on the first signal phase pulse signal according to the phase error correction control signal to generate a second signal phase pulse signal;
  • the phase code generator converts the second signal phase pulse signal into a second signal phase digital code, so that the receiver digitally encodes the second signal phase as a signal after carrier recovery and carrier generation Phase digital coding.
  • a transmitter including:
  • Downconverting mixer Downconverting mixer, amplitude detector, amplitude code generator, error matrix corrector, local oscillator frequency source, where: The downconverting mixer is connected to the local oscillator frequency source, and converts the radio frequency signal to be transmitted obtained from the local oscillator frequency source into an intermediate frequency analog signal, and then sends the intermediate frequency analog signal to the amplitude correction signal.
  • the downconverting mixer is connected to the local oscillator frequency source, and converts the radio frequency signal to be transmitted obtained from the local oscillator frequency source into an intermediate frequency analog signal, and then sends the intermediate frequency analog signal to the amplitude correction signal.
  • the amplitude detector is connected to the downconverting mixer, and the edge detector generates a first signal amplitude pulse signal according to the intermediate frequency analog signal sent by the downconverting mixer, and then the first signal amplitude pulse Sending a signal to the amplitude code generator;
  • the amplitude code generator is coupled to the amplitude detector, the amplitude code generator converting the first signal amplitude pulse signal into a first signal amplitude digital code, and transmitting the first signal amplitude digital code to The error matrix error corrector;
  • the error matrix error corrector is connected to the amplitude detector, and the error matrix error corrector generates an amplitude error correction control signal according to the first signal amplitude digital code, and then sends the amplitude error correction control signal To the discriminator;
  • the amplitude detector performs error correction on the first signal amplitude pulse signal according to the amplitude error correction control signal to generate a second signal amplitude pulse signal;
  • the amplitude code generator converts the second signal amplitude pulse signal into a second signal amplitude digital code, such that the receiver digitally encodes the second signal amplitude as a signal after carrier recovery and carrier generation Amplitude digital coding.
  • the receiver further includes: a phase detector, a phase code generator, wherein: the phase detector is connected to the downconverting mixer, and the phase detector is configured according to the downconverting mixer Transmitting the intermediate frequency analog signal to generate a first signal phase pulse signal, and transmitting the first signal phase pulse signal to the phase code generator;
  • the phase code generator is coupled to the phase detector, the phase code generator converting the first signal phase pulse signal into a first signal phase digital code, and transmitting the first signal phase digital code to The error matrix error corrector;
  • the error matrix corrector is connected to the phase detector, and the error matrix error corrector generates a phase error correction control signal according to the first signal phase digital code, and then sends the phase error correction control signal To the phase detector;
  • the phase detector performs error correction on the first signal phase pulse signal according to the phase error correction control signal to generate a second signal phase pulse signal;
  • an embodiment of the present invention provides a radio frequency signal receiving method, including: receiving, by a receiver, a radio frequency signal, and converting the obtained radio frequency signal into an intermediate frequency analog signal; generating a first signal amplitude pulse according to the intermediate frequency analog signal Signal
  • an embodiment of the present invention provides a method for transmitting a radio frequency signal, including: The transmitter converts the RF signal to be transmitted into an intermediate frequency analog signal;
  • the second signal phase pulse signal is converted to a second signal phase digital code such that the receiver digitally encodes the second signal phase as a signal phase digital coded after carrier recovery and carrier generation.
  • the transmitter, the receiver, and the radio frequency transceiver method provided by the embodiments of the present invention can implement the functions of carrier recovery and carrier generation in the radio circuit part of the receiver.
  • the baseband chip does not need to perform carrier recovery and carrier.
  • the generation does not have to bear the function of computing power consumption such as frequency offset suppression and phase noise suppression related to carrier recovery, thereby perfecting the function of the baseband chip, reducing the power consumption of the baseband chip, and since the baseband chip does not have to bear the carrier recovery again.
  • Carrier generation This function of performing complex computational processes reduces the process complexity and design difficulty of manufacturing baseband chips, which directly reduces the manufacturing cost of the baseband chip and further reduces the operation/use cost of the baseband chip.
  • FIG. 1a is a schematic diagram of a structure of a transceiver in the prior art
  • FIG. 1b is a schematic diagram of a working process of a baseband chip in the prior art
  • FIG. 2a is a schematic structural diagram of a receiver provided in Embodiment 1 of the present invention
  • FIG. 2 is a schematic structural diagram of a receiver according to Embodiment 1 of the present invention
  • FIG. 2 is a schematic structural diagram of a receiver according to Embodiment 1 of the present invention
  • FIG. 3 is a schematic structural diagram of a transmitter according to Embodiment 2 of the present invention
  • FIG. 3b is another schematic structural diagram of a transmitter according to Embodiment 2 of the present invention
  • 2 is a schematic structural diagram of a transmitter provided in FIG.
  • FIG. 4a is a flowchart of a method for receiving a radio frequency signal according to Embodiment 3 of the present invention
  • FIG. 4b is another embodiment of a radio frequency signal receiving method according to Embodiment 3 of the present invention
  • FIG. 4 is a flowchart of a radio frequency signal receiving method according to Embodiment 3 of the present invention
  • FIG. 5 a is a flowchart of a radio frequency signal transmitting method according to Embodiment 4 of the present invention
  • b is the invention Another flow chart of the radio frequency signal transmitting method provided by the fourth embodiment;
  • FIG. 4a is a flowchart of a method for receiving a radio frequency signal according to Embodiment 3 of the present invention
  • FIG. 4b is another embodiment of a radio frequency signal receiving method according to Embodiment 3 of the present invention
  • FIG. 4 is a flowchart of a radio frequency signal receiving method according to Embodiment 3 of the present invention
  • FIG. 5 a is a flowchart of
  • 5 c is still another flowchart of the radio frequency signal transmitting method according to Embodiment 4 of the present invention
  • 6 a is a schematic structural diagram of a radio frequency signal transceiving system according to Embodiment 5 of the present invention
  • FIG. 6 b is a schematic structural diagram of a specific example of a radio frequency circuit provided by the present invention
  • FIG. 6 c is another radio frequency provided by the present invention.
  • FIG. 6 is a schematic structural diagram of a specific example of a radio frequency circuit provided by the present invention.
  • Embodiment 1 The receiver described in this embodiment includes: a receiving antenna, a front-end frequency conversion module, an amplitude detector, an amplitude code generator, an error matrix error corrector, a power divider, an up-conversion mixer, and a local oscillator.
  • Frequency source, frequency source phase code generator where:
  • the front end frequency conversion module is configured to acquire a radio frequency signal from the receiving antenna, convert the obtained radio frequency signal into an intermediate frequency analog signal, and send the intermediate frequency analog signal to the edge detector, the front end frequency conversion module Includes: Low noise amplifier, downconverting mixer, gain control amplifier.
  • the amplitude detector is connected to the front end frequency conversion module, configured to generate a first signal amplitude pulse signal according to the intermediate frequency analog signal sent by the front end frequency conversion module, and then send the first signal amplitude pulse signal to the amplitude Code generator.
  • the amplitude code generator is connected to the amplitude detector for converting the first signal amplitude pulse signal as a pulse signal into a first signal amplitude digital code as a digital signal, and then the first signal An amplitude digital code is sent to the error matrix error corrector, the amplitude coded
  • the generator is an encoder for converting a pulse signal into a digital signal.
  • the error matrix corrector is connected to the amplitude detector and the amplitude code generator, and configured to generate an amplitude error correction control signal according to the first signal amplitude digital code, and then perform the amplitude error correction control A signal is sent to the discriminator.
  • the amplitude detector is configured to perform error correction on the first signal amplitude pulse signal according to the amplitude error correction control signal to generate a second signal amplitude pulse signal.
  • the amplitude code generator is further configured to convert the second signal amplitude pulse signal into a second signal amplitude digital code, so that the receiver digitally encodes the second signal amplitude as carrier recovery and carrier The resulting signal amplitude is digitally encoded.
  • phase detector is connected to the front end frequency conversion module, configured to generate a first signal phase pulse signal according to the intermediate frequency analog signal sent by the front end frequency conversion module, and then send the first signal phase pulse signal to The phase code generator.
  • the phase code generator is connected to the phase detector for converting the first signal phase pulse signal as a pulse signal into a first signal phase digital code as a digital signal, and the first signal
  • the phase digital code is sent to the error matrix error corrector, which is an encoder for converting a pulse signal into a digital signal.
  • the error matrix corrector is connected to the phase detector and connected to the phase code generator for generating a phase error correction control signal according to the first signal phase digital code, and then correcting the phase A control signal is sent to the phase detector.
  • the phase detector is configured to perform error correction on the first signal phase pulse signal according to the phase error correction control signal to generate a second signal phase pulse signal.
  • the phase code generator is further configured to convert the second signal phase pulse signal into a second signal phase digital code, so that the receiver digitally encodes the second signal as carrier recovery and carrier The generated signal phase digital code.
  • the power splitter is connected to the front end frequency conversion module, the amplitude detector and the phase detector, and configured to receive the intermediate frequency analog signal sent by the front end frequency conversion module, and divide the intermediate frequency analog signal into For two identical intermediate frequency analog signals, the two identical intermediate frequency analog signals are respectively separated.
  • the phase detector Sending to the identifier and the phase detector, so that the identifier generates the first signal amplitude pulse signal according to one of the intermediate frequency analog signals sent by the power splitter, the phase detector is configured according to The other intermediate frequency analog signal sent by the power splitter generates the first signal phase pulse signal.
  • the upconverting mixer is connected to the front end frequency conversion module, and is configured to upconvert an intermediate frequency analog signal sent by the front end frequency conversion module to generate another radio frequency signal.
  • the frequency source phase detector is connected to the local oscillator frequency source and the upconversion mixer, and configured to be used according to the radio frequency signal generated by the upconversion mixer and the radio frequency signal output by the local oscillator frequency source , perform phase error judgment and obtain a phase error analog signal of the local oscillator frequency source.
  • the frequency source phase code generator is connected to the frequency source phase detector for receiving the local frequency source phase error analog signal, and converting the local frequency source phase error analog signal into a local oscillator frequency Source phase error digital coding.
  • the error matrix error corrector is connected to the frequency source phase code generator for receiving the phase error digital code of the local oscillator frequency source, and generating error correction control according to the local frequency frequency source digital code of the local oscillator frequency source signal.
  • the local oscillator frequency source and the error matrix corrector are configured to receive the error correction control signal sent by the error matrix error corrector, and the local oscillator according to the error correction control signal Signal phase digital coding for error correction.
  • the upconverting mixer is coupled to the gain control amplifier of the front end variable frequency module, and the downconverting mixer of the front end variable frequency module is coupled to the frequency source phase detector.
  • the method may include: a receiving antenna 21, a front end variable frequency module 22, an amplitude detector 23, an amplitude code generator 24, and an error matrix corrector 25, wherein:
  • the front end frequency conversion module 22 acquires a radio frequency signal from the receiving antenna 21, and the front end frequency conversion module 22 converts the acquired radio frequency signal into an intermediate frequency analog signal, and then sends the intermediate frequency analog signal to the amplitude detector 23.
  • the front end conversion module 22 includes: a low noise amplifier 221, a down conversion mixer 222, and a gain control amplifier 223.
  • the amplitude detector 23 is connected to the front end frequency conversion module 22, and the amplitude detector 23 generates a first signal amplitude pulse signal according to the intermediate frequency analog signal sent by the front end frequency conversion module 22, and then the first signal amplitude pulse A signal is sent to the amplitude code generator 24.
  • the amplitude code generator 24 is connected to the amplitude detector 23, and the amplitude code generator 24 converts the first signal amplitude pulse signal into a first signal amplitude digital code, and then the first signal amplitude number The code is sent to the error matrix corrector 25.
  • the error matrix corrector 25 is connected to the amplitude detector 23, and the error matrix error corrector 25 generates an amplitude error correction control signal according to the first signal amplitude digital code, and then corrects the amplitude.
  • a control signal is sent to the amplitude detector 23.
  • the amplitude detector 23 performs error correction on the first signal amplitude pulse signal according to the amplitude error correction control signal to generate a second signal amplitude pulse signal.
  • the amplitude code generator 24 converts the second signal amplitude pulse signal into a second signal amplitude digital code, so that the receiver digitally encodes the second signal amplitude as carrier recovery and carrier generation. Signal amplitude digital coding.
  • the error matrix error corrector can error correct the error of the digital code generated in the transmitter/receiver.
  • the digital coding error in the receiver mainly causes the following: In the hardware link of the transmitter that performs data communication with the receiver, the transmission of the electrical signal has a certain probability of deviation, so that the receiver receives according to the received The digital code generated by the signal generates an error; the error generated during the spatial transmission of the wireless communication; in the hardware link of the receiver, the transmission of the electrical signal has a certain probability of deviation, thereby causing digital coding in the receiver Error.
  • the main causes of the error in the digital coding in the transmitter include: In the hardware link of the transmitter, the transmission of the electrical signal has a certain probability of generating a deviation, thereby causing an error in the digital coding in the transmitter.
  • the error matrix corrector in the receiver and the transmitter can be the same.
  • a standard signal source such as a standard signal amplitude digital error matrix, a signal phase digital error matrix, a frequency source phase digital error matrix, and the like may be pre-stored, such as: Standard QAM code source.
  • Technician can pre-exist error matrix correction In order to facilitate the error matrix corrector to compare the standard data with the signal amplitude digital code received by the receiver or generated by the transmitter, the signal phase digital code, and the frequency source phase digital code, and output the signal amplitude Digital error, signal phase digital error, frequency source phase digital error.
  • signal amplitude digital error, signal phase digital error, frequency source phase digital error can have many forms, such as:
  • Pre-stored standard signal amplitude digital code in the A-segment character is 1010, and the receiver receives according to The signal amplitude of the RF signal is analyzed.
  • the A-segment character in the digital code is 1011.
  • the process of analyzing the signal amplitude digital coding, the signal phase digital coding, the local frequency source phase error digital coding, and obtaining the corresponding error correction control signal may be various, and the following examples are provided. Explain the preferred options:
  • Figure 2d shows the error code matrix error corrector for signal amplitude digital coding, signal phase digital coding, and local oscillator frequency source phase error digital coding in the RF circuit of the receiver or transmitter in the 64Q AM scenario.
  • the analysis process carried out carried out.
  • the square marked with a diagonal line indicates the standard code source corresponding to the digital code of the signal amplitude
  • the square marked with the grid indicates the standard code source corresponding to the digital code of the signal phase, which is marked with the all black square. It is a standard code source corresponding to the phase error digital code of the local oscillator frequency source.
  • These standard code sources may be standard Q AM code sources pre-existing in the error matrix error corrector, and these standard Q AM code sources have been disclosed. In existing protocols, technicians can be aware of these standard QAM code sources directly from the protocol.
  • the error matrix error corrector can compare the signal amplitude digital code and the standard QAM code in the RF circuit by using existing technical means, such as through a comparator.
  • the signal amplitude digital coding in the source that is, the error matrix error corrector can compare the signal amplitude digital code in the RF circuit with the data corresponding to the hatched square shown in FIG. 2d, and pass the binary of the cartridge Addition and subtraction to get the difference between the two. Then, through the ⁇ modulator, the corresponding signal amplitude error correction control analog signal is output according to the obtained difference value.
  • the signal amplitude error correction output of the error matrix error corrector controls the analog signal to be transmitted to the amplitude detector, and the amplitude detector can correct the digital code of the signal amplitude. And the above error correction process can be repeated multiple times to ensure that the signal amplitude digital coding is correct.
  • the error matrix error corrector for signal phase digital coding and local oscillator frequency source phase error digital coding can be processed through the above process. That is, in the embodiment of the present invention, the error matrix corrector can perform the above process on the receiver, the transmitter or the transceiver (as shown in FIG. 6b, FIG. 6c or FIG. 6d, the radio circuit with integrated receiving and transmitting functions) In the signal amplitude digital coding, signal phase digital coding and local oscillator frequency source phase error digital coding for error correction.
  • the error correction process described above may be adopted for scenarios such as 1024QAM, 2048QAM, and 4096QAM, thereby implementing carrier recovery and carrier generation in scenarios such as 1024QAM, 2048QAM, and 4096QAM.
  • the structure of the RF circuit does not change, and it can be manufactured by existing industrial production equipment.
  • the receiver described in this embodiment may further include: a phase detector 26, a phase code generator 27, and a power divider 28, wherein:
  • the phase detector 26 is connected to the front end frequency conversion module 22, and configured to generate a first signal phase pulse signal according to the intermediate frequency analog signal sent by the front end frequency conversion module 22, and then send the first signal phase pulse signal to The phase code generator 27.
  • the phase code generator 27 is connected to the phase detector 26 for converting the first signal phase pulse signal as a pulse signal into a first signal phase digital code as a digital signal, and A signal phase digital code is sent to the error matrix error corrector 25, which is an encoder for converting a pulse signal into a digital signal.
  • the error matrix corrector 25 is connected to the phase detector 26 and connected to the phase code generator 27 for generating a phase error correction control signal according to the first signal phase digital code, and then A phase error correction control signal is sent to the phase detector 26.
  • the phase detector 26 is configured to perform error correction on the first signal phase pulse signal according to the phase error correction control signal to generate a second signal phase pulse signal.
  • the phase code generator 27 is further configured to convert the second signal phase pulse signal into a second signal phase digital code, so that the receiver digitally encodes the second signal as carrier recovery and The signal phase digital coded after carrier generation.
  • the power splitter 28 is connected to the front end variable frequency module 22, the amplitude detector 23 and the phase detector 26, and configured to receive the intermediate frequency analog signal sent by the front end variable frequency module 22, and
  • the intermediate frequency analog signal is divided into two identical intermediate frequency analog signals, and the two identical intermediate frequency analog signals are respectively sent to the amplitude detector 23 and the phase detector 26, so that the amplitude detector 23 is One of the intermediate frequency analog signals sent by the power splitter 28 generates the first signal amplitude pulse signal, and the phase detector 26 generates the first signal phase according to another intermediate frequency analog signal sent by the power splitter 28. Pulse signal.
  • the phase detector 26 is connected to the front end frequency conversion module 22, and the phase detector 26 generates a first signal phase pulse signal according to the intermediate frequency analog signal sent by the front end frequency conversion module 22, The first signal phase pulse signal is then sent to the phase code generator 27.
  • the phase code generator 27 is connected to the phase detector 26, and the phase code generator 27 converts the first signal phase pulse signal into a first signal phase digital code, and then the first signal phase number The code is sent to the error matrix corrector 25.
  • the error matrix corrector 25 is connected to the phase detector 26, and the error matrix error corrector 25 generates a phase error correction control signal according to the first signal phase digital code, and then corrects the phase. A control signal is sent to the phase detector 26.
  • the phase detector 26 performs error correction on the first signal phase pulse signal according to the phase error correction control signal to generate a second signal phase pulse signal.
  • the phase code generator 27 converts the second signal phase pulse signal into a second signal phase digital code, so that the receiver digitally encodes the second signal phase as carrier recovery and carrier generation. Signal phase digital coding.
  • the power splitter 28 is connected to the front end variable frequency module 22, the amplitude detector 23, and the phase detector 26, and the power splitter 28 receives the intermediate frequency analog signal sent by the front end variable frequency module 22, And dividing the intermediate frequency analog signal into two identical intermediate frequency analog signals, and then sending the two identical intermediate frequency analog signals to the amplitude detector 23 and the phase detector 26 respectively, so as to facilitate the amplitude discrimination
  • the device 23 generates the first signal amplitude pulse signal according to one of the intermediate frequency analog signals, and causes the phase detector 26 to simultaneously generate the first signal phase pulse signal according to another intermediate frequency analog signal therein.
  • the receiver in this embodiment may further include: an up-converting mixer 29, a local oscillator frequency source 210, a frequency source phase detector 211, and a frequency source phase code generator. 212 , where:
  • the upconverting mixer 29 is coupled to the front end variable frequency module 22, and the upconverting mixer 29 upconverts the intermediate frequency analog signal transmitted by the front end variable frequency module 22 to generate another radio frequency signal.
  • the frequency source phase detector 211 is connected to the local oscillator frequency source 210 and the upconversion mixer 29, and the frequency source phase detector 211 is based on the radio frequency signal generated by the upconversion mixer 29.
  • the radio frequency signal outputted by the local oscillator frequency source 210 is subjected to phase error judgment and the phase error analog signal of the local oscillator frequency source 210 is obtained.
  • the frequency source phase code generator 212 is connected to the frequency source phase detector 211, and the frequency source phase code generator 212 receives the local frequency source 210 phase error analog signal, and the local oscillator frequency source The 210 phase error analog signal is converted to the local frequency error digital code of the local oscillator frequency source.
  • the error matrix corrector 25 is connected to the frequency source phase code generator 212, and the error matrix error corrector 25 receives the local frequency frequency source phase error digital code, and according to the local oscillator frequency source The phase error digital code generates an error correction control signal.
  • the local oscillator frequency source 210 is connected to the error matrix corrector 25, and the local oscillator frequency source 210 receives the error correction control signal sent by the error matrix error corrector 25, and according to the correction The error control signal corrects the phase digital code of the local oscillator signal.
  • the upconverting mixer 29 is coupled to the gain control amplifier of the front end variable frequency module 22.
  • the buffer 1 and the buffer 2 in Fig. 2c are used in the transmitter shown in Fig. 2c to buffer the signal amplitude digital code and phase number output by the amplitude code generator 24 and the phase code generator 27. Encoding and synchronizing and refreshing the buffered signal amplitude digital encoding and phase digital encoding. It should be noted that the buffer synchronizes the buffered data (such as signal amplitude digital encoding and phase digital encoding in this embodiment). Specific embodiments of the refresh and refresh may be in any manner known to those skilled in the art.
  • an error matrix corrector In the embodiment of the present invention, an error matrix corrector, an amplitude detector, a phase detector, an amplitude code generator, a phase code generator and the like are added to the front end of the RF circuit of the receiver, so that the receiver/transmitter can pass
  • the error matrix error corrector compares the signal amplitude digital code, the signal phase digital code, and the frequency source phase digital code in the RF circuit with the standard code source pre-stored in the error matrix corrector, and the signal in the RF circuit Amplitude digital coding, signal phase digital coding, and frequency source phase digital coding are used for error correction, thereby completing carrier recovery and carrier generation in the radio frequency circuit.
  • the baseband chip does not need to consume computing resources for carrier recovery, carrier generation, especially frequency offset suppression and phase noise suppression related to carrier recovery, thereby improving the function of the baseband chip and reducing the baseband.
  • the power consumption of the chip, and the baseband chip does not have to bear the functions of carrier recovery and carrier generation, which need to perform complex operation flow, thereby reducing the process complexity and design difficulty of manufacturing the baseband chip, which will directly reduce the manufacturing cost of the baseband chip. Further reduce the operating/use cost of the baseband chip.
  • the transmitter described in this embodiment includes: a downconverting mixer, an amplitude detector, an amplitude code generator, an error matrix corrector, a local oscillator frequency source, a phase detector, a phase code generator, and a power splitter. a modulator, a gain control amplifier, an upconversion mixer, a power amplifier, a transmit antenna, wherein: the downconverting mixer is coupled to the local oscillator frequency source for use from the local oscillator frequency source The acquired RF signal to be transmitted is converted into an intermediate frequency analog signal, and the intermediate frequency analog signal is sent to the identifier.
  • the amplitude detector is connected to the downconverting mixer, configured to generate a first signal amplitude pulse signal according to the intermediate frequency analog signal sent by the downconverting mixer, and then send the first signal amplitude pulse signal To the amplitude code generator.
  • the amplitude code generator is connected to the amplitude detector for converting the first signal amplitude pulse signal as a pulse signal into a first signal amplitude digital code as a digital signal, and then the first signal
  • the amplitude digital code is sent to the error matrix error corrector, which is an encoder for converting a pulse signal into a digital signal.
  • the error matrix corrector is connected to the amplitude detector and the amplitude code generator, and configured to generate an amplitude error correction control signal according to the first signal amplitude digital code, and then perform the amplitude error correction control A signal is sent to the discriminator.
  • the amplitude detector is further configured to perform error correction on the first signal amplitude pulse signal according to the amplitude error correction control signal to generate a second signal amplitude pulse signal.
  • the amplitude code generator is further configured to convert the second signal amplitude pulse signal into a second signal amplitude digital code, so that the transmitter digitally encodes the second signal amplitude as carrier recovery and carrier The resulting signal amplitude is digitally encoded.
  • phase detector is connected to the downconverting mixer, and configured to generate a first signal phase pulse signal according to the intermediate frequency analog signal sent by the downconverting mixer, and then the first signal phase A pulse signal is sent to the phase code generator.
  • the phase code generator is connected to the phase detector for converting the first signal phase pulse signal as a pulse signal into a first signal phase digital code as a digital signal, and then the first signal
  • the phase digital code is sent to the error matrix error corrector, which is an encoder for converting a pulse signal into a digital signal.
  • the error matrix corrector is connected to the phase detector and the phase code generator, and is further configured to generate a phase error correction control signal according to the first signal phase digital code, and then correct the phase A control signal is sent to the phase detector.
  • the phase detector is configured to perform error correction on the first signal phase pulse signal according to the phase error correction control signal to generate a second signal phase pulse signal.
  • the phase code generator is further configured to convert the second signal phase pulse signal into a second signal phase digital code, so that the transmitter digitally encodes the second signal as carrier recovery and carrier The generated signal phase digital code.
  • the power divider is connected to the downconverting mixer, the amplitude detector and the phase detector, and configured to receive the intermediate frequency analog signal sent by the front end variable frequency module, and simulate the intermediate frequency
  • the signal is divided into two identical intermediate frequency analog signals, and the two identical intermediate frequency analog signals are respectively sent to the amplitude detector and the phase detector, so that the amplitude detector is issued according to the power splitter.
  • One of the intermediate frequency analog signals generates the first signal amplitude pulse signal, and is configured to generate the first signal phase pulse signal by the phase detector according to another intermediate frequency analog signal sent by the power splitter.
  • the modulator is coupled to the phase code generator and the amplitude code generator for generating another intermediate frequency analog signal based on the second signal phase digital code and the second signal amplitude digital code.
  • the upconverting mixer is connected to the local oscillator frequency source and the modulator, and is configured to regenerate a radio frequency signal according to an intermediate frequency analog signal generated by the modulator and a radio frequency signal output by the local oscillator frequency source. And transmitting the regenerated RF signal to the power amplifier.
  • the transmit antenna is coupled to the power amplifier for transmitting the regenerated RF signal processed by the power amplifier, and the power amplifier is coupled to the upconversion mixer.
  • the method may include: a downconverting mixer 31, an amplitude detector 32, an amplitude code generator 33, an error matrix corrector 34, and a local oscillator frequency source 35.
  • the downconverting mixer 31 is connected to the local oscillator frequency source 35, and converts the radio frequency signal to be transmitted obtained from the local oscillator frequency source 35 into an intermediate frequency analog signal, and then sends the intermediate frequency analog signal.
  • the discriminator 32 To the discriminator 32.
  • the amplitude detector 32 is connected to the down-conversion mixer 31, and the amplitude detector 32 generates a first signal amplitude pulse signal according to the intermediate frequency analog signal sent by the down-conversion mixer 31, and then the first A signal amplitude pulse signal is sent to the amplitude code generator 33.
  • the amplitude code generator 33 is connected to the amplitude detector 32, and the amplitude code generator 33 converts the first signal amplitude pulse signal into a first signal amplitude digital code, and then the first signal amplitude number The code is sent to the error matrix error corrector 34.
  • the error matrix corrector 34 is connected to the amplitude detector 32, and the error matrix error corrector 34 generates an amplitude error correction control signal according to the first signal amplitude digital code, and then corrects the amplitude.
  • a control signal is sent to the amplitude detector 32.
  • the amplitude detector 32 performs error correction on the first signal amplitude pulse signal according to the amplitude error correction control signal to generate a second signal amplitude pulse signal.
  • the amplitude code generator 33 converts the second signal amplitude pulse signal into a second signal amplitude digital code, so that the transmitter digitally encodes the second signal amplitude as carrier recovery and carrier generation. Signal amplitude digital coding.
  • the transmitter in this embodiment may further include: a power divider 36, a phase detector 37, and a phase code generator 38, where:
  • the phase detector 37 is connected to the downconverting mixer 31, and the phase detector 37 generates a first signal phase pulse signal according to the intermediate frequency analog signal sent by the downconverting mixer 31, and then the first A signal phase pulse signal is sent to the phase code generator 38.
  • the phase code generator 38 is connected to the phase detector 37, and the phase code generator 38 converts the first signal phase pulse signal into a first signal phase digital code, and then the first signal phase number The code is sent to the error matrix error corrector 34.
  • the error matrix corrector 34 is connected to the phase detector 37, and the error matrix error corrector 34 generates a phase error correction control signal according to the first signal phase digital code, and then corrects the phase.
  • a control signal is sent to the phase detector 37.
  • the phase detector 37 corrects the first signal phase pulse signal according to the phase error correction control signal to generate a second signal phase pulse signal.
  • the phase code generator 38 converts the second signal phase pulse signal into a second signal phase digital code, so that the transmitter digitally encodes the second signal phase as carrier recovery and carrier generation. Signal phase digital coding.
  • the power splitter 36 is connected to the downconverting mixer 31, the amplitude detector 32, the phase detector 37, and the power splitter 36 receives the intermediate frequency analog signal sent by the front end variable frequency module. And dividing the intermediate frequency analog signal into two identical intermediate frequency analog signals, and then sending the two identical intermediate frequency analog signals to the amplitude detector 32 and the phase detector 37, respectively, to facilitate the
  • the amplitude converter 32 generates the first signal amplitude pulse signal according to one of the intermediate frequency analog signals, and the phase detector 37 simultaneously generates the first signal phase pulse signal according to another intermediate frequency analog signal therein.
  • the transmitter in this embodiment may further include: a modulator 39, a gain control amplifier 310, an up-conversion mixer 311, a power amplifier 312, and a transmitting antenna 313, where:
  • the modulator 30 is coupled to the phase code generator 38 and the amplitude code generator 33, and the modulator 30 generates another intermediate frequency based on the second signal phase digital encoding and the second signal amplitude digital encoding. Analog signal.
  • the upconverting mixer 311 is connected to the local oscillator frequency source 35 and the modulator 39, and the upconversion mixer 311 generates an intermediate frequency analog signal and the local oscillator frequency source according to the modulator 39.
  • the output RF signal is 35, the RF signal is regenerated, and the regenerated RF signal is sent to the power amplifier 312.
  • the transmit antenna 313 is coupled to the power amplifier 312, and the power amplifier 312 is coupled to the upconversion mixer 311, and the transmit antenna 313 passes the regenerated radio frequency processed by the power amplifier 312. Signal transmission.
  • buffer 5 and the buffer 6 in FIG. 3c are the same as the buffer 1 and the buffer 2 in FIG. 2c, and are both digitally encoded and phase-encoded for the buffered signal amplitude. Synchronize and refresh.
  • the buffer 3 and the buffer 4 are further included in FIG. 3c, and the signal transmitted by the baseband chip can be received and buffered, and the buffered signal is transmitted to the modulator 39.
  • the signal transmission means of the baseband chip buffer 3 / buffer 4 modulator 39 and the signal processing manner can be well known to those skilled in the art. By means of prior art means.
  • an error matrix corrector In the embodiment of the present invention, an error matrix corrector, an amplitude detector, a phase detector, an amplitude code generator, a phase code generator and the like are added to the front end of the RF circuit of the transmitter, so that the receiver/transmitter can pass
  • the error matrix error corrector compares the signal amplitude digital code, the signal phase digital code, and the frequency source phase digital code in the RF circuit with the standard code source pre-stored in the error matrix corrector, and the signal in the RF circuit Amplitude digital coding, signal phase digital coding, and frequency source phase digital coding are used for error correction, thereby completing carrier recovery and carrier generation in the radio frequency circuit.
  • the baseband chip does not need to consume computing resources for carrier recovery, carrier generation, especially frequency offset suppression and phase noise suppression related to carrier recovery, thereby improving the function of the baseband chip and reducing the baseband.
  • the power consumption of the chip, and the baseband chip does not have to bear the functions of carrier recovery and carrier generation, which need to perform complex operation flow, thereby reducing the process complexity and design difficulty of manufacturing the baseband chip, which will directly reduce the manufacturing cost of the baseband chip. Further reduce the operating/use cost of the baseband chip.
  • An embodiment of the present invention provides a radio frequency signal receiving method, which is executed by a receiver, as shown in FIG. 4a, and includes:
  • the receiver receives the radio frequency signal, and converts the obtained radio frequency signal into an intermediate frequency analog signal.
  • the radio frequency signal receiving method provided in this embodiment may further include:
  • the receiver divides the intermediate frequency analog signal into two identical intermediate frequency analog signals.
  • phase error correction control signal Generate a phase error correction control signal according to the first signal phase digital code, and perform error correction on the first signal phase pulse signal according to the phase error correction control signal to generate a second signal phase pulse signal.
  • the radio frequency signal receiving method provided in this embodiment further includes:
  • the receiver upconverts the intermediate frequency analog signal to generate another radio frequency signal.
  • the functions of carrier recovery and carrier generation can be implemented in the radio frequency circuit part of the receiver. Compared with the prior art, the baseband chip does not need to perform carrier recovery and carrier generation, and in particular, does not have to bear the frequency associated with carrier recovery.
  • the functions of partial suppression, phase noise suppression and the like consume computing resources, so that the function of the baseband chip is refined, the power consumption of the baseband chip is reduced, and since the baseband chip does not have to bear the functions of carrier recovery and carrier generation, which need to perform a complicated operation flow, Thereby reducing the process complexity and design difficulty of manufacturing the baseband chip, which will directly reduce the baseband chip The manufacturing cost further reduces the operating/use cost of the baseband chip.
  • An embodiment of the present invention provides a method for transmitting a radio frequency signal, which is executed by a transmitter, as shown in FIG. 5a, and includes:
  • the transmitter converts the RF signal to be transmitted into an intermediate frequency analog signal.
  • the radio frequency signal transmitting method provided in this embodiment after converting the radio frequency signal to be transmitted into the intermediate frequency analog signal, further includes:
  • the transmitter divides the intermediate frequency analog signal into two identical intermediate frequency analog signals.
  • the method for transmitting radio frequency signals provided by this embodiment further includes:
  • the transmitter generates another intermediate frequency analog signal according to the second signal phase digital code and the second signal amplitude digital code.
  • the functions of carrier recovery and carrier generation can be implemented in the radio frequency circuit part of the transmitter.
  • the baseband chip does not need to perform carrier recovery and carrier generation, and in particular, does not have to bear the frequency associated with carrier recovery.
  • the functions of partial suppression, phase noise suppression and the like consume computing resources, so that the function of the baseband chip is refined, the power consumption of the baseband chip is reduced, and since the baseband chip does not have to bear the functions of carrier recovery and carrier generation, which need to perform a complicated operation flow, Thereby, the process complexity and design difficulty of manufacturing the baseband chip are reduced, which will directly reduce the manufacturing cost of the baseband chip, and further reduce the operation/use cost of the baseband chip.
  • An embodiment of the present invention provides a radio frequency signal transceiving system, as shown in FIG. 6a, including: a receiver 61 and a transmitter 62.
  • the radio frequency signal transceiving system includes the receiver described in Embodiment 1 and the transmitter described in Embodiment 2.
  • the receiver 61 and the transmitter 62 can transmit and receive radio frequency signals through a wireless network, and the specific implementation may be any manner known to those skilled in the art.
  • one end of the radio frequency signal transceiving system in this embodiment can have both the receiver and the transmitter, that is, the receiver described in Embodiment 1 and the method described in Embodiment 2 can be used.
  • the transmitter is integrated in the same RF circuit, and those skilled in the art can use the conventional technical means to simultaneously perform the functions of the error matrix corrector in the transmitter and the receiver, so that the RF circuit can be implemented at the same time.
  • the functions of the receiver described in Example 1 and the transmitter described in Embodiment 2 for example: as shown in FIG. 6b,
  • the radio frequency circuit of the transmitter and the receiver are integrated together, and an error matrix corrector is shared, and the specific manner of carrier recovery and carrier generation of the radio frequency circuit connected to the baseband chip shown in FIG. 6b can be implemented with the foregoing implementation.
  • the example is the same.
  • the RF circuit shown in FIG. 6b further includes two filters, and the two filters respectively perform interference cancellation on the signal flowing through the receiving antenna or the transmitting antenna.
  • a specific implementation of interference cancellation using a filter may be in a manner well known to those skilled in the art.
  • the RF circuit shown in FIG. 6b further includes a duplexer, which can perform interference cancellation on the signal flowing through the transceiver antenna. In this embodiment, the way.
  • the function of carrier recovery and carrier generation can be implemented in the radio frequency circuit part of the transmitter/receiver in the radio frequency signal transceiving system.
  • the baseband chip of the radio frequency signal transceiving system does not need to perform carrier recovery and carrier.
  • the generation does not have to bear the function of computing power consumption such as frequency offset suppression and phase noise suppression related to carrier recovery, thereby optimizing the function of the baseband chip, reducing the power consumption of the baseband chip, thereby reducing the transmitter/receiver.
  • the power consumption is reduced, and the power consumption of the RF signal transmitting and receiving system including the above transmitter/receiver is reduced, thereby saving power, thereby reducing the operating cost of the entire system.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (Random Acs s Memo r y , RAM).

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Abstract

本发明公开了一种发射机、接收机及射频收发方法，涉及无线通讯技术领域，能在射频电路前端进行载波恢复及生成，降低基带芯片的运行成本。包括：鉴幅器/鉴相器根据中频模拟信号未纠错的信号幅度脉冲信号/信号相位脉冲信号；并由误码矩阵纠错器生成幅度/相位纠错控制信号；鉴幅器/鉴相器再根据幅度/相位纠错控制信号对信号幅度脉冲信号/信号相位脉冲信号进行纠错，再由幅度码生成器/相位码生成器将纠错后的脉冲信号转换为相应的数字编码。适用于收/发射频信号。

Description

一种发射机、 接收机及射频收发方法 技术领域
本发明涉及无线通讯技术领域， 尤其涉及一种发射机、接收机及射频 收发方法。
背景技术 在现有的通信系统中， 基带芯片与射频电路往往需要协同工作， 其中 射频电路一般负责射频信号的发送或接收，基带芯片一般负责对射频信号 进行一系列的处理， 例如： 在发射机， 基带芯片可以将音频信号编译成用 来发射的射频信号； 在接收机， 基带芯片可以把收到的射频信号解译为音 频信号。 同时， 基带芯片也具备编译 /解译地址信息、 文字信息、 图片信 息等信号处理功能。
其中， 基带芯片还有一项重要的功能是： 通过一系列的复杂算法， 对 流经射频电路的信号进行载波恢复、载波生成等处理，以修正信号的误差， 从而保证射频电路发送 /接收到的射频信号的准确度。 例如：
如图 l a所示， 为现有技术中的一种射频电路架构， 其中的接收机和 发射机集成在了一起， 并与同一个基带芯片相连， 以便于基带芯片对流经 接收机和发射机的信号进行载波恢复、 载波生成等处理。 比如： 如图 l b 所示， 为基带芯片对信号进行载波恢复的大致处理流程， 其中： 基带芯片 通过鉴相器根据判决所得的误差， 获取相位误差， 再通过环路滤波器以及 数字振荡器依据相应的算法处理后， 输出修正了误差的相位信号。
现有技术的问题：
为了能够提高收 /发机的运行效率， 就需要提高射频电路的频谱效率， 而提高调制模式是一个提高频谱效率的主要方式。 但是， 在提高调制模式 后， 例： ¾口： 由 64QAM ( Quadrature Amplitude Modulation , 正交振幅调制） 提高到 1024QAM , 基带芯片也需要增加元件， 以保证载波恢复、 载波生 成等功能能够正常运作。 并且在现有技术中， 想要保证基带芯片在高调制 模式下能够正常运行， 可行的方案只有在基带芯片上集成更多的元件， 例 如： 在 64QAM场景下， 基带芯片需要 26个门电路， 而在 1024QAM场景 下， 就需要 21Q个门电路。 进一步的， 在 2048QAM或 4096QAM等场景 下， 所需要的门电路的数量更加会成指数倍增加， 这在工业制造上是无法 实现的。 并且， 想要在高调制模式下运行， 一个基带芯片上需要增加的元 件不仅仅是门电路， 基带芯片中的其他元件， 也需要成倍增加， 需要消耗 巨大的成本， 且由于元件的增多， 基带芯片运行时的功耗也很大。
使得现有技术中，基带芯片与射频电路在高调制模式下进行载波恢复、 载 波生成时所需的成本 4艮高。 发明内容 本发明的实施例提供一种发射机、接收机及射频收发方法， 能够在射 频电路前端进行载波恢复、载波生成，使得基带芯片不必再承担载波恢复、 载波生成的功能， 从而降低基带芯片的运行成本。
为达到上述目的， 本发明的实施例采用如下技术方案：
一方面， 本发明的实施例提供一种接收机， 包括：
接收天线、 前端变频模块、鉴幅器、 幅度码生成器、误码矩阵纠错器， 其中：
所述前端变频模块从所述接收天线获取射频信号，所述前端变频模块 将所获取的射频信号转换为中频模拟信号，再将所述中频模拟信号发送至 所述鉴幅器， 所述前端变频模块包括： 低噪声放大器、 下变频混频器、 增 益控制放大器；
所述鉴幅器与所述前端变频模块相连，所述鉴幅器根据所述前端变频 模块发送的中频模拟信号生成第一信号幅度脉沖信号，再将所述第一信号 幅度脉沖信号发送至所述幅度码生成器；
所述幅度码生成器与所述鉴幅器相连，所述幅度码生成器将所述第一 信号幅度脉沖信号转换为第一信号幅度数字编码，再将所述第一信号幅度 数字编码发送至所述误码矩阵纠错器； 所述误码矩阵纠错器与所述鉴幅器相连，所述误码矩阵纠错器根据所 述第一信号幅度数字编码生成幅度纠错控制信号，再将所述幅度纠错控制 信号发送至所述鉴幅器；
所述鉴幅器根据所述幅度纠错控制信号对所述第一信号幅度脉沖信 号进行纠错， 以生成第二信号幅度脉沖信号；
所述幅度码生成器将所述第二信号幅度脉沖信号转换为第二信号幅 度数字编码，以使所述接收机将所述第二信号幅度数字编码作为进行了载 波恢复及载波生成后的信号幅度数字编码。
进一步的， 所述接收机还包括： 鉴相器、 相位码生成器， 其中： 所述鉴相器与所述前端变频模块相连，所述鉴相器根据所述前端变频 模块发送的中频模拟信号生成第一信号相位脉沖信号，再将所述第一信号 相位脉沖信号发送至所述相位码生成器；
所述相位码生成器与所述鉴相器相连，所述相位码生成器将所述第一 信号相位脉沖信号转换为第一信号相位数字编码，再将所述第一信号相位 数字编码发送至所述误码矩阵纠错器；
所述误码矩阵纠错器与所述鉴相器相连，所述误码矩阵纠错器根据所 述第一信号相位数字编码生成相位纠错控制信号，再将所述相位纠错控制 信号发送至所述鉴相器；
所述鉴相器根据所述相位纠错控制信号对所述第一信号相位脉沖信 号进行纠错， 以生成第二信号相位脉沖信号；
所述相位码生成器将所述第二信号相位脉沖信号转换为第二信号相 位数字编码，以使所述接收机将所述第二信号相位数字编码作为进行了载 波恢复及载波生成后的信号相位数字编码。 另一方面， 本发明的实施例提供一种发射机， 包括：
下变频混频器、 鉴幅器、 幅度码生成器、 误码矩阵纠错器、 本振频率 源， 其中： 所述下变频混频器与所述本振频率源相连，将从所述本振频率源获取 的待发送的射频信号转换为中频模拟信号，再将所述中频模拟信号发送至 所述鉴幅器；
所述鉴幅器与所述下变频混频器相连，所述鉴幅器根据所述下变频混 频器发送的中频模拟信号生成第一信号幅度脉沖信号，再将所述第一信号 幅度脉沖信号发送至所述幅度码生成器；
所述幅度码生成器与所述鉴幅器相连，所述幅度码生成器将所述第一 信号幅度脉沖信号转换为第一信号幅度数字编码，再将所述第一信号幅度 数字编码发送至所述误码矩阵纠错器；
所述误码矩阵纠错器与所述鉴幅器相连，所述误码矩阵纠错器根据所 述第一信号幅度数字编码生成幅度纠错控制信号，再将所述幅度纠错控制 信号发送至所述鉴幅器；
所述鉴幅器根据所述幅度纠错控制信号对所述第一信号幅度脉沖信 号进行纠错， 以生成第二信号幅度脉沖信号；
所述幅度码生成器将所述第二信号幅度脉沖信号转换为第二信号幅 度数字编码，以使所述接收机将所述第二信号幅度数字编码作为进行了载 波恢复及载波生成后的信号幅度数字编码。
进一步的， 所述的接收机还包括： 鉴相器、 相位码生成器， 其中： 所述鉴相器与所述下变频混频器相连，所述鉴相器根据所述下变频混 频器发送的中频模拟信号生成第一信号相位脉沖信号，再将所述第一信号 相位脉沖信号发送至所述相位码生成器；
所述相位码生成器与所述鉴相器相连，所述相位码生成器将所述第一 信号相位脉沖信号转换为第一信号相位数字编码，再将所述第一信号相位 数字编码发送至所述误码矩阵纠错器；
所述误码矩阵纠错器与所述鉴相器相连，所述误码矩阵纠错器根据所 述第一信号相位数字编码生成相位纠错控制信号，再将所述相位纠错控制 信号发送至所述鉴相器； 所述鉴相器根据所述相位纠错控制信号对所述第一信号相位脉沖信 号进行纠错， 以生成第二信号相位脉沖信号；
所述相位码生成器将所述第二信号相位脉沖信号转换为第二信号相 位数字编码，以使所述接收机将所述第二信号相位数字编码作为进行了载 波恢复及载波生成后的信号相位数字编码。 再一方面， 本发明的实施例提供一种射频信号接收方法， 包括： 接收机接收射频信号， 并将所获取的射频信号转换为中频模拟信号； 根据所述中频模拟信号生成第一信号幅度脉沖信号；
将所述第一信号幅度脉沖信号转换为第一信号幅度数字编码； 根据所述第一信号幅度数字编码生成幅度纠错控制信号，并根据所述 幅度纠错控制信号对所述第一信号幅度脉沖信号进行纠错，以生成第二信 号幅度脉沖信号；
将所述第二信号幅度脉沖信号转换为第二信号幅度数字编码，并将所 述第二信号幅度数字编码作为进行了载波恢复及载波生成后的信号幅度 数字编码。
进一步的， 还包括：
根据所述中频模拟信号生成第一信号相位脉沖信号；
将所述第一信号相位脉沖信号转换为第一信号相位数字编码； 根据所述第一信号相位数字编码生成相位纠错控制信号，并根据所述 相位纠错控制信号对所述第一信号相位脉沖信号进行纠错，以生成第二信 号相位脉沖信号；
将所述第二信号相位脉沖信号转换为第二信号相位数字编码，并将所 述第二信号相位数字编码作为进行了载波恢复及载波生成后的信号相位 数字编码。 再一方面， 本发明的实施例提供一种射频信号发射方法， 包括: 发射机将待发送的射频信号转换为中频模拟信号；
根据所述中频模拟信号生成第一信号幅度脉沖信号；
将所述第一信号幅度脉沖信号转换为第一信号幅度数字编码； 根据所述第一信号幅度数字编码生成幅度纠错控制信号，并根据所述 幅度纠错控制信号对所述第一信号幅度脉沖信号进行纠错，以生成第二信 号幅度脉沖信号；
将所述第二信号幅度脉沖信号转换为第二信号幅度数字编码，以使所 述发射机将所述第二信号幅度数字编码作为进行了载波恢复及载波生成 后的信号幅度数字编码。
进一步的， 还包括：
根据所述中频模拟信号生成第一信号相位脉沖信号；
将所述第一信号相位脉沖信号转换为第一信号相位数字编码； 根据所述第一信号相位数字编码生成相位纠错控制信号，并根据所述 相位纠错控制信号对所述第一信号相位脉沖信号进行纠错，以生成第二信 号相位脉沖信号；
将所述第二信号相位脉沖信号转换为第二信号相位数字编码，以使所 述接收机将所述第二信号相位数字编码作为进行了载波恢复及载波生成 后的信号相位数字编码。
本发明实施例提供的发射机、接收机及射频收发方法， 能够在接收机的射 频电路部分就实现载波恢复、 载波生成的功能， 与现有技术相比， 基带芯 片不必再进行载波恢复、载波生成， 尤其是不必再承担与载波恢复相关的 频偏抑制、 相噪抑制等功能消耗运算资源， 从而精筒了基带芯片的功能， 降低了基带芯片功耗， 并且由于基带芯片不必再承担载波恢复、 载波生成 这种需要执行复杂运算流程的功能，从而降低了制造基带芯片的工艺复杂 度和设计难度， 这将直接降低基带芯片的制造成本， 进一步降低基带芯片 的运行 /使用成本。 附图说明 为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所 需要使用的附图作筒单地介绍， 显而易见地， 下面描述中的附图仅仅是本 发明的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造性劳动 的前提下， 还可以根据这些附图获得其它的附图。
图 l a为现有技术中的收发机结构示意图； 图 l b为现有技术中的基带芯片的工作流程示意图； 图 2 a为本发明实施例 1提供的接收机的一种结构示意图； 图 2 b为本发明实施例 1提供的接收机的另一种结构示意图； 图 2 c为本发明实施例 1提供的接收机的再一种结构示意图； 图 2 d为本发明实施例 1提供的具体实例的示意图； 图 3 a为本发明实施例 2提供的发射机的一种结构示意图； 图 3 b为本发明实施例 2提供的发射机的另一种结构示意图； 图 3 c为本发明实施例 2提供的发射机的再一种结构示意图； 图 4 a为本发明实施例 3提供的射频信号接收方法的一种流程图； 图 4 b为本发明实施例 3提供的射频信号接收方法的另一种流程图； 图 4 c为本发明实施例 3提供的射频信号接收方法的再一种流程图； 图 5 a为本发明实施例 4提供的射频信号发射方法的一种流程图； 图 5 b为本发明实施例 4提供的射频信号发射方法的另一种流程图； 图 5 c为本发明实施例 4提供的射频信号发射方法的再一种流程图； 图 6 a为本发明实施例 5提供的射频信号收发系统的结构示意图； 图 6 b为本发明提供的一种射频电路的具体实例的结构示意图； 图 6 c为本发明提供的另一种射频电路的具体实例的结构示意图； 图 6 d为本发明提供的再一种射频电路的具体实例的结构示意图。
具体实施方式 下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进 行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例， 而不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没 有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的 范围。
为使本发明技术方案的优点更加清楚，下面结合附图和实施例对本发 明作详细说明。
实施例 1 本实施例中所述的接收机， 包括： 接收天线、 前端变频模块、鉴幅器、 幅度码生成器、 误码矩阵纠错器、 功分器、 上变频混频器、 本振频率源、 频率源相位码生成器， 其中：
所述前端变频模块， 用于从所述接收天线获取射频信号， 并将所获取 的射频信号转换为中频模拟信号，再将所述中频模拟信号发送至所述鉴幅 器， 所述前端变频模块包括： 低噪声放大器、 下变频混频器、 增益控制放 大器。
所述鉴幅器， 与所述前端变频模块相连， 用于根据所述前端变频模块 发送的中频模拟信号生成第一信号幅度脉沖信号，再将所述第一信号幅度 脉沖信号发送至所述幅度码生成器。
所述幅度码生成器， 与所述鉴幅器相连， 用于将作为脉沖信号的所述 第一信号幅度脉沖信号转换为作为数字信号的第一信号幅度数字编码，再 将所述第一信号幅度数字编码发送至所述误码矩阵纠错器，所述幅度码生 成器为一种用于将脉沖信号转换为数字信号的编码器。
所述误码矩阵纠错器， 与所述鉴幅器和所述幅度码生成器相连， 用于 根据所述第一信号幅度数字编码生成幅度纠错控制信号，再将所述幅度纠 错控制信号发送至所述鉴幅器。
所述鉴幅器，用于根据所述幅度纠错控制信号对所述第一信号幅度脉 沖信号进行纠错， 以生成第二信号幅度脉沖信号。
所述幅度码生成器，还用于将所述第二信号幅度脉沖信号转换为第二 信号幅度数字编码，以使所述接收机将所述第二信号幅度数字编码作为进 行了载波恢复及载波生成后的信号幅度数字编码。
进一步的， 所述鉴相器， 与所述前端变频模块相连， 用于根据所述前 端变频模块发送的中频模拟信号生成第一信号相位脉沖信号，再将所述第 一信号相位脉沖信号发送至所述相位码生成器。
所述相位码生成器， 与所述鉴相器相连， 用于将作为脉沖信号的所述 第一信号相位脉沖信号转换为作为数字信号的第一信号相位数字编码，并 将所述第一信号相位数字编码发送至所述误码矩阵纠错器，所述相位码生 成器为一种用于将脉沖信号转换为数字信号的编码器。
所述误码矩阵纠错器， 与所述鉴相器相连和所述相位码生成器相连， 用于根据所述第一信号相位数字编码生成相位纠错控制信号，再将所述相 位纠错控制信号发送至所述鉴相器。
所述鉴相器，用于根据所述相位纠错控制信号对所述第一信号相位脉 沖信号进行纠错， 以生成第二信号相位脉沖信号。
所述相位码生成器，还用于将所述第二信号相位脉沖信号转换为第二 信号相位数字编码，以使所述接收机将所述第二信号相位数字编码作为进 行了载波恢复及载波生成后的信号相位数字编码。
所述功分器， 与所述前端变频模块、 所述鉴幅器和所述鉴相器相连， 用于接收所述前端变频模块发送的所述中频模拟信号，并将所述中频模拟 信号分为两路相同的中频模拟信号，再将这两路相同的中频模拟信号分别 发送至所述鉴幅器和所述鉴相器，以便于所述鉴幅器根据所述功分器发出 的其中一路中频模拟信号生成所述第一信号幅度脉沖信号，所述鉴相器根 据所述功分器发出的另一路中频模拟信号生成所述第一信号相位脉沖信 号。
所述上变频混频器， 与所述前端变频模块相连， 用于将所述前端变频 模块发送的中频模拟信号进行上变频， 以产生另一路射频信号。
所述频率源鉴相器， 与所述本振频率源和所述上变频混频器相连， 用 于根据所述上变频混频器产生的射频信号与所述本振频率源输出的射频 信号， 进行相位误差判断并获取本振频率源相位误差模拟信号。
所述频率源相位码生成器， 与所述频率源鉴相器相连， 用于接收所述 本振频率源相位误差模拟信号，并将所述本振频率源相位误差模拟信号转 换为本振频率源相位误差数字编码。
所述误码矩阵纠错器， 与所述频率源相位码生成器相连， 用于接收所 述本振频率源相位误差数字编码，并根据所述本振频率源相位误差数字编 码生成纠错控制信号。
所述本振频率源， 与所述误码矩阵纠错器， 用于接收所述误码矩阵纠 错器发送的所述纠错控制信号，并根据所述纠错控制信号对所述本振信号 相位数字编码进行纠错。
所述上变频混频器与所述前端变频模块中的所述增益控制放大器相 连， 所述前端变频模块中的下变频混频器与所述频率源鉴相器相连。
具体的， 在本实施例中， 如图 2a所示， 可以包括： 接收天线 21、 前 端变频模块 22、鉴幅器 23、 幅度码生成器 24、误码矩阵纠错器 25 , 其中： 所述前端变频模块 22从所述接收天线 21获取射频信号，所述前端变频模 块 22将所获取的射频信号转换为中频模拟信号， 再将所述中频模拟信号 发送至所述鉴幅器 23。
其中， 所述前端变频模块 22包括： 低噪声放大器 221、 下变频混频器 222、 增益控制放大器 223。 所述鉴幅器 23与所述前端变频模块 22相连，所述鉴幅器 23根据所述前 端变频模块 22发送的中频模拟信号生成第一信号幅度脉沖信号，再将所述 第一信号幅度脉沖信号发送至所述幅度码生成器 24。
所述幅度码生成器 24与所述鉴幅器 23相连，所述幅度码生成器 24将所 述第一信号幅度脉沖信号转换为第一信号幅度数字编码，再将所述第一信 号幅度数字编码发送至所述误码矩阵纠错器 25。
所述误码矩阵纠错器 25与所述鉴幅器 23相连，所述误码矩阵纠错器 25 根据所述第一信号幅度数字编码生成幅度纠错控制信号，再将所述幅度纠 错控制信号发送至所述鉴幅器 23。
所述鉴幅器 23根据所述幅度纠错控制信号对所述第一信号幅度脉沖 信号进行纠错， 以生成第二信号幅度脉沖信号。
所述幅度码生成器 24将所述第二信号幅度脉沖信号转换为第二信号 幅度数字编码，以使所述接收机将所述第二信号幅度数字编码作为进行了 载波恢复及载波生成后的信号幅度数字编码。
在本发明实施例中， 误码矩阵纠错器可以对发射机 /接收机中产生的 数字编码的误差进行误码纠错。 其中， 接收机中的数字编码的误差主要产 生原因包括： 在与接收机进行数据通信的发射机的硬件链路中， 电信号的 传输会有一定几率产生偏差，从而使接收机根据所接收到的信号生成的数 字编码产生误差； 在无线通讯的空间传输过程中产生的误差； 在接收机的 硬件链路中， 电信号的传输会有一定几率产生偏差， 从而使接收机中的数 字编码产生的误差。 再其中， 发射机中的数字编码的误差主要产生原因包 括： 在发射机的硬件链路中， 电信号的传输会有一定几率产生偏差， 从而 使发射机中的数字编码产生的误差。
需要说明的是，接收机和发射机中的误码矩阵纠错器可以相同。例如： 在误码矩阵纠错器中可以预存标准的信号幅度数字误码矩阵、信号相 位数字误码矩阵、频率源相位数字误码矩阵等通信协议中已经制定的标准 码源， 如： 协议中的标准 QAM码源。 技术人员可以预存在误码矩阵纠错 器中， 以便于误码矩阵纠错器将这些标准数据， 与接收机接收到的或发射 机生成的信号幅度数字编码、 信号相位数字编码、 以及频率源相位数字编 码进行对比， 并输出信号幅度数字误码、 信号相位数字误码、 频率源相位 数字误码。
其中， 信号幅度数字误码、 信号相位数字误码、 频率源相位数字误码 可以有多种形式， 比如： 预存的标准的信号幅度数字编码中的 A段字符是 1010,而接收机根据接收到的射频信号所解析出的信号幅度数字编码中的 A段字符是 1011 , 则误码矩阵纠错器可以通过筒单的二进制加减法获取信 号幅度数字误码， 即为 1011-1010=1。
进一步的， 误码矩阵纠错器中对信号幅度数字编码、信号相位数字编 码、 本振频率源相位误差数字编码进行分析， 并获取相应的纠错控制信号 的过程， 可以有多种， 下面举例说明其中的优选方案：
图 2d所示的是在 64Q AM的场景下， 存在于接收机或发射机的射频电 路中的误码矩阵纠错器对信号幅度数字编码、 信号相位数字编码、 本振频 率源相位误差数字编码进行的分析过程。 其中， 标注了斜线的方块表示的 是信号幅度数字编码所对应的标准码源，标注了网格的方块表示的是信号 相位数字编码所对应的标准码源，标注了全黑色的方块表示的是本振频率 源相位误差数字编码所对应的标准码源，这些标准码源可以是预存在误码 矩阵纠错器中的标准 Q AM码源， 并且这些标准 Q AM码源已被公开在了现 有的协议中， 技术人员可以直接从协议中知晓这些标准 QAM码源。
当射频电路中的信号幅度数字编码传输到了误码矩阵纠错器，误码矩 阵纠错器可以通过现有的技术手段，如通过比较器来对比射频电路中的信 号幅度数字编码和标准 Q A M码源中的信号幅度数字编码， 即误码矩阵纠 错器可以将射频电路中的信号幅度数字编码与图 2d所示的标注了斜线的 方块所对应的数据进行对比， 并通过筒单的二进制加减法获取二者的差 值。 再通过∑ Δ调制器， 根据所获取的差值输出对应的信号幅度纠错控制 模拟信号。 误码矩阵纠错器输出的信号幅度纠错控制模拟信号传输至鉴幅器后， 鉴幅器可以以此对信号幅度数字编码进行矫正。并且上述的误码纠错过程 可以多次循环， 以确保信号幅度数字编码的正确。
同理，误码矩阵纠错器对于信号相位数字编码和本振频率源相位误差 数字编码可以通过上述过程进行处理。 即在本发明实施例中， 误码矩阵纠 错器可以通过上述过程对接收机、 发射机或收发机（如图 6b、 图 6c或图 6d 所示的同时集成了接收和发射功能的射频电路） 中的信号幅度数字编码、 信号相位数字编码和本振频率源相位误差数字编码进行纠错。
需要进一步说明的是， 在本实施例中， 对于 1024QAM、 2048QAM , 4096QAM等场景皆可采用上述的误码纠错过程，从而实现了在 1024QAM、 2048QAM , 4096QAM等场景下进行载波恢复、 载波生成， 并且射频电路 的结构并不会改变， 可以通过现有的工业生产设备制造出来。 进一步的， 本实施例中所述的接收机， 如图 2b所示， 还可以包括： 鉴 相器 26、 相位码生成器 27、 功分器 28 , 其中：
所述鉴相器 26 , 与所述前端变频模块 22相连， 用于根据所述前端变频 模块 22发送的中频模拟信号生成第一信号相位脉沖信号，再将所述第一信 号相位脉沖信号发送至所述相位码生成器 27。
所述相位码生成器 27 , 与所述鉴相器 26相连， 用于将作为脉沖信号的 所述第一信号相位脉沖信号转换为作为数字信号的第一信号相位数字编 码， 并将所述第一信号相位数字编码发送至所述误码矩阵纠错器 25 , 所述 相位码生成器 27为一种用于将脉沖信号转换为数字信号的编码器。
所述误码矩阵纠错器 25 ,与所述鉴相器 26相连和所述相位码生成器 27 相连， 用于根据所述第一信号相位数字编码生成相位纠错控制信号， 再将 所述相位纠错控制信号发送至所述鉴相器 26。
所述鉴相器 26 ,用于根据所述相位纠错控制信号对所述第一信号相位 脉沖信号进行纠错， 以生成第二信号相位脉沖信号。 所述相位码生成器 27 ,还用于将所述第二信号相位脉沖信号转换为第 二信号相位数字编码，以使所述接收机将所述第二信号相位数字编码作为 进行了载波恢复及载波生成后的信号相位数字编码。
所述功分器 28 , 与所述前端变频模块 22、 所述鉴幅器 23和所述鉴相器 26相连， 用于接收所述前端变频模块 22发送的所述中频模拟信号， 并将所 述中频模拟信号分为两路相同的中频模拟信号，再将这两路相同的中频模 拟信号分别发送至所述鉴幅器 23和所述鉴相器 26 , 以便于所述鉴幅器 23 根据所述功分器 28发出的其中一路中频模拟信号生成所述第一信号幅度 脉沖信号，所述鉴相器 26根据所述功分器 28发出的另一路中频模拟信号生 成所述第一信号相位脉沖信号。
具体的， 在本实施例中， 所述鉴相器 26与所述前端变频模块 22相连， 所述鉴相器 26根据所述前端变频模块 22发送的中频模拟信号生成第一信 号相位脉沖信号，再将所述第一信号相位脉沖信号发送至所述相位码生成 器 27。
所述相位码生成器 27与所述鉴相器 26相连，所述相位码生成器 27将所 述第一信号相位脉沖信号转换为第一信号相位数字编码，再将所述第一信 号相位数字编码发送至所述误码矩阵纠错器 25。
所述误码矩阵纠错器 25与所述鉴相器 26相连，所述误码矩阵纠错器 25 根据所述第一信号相位数字编码生成相位纠错控制信号，再将所述相位纠 错控制信号发送至所述鉴相器 26。
所述鉴相器 26根据所述相位纠错控制信号对所述第一信号相位脉沖 信号进行纠错， 以生成第二信号相位脉沖信号。
所述相位码生成器 27将所述第二信号相位脉沖信号转换为第二信号 相位数字编码，以使所述接收机将所述第二信号相位数字编码作为进行了 载波恢复及载波生成后的信号相位数字编码。
所述功分器 28与所述前端变频模块 22、 所述鉴幅器 23、 所述鉴相器 26 相连， 所述功分器 28接收所述前端变频模块 22发送的所述中频模拟信号， 并将所述中频模拟信号分为两路相同的中频模拟信号，再将这两路相同的 中频模拟信号分别发送至所述鉴幅器 23和所述鉴相器 26 ,以便于所述鉴幅 器 23根据其中一路中频模拟信号生成所述第一信号幅度脉沖信号，并以便 于所述鉴相器 26同时根据其中的另一路中频模拟信号生成所述第一信号 相位脉沖信号。 再进一步的， 本实施例中所述的接收机， 如图 2c所示， 还可以包括： 上变频混频器 29、 本振频率源 210、 频率源鉴相器 211、 频率源相位码生成 器 212 , 其中：
所述上变频混频器 29与所述前端变频模块 22相连，所述上变频混频器 29将所述前端变频模块 22发送的中频模拟信号进行上变频，以产生另一路 射频信号。
所述频率源鉴相器 211与所述本振频率源 210和所述上变频混频器 29 相连， 所述频率源鉴相器 211根据所述上变频混频器 29产生的射频信号与 所述本振频率源 210输出的射频信号， 进行相位误差判断并获取本振频率 源 210相位误差模拟信号。
所述频率源相位码生成器 212与所述频率源鉴相器 211相连，所述频率 源相位码生成器 212接收所述本振频率源 210相位误差模拟信号，并将所述 本振频率源 210相位误差模拟信号转换为本振频率源相位误差数字编码。
所述误码矩阵纠错器 25与所述频率源相位码生成器 212相连， 所述误 码矩阵纠错器 25接收所述本振频率源相位误差数字编码，并根据所述本振 频率源相位误差数字编码生成纠错控制信号。
所述本振频率源 210与所述误码矩阵纠错器 25相连， 所述本振频率源 210接收所述误码矩阵纠错器 25发送的所述纠错控制信号， 并根据所述纠 错控制信号对本振信号相位数字编码进行纠错。
其中，所述上变频混频器 29与所述前端变频模块 22中的所述增益控制 放大器相连。 需要说明的是， 在图 2c中的緩沖器 1和緩沖器 2 , 在图 2c所示的发射机 中用于緩存幅度码生成器 24和相位码生成器 27输出的信号幅度数字编码 和相位数字编码，并对所緩存的信号幅度数字编码和相位数字编码进行同 步和刷新， 需要说明的是， 緩沖器对所緩存的数据（如本实施例中的信号 幅度数字编码和相位数字编码）进行同步和刷新的具体实施方式可以是本 领域技术人员所熟知的任意方式。
对本实施例有益效果的分析：
本发明实施例通过在接收机的射频电路的前端加入了误码矩阵纠错 器、 鉴幅器、 鉴相器、 幅度码生成器、 相位码生成器等元件， 使得接收机 /发射机可以通过误码矩阵纠错器将射频电路中的信号幅度数字编码、 信 号相位数字编码、以及频率源相位数字编码与误码矩阵纠错器中预存的标 准码源进行对比， 并对射频电路中的信号幅度数字编码、信号相位数字编 码、 以及频率源相位数字编码进行纠错， 从而在射频电路中完成了载波恢 复、 载波生成。
与现有技术相比， 基带芯片不必再为载波恢复、 载波生成， 尤其是与 载波恢复相关的频偏抑制、 相噪抑制等功能消耗运算资源， 从而精筒了基 带芯片的功能， 降低了基带芯片功耗， 并且由于基带芯片不必再承担载波 恢复、 载波生成这种需要执行复杂运算流程的功能， 从而降低了制造基带 芯片的工艺复杂度和设计难度， 这将直接降低基带芯片的制造成本， 进一 步降低基带芯片的运行 /使用成本。
实施例 2
本实施例中所述的发射机， 包括： 下变频混频器、 鉴幅器、 幅度码生 成器、 误码矩阵纠错器、 本振频率源、 鉴相器、 相位码生成器、 功分器、 调制器、 增益控制放大器、 上变频混频器、 功率放大器、 发射天线， 其中： 所述下变频混频器， 与所述本振频率源相连， 用于将从所述本振频率 源获取的待发送的射频信号转换为中频模拟信号，再将所述中频模拟信号 发送至所述鉴幅器。 所述鉴幅器， 与所述下变频混频器相连， 用于根据所述下变频混频器 发送的中频模拟信号生成第一信号幅度脉沖信号，再将所述第一信号幅度 脉沖信号发送至所述幅度码生成器。
所述幅度码生成器， 与所述鉴幅器相连， 用于将作为脉沖信号的所述 第一信号幅度脉沖信号转换为作为数字信号的第一信号幅度数字编码，再 将所述第一信号幅度数字编码发送至所述误码矩阵纠错器，所述幅度码生 成器为一种用于将脉沖信号转换为数字信号的编码器。
所述误码矩阵纠错器， 与所述鉴幅器和所述幅度码生成器相连， 用于 根据所述第一信号幅度数字编码生成幅度纠错控制信号，再将所述幅度纠 错控制信号发送至所述鉴幅器。
所述鉴幅器，还用于根据所述幅度纠错控制信号对所述第一信号幅度 脉沖信号进行纠错， 以生成第二信号幅度脉沖信号。
所述幅度码生成器，还用于将所述第二信号幅度脉沖信号转换为第二 信号幅度数字编码，以使所述发射机将所述第二信号幅度数字编码作为进 行了载波恢复及载波生成后的信号幅度数字编码。
进一步的， 所述鉴相器， 与所述下变频混频器相连， 用于根据所述下 变频混频器发送的中频模拟信号生成第一信号相位脉沖信号，再将所述第 一信号相位脉沖信号发送至所述相位码生成器。
所述相位码生成器， 与所述鉴相器相连， 用于将作为脉沖信号的所述 第一信号相位脉沖信号转换为作为数字信号的第一信号相位数字编码，再 将所述第一信号相位数字编码发送至所述误码矩阵纠错器，所述相位码生 成器为一种用于将脉沖信号转换为数字信号的编码器。
所述误码矩阵纠错器， 与所述鉴相器和所述相位码生成器相连， 还用 于根据所述第一信号相位数字编码生成相位纠错控制信号，再将所述相位 纠错控制信号发送至所述鉴相器。
所述鉴相器，用于根据所述相位纠错控制信号对所述第一信号相位脉 沖信号进行纠错， 以生成第二信号相位脉沖信号。 所述相位码生成器，还用于将所述第二信号相位脉沖信号转换为第二 信号相位数字编码，以使所述发射机将所述第二信号相位数字编码作为进 行了载波恢复及载波生成后的信号相位数字编码。
所述功分器， 与所述下变频混频器、 所述鉴幅器和所述鉴相器相连， 用于接收所述前端变频模块发送的所述中频模拟信号，并将所述中频模拟 信号分为两路相同的中频模拟信号，再将这两路相同的中频模拟信号分别 发送至所述鉴幅器和所述鉴相器，以便于所述鉴幅器根据所述功分器发出 的其中一路中频模拟信号生成所述第一信号幅度脉沖信号，并以便于所述 鉴相器根据所述功分器发出的另一路中频模拟信号生成所述第一信号相 位脉沖信号。
所述调制器， 与所述相位码生成器和所述幅度码生成器相连， 用于根 据所述第二信号相位数字编码和所述第二信号幅度数字编码生成另一路 中频模拟信号。
所述上变频混频器， 与所述本振频率源和所述调制器相连， 用于根据 所述调制器生成的中频模拟信号和所述本振频率源输出的射频信号，重新 生成射频信号， 并将重新生成的射频信号发送至所述功率放大器。
所述发射天线， 与所述功率放大器相连， 用于将经过所述功率放大器 处理后的所述重新生成的射频信号发送，所述功率放大器与所述上变频混 频器相连。
具体的， 在本实施例中， 如图 3a所示， 可以包括： 下变频混频器 31、 鉴幅器 32、 幅度码生成器 33、 误码矩阵纠错器 34、 本振频率源 35 , 其中： 所述下变频混频器 31与所述本振频率源 35相连，将从所述本振频率源 35获取的待发送的射频信号转换为中频模拟信号，再将所述中频模拟信号 发送至所述鉴幅器 32。
所述鉴幅器 32与所述下变频混频器 31相连，所述鉴幅器 32根据所述下 变频混频器 31发送的中频模拟信号生成第一信号幅度脉沖信号，再将所述 第一信号幅度脉沖信号发送至所述幅度码生成器 33。 所述幅度码生成器 33与所述鉴幅器 32相连，所述幅度码生成器 33将所 述第一信号幅度脉沖信号转换为第一信号幅度数字编码，再将所述第一信 号幅度数字编码发送至所述误码矩阵纠错器 34。
所述误码矩阵纠错器 34与所述鉴幅器 32相连，所述误码矩阵纠错器 34 根据所述第一信号幅度数字编码生成幅度纠错控制信号，再将所述幅度纠 错控制信号发送至所述鉴幅器 32。
所述鉴幅器 32根据所述幅度纠错控制信号对所述第一信号幅度脉沖 信号进行纠错， 以生成第二信号幅度脉沖信号。
所述幅度码生成器 33将所述第二信号幅度脉沖信号转换为第二信号 幅度数字编码，以使所述发射机将所述第二信号幅度数字编码作为进行了 载波恢复及载波生成后的信号幅度数字编码。
进一步的， 本实施例中所述的发射机， 如图 3b所示， 还可以包括： 功 分器 36、 鉴相器 37、 相位码生成器 38 , 其中：
所述鉴相器 37与所述下变频混频器 31相连，所述鉴相器 37根据所述下 变频混频器 31发送的中频模拟信号生成第一信号相位脉沖信号，再将所述 第一信号相位脉沖信号发送至所述相位码生成器 38。
所述相位码生成器 38与所述鉴相器 37相连，所述相位码生成器 38将所 述第一信号相位脉沖信号转换为第一信号相位数字编码，再将所述第一信 号相位数字编码发送至所述误码矩阵纠错器 34。
所述误码矩阵纠错器 34与所述鉴相器 37相连，所述误码矩阵纠错器 34 根据所述第一信号相位数字编码生成相位纠错控制信号，再将所述相位纠 错控制信号发送至所述鉴相器 37。
所述鉴相器 37根据所述相位纠错控制信号对所述第一信号相位脉沖 信号进行纠错， 以生成第二信号相位脉沖信号。
所述相位码生成器 38将所述第二信号相位脉沖信号转换为第二信号 相位数字编码，以使所述发射机将所述第二信号相位数字编码作为进行了 载波恢复及载波生成后的信号相位数字编码。 所述功分器 36与所述下变频混频器 31、 所述鉴幅器 32、 所述鉴相器 37 相连， 所述功分器 36接收所述前端变频模块发送的所述中频模拟信号， 并 将所述中频模拟信号分为两路相同的中频模拟信号，再将这两路相同的中 频模拟信号分别发送至所述鉴幅器 32和所述鉴相器 37 ,以便于所述鉴幅器 32根据其中一路中频模拟信号生成所述第一信号幅度脉沖信号，并以便于 所述鉴相器 37同时根据其中的另一路中频模拟信号生成所述第一信号相 位脉沖信号。
再进一步的， 本实施例中所述的发射机， 如图 3c所示， 还可以包括： 调制器 39、 增益控制放大器 310、 上变频混频器 311、 功率放大器 312、 发 射天线 313 , 其中：
所述调制器 30与所述相位码生成器 38和所述幅度码生成器 33相连，所 述调制器 30根据所述第二信号相位数字编码和所述第二信号幅度数字编 码生成另一路中频模拟信号。
所述上变频混频器 311与所述本振频率源 35和所述调制器 39相连， 所 述上变频混频器 311根据所述调制器 39生成的中频模拟信号和所述本振频 率源 35输出的射频信号， 重新生成射频信号， 并将重新生成的射频信号发 送至所述功率放大器 312。
所述发射天线 313与所述功率放大器 312相连， 所述功率放大器 312与 所述上变频混频器 311相连， 所述发射天线 313将经过所述功率放大器 312 处理后的所述重新生成的射频信号发送。
需要说明的是， 在图 3c中的緩沖器 5和緩沖器 6 , 与图 2c中的緩沖器 1 和緩沖器 2作用和执行方式相同， 都是对所緩存的信号幅度数字编码和相 位数字编码进行同步和刷新。
进一步需要说明的是， 在图 3c中还包括緩沖器 3和緩沖器 4 , 可以接收 并緩存基带芯片发送的信号， 并将所緩存的信号传输至调制器 39。 其中， 基带芯片 緩沖器 3/緩沖器 4 调制器 39的信号传输手段以及信号处理方 式可以为本领域技术人员所熟知的方式。 通过已有技术手段。
对本实施例有益效果的分析：
本发明实施例通过在发射机的射频电路的前端加入了误码矩阵纠错 器、 鉴幅器、 鉴相器、 幅度码生成器、 相位码生成器等元件， 使得接收机 /发射机可以通过误码矩阵纠错器将射频电路中的信号幅度数字编码、 信 号相位数字编码、以及频率源相位数字编码与误码矩阵纠错器中预存的标 准码源进行对比， 并对射频电路中的信号幅度数字编码、信号相位数字编 码、 以及频率源相位数字编码进行纠错， 从而在射频电路中完成了载波恢 复、 载波生成。
与现有技术相比， 基带芯片不必再为载波恢复、 载波生成， 尤其是与 载波恢复相关的频偏抑制、 相噪抑制等功能消耗运算资源， 从而精筒了基 带芯片的功能， 降低了基带芯片功耗， 并且由于基带芯片不必再承担载波 恢复、 载波生成这种需要执行复杂运算流程的功能， 从而降低了制造基带 芯片的工艺复杂度和设计难度， 这将直接降低基带芯片的制造成本， 进一 步降低基带芯片的运行 /使用成本。
实施例 3
本发明实施例提供一种射频信号接收方法， 由接收机执行， 如图 4a 所示， 包括：
401 , 接收机接收射频信号， 并将所获取的射频信号转换为中频模拟 信号。
402 , 根据所述中频模拟信号生成第一信号幅度脉沖信号。
403 , 将所述第一信号幅度脉沖信号转换为第一信号幅度数字编码。
404 , 根据所述第一信号幅度数字编码生成幅度纠错控制信号， 并根 据所述幅度纠错控制信号对所述第一信号幅度脉沖信号进行纠错，以生成 第二信号幅度脉沖信号。
405 , 将所述第二信号幅度脉沖信号转换为第二信号幅度数字编码， 并将所述第二信号幅度数字编码作为进行了载波恢复及载波生成后的信 号幅度数字编码。
并列的， 如图 4b所示， 本实施例提供的射频信号接收方法， 还可以包 括：
406,所述接收机将所述中频模拟信号分为两路相同的中频模拟信号。
407, 根据所述中频模拟信号生成第一信号相位脉沖信号。
408, 将所述第一信号相位脉沖信号转换为第一信号相位数字编码。
409, 根据所述第一信号相位数字编码生成相位纠错控制信号， 并根 据所述相位纠错控制信号对所述第一信号相位脉沖信号进行纠错，以生成 第二信号相位脉沖信号。
410, 将所述第二信号相位脉沖信号转换为第二信号相位数字编码， 并将所述第二信号相位数字编码作为进行了载波恢复及载波生成后的信 号相位数字编码。
进一步的，如图 4c所示，本实施例提供的射频信号接收方法，还包括：
411, 所述接收机将所述中频模拟信号进行上变频， 以产生另一路射 频信号。
412, 根据所述另一路射频信号和所述接收机中的本振频率源输出的 射频信号， 进行相位误差判断并获取本振频率源相位误差模拟信号。
413, 将所述本振频率源相位误差模拟信号转换为本振频率源相位误 差数字编码。
414, 根据所述本振频率源相位误差数字编码生成纠错控制信号。
415, 根据所述纠错控制信号对本振信号相位数字编码进行纠错。 本实施例能够在接收机的射频电路部分就实现载波恢复、载波生成的 功能， 与现有技术相比， 基带芯片不必再进行载波恢复、 载波生成， 尤其 是不必再承担与载波恢复相关的频偏抑制、 相噪抑制等功能消耗运算资 源， 从而精筒了基带芯片的功能， 降低了基带芯片功耗， 并且由于基带芯 片不必再承担载波恢复、 载波生成这种需要执行复杂运算流程的功能， 从 而降低了制造基带芯片的工艺复杂度和设计难度，这将直接降低基带芯片 的制造成本， 进一步降低基带芯片的运行 /使用成本。
实施例 4
本发明实施例提供一种射频信号发射方法， 由发射机执行， 如图 5a 所示， 包括：
501, 发射机将待发送的射频信号转换为中频模拟信号。
502, 根据所述中频模拟信号生成第一信号幅度脉沖信号。
503, 将所述第一信号幅度脉沖信号转换为第一信号幅度数字编码。
504, 根据所述第一信号幅度数字编码生成幅度纠错控制信号， 并根 据所述幅度纠错控制信号对所述第一信号幅度脉沖信号进行纠错，以生成 第二信号幅度脉沖信号。
505, 将所述第二信号幅度脉沖信号转换为第二信号幅度数字编码， 以使所述发射机将所述第二信号幅度数字编码作为进行了载波恢复及载 波生成后的信号幅度数字编码。
并列的， 如图 5b所示， 本实施例提供的射频信号发射方法， 在将待发 送的射频信号转换为中频模拟信号后， 还包括：
507,所述发射机将所述中频模拟信号分为两路相同的中频模拟信号。
508, 根据所述中频模拟信号生成第一信号相位脉沖信号。
509, 将所述第一信号相位脉沖信号转换为第一信号相位数字编码。
510, 根据所述第一信号相位数字编码生成相位纠错控制信号， 并根 据所述相位纠错控制信号对所述第一信号相位脉沖信号进行纠错，以生成 第二信号相位脉沖信号。
511, 将所述第二信号相位脉沖信号转换为第二信号相位数字编码。 进一步的，如图 5c所示，本实施例提供的射频信号发射方法，还包括：
511, 所述发射机根据所述第二信号相位数字编码和所述第二信号幅 度数字编码生成另一路中频模拟信号。
512, 根据所生成的另一路中频模拟信号和所述发射机中的本振频率 源输出的射频信号， 重新生成射频信号。 5 1 3 , 对所述重新生成射频信号进行功率放大后， 发送所述重新生成 射频信号。
本实施例能够在发射机的射频电路部分就实现载波恢复、载波生成的 功能， 与现有技术相比， 基带芯片不必再进行载波恢复、 载波生成， 尤其 是不必再承担与载波恢复相关的频偏抑制、 相噪抑制等功能消耗运算资 源， 从而精筒了基带芯片的功能， 降低了基带芯片功耗， 并且由于基带芯 片不必再承担载波恢复、 载波生成这种需要执行复杂运算流程的功能， 从 而降低了制造基带芯片的工艺复杂度和设计难度，这将直接降低基带芯片 的制造成本， 进一步降低基带芯片的运行 /使用成本。
实施例 5
本发明实施例提供一种射频信号收发系统， 如图 6 a所示， 包括： 接收机 61和发射机 62。
其中， 在本实施例所述的射频信号收发系统中， 包括了实施例 1所述 的接收机和实施例 2所述的发射机。
在本实施例中，接收机 61和发射机 62可以通过无线网络进行射频信号 的发送与接收， 具体实现方式可以是本领域技术人员所熟知的任意方式。
需要说明的是，本实施例所述的射频信号收发系统中的其中一端可以 同时具备接收机和发射机这二种功能， 即可以将实施例 1所述的接收机和 实施例 2所述的发射机集成在同一个射频电路中， 并且， 本领域技术人员 可以通过惯用的技术手段使误码矩阵纠错器同时承担在发射机和接收机 中的功能， 从而使这一个射频电路同时具备实施例 1所述的接收机和实施 例 2所述的发射机的功能， 例如： 如图 6 b所示，
发射机和接收机的射频电路集成在了一起，并且共用一个误码矩阵纠 错器， 并且图 6b所示的与基带芯片相连的射频电路进行载波恢复、 载波生 成的具体方式可以与前述的实施例相同。
进一步的， 如图 6 c所示， 在图 6b所示的射频电路中还包括 2个滤波器， 这 2个滤波器分别对流经接收天线或发射天线的信号进行干扰消除， 在本 实施例中，利用滤波器进行干扰消除的具体实施方式可以为本领域技术人 员所熟知的方式。
再进一步的， 如图 6d所示， 在图 6 b所示的射频电路中还包括 1个双工 器，这个双工器可以对流经收发天线的信号进行干扰消除，在本实施例中， 的方式。
本实施例能够在射频信号收发系统中的发射机 /接收机的射频电路部 分就实现载波恢复、 载波生成的功能， 与现有技术相比， 射频信号收发系 统基带芯片不必再进行载波恢复、 载波生成， 尤其是不必再承担与载波恢 复相关的频偏抑制、相噪抑制等功能消耗运算资源， 从而精筒了基带芯片 的功能， 降低了基带芯片功耗， 从而降低了发射机 /接收机的运行功耗， 同时也就降低了包括了上述发射机 /接收机的射频信号收发系统的功耗， 节约了电能， 从而降低了整个系统运行成本。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分 流程， 是可以通过计算机程序来指令相关的硬件来完成， 所述的程序可存 储于一计算机可读取存储介质中， 该程序在执行时， 可包括如上述各方法 的实施例的流程。 其中， 所述的存储介质可为磁碟、 光盘、 只读存储记忆 体 ( Read-On l y Memo r y , ROM )或随机存储记忆体 ( Random Ac ce s s Memo r y , RAM ) 等。
以上所述，仅为本发明的具体实施方式， 但本发明的保护范围并不局 限于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可 轻易想到的变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发 明的保护范围应该以权利要求的保护范围为准。

Claims

权 利 要 求 书
1、 一种接收机， 其特征在于， 包括： 接收天线、 前端变频模块、 鉴幅 器、 幅度码生成器、 误码矩阵纠错器， 其中：
所述前端变频模块， 用于从所述接收天线获取射频信号， 并将所获取 的射频信号转换为中频模拟信号， 再将所述中频模拟信号发送至所述鉴幅 器， 所述前端变频模块包括： 低噪声放大器、 下变频混频器、 增益控制放 大器；
所述鉴幅器， 与所述前端变频模块相连， 用于根据所述前端变频模块 发送的中频模拟信号生成第一信号幅度脉沖信号， 再将所述第一信号幅度 脉沖信号发送至所述幅度码生成器；
所述幅度码生成器， 与所述鉴幅器相连， 用于将作为脉沖信号的所述 第一信号幅度脉沖信号转换为作为数字信号的第一信号幅度数字编码， 再 将所述第一信号幅度数字编码发送至所述误码矩阵纠错器， 所述幅度码生 成器为一种用于将脉沖信号转换为数字信号的编码器；
所述误码矩阵纠错器， 与所述鉴幅器和所述幅度码生成器相连， 用于 根据所述第一信号幅度数字编码生成幅度纠错控制信号， 再将所述幅度纠 错控制信号发送至所述鉴幅器；
所述鉴幅器， 用于根据所述幅度纠错控制信号对所述第一信号幅度脉 沖信号进行纠错， 以生成第二信号幅度脉沖信号；
所述幅度码生成器， 还用于将所述第二信号幅度脉沖信号转换为第二 信号幅度数字编码， 以使所述接收机将所述第二信号幅度数字编码作为进 行了载波恢复及载波生成后的信号幅度数字编码。
2、 根据权利要求 1所述的接收机， 其特征在于， 还包括： 鉴相器、 相 位码生成器， 其中：
所述鉴相器， 与所述前端变频模块相连， 用于根据所述前端变频模块 发送的中频模拟信号生成第一信号相位脉沖信号， 再将所述第一信号相位 脉沖信号发送至所述相位码生成器；
所述相位码生成器， 与所述鉴相器相连， 用于将作为脉沖信号的所述 第一信号相位脉沖信号转换为作为数字信号的第一信号相位数字编码， 并 将所述第一信号相位数字编码发送至所述误码矩阵纠错器， 所述相位码生 成器为一种用于将脉沖信号转换为数字信号的编码器；
所述误码矩阵纠错器， 与所述鉴相器相连和所述相位码生成器相连， 用于根据所述第一信号相位数字编码生成相位纠错控制信号， 再将所述相 位纠错控制信号发送至所述鉴相器；
所述鉴相器， 用于根据所述相位纠错控制信号对所述第一信号相位脉 沖信号进行纠错， 以生成第二信号相位脉沖信号；
所述相位码生成器， 还用于将所述第二信号相位脉沖信号转换为第二 信号相位数字编码， 以使所述接收机将所述第二信号相位数字编码作为进 行了载波恢复及载波生成后的信号相位数字编码。
3、 根据权利要求 1或 2所述的接收机， 其特征在于， 还包括： 功分器， 其中：
所述功分器， 与所述前端变频模块、 所述鉴幅器和所述鉴相器相连， 用于接收所述前端变频模块发送的所述中频模拟信号， 并将所述中频模拟 信号分为两路相同的中频模拟信号， 再将这两路相同的中频模拟信号分别 发送至所述鉴幅器和所述鉴相器， 以便于所述鉴幅器根据所述功分器发出 的其中一路中频模拟信号生成所述第一信号幅度脉沖信号， 所述鉴相器根 据所述功分器发出的另一路中频模拟信号生成所述第一信号相位脉沖信 号。
4、 根据权利要求 1所述的接收机， 其特征在于， 还包括： 上变频混频 器、 本振频率源、 频率源相位码生成器， 其中：
所述上变频混频器， 与所述前端变频模块相连， 用于将所述前端变频 模块发送的中频模拟信号进行上变频， 以产生另一路射频信号；
所述频率源鉴相器， 与所述本振频率源和所述上变频混频器相连， 用 于根据所述上变频混频器产生的射频信号与所述本振频率源输出的射频信 号， 进行相位误差判断并获取本振频率源相位误差模拟信号；
所述频率源相位码生成器， 与所述频率源鉴相器相连， 用于接收所述 本振频率源相位误差模拟信号， 并将所述本振频率源相位误差模拟信号转 换为本振频率源相位误差数字编码；
所述误码矩阵纠错器， 与所述频率源相位码生成器相连， 用于接收所 述本振频率源相位误差数字编码， 并根据所述本振频率源相位误差数字编 码生成纠错控制信号；
所述本振频率源， 与所述误码矩阵纠错器， 用于接收所述误码矩阵纠 错器发送的所述纠错控制信号， 并根据所述纠错控制信号对所述本振信号 相位数字编码进行纠错。
5、 根据权利要求 1或 4所述的接收机， 其特征在于， 所述上变频混频器 与所述前端变频模块中的所述增益控制放大器相连， 所述前端变频模块中 的下变频混频器与所述频率源鉴相器相连。
6、 一种发射机， 其特征在于， 包括： 下变频混频器、 鉴幅器、 幅度码 生成器、 误码矩阵纠错器、 本振频率源， 其中：
所述下变频混频器， 与所述本振频率源相连， 用于将从所述本振频率 源获取的待发送的射频信号转换为中频模拟信号， 再将所述中频模拟信号 发送至所述鉴幅器；
所述鉴幅器， 与所述下变频混频器相连， 用于根据所述下变频混频器 发送的中频模拟信号生成第一信号幅度脉沖信号， 再将所述第一信号幅度 脉沖信号发送至所述幅度码生成器；
所述幅度码生成器， 与所述鉴幅器相连， 用于将作为脉沖信号的所述 第一信号幅度脉沖信号转换为作为数字信号的第一信号幅度数字编码， 再 将所述第一信号幅度数字编码发送至所述误码矩阵纠错器， 所述幅度码生 成器为一种用于将脉沖信号转换为数字信号的编码器；
所述误码矩阵纠错器， 与所述鉴幅器和所述幅度码生成器相连， 用于 根据所述第一信号幅度数字编码生成幅度纠错控制信号， 再将所述幅度纠 错控制信号发送至所述鉴幅器；
所述鉴幅器， 还用于根据所述幅度纠错控制信号对所述第一信号幅度 脉沖信号进行纠错， 以生成第二信号幅度脉沖信号；
所述幅度码生成器， 还用于将所述第二信号幅度脉沖信号转换为第二 信号幅度数字编码， 以使所述发射机将所述第二信号幅度数字编码作为进 行了载波恢复及载波生成后的信号幅度数字编码。
7、 根据权利要求 6所述的发射机， 其特征在于， 还包括： 鉴相器、 相 位码生成器， 其中：
所述鉴相器， 与所述下变频混频器相连， 用于根据所述下变频混频器 发送的中频模拟信号生成第一信号相位脉沖信号， 再将所述第一信号相位 脉沖信号发送至所述相位码生成器；
所述相位码生成器， 与所述鉴相器相连， 用于将作为脉沖信号的所述 第一信号相位脉沖信号转换为作为数字信号的第一信号相位数字编码， 再 将所述第一信号相位数字编码发送至所述误码矩阵纠错器， 所述相位码生 成器为一种用于将脉沖信号转换为数字信号的编码器；
所述误码矩阵纠错器， 与所述鉴相器和所述相位码生成器相连， 用于 根据所述第一信号相位数字编码生成相位纠错控制信号， 再将所述相位纠 错控制信号发送至所述鉴相器；
所述鉴相器， 用于根据所述相位纠错控制信号对所述第一信号相位脉 沖信号进行纠错， 以生成第二信号相位脉沖信号；
所述相位码生成器， 还用于将所述第二信号相位脉沖信号转换为第二 信号相位数字编码， 以使所述发射机将所述第二信号相位数字编码作为进 行了载波恢复及载波生成后的信号相位数字编码。
8、 根据权利要求 6或 7所述的发射机， 其特征在于， 还包括： 功分器， 其中：
所述功分器， 与所述下变频混频器、 所述鉴幅器和所述鉴相器相连， 用于接收所述前端变频模块发送的所述中频模拟信号， 并将所述中频模拟 信号分为两路相同的中频模拟信号， 再将这两路相同的中频模拟信号分别 发送至所述鉴幅器和所述鉴相器， 以便于所述鉴幅器根据所述功分器发出 的其中一路中频模拟信号生成所述第一信号幅度脉沖信号， 并以便于所述 鉴相器根据所述功分器发出的另一路中频模拟信号生成所述第一信号相位 脉沖信号。
9、 根据权利要求 6所述的发射机， 其特征在于， 还包括： 调制器、 增 益控制放大器、 上变频混频器、 功率放大器、 发射天线， 其中：
所述调制器， 与所述相位码生成器和所述幅度码生成器相连， 用于根 据所述第二信号相位数字编码和所述第二信号幅度数字编码生成另一路中 频模拟信号；
所述上变频混频器， 与所述本振频率源和所述调制器相连， 用于根据 所述调制器生成的中频模拟信号和所述本振频率源输出的射频信号， 重新 生成射频信号， 并将重新生成的射频信号发送至所述功率放大器；
所述发射天线， 与所述功率放大器相连， 用于将经过所述功率放大器 处理后的所述重新生成的射频信号发送， 所述功率放大器与所述上变频混 频器相连。
10、 一种射频信号接收方法， 其特征在于， 包括：
接收机接收射频信号， 并将所获取的射频信号转换为中频模拟信号； 根据所述中频模拟信号生成第一信号幅度脉沖信号；
将所述第一信号幅度脉沖信号转换为第一信号幅度数字编码； 对所述第一信号幅度数字编码与误码矩阵纠错器中所存储的信号幅度 数字编码的标准码源进行比较， 生成幅度纠错控制信号， 并根据所述幅度 纠错控制信号对所述第一信号幅度脉沖信号进行纠错， 以生成第二信号幅 度脉沖信号；
将所述第二信号幅度脉沖信号转换为第二信号幅度数字编码， 并将所 述第二信号幅度数字编码作为进行了载波恢复及载波生成后的信号幅度数 字编码。
11、 根据权利要求 10所述的射频信号接收方法， 其特征在于， 还包括： 根据所述中频模拟信号生成第一信号相位脉沖信号；
将所述第一信号相位脉沖信号转换为第一信号相位数字编码； 根据所述第一信号相位数字编码与误码矩阵纠错器中所存储的信号相 位数字编码的标准码源进行比较， 生成相位纠错控制信号， 并根据所述相 位纠错控制信号对所述第一信号相位脉沖信号进行纠错， 以生成第二信号 相位脉沖信号；
将所述第二信号相位脉沖信号转换为第二信号相位数字编码， 并将所 述第二信号相位数字编码作为进行了载波恢复及载波生成后的信号相位数 字编码。
12、 根据权利要求 10或 11所述的射频信号接收方法， 其特征在于， 在 将所获取的射频信号转换为中频模拟信号后， 还包括：
将所述中频模拟信号分为两路相同的中频模拟信号， 以便于所述接收 机根据其中一路中频模拟信号生成所述第一信号幅度脉沖信号， 同时根据 其中的另一路中频模拟信号生成所述第一信号相位脉沖信号。
13、 根据权利要求 10所述的射频信号接收方法， 其特征在于， 还包括： 将所述中频模拟信号进行上变频， 以产生另一路射频信号；
根据所述另一路射频信号和所述接收机中的本振频率源输出的射频信 号， 进行相位误差判断并获取本振频率源相位误差模拟信号；
将所述本振频率源相位误差模拟信号转换为本振频率源相位误差数字 编码；
根据所述本振频率源相位误差数字编码和误码矩阵纠错器中所存储的 本振信号相位数字编码的标准码源进行比较， 生成纠错控制信号；
根据所述纠错控制信号对所述本振信号相位数字编码进行纠错。
1 4、 一种射频信号发射方法， 其特征在于， 包括：
发射机将待发送的射频信号转换为中频模拟信号； 根据所述中频模拟信号生成第一信号幅度脉沖信号；
将所述第一信号幅度脉沖信号转换为第一信号幅度数字编码； 根据所述第一信号幅度数字编码生成幅度纠错控制信号， 并根据所述 幅度纠错控制信号对所述第一信号幅度脉沖信号进行纠错， 以生成第二信 号幅度脉沖信号；
将所述第二信号幅度脉沖信号转换为第二信号幅度数字编码， 以使所 述发射机将所述第二信号幅度数字编码作为进行了载波恢复及载波生成后 的信号幅度数字编码。
1 5、 根据权利要求 14所述的射频信号发射方法， 其特征在于， 还包括： 根据所述中频模拟信号生成第一信号相位脉沖信号；
将所述第一信号相位脉沖信号转换为第一信号相位数字编码； 根据所述第一信号相位数字编码生成相位纠错控制信号， 并根据所述 相位纠错控制信号对所述第一信号相位脉沖信号进行纠错， 以生成第二信 号相位脉沖信号；
将所述第二信号相位脉沖信号转换为第二信号相位数字编码， 以使所 述发射机将所述第二信号相位数字编码作为进行了载波恢复及载波生成后 的信号相位数字编码。
1 6、 根据权利要求 14或 1 5所述的射频信号发射方法， 其特征在于， 在 将待发送的射频信号转换为中频模拟信号后， 还包括：
将所述中频模拟信号分为两路相同的中频模拟信号， 以便于所述发射 机根据其中一路中频模拟信号生成所述第一信号幅度脉沖信号， 同时根据 其中的另一路中频模拟信号生成所述第一信号相位脉沖信号。
1 7、 根据权利要求 14所述的射频信号发射方法， 其特征在于， 还包括： 根据所述第二信号相位数字编码和所述第二信号幅度数字编码生成另 一路中频模拟信号；
根据所生成的另一路中频模拟信号和所述发射机中的本振频率源输出 的射频信号， 重新生成射频信号； 对所述重新生成射频信号进行功率放大后， 发送所述重新生成射频信号。
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WO2015103692A1 (en) * 2014-01-09 2015-07-16 Gestion Valeo Societe En Commandite (Valeo Management L.P.) Systems relating to ultra wideband broad casting comprising dynamic frequency and bandwidth hopping
CN104158552B (zh) * 2014-08-01 2016-11-23 华为技术有限公司 零中频发射机、接收机及相关方法和系统
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CN114026802B (zh) * 2019-06-28 2023-01-06 华为技术有限公司 一种用于校正多个传输通道间偏差的装置及无线通信设备
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101662822A (zh) * 2009-09-28 2010-03-03 西安交通大学 一种基于恒模信号的节能型无线通信收发机
US20100188148A1 (en) * 2009-01-26 2010-07-29 Texas Instruments Incorporated Predistortion mechanism for compensation of transistor size mismatch in a digital power amplifier
CN101848533A (zh) * 2010-04-28 2010-09-29 广州市广晟微电子有限公司 一种td-scdma终端射频自环自动增益控制方法
CN102035611A (zh) * 2010-12-29 2011-04-27 武汉邮电科学研究院 远端射频单元多天线实时校准系统及其方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4458356A (en) * 1982-07-02 1984-07-03 Bell Telephone Laboratories, Incorporated Carrier recovery circuit
US6255906B1 (en) * 1999-09-30 2001-07-03 Conexant Systems, Inc. Power amplifier operated as an envelope digital to analog converter with digital pre-distortion
US7027789B2 (en) 2000-09-11 2006-04-11 Xytrans, Inc. Self-tuned millimeter wave RF transceiver module
US8000428B2 (en) 2001-11-27 2011-08-16 Texas Instruments Incorporated All-digital frequency synthesis with DCO gain calculation
CN101383647B (zh) * 2007-09-06 2012-01-11 电信科学技术研究院 对工作天线进行校准的方法及装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100188148A1 (en) * 2009-01-26 2010-07-29 Texas Instruments Incorporated Predistortion mechanism for compensation of transistor size mismatch in a digital power amplifier
CN101662822A (zh) * 2009-09-28 2010-03-03 西安交通大学 一种基于恒模信号的节能型无线通信收发机
CN101848533A (zh) * 2010-04-28 2010-09-29 广州市广晟微电子有限公司 一种td-scdma终端射频自环自动增益控制方法
CN102035611A (zh) * 2010-12-29 2011-04-27 武汉邮电科学研究院 远端射频单元多天线实时校准系统及其方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2906000A4 *

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