WO2015067034A1 - 一种零中频信号的修正方法及装置、存储介质 - Google Patents
一种零中频信号的修正方法及装置、存储介质 Download PDFInfo
- Publication number
- WO2015067034A1 WO2015067034A1 PCT/CN2014/078316 CN2014078316W WO2015067034A1 WO 2015067034 A1 WO2015067034 A1 WO 2015067034A1 CN 2014078316 W CN2014078316 W CN 2014078316W WO 2015067034 A1 WO2015067034 A1 WO 2015067034A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- signal
- digital baseband
- analog
- baseband signal
- channel
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000012937 correction Methods 0.000 title claims abstract description 13
- 238000006243 chemical reaction Methods 0.000 claims abstract description 25
- 238000005070 sampling Methods 0.000 claims abstract description 12
- 238000004590 computer program Methods 0.000 claims description 6
- 230000005540 biological transmission Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 238000001228 spectrum Methods 0.000 description 7
- 238000012545 processing Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
- H04B1/0028—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at baseband stage
Definitions
- the present invention relates to a wireless communication technology, and in particular, to a method and apparatus for correcting a zero intermediate frequency signal, and a storage medium. Background technique
- Figure 1 is a schematic diagram of the architecture of a classic digital zero-IF transmitter in the prior art.
- the classical digital zero-IF transmitter architecture mixes the output signal of the analog circuit into part of the dc, and the main cause of dc is the presence of local oscillator leakage during the analog mixing process.
- digital to analog converter usually, digital to analog converter
- FIG. 2 shows the power spectrum of the DAC ingress signal in the classic digital zero-IF transmitter architecture. It can be seen from Figure 2 that the center of the spectrum is at zero frequency. However, high-order modulation transmission systems require high DC residual current at zero frequency, and generally require an error peak of less than -40db at zero frequency. However, if only DAC is used for DC compensation, there will usually be a comparison at zero frequency. Large residual error, where the error peak is generally -25db - 30db, and this error amount will be larger for high-order modulation transmission systems such as QAM, Quadrature Amplitude Modulation, and QAM above 128. influences. Summary of the invention
- an embodiment of the present invention provides a method and apparatus for correcting a zero-IF signal, and a storage medium, which can improve the performance of a high-order modulation transmission system and improve the randomness of a zero-IF transmitter.
- An embodiment of the present invention provides a method for correcting a zero intermediate frequency signal, where the method includes: when receiving an I digital baseband signal to be transmitted and a Q digital baseband signal, the digitally controlled oscillator NCO pairs the I to be transmitted The digital baseband signal and the Q digital baseband signal are frequency-converted, and the converted I-channel digital baseband signal and the Q-channel digital baseband signal are output;
- the carrier frequency of the converted I-channel digital baseband signal and the Q-channel digital baseband signal is much smaller than the baseband sampling frequency.
- the method further includes:
- performing IQ modulation on the I-channel analog signal and the Q-channel analog signal comprises: up-converting the I-channel analog signal and the Q-channel analog signal.
- the up-converting the I-channel analog signal and the Q-channel analog signal include:
- the NCO converts the I-channel digital baseband signal and the Q-channel digital baseband signal to be transmitted to the first threshold Y, the carrier frequency of the I-channel converted analog signal and the Q-channel analog signal is converted to X-Y;
- X is the carrier frequency of the analog IF signal to be output, and Y is less than X.
- the up-converting the I-channel analog signal and the Q-channel analog signal further includes:
- the carrier frequency of the DAC-converted I-channel analog signal and the Q-channel analog signal is up-converted to X+N; Where X is the carrier frequency of the analog intermediate frequency signal to be output, and N is less than X.
- An embodiment of the present invention further provides a device for correcting a zero intermediate frequency signal, the device comprising a digitally controlled oscillator NCO configured to receive an I-channel digital baseband signal and a Q-channel digital baseband signal to be transmitted, The transmitted I-channel digital baseband signal and the Q-channel digital baseband signal are frequency-converted, and the converted I-channel digital baseband signal and the Q-channel digital baseband signal are output;
- a digitally controlled oscillator NCO configured to receive an I-channel digital baseband signal and a Q-channel digital baseband signal to be transmitted, The transmitted I-channel digital baseband signal and the Q-channel digital baseband signal are frequency-converted, and the converted I-channel digital baseband signal and the Q-channel digital baseband signal are output;
- the carrier frequency of the converted I-channel digital baseband signal and the Q-channel digital baseband signal is much smaller than the baseband sampling frequency.
- the device further includes a digital-to-analog converter DAC and an analog up-conversion module; wherein the DAC is configured to convert the converted I-channel digital baseband signal and the Q-channel digital baseband signal into an I-channel analog signal and Q Road analog signal;
- the analog up-conversion module is configured to perform IQ modulation on the I-channel analog signal and the Q-channel analog signal and output an analog intermediate frequency signal.
- the analog up-conversion module is further configured to up-convert the I-channel analog signal and the Q-channel analog signal.
- the analog up-conversion module is further configured to convert the DAC-converted I-channel analog signal and the Q-channel when the NCO converts the I-channel digital baseband signal and the Q-channel digital baseband signal to be transmitted to the first threshold Y.
- the carrier frequency of the analog signal is upconverted to XY;
- X is the carrier frequency of the analog IF signal to be output, and Y is less than X.
- the analog up-conversion module is further configured to convert the DAC-converted I-channel analog signal and Q when the NCO converts the I-channel digital baseband signal and the Q-channel digital baseband signal to be transmitted to the second threshold-N.
- the carrier frequency of the analog signal is upconverted to X+N;
- X is the carrier frequency of the analog IF signal to be output, and ⁇ is less than X.
- a storage medium having a computer program stored therein, the computer program being configured to perform the aforementioned method of correcting a zero intermediate frequency signal.
- the method and device for correcting the zero intermediate frequency signal solve the problem due to the high
- the order modulation transmission system has a high requirement for DC residual at zero frequency and a large DC residual after DC to DC.
- the zero intermediate frequency signal is corrected by using a digitally controlled oscillator (NCO, Number Controlled Oscillator), that is, the digital baseband signal is subjected to a small spectrum shift before entering the DAC, and the DAC still uses the baseband sample.
- NCO Number Controlled Oscillator
- the mode is sampled, which can reduce the peak error at zero frequency to below -55db, avoiding the influence of excessive peak error on the high-order modulation system, improving the randomness of the zero-IF transmitter, and greatly improving the high-order. Modulate the performance of the transmission system.
- FIG. 1 is a schematic diagram of a classic digital zero intermediate frequency transmitter architecture in the prior art
- FIG. 2 is a schematic diagram of a power spectrum of a DAC ingress signal in a classic digital zero-IF transmitter architecture
- FIG. 3 is a schematic flowchart of an implementation of a method for correcting a zero-IF signal according to an embodiment of the present invention
- FIG. 4 is a schematic diagram of a zero-IF signal correction apparatus according to an embodiment of the present invention
- FIG. 5 is a schematic structural diagram of a zero intermediate frequency transmitter according to an embodiment of the present invention
- FIG. 3 is a schematic flowchart of a method for correcting a zero-IF signal according to an embodiment of the present invention. As shown in FIG. 3, the process includes the following steps:
- Step 301 When receiving the I-channel digital baseband signal and the Q-channel digital baseband signal to be transmitted, the digitally controlled oscillator NCO performs frequency conversion on the I-channel digital baseband signal to be transmitted and the Q-channel digital baseband signal.
- the NCO Before transmitting the I-channel digital baseband signal and the Q-channel digital baseband signal to be transmitted to the DAC, the NCO inputs the I-channel digital baseband signal and the Q-channel digital baseband signal to be transmitted. Line frequency conversion.
- the carrier frequency of the converted I-channel digital baseband signal and the Q-channel digital baseband signal is much smaller than the baseband sampling frequency of the DAC.
- Step 302 Output the converted digital baseband signal and the Q digital baseband signal after the frequency conversion.
- the carrier frequency of the I-channel digital baseband signal and the Q-channel digital baseband signal converted by the NCO is much smaller than the baseband sampling frequency of the DAC, so that the DAC can be sampled in the baseband sampling mode.
- the method further includes:
- performing IQ modulation on the I-channel analog signal and the Q-channel analog signal includes: up-converting the I-channel analog signal and the Q-channel analog signal.
- the up-converting the I-channel analog signal and the Q-channel analog signal include:
- the NCO converts the I-channel digital baseband signal and the Q-channel digital baseband signal to be transmitted to the first threshold Y, the carrier frequency of the I-channel converted analog signal and the Q-channel analog signal is converted to X-Y;
- X is the carrier frequency of the analog IF signal to be output.
- the Y is a carrier frequency of the converted I-channel analog signal and the Q-channel analog signal, wherein Y is a positive value and Y is smaller than X.
- the up-converting the I-channel analog signal and the Q-channel analog signal further includes: When the NCO converts the I-channel digital baseband signal and the Q-channel digital baseband signal to be transmitted to the second threshold-N, the carrier frequency of the DAC-converted I-channel analog signal and the Q-channel analog signal is up-converted to X+N;
- X is the carrier frequency of the analog IF signal to be output.
- the N is a carrier frequency of the converted I-channel analog signal and the Q-channel analog signal, where N is a positive value and N is less than X.
- FIG. 4 is a schematic structural diagram of a device for correcting a zero-IF signal according to an embodiment of the present invention. As shown in FIG. 4, the device includes:
- the NCO 41 configured to receive the I-channel digital baseband signal and the Q-channel digital baseband signal to be transmitted, perform frequency conversion on the I-channel digital baseband signal to be transmitted and the Q-channel digital baseband signal, and output the converted I-path Digital baseband signal and Q digital baseband signal;
- the carrier frequency of the converted I-channel digital baseband signal and the Q-channel digital baseband signal is much smaller than the baseband sampling frequency of the DAC.
- the device further includes a DAC 42 and an analog up-conversion module 43.
- the DAC 42 is configured to convert the converted I-channel digital baseband signal and the Q-channel digital baseband signal into an I-channel analog signal. And Q road analog signals;
- the analog up-conversion module 43 is configured to perform IQ modulation on the I-channel analog signal and the Q-channel analog signal and output an analog intermediate frequency signal.
- the analog up-conversion module 43 is further configured to up-convert the I-channel analog signal and the Q-channel analog signal.
- the analog up-conversion module 43 is further configured to convert the DAC-converted I-channel analog signal and Q when the NCO converts the I-channel digital baseband signal and the Q-channel digital baseband signal to be transmitted to the first threshold Y.
- the carrier frequency of the analog signal is upconverted to XY;
- X is the carrier frequency of the analog IF signal to be output.
- the Y is an I-channel analog signal after frequency conversion and a carrier frequency of the Q-channel analog signal Rate, where Y is a positive value and ⁇ is less than X.
- the analog up-conversion module 43 is further configured to: when the NCO converts the I-channel digital baseband signal and the Q-channel digital baseband signal to be transmitted to the second threshold- ⁇ , the DAC-converted I-channel analog signal and The carrier frequency of the Q channel analog signal is upconverted to ⁇ + ⁇ ;
- X is the carrier frequency of the analog IF signal to be output.
- the ⁇ is the carrier frequency of the converted I-channel analog signal and the Q-channel analog signal, where ⁇ is a positive value and ⁇ is less than X.
- the NC0 41, the DAC 42, and the analog up-conversion module 43 can each be an application processor (AP), a central processing unit (CPU), and a digital signal processor in the correction device of the zero-IF signal.
- AP application processor
- CPU central processing unit
- DSP Digital Signal Processor
- FPGA Field Programmable Gate Array
- the zero-IF transmitter architecture includes a baseband modulator 51, a zero-IF signal correcting device 52, and an intermediate frequency amplifier 53;
- the baseband modulator 51 is configured to modulate a baseband signal to generate an I-channel digital baseband signal and a Q-channel digital baseband signal;
- the method for generating the I-channel digital baseband signal and the Q-channel digital baseband signal by the baseband modulator 51 is the same as the method for generating the I-channel digital baseband signal and the Q-channel digital baseband signal in the prior art, and details are not described herein again.
- the zero intermediate frequency signal correction device 52 is configured to pair the I digital baseband signal and Q
- the digital baseband signal is converted, and the converted digital I baseband signal and the Q digital baseband signal are converted into an I analog signal and a Q analog signal are sent to the intermediate frequency amplifier 53;
- the intermediate frequency amplifier 53 is configured to amplify the analog intermediate frequency signal and output the amplified analog intermediate frequency signal.
- the correction device 52 of the zero intermediate frequency signal may be specifically configured as shown in FIG.
- the apparatus for correcting the zero intermediate frequency signal includes an NCO 41, a DAC 42 and an analog up-conversion module 43;
- the NCO 41 is configured to receive the I-channel digital baseband signal and the Q-channel digital baseband signal to be transmitted when the baseband modulator 51 transmits the I-channel digital baseband signal and the Q-channel digital baseband signal to be transmitted. And outputting the converted I-channel digital baseband signal and the Q-channel digital baseband signal to the DAC 42;
- the DAC 42 is configured to convert the converted I-channel digital baseband signal and the Q-channel digital baseband signal into an I-channel analog signal and a Q-channel analog signal, and send an I-channel analog signal and a Q-channel analog to the analog up-conversion module 43.
- the analog up-conversion module 43 is configured to perform IQ modulation on the I-channel analog signal and the Q-channel analog signal and output an analog intermediate frequency signal to the intermediate frequency amplifier 53.
- Figure 6 as can be seen from Figure 6:
- the center frequency of the baseband signal of the zero-IF transmitter architecture shown in Figure 5 is 2.5M, instead of the center frequency of the baseband signal in the classical zero-IF transmitter architecture shown in Figure 2.
- the digital baseband signal is subjected to a smaller spectrum shift before entering the DAC.
- the embodiment of the invention further describes a storage medium, wherein the storage medium stores a computer program, and the computer program is configured to perform the method for correcting the zero intermediate frequency signal of the foregoing embodiment.
- the zero intermediate frequency signal is corrected by using a digitally controlled oscillator (NCO, Number Controlled Oscillator), that is, the digital baseband signal is subjected to a small spectrum shift before entering the DAC, and the DAC still uses the baseband sample.
- NCO Number Controlled Oscillator
- the mode is sampled, which can reduce the peak error at zero frequency to below -55db, avoiding the influence of excessive peak error on the high-order modulation system, improving the randomness of the zero-IF transmitter, and greatly improving the high-order. Modulate the performance of the transmission system.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Transmitters (AREA)
Abstract
本发明公开了一种零中频信号的修正方法及装置，其中，所述零中频信号的修正方法包括：在将待传输的I路数字基带信号和Q路数字基带信号发送至数模转换器（DAC）之前，利用数字控制振荡器（NCO）对所述待传输的I路数字基带信号和Q路数字基带信号进行变频；其中，变频后的I路数字基带信号和Q路数字基带信号的载波频率远小于DAC的基带采样频率。
Description
一种零中频信号的修正方法及装置、 存储介质 技术领域
本发明涉及无线通信技术， 尤其涉及一种零中频信号的修正方法及装 置、 存储介质。 背景技术
图 1 为现有技术中经典数字零中频发射机架构示意图。 一般情况下， 经典数字零中频发射机架构会使模拟电路的输出信号混入部分直流， 而产 生直流的主要原因是模拟混频过程中存在本振泄露。 通常， 数模转换器
( DAC, Digital to Analog Converter ) 自身具有去直流的功能， 且 DAC是 使用一种类似于盲估计的方法来进行去直流补偿的。 图 2 为经典数字零中 频发射机架构中 DAC入口信号功率谱示意图， 由图 2中可以看出： 频谱的 中心位置在零频处。 但是， 高阶调制传输系统在零频处对直流残留量要求 高， 一般要求在零频处的误差峰值达到 -40db 以下； 而如果仅仅釆用 DAC 进行直流补偿， 在零频处通常会有较大的残留误差， 其中， 误差峰值一般 为 -25db— 30db， 而这种误差量对 128 数字调制器 （ QAM， Quadrature Amplitude Modulation )、及 128 以上的 QAM等高阶调制传输系统会产生较 大的影响。 发明内容
为解决上述技术问题， 本发明实施例提供一种零中频信号的修正 方法及装置、 存储介质， 能改善高阶调制传输系统的性能， 提高零中频发 射机的随机性。
本发明实施例的技术方案是这样实现的：
本发明实施例提供了一种零中频信号的修正方法， 所述方法包括： 接收到待传输的 I路数字基带信号和 Q路数字基带信号时， 数字控制 振荡器 NCO对所述待传输的 I路数字基带信号和 Q路数字基带信号进行变 频， 并输出变频后的 I路数字基带信号和 Q路数字基带信号；
其中， 变频后的 I路数字基带信号和 Q路数字基带信号的载波频率远 小于基带釆样频率。
优选地， 所述输出变频后的 I路数字基带信号和 Q路数字基带信号之 后， 所述方法还包括：
将变频后的 I路数字基带信号和 Q路数字基带信号转换成 I路模拟信号 和 Q路模拟信号；
对所述 I路模拟信号和所述 Q路模拟信号进行 IQ调制并输出模拟中频 信号。
优选地，所述对所述 I路模拟信号和 Q路模拟信号进行 IQ调制，包括： 对所述 I路模拟信号和所述 Q路模拟信号进行上变频。
优选地， 所述对所述 I路模拟信号和所述 Q路模拟信号进行上变频， 包括：
当 NCO将待传输的 I路数字基带信号和 Q路数字基带信号变频至第一 阈值 Y时，将 DAC转换后的 I路模拟信号和 Q路模拟信号的载波频率上变 频为 X-Y;
其中， X为待输出的模拟中频信号的载波频率， Y小于 X。
优选地， 所述对所述 I路模拟信号和所述 Q路模拟信号进行上变频， 还包括：
当 NCO将待传输的 I路数字基带信号和 Q路数字基带信号变频至第二 阈值 -N时， 将 DAC转换后的 I路模拟信号和 Q路模拟信号的载波频率上 变频为 X+N;
其中， X为待输出的模拟中频信号的载波频率 , N小于 X。
本发明实施例还提供了一种零中频信号的修正装置， 所述装置包括数 字控制振荡器 NCO， 配置为接收到待传输的 I路数字基带信号和 Q路数字 基带信号时， 对所述待传输的 I路数字基带信号和 Q路数字基带信号进行 变频， 并输出变频后的 I路数字基带信号和 Q路数字基带信号；
其中， 变频后的 I路数字基带信号和 Q路数字基带信号的载波频率远 小于基带釆样频率。
优选地， 所述装置还包括数模转换器 DAC和模拟上变频模块； 其中， 所述 DAC， 配置为将变频后的 I路数字基带信号和 Q路数字基带信号 转换成 I路模拟信号和 Q路模拟信号；
所述模拟上变频模块， 配置为对所述 I路模拟信号和所述 Q路模拟信 号进行 IQ调制并输出模拟中频信号。
优选地， 所述模拟上变频模块， 还配置为对所述 I路模拟信号和 Q路 模拟信号进行上变频。
优选地， 所述模拟上变频模块， 还配置为当 NCO将待传输的 I路数字 基带信号和 Q路数字基带信号变频至第一阈值 Y时， 将 DAC转换后的 I 路模拟信号和 Q路模拟信号的载波频率上变频为 X-Y;
其中， X为待输出的模拟中频信号的载波频率， Y小于 X。
优选地， 所述模拟上变频模块， 还配置为当 NCO将待传输的 I路数字 基带信号和 Q路数字基带信号变频至第二阈值 -N时， 将 DAC转换后的 I 路模拟信号和 Q路模拟信号的载波频率上变频为 X+N;
其中， X为待输出的模拟中频信号的载波频率 , Ν小于 X。
一种存储介质， 所述存储介质中存储有计算机程序， 所述计算机程序 配置为执行前述的零中频信号的修正方法。
本发明实施例所提供的零中频信号的修正方法及装置， 解决了由于高
阶调制传输系统在零频处对直流残留量要求高而 DAC去直流后直流残留仍 然较大的问题。 本发明实施例通过釆用数字控制振荡器 （NCO， Number Controlled Oscillator )对零中频信号进行修正， 即在数字基带信号进入 DAC 之前对其进行一次较小的频谱搬移， DAC仍然釆用基带釆样模式进行釆样， 可以使得零频处的峰值误差降低到 -55db以下，避免了峰值误差过大对高阶 调制系统造成的影响， 提高了零中频发射机的随机性， 大大地改善了高阶 调制传输系统的性能。 附图说明
图 1为现有技术中经典数字零中频发射机架构示意图；
图 2为经典数字零中频发射机架构中 DAC入口信号功率谱示意图； 图 3为本发明实施例零中频信号的修正方法的实现流程示意图； 图 4为本发明实施例零中频信号的修正装置的组成结构示意图； 图 5为本发明实施例零中频发射机架构示意图； 图。 具体实施方式
下面结合附图及具体实施例对本发明作进一步详细的说明。
图 3为本发明实施例零中频信号的修正方法的实现流程示意图，如图 3 所示， 该流程包括以下步骤：
步骤 301 : 接收到待传输的 I路数字基带信号和 Q路数字基带信号时， 数字控制振荡器 NCO对所述待传输的 I路数字基带信号和 Q路数字基带信 号进行变频；
具体地， 在将待传输的 I路数字基带信号和 Q路数字基带信号发送至 DAC之前， NCO对所述待传输的 I路数字基带信号和 Q路数字基带信号进
行变频。
具体地， 变频后的 I路数字基带信号和 Q路数字基带信号的载波频率 远小于 DAC的基带釆样频率。
步骤 302: 输出变频后的 I路数字基带信号和 Q路数字基带信号。
这里，利用 NCO变频后的 I路数字基带信号和 Q路数字基带信号的载 波频率远小于 DAC的基带釆样频率， 以便于 DAC釆用基带釆样模式进行 釆样。
优选地， 所述输出变频后的 I路数字基带信号和 Q路数字基带信号之 后， 所述方法还包括：
将变频后的 I路数字基带信号和 Q路数字基带信号转换成 I路模拟信号 和 Q路模拟信号；
对所述 I路模拟信号和所述 Q路模拟信号进行 IQ调制并输出模拟中频 信号。
具体地，所述对所述 I路模拟信号和 Q路模拟信号进行 IQ调制，包括： 对所述 I路模拟信号和所述 Q路模拟信号进行上变频。
具体地， 所述对所述 I路模拟信号和所述 Q路模拟信号进行上变频， 包括：
当 NCO将待传输的 I路数字基带信号和 Q路数字基带信号变频至第一 阈值 Y时，将 DAC转换后的 I路模拟信号和 Q路模拟信号的载波频率上变 频为 X-Y;
其中， X为待输出的模拟中频信号的载波频率。
这里， 所述 Y为变频后的 I路模拟信号和所述 Q路模拟信号的载波频 率， 其中， Y为正值， Y小于 X。
具体地， 所述对所述 I路模拟信号和所述 Q路模拟信号进行上变频， 还包括：
当 NCO将待传输的 I路数字基带信号和 Q路数字基带信号变频至第二 阈值 -N时， 将 DAC转换后的 I路模拟信号和 Q路模拟信号的载波频率上 变频为 X+N;
其中， X为待输出的模拟中频信号的载波频率。
这里， 所述 N为变频后的 I路模拟信号和所述 Q路模拟信号的载波频 率， 其中， N为正值， N小于 X。
图 4为本发明实施例零中频信号的修正装置的组成结构示意图，如图 4 所示， 所述装置包括：
NCO 41， 配置为接收到待传输的 I路数字基带信号和 Q路数字基带信 号时， 对所述待传输的 I路数字基带信号和 Q路数字基带信号进行变频， 并输出变频后的 I路数字基带信号和 Q路数字基带信号；
其中， 变频后的 I路数字基带信号和 Q路数字基带信号的载波频率远 小于 DAC的基带釆样频率。
如图 4所示， 所述装置还包括 DAC 42和模拟上变频模块 43； 其中， 所述 DAC 42，配置为将变频后的 I路数字基带信号和 Q路数字基带信 号转换成 I路模拟信号和 Q路模拟信号；
所述模拟上变频模块 43， 配置为对所述 I路模拟信号和所述 Q路模拟 信号进行 IQ调制并输出模拟中频信号。
优选地， 所述模拟上变频模块 43， 还配置为对所述 I路模拟信号和 Q 路模拟信号进行上变频。
具体地， 所述模拟上变频模块 43， 还配置为当 NCO将待传输的 I路数 字基带信号和 Q路数字基带信号变频至第一阈值 Y时，将 DAC转换后的 I 路模拟信号和 Q路模拟信号的载波频率上变频为 X-Y;
其中， X为待输出的模拟中频信号的载波频率。
这里， 所述 Y为变频后的 I路模拟信号和所述 Q路模拟信号的载波频
率， 其中， Y为正值， Υ小于 X。
具体地， 所述模拟上变频模块 43， 还配置为当 NCO将待传输的 I路数 字基带信号和 Q路数字基带信号变频至第二阈值 -Ν时，将 DAC转换后的 I 路模拟信号和 Q路模拟信号的载波频率上变频为 Χ+Ν;
其中， X为待输出的模拟中频信号的载波频率。
这里， 所述 Ν为变频后的 I路模拟信号和所述 Q路模拟信号的载波频 率， 其中， Ν为正值， Ν小于 X。
本领域技术人员应当理解， 图 4 中所示的零中频信号的修正装置中的 各处理模块的实现功能可参照前述零中频信号的修正方法的相关描述而理 解。 本领域技术人员应当理解， 图 4 所示的零中频信号的修正装置中各处 理模块的功能可通过运行于处理器上的程序而实现， 也可通过具体地逻辑 电路而实现。
这里， NC0 41、 DAC 42、 和模拟上变频模块 43均可由零中频信号的 修正装置中的应用处理器（ AP， Application Processor )、 中央处理器（ CPU, Central Processing Unit )、 数字信号处理器（DSP， Digital Signal Processor ) 或可编程门阵列 （FPGA， Field Programmable Gate Array ) 实现。
图 5为本发明实施例零中频发射机架构示意图， 如图 5所示， 所述零 中频发射机架构包括基带调制器 51、零中频信号的修正装置 52和中频放大 器 53; 其中，
所述基带调制器 51， 配置为将基带信号进行调制， 产生 I路数字基带 信号和 Q路数字基带信号；
这里， 所述基带调制器 51产生 I路数字基带信号和 Q路数字基带信号 的方法与现有技术中产生 I路数字基带信号和 Q路数字基带信号的方法相 同， 在此不再赘述。
所述零中频信号的修正装置 52， 配置为对所述 I路数字基带信号和 Q
路数字基带信号进行变频， 并将变频后的 I路数字基带信号和 Q路数字基 带信号转换成 I路模拟信号和 Q路模拟信号发送至中频放大器 53;
所述中频放大器 53， 配置为对模拟中频信号进行放大， 并输出放大后 的模拟中频信号。
这里，所述零中频信号的修正装置 52具体地组成结构可以如图 4所示。 具体地， 所述零中频信号的修正装置包括 NCO 41、 DAC 42和模拟上 变频模块 43; 其中，
所述 NCO 41， 配置为接收到基带调制器 51发送的待传输的 I路数字 基带信号和 Q路数字基带信号时， 对所述待传输的 I路数字基带信号和 Q 路数字基带信号进行变频，并向 DAC 42输出变频后的 I路数字基带信号和 Q路数字基带信号；
所述 DAC 42，配置为将变频后的 I路数字基带信号和 Q路数字基带信 号转换成 I路模拟信号和 Q路模拟信号， 并向模拟上变频模块 43发送 I路 模拟信号和 Q路模拟信号；
所述模拟上变频模块 43， 配置为对所述 I路模拟信号和所述 Q路模拟 信号进行 IQ调制并向中频放大器 53输出模拟中频信号。 图， 由图 6可以看出： 图 5所示的零中频发射机架构的基带信号的中心频 率在 2.5M， 而不是如图 2所示的经典零中频发射机架构中的基带信号的中 心频率在零频， 由此可见， 釆用本发明实施例的技术方案， 在数字基带信 号进入 DAC之前， 对其进行一次较小的频谱搬移。 由于频谱搬移后的基带 信号的频率远远小于 DAC的基带釆样频率， DAC仍然可以釆用基带釆样 模式进行釆样， 如此， 可以使得零频处的峰值误差降低到 -55db以下， 避免 了峰值误差过大对高阶调制系统造成的影响， 提高了零中频发射机的随机 性， 大大地改善了高阶调制传输系统的性能。
本发明实施例还记载了一种存储介质， 所述存储介质中存储有计算机 程序， 所述计算机程序配置为执行前述实施例的零中频信号的修正方法。
以上所述， 仅为本发明的较佳实施例而已， 并非用于限定本发明的保 护范围。 因此， 凡按照本发明原理所作的任何修改、 等同替换和改进等， 均包含在本发明的保护范围之内。
工业实用性
本发明实施例通过釆用数字控制振荡器 （NCO， Number Controlled Oscillator )对零中频信号进行修正， 即在数字基带信号进入 DAC之前对其 进行一次较小的频谱搬移， DAC仍然釆用基带釆样模式进行釆样， 可以使 得零频处的峰值误差降低到 -55db以下，避免了峰值误差过大对高阶调制系 统造成的影响， 提高了零中频发射机的随机性， 大大地改善了高阶调制传 输系统的性能。
Claims
1、 一种零中频信号的修正方法， 包括：
接收到待传输的 I路数字基带信号和 Q路数字基带信号时， 数字控制 振荡器 NCO对所述待传输的 I路数字基带信号和 Q路数字基带信号进行变 频， 并输出变频后的 I路数字基带信号和 Q路数字基带信号；
其中， 变频后的 I路数字基带信号和 Q路数字基带信号的载波频率远 小于基带釆样频率。
2、 根据权利要求 1所述的方法， 其中， 所述输出变频后的 I路数字基 带信号和 Q路数字基带信号之后， 所述方法还包括：
将变频后的 I路数字基带信号和 Q路数字基带信号转换成 I路模拟信号 和 Q路模拟信号；
对所述 I路模拟信号和所述 Q路模拟信号进行 IQ调制并输出模拟中频 信号。
3、 根据权利要求 2所述的方法， 其中， 所述对所述 I路模拟信号和 Q 路模拟信号进行 IQ调制， 包括：
对所述 I路模拟信号和所述 Q路模拟信号进行上变频。
4、 根据权利要求 3所述的方法， 其中， 所述对所述 I路模拟信号和所 述 Q路模拟信号进行上变频， 包括：
当 NCO将待传输的 I路数字基带信号和 Q路数字基带信号变频至第一 阈值 Y时，将 DAC转换后的 I路模拟信号和 Q路模拟信号的载波频率上变 频为 X-Y;
其中， X为待输出的模拟中频信号的载波频率，Υ小于 X。
5、 根据权利要求 3所述的方法， 其中， 所述对所述 I路模拟信号和所 述 Q路模拟信号进行上变频， 还包括：
当 NCO将待传输的 I路数字基带信号和 Q路数字基带信号变频至第二 阈值 -N时， 将 DAC转换后的 I路模拟信号和 Q路模拟信号的载波频率上 变频为 X+N;
其中， X为待输出的模拟中频信号的载波频率 , Ν小于 X。
6、 一种零中频信号的修正装置， 包括数字控制振荡器 NCO， 配置为接 收到待传输的 I路数字基带信号和 Q路数字基带信号时，对所述待传输的 I 路数字基带信号和 Q路数字基带信号进行变频， 并输出变频后的 I路数字 基带信号和 Q路数字基带信号；
其中， 变频后的 I路数字基带信号和 Q路数字基带信号的载波频率远 小于基带釆样频率。
7、 根据权利要求 6 所述的装置， 其中， 所述装置还包括数模转换器 DAC和模拟上变频模块； 其中，
所述 DAC， 配置为将变频后的 I路数字基带信号和 Q路数字基带信号 转换成 I路模拟信号和 Q路模拟信号；
所述模拟上变频模块， 配置为对所述 I路模拟信号和所述 Q路模拟信 号进行 IQ调制并输出模拟中频信号。
8、 根据权利要求 7所述的装置， 其中， 所述模拟上变频模块， 还配置 为对所述 I路模拟信号和 Q路模拟信号进行上变频。
9、 根据权利要求 8所述的装置， 其中， 所述模拟上变频模块， 还配置 为当 NCO将待传输的 I路数字基带信号和 Q路数字基带信号变频至第一阈 值 Y时，将 DAC转换后的 I路模拟信号和 Q路模拟信号的载波频率上变频 为 X-Y;
其中， X为待输出的模拟中频信号的载波频率， Y小于 X。
10、 根据权利要求 8所述的装置， 其中， 所述模拟上变频模块， 还配 置为当 NCO将待传输的 I路数字基带信号和 Q路数字基带信号变频至第二
阈值 -N时， 将 DAC转换后的 I路模拟信号和 Q路模拟信号的载波频率上 变频为 X+N;
其中， X为待输出的模拟中频信号的载波频率， N小于 X。
11、 一种存储介质， 所述存储介质中存储有计算机程序， 所述计算机 程序配置为执行权利要求 1至 5任一项所述的零中频信号的修正方法。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310544345.9 | 2013-11-05 | ||
| CN201310544345.9A CN104617963B (zh) | 2013-11-05 | 2013-11-05 | 一种零中频信号的修正方法及装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2015067034A1 true WO2015067034A1 (zh) | 2015-05-14 |
Family
ID=53040846
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/CN2014/078316 WO2015067034A1 (zh) | 2013-11-05 | 2014-05-23 | 一种零中频信号的修正方法及装置、存储介质 |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN104617963B (zh) |
| WO (1) | WO2015067034A1 (zh) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3764549A1 (en) * | 2015-12-17 | 2021-01-13 | Huawei Technologies Co. Ltd. | Method for determining calibration parameter of zero intermediate frequency radio receiver, and zero intermediate frequency radio receiver |
| WO2019227452A1 (zh) * | 2018-05-31 | 2019-12-05 | 华为技术有限公司 | 射频发射机和信号处理方法 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101304395A (zh) * | 2008-06-27 | 2008-11-12 | 中兴通讯股份有限公司 | 一种零中频发射机及其边带和本振泄漏的校正方法和装置 |
| CN201947220U (zh) * | 2011-01-21 | 2011-08-24 | 成都凯腾四方数字广播电视设备有限公司 | 一种宽带上变频器 |
| CN102176656A (zh) * | 2011-01-21 | 2011-09-07 | 成都凯腾四方数字广播电视设备有限公司 | 一种宽带上变频器及上变频方法 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100511976C (zh) * | 2007-08-30 | 2009-07-08 | 京信通信系统（中国）有限公司 | 数字预失真功率放大器及其实现方法 |
| CN101540626B (zh) * | 2008-03-20 | 2013-06-05 | 中兴通讯股份有限公司 | 收发信机及零中频发射校准方法 |
-
2013
- 2013-11-05 CN CN201310544345.9A patent/CN104617963B/zh active Active
-
2014
- 2014-05-23 WO PCT/CN2014/078316 patent/WO2015067034A1/zh active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101304395A (zh) * | 2008-06-27 | 2008-11-12 | 中兴通讯股份有限公司 | 一种零中频发射机及其边带和本振泄漏的校正方法和装置 |
| CN201947220U (zh) * | 2011-01-21 | 2011-08-24 | 成都凯腾四方数字广播电视设备有限公司 | 一种宽带上变频器 |
| CN102176656A (zh) * | 2011-01-21 | 2011-09-07 | 成都凯腾四方数字广播电视设备有限公司 | 一种宽带上变频器及上变频方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104617963A (zh) | 2015-05-13 |
| CN104617963B (zh) | 2019-07-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP2541781B1 (en) | Rf transmitter architecture and method therefor | |
| EP2515444B1 (en) | RF transmitter and method therefor | |
| US9647866B2 (en) | RF transmitter, integrated circuit device, wireless communication unit and method therefor | |
| JP5896392B2 (ja) | 通信補正のための装置及び方法 | |
| KR20180020235A (ko) | 송신기 | |
| WO2006118317A1 (en) | Polar modulation transmitter circuit and communications device | |
| US9059661B2 (en) | Variable-size mixer for high gain range transmitter | |
| EP2698958B1 (en) | Digital analog predistortion processing apparatus, signal transmission system and signal transmission method | |
| CN107005527B (zh) | 信号发送设备及信号发送方法 | |
| JP2007104007A (ja) | 直交変調器及び直交変調器におけるベクトル補正方法 | |
| WO2015067034A1 (zh) | 一种零中频信号的修正方法及装置、存储介质 | |
| CN102833198A (zh) | 针对零中频架构的iq不平衡校正系统及方法 | |
| US9954627B2 (en) | Quadrature demodulator and wireless receiver | |
| US10516406B1 (en) | Digital to analog converter linearization system | |
| CN112119618B (zh) | 用于发射器的信号处理装置和用于这种装置的方法 | |
| US9240920B2 (en) | Wireless transmitter for multi-mode concurrent transmission of signals complying with different communication standards | |
| JP5870739B2 (ja) | プリディストーション装置 | |
| WO2018137184A1 (zh) | 一种信号处理方法及设备 | |
| TW202239154A (zh) | 收發裝置及其校正方法 | |
| JP2005039725A (ja) | データ変換装置および送信機 | |
| US20130082756A1 (en) | Signal input device of digital-rf converter | |
| CN108352814B (zh) | 正交数字功率放大器 | |
| TWI517602B (zh) | 訊號傳送或接收電路、以及訊號傳送或接收方法 | |
| US9319076B2 (en) | Modulation method for improving signal conversion gain and high-gain modulator thereof | |
| KR20130036697A (ko) | 디지털-ｒｆ 변환기의 신호 입력 장치 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 14860060 Country of ref document: EP Kind code of ref document: A1 |
|
| NENP | Non-entry into the national phase |
Ref country code: DE |
|
| 122 | Ep: pct application non-entry in european phase |
Ref document number: 14860060 Country of ref document: EP Kind code of ref document: A1 |