WO2014063387A1 - 液晶面板驱动电路 - Google Patents

液晶面板驱动电路 Download PDF

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Publication number
WO2014063387A1
WO2014063387A1 PCT/CN2012/084108 CN2012084108W WO2014063387A1 WO 2014063387 A1 WO2014063387 A1 WO 2014063387A1 CN 2012084108 W CN2012084108 W CN 2012084108W WO 2014063387 A1 WO2014063387 A1 WO 2014063387A1
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WIPO (PCT)
Prior art keywords
electrically connected
pin
driving source
electrical switch
resistor
Prior art date
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Ceased
Application number
PCT/CN2012/084108
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English (en)
French (fr)
Inventor
陈胤宏
田夏
贾沛
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US13/805,662 priority Critical patent/US8890791B2/en
Publication of WO2014063387A1 publication Critical patent/WO2014063387A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling

Definitions

  • the present invention relates to the field of liquid crystal displays, and more particularly to a liquid crystal panel area circuit of a liquid crystal display device. Background technique
  • liquid crystal display devices With the development of science and technology and the improvement of people's quality of life, liquid crystal display devices have been widely seen in life, and people are increasingly demanding liquid crystal display devices, and have begun to pursue large display screens and fast response speeds.
  • the wiring delay increases with the number of pixel electrodes driven by the TFT (Thin Film Transistor) substrate and the parasitic capacitance of the thin film transistor The effect of the feedback voltage on each pixel electrode makes the difficulty of accurately controlling the pixel electrode also follow the booster port.
  • TFT Thin Film Transistor
  • Figure 1 is a structural diagram of a VA type liquid crystal display device, in which the liquid crystal molecules 100 are in a driving circuit
  • the 500 is vertically arranged between the two substrates 300 and 400 without applying a driving voltage, and when a driving voltage is applied, the liquid crystal molecules 100 in the vicinity of the pixel electrode 200 are deflected by 0-90.
  • FIG. 2 is a schematic diagram showing the structure of a driving circuit of a basic TFT array substrate.
  • the pixel electrodes 200 are distributed on the entire TFT substrate, and each pixel electrode 200 is connected to at least one drain of a thin film transistor, the source of each thin film transistor.
  • the bus bus commonly controls the data writing of the pixel electrodes through the thin film transistors, and the pixel electrodes P(i, j) of the jth row of the i-th column on the TFT substrate are collectively subjected to the gate line G(j) and Control of the data line S(i), when the pixel electrode P(i,j) is written, the gate line G1 is at a high level to ensure that the thin film transistor T(i,j) is in a conducting state, At the time of the driving voltage applied to the data line S(i), the liquid crystal molecules in the vicinity of the pixel electrode P(i, j) are deflected in a predetermined deflection direction, thereby realizing display of an image. Such a write operation is performed in rows, and all pixel
  • Figure 3 is a schematic diagram showing the equivalent driving line connection of each pixel electrode, wherein the i-th data line S(i) is connected to the source s of the i-th column j-th thin film transistor T(i, j), the jth
  • the gate strobe line G(j) is connected to the gate g of the thin film transistor T(i, j) of the i-th column j-th row, and the drain d and the ith of the i-th column j-th thin film transistor T(i, j)
  • the pixel electrode P(i, j) of the jth row of the column is connected.
  • Capacitor C gd is a parasitic capacitance between the gate g and the drain d.
  • the parasitic capacitance C gd is inherent in the TFT transistor, and C k is the equivalent capacitance of the liquid crystal layer between the TFT substrate and the CF substrate, and C s is A compensation capacitor between the TFT substrate and Vcom, which is present to compensate for the voltage drop on c lc by discharge, to appropriately increase the retention time of the liquid crystal molecule deflection direction in the c lc region.
  • C gd is inherent in the TFT transistor
  • C k is the equivalent capacitance of the liquid crystal layer between the TFT substrate and the CF substrate
  • C s is A compensation capacitor between the TFT substrate and Vcom, which is present to compensate for the voltage drop on c lc by discharge, to appropriately increase the retention time of the liquid crystal molecule deflection direction in the c lc region.
  • the presence of the parasitic capacitance C gd between the drain d and the drain d will directly affect the control of the turn-on and turn-off of the TFT by the gate voltage V g , particularly at the pixel electrode P (n, j at the end far from the gate bus line).
  • the response time is long, and there is also a gating.
  • the voltage changes from high to low the decay of the thin film transistor T(n, j) is extended by ⁇ , that is, the thin film transistor that should have been turned off is abnormally turned on, which will bring about the thin film transistor.
  • the driving time of the pixel electrode P(n, j) connected to the drain d is extended by AT dx , resulting in a difference in transmittance and contrast abnormality due to abnormal deflection of liquid crystal molecules in the vicinity of the pixel electrode.
  • the resistance variable element is formed, and the driving voltage is high level VD1 generated by the high level generating circuit VD1 X and the low level VD2 generated by the low level generating circuit VD2 X is formed by the conduction and closing of the controlled switch 3b.
  • the drive voltage of the line When the 3b is in a high level with VD1, the parasitic capacitances Cgd and Clc are charged to drive the pixel electrode; when 3b is in a low level with VD2, the SC is utilized.
  • the electric voltage reduces the delay of the gate line voltage and improves the image display quality.
  • VDla signal generating circuit shown in FIG. 6A is used on the basis of the structure of FIG.
  • VD1a shown in FIG. 6B is generated at a high level, and a waveform having a falling edge of a certain falling rate is formed at the end of the high level one cycle, at the end of one cycle of the VDla At the same time, it is ensured that the control switch 3b is connected to the low level VD2 generating circuit.
  • One cycle of the high level VDla and VD2 - a low level period together constitute a strobe One cycle of the strobe signal VG on the line.
  • Stc is a voltage similar to GCK, or it can be the basic voltage obtained by GCK/GSP conversion. It mainly uses an inverting amplifier to control the conduction and termination of the SW2 switch.
  • VDlb signal generating circuit structure shown in Fig. 7A is used as the VD1 high level generating circuit on the basis of the structure of Fig. 5, and the resistance variable element in Fig. 5 is removed or affected by the voltage control.
  • VD1b shown in FIG. 7B is generated at a high level, and at the end of the high level one cycle, a waveform having a falling edge with a certain falling rate is formed, at the end of one cycle of the VDlb. At the same time, it is ensured that the control switch 3b is connected to the low level VD2 generating circuit. Similarly, one cycle of the high level VDlb and the low period of VD2 together form one cycle of the strobe signal VG on the gate line.
  • VDlb is in the same direction as Vdd, and is a voltage proportional to the Vdd size.
  • the voltage is a high level and is sufficient for the TFT to be turned on.
  • the equivalent parasitic capacitance C n at the pixel electrode T(n, j) far from the gate bus G is Parallel connection of the first n-1 parasitic capacitances, which will bring about a different discharge voltage of the parasitic capacitance at the pixel electrode T(i, j), that is, all the thin film transistors connected on one entire gate line, At the time when the gate voltage is changed from the high level to the low level, the negative voltage generated by the discharge of the gate parasitic capacitance of the thin film transistor is varied.
  • the above-mentioned driving circuit scheme cannot solve the problem that the on-time of the thin film transistor is prolonged. Summary of the invention
  • An object of the present invention is to provide a liquid crystal surface driving circuit capable of reducing the influence of parasitic capacitance on the on-time of a thin film transistor and improving the display quality of a large-sized liquid crystal display to which the circuit is applied.
  • the present invention provides a liquid crystal panel driving circuit, including: a gate driver, a source driver, a plurality of gate lines, and a plurality of data lines, wherein the plurality of gate lines and data lines define a plurality of pixel units
  • Each pixel unit includes a thin film transistor, a common electrode, a pixel electrode electrically connected to the thin film transistor, and a storage capacitor.
  • the thin film transistor is electrically connected to the gate driver and the source driver through the gate line and the data line, respectively.
  • the gate driver comprises a driving synthesis circuit
  • the driving synthesis circuit comprises: a first electrical switch, and An amplifier electrically connected to the first electrical switch, a first driving source electrically connected to the first electrical switch, a second driving source electrically connected to the first electrical switch, and an electrical interface connected to the amplifier a resistor, a third driving source electrically connected to the amplifier, a second resistor electrically connected to the first electrical switch, and a resistor
  • the second electrical switch is connected between the second resistor and the amplifier, the third resistor electrically connected to the amplifier, and the fourth driving source electrically connected to the second electrical switch.
  • the thin film transistor includes: a gate, a source, and a drain, the gate is electrically connected to the gate driver through a gate line, and the source is electrically connected to the source driver through the data line, The drain is electrically connected to the pixel electrode.
  • the first electrical switch includes: first, second, and third pins, the first pin is electrically connected to the first driving source, and the second pin is electrically connected to the second driving source and the amplifier
  • the third pin is electrically connected to one end of the second resistor.
  • the second electrical switch includes: fourth, fifth, and sixth pins, the fourth pin is electrically connected to the other end of the second resistor, and the fifth pin is electrically connected to the fourth driving source
  • the sixth pin is electrically connected to the amplifier and one end of the first resistor.
  • the amplifier includes: seventh, eighth, and ninth pins, the seventh pin is electrically connected to the second driving source and the second pin of the first electrical switch, and the eighth pin is electrically connected To the third driving source and the other end of the first resistor, the ninth pin is electrically connected to the sixth lead of the second electrical switch a pin, one end of the first resistor, and a third resistor.
  • the gate of the thin film transistor and the second resistor are electrically connected to the first electrical switch connection end.
  • the first electrical switch is turned on when the second pin is controlled by the high level, and is turned off when the second pin is controlled by the low level; the second electrical switch is turned on when the fifth pin is controlled by the high level, Disconnected during low level control.
  • the first driving source is a square wave
  • the second driving source is a square wave having the same phase and period as the first driving source
  • the third driving source is a triangular wave
  • the fourth driving source is A square wave of high frequency.
  • the present invention also provides a liquid crystal panel driving circuit, comprising: a gate driver, a source driver, a plurality of gate lines, and a plurality of data lines, the plurality of gate lines and data lines defining a plurality of pixel units, each pixel
  • the unit includes a thin film transistor, a common electrode, a pixel electrode electrically connected to the thin film transistor, and a storage capacitor.
  • the thin film transistor is electrically connected to the gate driver and the source driver through the gate line and the data line, respectively.
  • the common electrode and the pixel electrode form a liquid crystal capacitor
  • the storage capacitor is connected in parallel with the liquid crystal capacitor
  • the gate driver includes a driving synthesis circuit
  • the driving synthesis circuit comprises: a first electrical switch, and a first electrical switch An electrically connected amplifier, a first driving source of the amplifier electrically connected to the first electrical switch, a second driving source electrically connected to the first electrical switch, a first resistor electrically connected to the amplifier, and a third driving source electrically connected to the amplifier, a second resistor electrically connected to the first electrical switch, and electrically connected to the second electrical a second electrical switch between the resistor and the amplifier, a third resistor electrically connected to the amplifier, and a fourth driving source electrically connected to the second electrical switch;
  • the thin film transistor includes: a gate, a source, and a drain, the gate is electrically connected to the gate driver through a gate line, and the source is electrically connected to the source driver through the data line
  • the drain is electrically connected to the pixel electrode;
  • the first electrical switch includes: first, second, and third pins, the first pin is electrically connected to the first driving source, and the second pin is electrically connected to the second driving source And an amplifier, the third pin is electrically connected to one end of the second resistor;
  • the second electrical switch includes: fourth, fifth, and sixth pins, the fourth pin is electrically connected to the other end of the second resistor, and the fifth pin is electrically connected to the fourth a driving source, the sixth pin is electrically connected to the amplifier and one end of the first resistor;
  • the amplifier includes: seventh, eighth, and ninth pins, wherein the seventh pin is electrically connected to the second driving source and the second pin of the first electrical switch, and the eighth pin is electrically Connected to the third driving source and the other end of the first resistor, the ninth pin is electrically connected to the sixth pin of the second electrical switch, one end of the first resistor, and the third resistor;
  • the first electrical switch is turned on when the second pin is controlled by the high level, and is turned off when the second pin is controlled by the low level; the second electrical switch is turned on when the fifth pin is controlled by the high level. , disconnected when controlled by low level;
  • the first driving source is a square wave
  • the second driving source is a square wave having the same phase and period as the first driving source
  • the third driving source is a triangular wave
  • the fourth The driving source is a high frequency square wave.
  • the liquid crystal panel driving circuit of the present invention synthesizes a square wave driving voltage and a triangular wave having a certain slope by an electric switch control, and forms a driving voltage driving film having a falling edge of a falling rate at the end of a high level.
  • the gate of the transistor reduces the time during which the parasitic capacitance is extended by the thin film transistor due to the discharge, thereby reducing the possibility of abnormal conduction of the thin film transistor in a non-conducting state, further improving the precision of the thin film transistor control, and avoiding A phenomenon in which the transmittance of the liquid crystal molecules is abnormally deflected and the contrast is abnormal, and the quality of the liquid crystal display using the circuit in a large size is improved.
  • Figure 1 is a basic structure of a VA liquid crystal display device
  • FIG. 2 is a schematic structural view of a driving circuit of a TFT array substrate
  • FIG. 3 is a schematic diagram showing an equivalent connection of a driving circuit of a pixel electrode
  • Figure 4 shows the gate drive voltage waveform brought by the parasitic capacitance
  • Figure 5 is a schematic view showing the connection of a conventional driving circuit
  • FIGS. 6A-B are schematic diagrams showing the connection of a conventional driving circuit and the waveform diagram of the connection mode;
  • FIG. 7A-B is a schematic diagram showing the connection of another conventional driving circuit and a waveform diagram of the connection mode;
  • FIG. 8 is a liquid crystal panel of the present invention;
  • FIG. 9 is a schematic structural diagram of a driving synthesis circuit in a liquid crystal panel driving circuit of the present invention;
  • FIG. 10 is a waveform diagram of first, second, third, and fourth driving sources in a liquid crystal panel driving circuit of the present invention;
  • FIG. 11 is a waveform diagram of an output terminal VDlc in a liquid crystal panel driving circuit of the present invention
  • Figure 12 is a descending edge V, sl of the liquid crystal panel driving circuit of the present invention.
  • Waveform of p Waveform of p .
  • the present invention provides a liquid crystal panel driving circuit, comprising: a gate driver 10, a source driver 20, a plurality of gate lines G(M), and a plurality of data lines S(N),
  • the plurality of gate lines G(M) and the data lines S(N) define a plurality of pixel units, each of the pixel units including a thin film transistor T, a common electrode 40, and a pixel electrode 30 electrically connected to the thin film transistor
  • a storage capacitor Cs the thin film transistor T is electrically connected to the gate driver 10 and the source driver 20 through the gate line G (M) and the data line S (N), respectively, the common electrode 40 and the pixel electrode 30
  • a liquid crystal capacitor Clc is formed, and the storage capacitor Cs is connected in parallel with the liquid crystal capacitor Clc.
  • the plurality of gate lines G(1), G(2) G(M) form a gate bus structure G
  • the plurality of data lines S(1), S(2) ) S (N) forms a data bus structure S.
  • the gate driver 10 includes a driving synthesis circuit, and the driving synthesis circuit includes: a first electrical switch SW1, an amplifier Q electrically connected to the first electrical switch SW1, a first driving source Vdd, a second driving source Stc, a first resistor R1 electrically connected to the two interfaces of the amplifier Q, a third driving source Vddl electrically connected to the amplifier Q, and a second resistor R2 electrically connected to the first electrical switch SW1 are electrically connected to the second resistor A second electrical switch SW2 between R2 and the amplifier Q, a third resistor R3 electrically connected to the amplifier Q, and a fourth driving source Vmc electrically connected to the second electrical switch SW2.
  • the first, second, third, and fourth driving sources Vdd, Stc, Vddl, and Vmc may be generated by a power source and a corresponding circuit.
  • the thin film transistor T includes: a gate g, a source s and a drain d, and the gate g is electrically connected to the gate driver through the gate line G(M).
  • the source s is electrically connected to the source driver 20 through the data line S(N)
  • the drain d is electrically connected to the pixel electrode 30, and the gate g and the drain d are formed due to structural characteristics.
  • a parasitic capacitance C gd The gate driver applies with ⁇ "falling-down rate of a V, sl. P at the end of a high driving voltage, so as to avoid parasitic capacitance Cgd conduction time of the gate g 10 g gate thin film transistor T The falling edge of V, sl .
  • the discharge voltage applied to the gate g is reduced, and the gate g is reduced.
  • the delay time ensures the accuracy of turning on or off the TFT of the thin film transistor.
  • the first electrical switch SW1 includes: first, second, and third pins 1, 2, and 3.
  • the first pin 1 is electrically connected to the first driving source V dd
  • the second pin 2 Electrically connected to the second The driving source Stc and the amplifier Q are electrically connected to the second resistor R2-terminal.
  • the second electrical switch SW2 includes: fourth, fifth, and sixth pins 4, 5, and 6, the fourth pin 4 is electrically connected to the other end of the second resistor R2, the fifth pin 5 is electrically connected to the fourth driving source Vmc, and the sixth pin 6 is electrically connected to one end of the amplifier Q and the first resistor R1.
  • the first electrical switch SW1 is turned on when the second pin 2 is controlled by the high level, and is turned off when controlled by the low level; the second electrical switch SW2 is controlled when the fifth pin 5 is controlled by the high level Turned on, disconnected when controlled by low level.
  • the second and fourth driving sources Stc and Vmc are used to drive the first or second electrical switches SW1 and SW2 to be turned on or off, respectively, so that the first driving source Vdd and the third driving source Vddl are combined.
  • the amplifier Q includes: seventh, eighth, and ninth pins 7, 8, and 9, the seventh pin 7 is electrically connected to the second driving source Stc and the second pin 2 of the first electrical switch SW1
  • the eighth pin 8 is electrically connected to the third driving source Stc and the other end of the first resistor R1
  • the ninth pin 9 is electrically connected to the sixth pin 6 of the second electrical switch SW2.
  • One end of the resistor R1 and the third resistor R3, and the other end of the third resistor R3 is connected to the ground.
  • the gate g of the thin film transistor T and the second resistor R2 are electrically connected to the connection end of the first electrical switch SW1.
  • the first driving source V dd is a square wave
  • the second driving source 8 1 is a square wave having the same phase and period as the first driving source V dd
  • the third driving source V ddl is A triangular wave
  • the fourth driving source V mc is a high frequency square wave.
  • the fourth driving source V mc can be a control clock signal.
  • the driving voltage V on the gate g of the thin film transistor T includes: the driving voltage V on the gate line G ( M ) is generated by a high level VD1 circuit VD1 X and a low
  • the level VD2 generating circuit VD2 X is commonly generated, and the high level generating circuit VD1 X generates a voltage falling edge V, sl at the high level end timing. p .
  • the voltage drops along V, sl . p has a negative linear voltage drop or has a negative step voltage drop.
  • the first driving source V dd the second driving source S tc , and the third driving source
  • V ddl the fourth driving source V mc
  • VD1 c the falling edge V, sl .
  • the waveform of p is as shown.
  • S tc and V mc are clock signals after CLK conversion, and the amplitude of the first driving source V dd is the same as the amplitude of the voltage signal on the gate line G (j).
  • the first driving source V dd When the second driving source S tc is at a high level, the first driving source V dd is at a high level, the first electrical switch SW1 is closed, and the second electrical switch SW2 is turned on, at which time the output terminal VDlc is at a high level VD1;
  • the second driving source S tc is at a low level, the first driving source V dd is at a low level, the first electrical switch SW1 is turned on, and the second electrical switch SW2 is controlled to be turned on or off by a change in the level of the fourth driving source V mc Acting, the first driving source V ddl voltage signal having a linear falling waveform is connected to the second electrical switch SW2 through the amplifier, and the signal of the first driving source V ddl passes through the amplifier Q and is applied under the control of the second electrical switch SW2 To the output VDlc.
  • the output terminal VDlc and the low level VD2 composite signal are used to drive the gate line G(j), and the falling edge is V, sl .
  • the generation of p is controlled by the fourth driving source V mc , and the fourth driving source V mc is at a low level when the second driving source S te is at a high level, and a high level to a low level at the second driving source S to
  • the time t x has a high frequency f during which the second electrical switch SW2 is turned on and off at a high speed, and the third driving source V ddl applied thereto is sampled to form as shown in FIG. 11 .
  • the falling edge is V, sl . p waveform.
  • the falling edge is V, sl .
  • the p- waveform can obtain different falling edges V, sl according to the length of time t x and the different parameters of the frequency f in the time period. p waveform.
  • the falling edge is V, sl .
  • the p waveform forms a high level VDlc of the gate line G(j) together with the high level when the first electric switch SW1 is closed and the second electric switch SW2 is turned on.
  • the liquid crystal panel driving circuit of the present invention synthesizes a square wave driving voltage and a triangular wave having a certain slope by an electric switch control, and forms a driving voltage driving thin film transistor having a falling edge of a falling rate at the end of the high level.
  • the gate thereby reducing the parasitic capacitance caused by the discharge, prolonging the conduction time of the thin film transistor, thereby reducing the possibility of abnormal conduction of the thin film transistor in a non-conducting state, further improving the precision of the thin film transistor control, and avoiding the liquid crystal
  • the change in transmittance and the abnormality in contrast caused by the abnormal deflection of the molecule enhance the quality of the liquid crystal display using the circuit in a large size.

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Abstract

一种液晶面板驱动电路，包括栅极驱动器（10）、源极驱动器（20）、多条选通线（G（M））及多条数据线（S（N））。该多条选通线（G（M））和数据线（S（N））界定多个像素单元。每一像素单元包括薄膜晶体管（T）、公共电极（40）、像素电极（30）及存储电容（Cs）。薄膜晶体管（T）通过选通线（G（M））及数据线（S（N））分别与栅极驱动器（10）及源极驱动器（20）电性连接。栅极驱动器（10）包括驱动合成电路，驱动合成电路包括第一电开关（SW1）、放大器（Q）、第一驱动源（Vdd）、第二驱动源（Stc）、第一电阻（R1）、第三驱动源（Vddl）、第二电阻（R2）、第三电阻（R3）、第二电开关（SW2）及第四驱动源（Vmc）。该液晶面驱动电路能够减小寄生电容（Cgd）对薄膜晶体管（T）导通时间的延时影响，提高大尺寸液晶显示器显示质量。

Description

液晶面板驱动电路 技术领域
本发明涉及一种液晶显示器领域， 尤其涉及一种液晶显示器件的液晶 面板区动电路。 背景技术
随着科学技术的发展以及人们生活质量的提高， 液晶显示器件在生活 中已经随处可见， 并且人们对液晶显示器件的要求越来越高， 开始追求大 的显示画面、 快的响应速度。 但是随着液晶显示器件的增大布线的复杂度 提高， 而且随着 TFT ( Thin Film Transistor 、 薄膜场效应晶体管）基板驱 动像素电极数量的增加线路延时以及因为薄膜晶体管寄生电容的存在所带 来的反馈电压对每个像素电极的影响使得精确控制像素电极的难度也跟着 增力口。
图 1 为 VA型液晶显示器件结构图， 图中液晶分子 100 在驱动电路
500没有施加驱动电压的情况下垂直排列于两基板 300及 400之间， 当施 加驱动电压时， 处于像素电极 200附近的液晶分子 100偏转 0-90° 。
图 2为基本的 TFT阵列基板的驱动电路结构示意图， 图中在整个 TFT 基板上分布着像素电极 200, 每一个像素电极 200至少与一个薄膜晶体管 的漏极 d相连， 每个薄膜晶体管的源极 S至少连接一条数据线路， 数条数 据线路共同构成了数据总线结构； 每一个薄膜晶体管的栅极 g至少连接一 条选通线路， 数条选通线路共同构成了选通总线结构； 数据总线和选通总 线通过薄膜晶体管共同控制这些像素电极的数据写入， 如图 2所示的 TFT 基板上的第 i列第 j行的像素电极 P(i,j)共同受到选通线路 G(j)和数据线路 S(i)的控制， 当对该像素电极 P(i,j)进行写操作时， 选通线路 G①处于高电 平控制， 保证薄膜晶体管 T(i,j)处于导通状态， 此时通过数据线路 S(i)上所 加的驱动电压的大小使与像素电极 P(i,j)附近的液晶分子按照预定的偏转方 向偏转， 从而实现图像的显示。 这样的写操作是按行进行的， 当选通线路 G(j)处于高电平时将对第 j行的所有像素电极进行写操作。
图 3所示是每一个像素电极的等效驱动线路连接示意图， 其中第 i条 数据线路 S(i)与第 i列第 j行薄膜晶体管 T(i, j)的源极 s相连， 第 j条选通 线路 G(j)与第 i列第 j行薄膜晶体管 T(i, j)的栅极 g相连， 第 i列第 j行薄 膜晶体管 T(i, j)的漏极 d与第 i列第 j行像素电极 P(i, j)相连。 电容 Cgd是 栅极 g和漏极 d之间的寄生电容， 该寄生电容 Cgd是在 TFT三极管中固有 的， Ck是处在 TFT基板和 CF基板之间的液晶层的等效电容， Cs是处在 TFT基板和 Vcom之间的一个补偿电容， 该电容的存在是为了通过放电保 证 clc上电压降低时的补偿， 以适当增大 clc区域中的液晶分子偏转方向的 保持时间。 然而随着矩阵分布的 TFT像素电极的行和列数量的增加， 增长 的选通线路和数据线路的会带来驱动线路的延时； 另一方面如图 4所示薄 膜晶体管中的栅极 g和漏极 d之间寄生电容 Cgd的存在将直接影响栅极电 压 Vg对 TFT的导通和截止的控制， 特别是在离选通总线线路较远的末端 的像素电极 P(n, j)附近， 由于选通信号在之前所经过的 n-1个薄膜晶体管 的寄生电容 cgd带来的的放电电压的影响以及线路延时影响， 此处不但响 应时间较长， 同时也存在选通电压由高变低时因放电带来的衰减使得薄膜 晶体管 T(n, j)导通时间 η延长 Δ η , 也就是说本来应该已经截止的薄膜晶 体管异常导通， 这样会带来在薄膜晶体管漏极 d相连的像素电极 P(n, j)的 驱动时间延长 A Tdx, 导致该像素电极附近的液晶分子偏转异常带来的透射 率差异和对比度异常。
在美国专利 US7304626 中， 针对寄生电容造成的 TFT栅极电压延时 带来的显示的异常提出了：
Figure imgf000004_0001
制的电阻可变元件， 驱动电压采用高电平产生电路 VD1X产生的高电平 VD1与低电平产生电路 VD2X产生的低电平 VD2通过受控开关 3b的导通 与闭合形成选通线路的驱动电压。 当 3b处于与 VD1 高电平导通时对寄生 电容 Cgd和 Clc充电， 驱动像素电极； 当 3b处于与 VD2低电平导通时， 利用 SC
Figure imgf000004_0002
电电压， 减少选通线路电压的延时， 提高图像显示质量。
2、 采用图 6A所示的 VDla信号发生电路结构在图 5结构的基础上作
Figure imgf000004_0003
利用图 6A所示的电路结构图生成如图 6B中所示的 VDla在高电平， 该高电平一个周期结束时形成具有一个一定下降率的下降沿的波形， 在该 VDla一个周期结束时刻同时保证控制开关 3b处于与低电平 VD2产生电 路连接。 该高电平 VDla的一个周期和 VD2—个低电平周期共同构成选通 线路上的选通信号 VG的一个周期。
其中 Stc是一个与 GCK相似波形的电压， 也可以是 GCK/GSP变换得 到的基本电压， 它主要是用一个反相放大器来控制 SW2 开关的导通与截 止的。
当 Stc是高电平时， SW1 导通， 而 SW2处是低电平， 此时 SW2截 止， 通过的电压是 Vdd, 同时 Vdd给 Cent电容充电， VDla稳定后的电压 是 Vdd; 当 Stc是氐电平时， SW1截止， 而 SW2处于高电平， 此时 SW2 导通， 此时 VDla的电压是在 Stc的基础上经过 Rent分压得到的。 已经充 电的 Cent此时将会放电， 使 VDla有一个不变的下降率， 具体波形如图 6B , 进而得到选通线路施加到薄膜晶体管栅极上的驱动电压的波形为 VG ( j )所示的波形。
3、 采用图 7A所示的 VDlb信号发生电路结构在图 5结构的基础上作 为 VD1 高电平的发生电路， 同时去掉图 5 中电阻可变元件或者受电压控 的影响。
利用图 7A所示的电路结构图生成如图 7B中所示的 VDlb在高电平， 该高电平一个周期结束时形成具有一个一定下降率的下降沿的波形， 在该 VDlb一个周期结束时刻同时保证控制开关 3b处于与低电平 VD2产生电 路连接。 同样的在该高电平 VDlb的一个周期和 VD2—个低电平周期共同 构成选通线路上的选通信号 VG的一个周期。
图 7A虚线框中是一个直流的充放电震荡电路， 虚线框外是一个运算 放大器。 其中 Stc 仍然是一个与 GCK 相似波形的电压， 也可以是 GCK/GSP变换得到的基本电压， Vet是放大器负极的电压， Ret与 Cct依 然是充放电单元。 Cct充电饱和时的电压正是直流电流 let经过 Ret所形成 的电压 Vct。
当 Stc是高电平的时候， SW3打开， 此时的输出电压 VDlb是与 Vdd 同向的， 并受 Vdd大小成比例的一个电压， 其电压是一个高电平， 并足以 让 TFT导通。
当 Stc是低电平时候， SW3 闭合， 此时在放大器的负极的输入端将会 Cct 的放电形成的正的电压升， 该接在放大器负极的正的电压升经过放大 器后形成放大的负的电压降。 该负的电压降与 SW3 打开时的高电平共同 形成的 VDlb同样作为图 5中的 VD1的高电平。
上述方案尽管可以减小寄生电容放电电压对选通电压带来的延时的影 响， 但是在远离选通总线 G的像素电极 T(n, j)处的等效寄生电容 Cn为所 述前 n-1 个寄生电容的并联， 这样会带来寄生电容在与像素电极 T(i, j)处 不同的放电电压， 也就是说在整个一条选通线路上连接的所有的薄膜晶体 管， 在选通电压由高电平变为低电平的时刻， 薄膜晶体管的栅极寄生电容 的放电产生的负电压是变化的。 利用上述驱动电路方案不能很好地解决薄 膜晶体管导通时间延长的问题。 发明内容
本发明的目的在于提供一种液晶面驱动电路， 能够减小寄生电容对薄 膜晶体管导通时间的延时影响， 提高应用该电路的大尺寸液晶显示器显示 质量。
为实现上述目的， 本发明提供一种液晶面板驱动电路， 包括： 栅极驱 动器、 源极驱动器、 多条选通线及多条数据线， 该多条选通线和数据线界 定多个像素单元， 每一像素单元包括一薄膜晶体管、 一公共电极、 一与薄 膜晶体管电性连接的像素电极及一存储电容， 所述薄膜晶体管通过选通线 及数据线分别与栅极驱动器及源极驱动器电性连接， 所述公共电极与像素 电极形成一液晶电容， 所述存储电容与该液晶电容并联连接， 所述栅极驱 动器包括一驱动合成电路， 所述驱动合成电路包括： 第一电开关、 与第一 电开关电性连接的放大器、 与第一电开关电性连接的放大器第一驱动源、 与第一电开关电性连接的放大器第二驱动源、 电性接于放大器两接口上的 第一电阻、 与放大器电性连接的第三驱动源、 与第一电开关电性连接的第 二电阻、 电性连接于第二电阻与放大器之间的第二电开关、 与放大器电性 连接的第三电阻及与第二电开关电性连接的第四驱动源。
所述薄膜晶体管包括： 一栅极、 一源极及一漏极， 所述栅极通过选通 线电性连接至栅极驱动器， 所述源极通过数据线电性连接至源极驱动器， 所述漏极与像素电极电性连接。
所述第一电开关包括： 第一、 第二及第三引脚， 所述第一引脚电性连 接至第一驱动源， 所述第二引脚电性连接至第二驱动源及放大器， 所述第 三引脚电性连接至第二电阻一端。
所述第二电开关包括： 第四、 第五及第六引脚， 所述第四引脚电性连 接至第二电阻的另一端， 所述第五引脚电性连接至第四驱动源， 所述第六 引脚电性连接至放大器及第一电阻的一端。
所述放大器包括： 第七、 第八及第九引脚， 所述第七引脚电性连接至 第二驱动源及第一电开关的第二引脚， 所述第八引脚电性连接至第三驱动 源及第一电阻的另一端， 所述第九引脚电性连接至第二电开关的第六引 脚、 第一电阻的一端及第三电阻。
所述薄膜晶体管的栅极与第二电阻与第一电开关连接端电性连接。 所述第一电开关在第二引脚被高电平控制时导通， 被低电平控制时断 开； 所述第二电开关在第五引脚被高电平控制时导通， 被低电平控制时断 开。
所述第一驱动源为一方形波， 所述第二驱动源为一与第一驱动源具有 相同相位及周期的方形波， 所述第三驱动源为一三角形波， 所述第四驱动 源为一高频率的方形波。
本发明还提供一种液晶面板驱动电路， 包括： 栅极驱动器、 源极驱动 器、 多条选通线及多条数据线， 该多条选通线和数据线界定多个像素单 元， 每一像素单元包括一薄膜晶体管、 一公共电极、 一与薄膜晶体管电性 连接的像素电极及一存储电容， 所述薄膜晶体管通过选通线及数据线分别 与栅极驱动器及源极驱动器电性连接， 所述公共电极与像素电极形成一液 晶电容， 所述存储电容与该液晶电容并联连接， 所述栅极驱动器包括一驱 动合成电路， 所述驱动合成电路包括： 第一电开关、 与第一电开关电性连 接的放大器、 与第一电开关电性连接的放大器第一驱动源、 与第一电开关 电性连接的放大器第二驱动源、 电性接于放大器两接口上的第一电阻、 与 放大器电性连接的第三驱动源、 与第一电开关电性连接的第二电阻、 电性 连接于第二电阻与放大器之间的第二电开关、 与放大器电性连接的第三电 阻及与第二电开关电性连接的第四驱动源；
其中， 所述薄膜晶体管包括： 一栅极、 一源极及一漏极， 所述栅极通 过选通线电性连接至栅极驱动器， 所述源极通过数据线电性连接至源极驱 动器， 所述漏极与像素电极电性连接；
其中， 所述第一电开关包括： 第一、 第二及第三引脚， 所述第一引脚 电性连接至第一驱动源， 所述第二引脚电性连接至第二驱动源及放大器， 所述第三引脚电性连接至第二电阻一端；
其中， 所述第二电开关包括： 第四、 第五及第六引脚， 所述第四引脚 电性连接至第二电阻的另一端， 所述第五引脚电性连接至第四驱动源， 所 述第六引脚电性连接至放大器及第一电阻的一端；
其中， 所述放大器包括： 第七、 第八及第九引脚， 所述第七引脚电性 连接至第二驱动源及第一电开关的第二引脚， 所述第八引脚电性连接至第 三驱动源及第一电阻的另一端， 所述第九引脚电性连接至第二电开关的第 六引脚、 第一电阻的一端及第三电阻；
其中， 所述薄膜晶体管的栅极与第二电阻与第一电开关连接端电性连 接；
其中， 所述第一电开关在第二引脚被高电平控制时导通， 被低电平控 制时断开； 所述第二电开关在第五引脚被高电平控制时导通， 被低电平控 制时断开；
其中， 所述第一驱动源为一方形波， 所述第二驱动源为一与第一驱动 源具有相同相位及周期的方形波， 所述第三驱动源为一三角形波， 所述第 四驱动源为一高频率的方形波。
本发明的有益效果： 本发明液晶面板驱动电路通过电开关控制将方形 波驱动电压与具有一定斜率的三角形波合成到一起， 形成高电平结束时具 有一下降率的下降沿的驱动电压驱动薄膜晶体管的栅极， 从而减少寄生电 容因放电带来的延长薄膜晶体管导通的时间， 进而减小薄膜晶体管非导通 状态下的异常导通的可能性， 进一步提高薄膜晶体管控制的精度， 避免了 液晶分子异常偏转带来的透射率的改变和对比度异常的现象， 提高大尺寸 使用该电路的液晶显示器的质量。
为了能更进一步了解本发明的特征以及技术内容， 请参阅以下有关本 发明的详细说明与附图， 然而附图仅提供参考与说明用， 并非用来对本发 明加以限制。 附图说明
下面结合附图， 通过对本发明的具体实施方式详细描述， 将使本发明 的技术方案及其它有益效果显而易见。
附图中，
图 1为 VA液晶显示器件的基本结构；
图 2为 TFT阵列基板的驱动电路结构示意图；
图 3为像素电极的驱动电路等效连接示意图；
图 4为寄生电容带来的选通驱动电压波形；
图 5为一现有驱动电路连接示意图；
图 6A-B为一现有驱动电路连接示意图及该连接方式下的波形图； 图 7A-B为另一现有驱动电路连接示意图及该连接方式下的波形图； 图 8为本发明液晶面板驱动电路中像素单元电路结构示意图； 图 9为本发明液晶面板驱动电路中驱动合成电路结构示意图； 图 10 为本发明液晶面板驱动电路中第一、 第二、 第三及第四驱动源 的波形图；
图 11为本发明液晶面板驱动电路中输出端 VDlc的波形图； 图 12为本发明液晶面板驱动电路中下降沿 V，sl。p的波形图。 具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果， 以下结合本发明 的优选实施例及其附图进行详细描述。
请参阅图 5、 8 至 12, 本发明提供一种液晶面板驱动电路， 包括： 栅 极驱动器 10、 源极驱动器 20、 多条选通线 G(M)及多条数据线 S(N), 该多 条选通线 G(M)和数据线 S(N)界定多个像素单元， 每一像素单元包括一薄 膜晶体管 T、 一公共电极 40、 一与薄膜晶体管 Τ 电性连接的像素电极 30 及一存储电容 Cs, 所述薄膜晶体管 T通过选通线 G(M)及数据线 S(N)分别 与栅极驱动器 10及源极驱动器 20电性连接， 所述公共电极 40与像素电 极 30形成一液晶电容 Clc, 所述存储电容 Cs与该液晶电容 Clc并联连 接。
其中， 所述多条选通线 G(l), G(2) ... ... G(M)形成一选通总线结构 G, 所述多条数据线 S(l), S(2) ... ... S(N)形成一数据总线结构 S。
所述栅极驱动器 10 包括一驱动合成电路， 所述驱动合成电路包括： 第一电开关 SW1、 与第一电开关 SW1 电性连接的放大器 Q、 第一驱动源 Vdd、 第二驱动源 Stc、 电性接于放大器 Q两接口上的第一电阻 Rl、 与放 大器 Q电性连接的第三驱动源 Vddl、 与第一电开关 SW1电性连接的第二 电阻 R2、 电性连接于第二电阻 R2与放大器 Q之间的第二电开关 SW2、 与放大器 Q电性连接的第三电阻 R3及与第二电开关 SW2电性连接的第四 驱动源 Vmc。 所述第一、 第二、 第三及第四驱动源 Vdd、 Stc、 Vddl 及 Vmc可由电源及相应的电路产生。
在本较佳实施例中， 所述薄膜晶体管 T包括： 一栅极 g、 一源极 s及 —漏极 d, 所述栅极 g通过选通线 G(M)电性连接至栅极驱动器 10, 所述 源极 s通过数据线 S(N)电性连接至源极驱动器 20, 所述漏极 d与像素电极 30电性连接， 所述栅极 g与漏极 d因结构特性而形成一寄生电容 Cgd。 所 述栅极驱动器 10对薄膜晶体管 T的栅极 g施加一高电平结束时具^"一下 降率的下降沿 V，sl。p驱动电压， 从而避免寄生电容 Cgd对栅极 g导通时间 的影响。 所述下降沿 V，sl。p在下降的电压时刻内可以部分或者全部 ·ί氐消因 为寄生电容 cgd的存在带 的施加在栅极 g上的放电电压， 减少对栅极 g 的延时时间， 保证薄膜晶体管 TFT的导通或者截止的精确性。
所述第一电开关 SW1 包括： 第一、 第二及第三引脚 1、 2及 3 , 所述 第一引脚 1 电性连接至第一驱动源 Vdd, 所述第二引脚 2 电性连接至第二 驱动源 Stc及放大器 Q , 所述第三引脚 3 电性连接至第二电阻 R2—端。 所述第二电开关 SW2 包括： 第四、 第五及第六引脚 4、 5及 6 , 所述第四 引脚 4电性连接至第二电阻 R2的另一端， 所述第五引脚 5 电性连接至第 四驱动源 Vmc , 所述第六引脚 6电性连接至放大器 Q及第一电阻 R1的一 端。 所述第一电开关 SW1 在第二引脚 2被高电平控制时导通， 被低电平 控制时断开； 所述第二电开关 SW2在第五引脚 5被高电平控制时导通， 被低电平控制时断开。 如此利用第二、 第四驱动源 Stc、 Vmc 来分别驱动 第一、 第二电开关 SW1、 SW2 的导通或断开， 从而实现第一驱动源 Vdd 与第三驱动源 Vddl合成在一起。
所述放大器 Q 包括： 第七、 第八及第九引脚 7、 8及 9 , 所述第七引 脚 7电性连接至第二驱动源 Stc及第一电开关 SW1的第二引脚 2 , 所述第 八引脚 8 电性连接至第三驱动源 Stc及第一电阻 R1 的另一端， 所述第九 引脚 9电性连接至第二电开关 SW2的第六引脚 6、 第一电阻 R1的一端及 第三电阻 R3 , 所述第三电阻 R3另一端连接至地线。 所述薄膜晶体管 T的 栅极 g与第二电阻 R2的与第一电开关 SW1连接端电性连接。
所述第一驱动源 Vdd为一方形波， 所述第二驱动源 81£；为一与第一驱动 源 Vdd具有相同相位及周期的方形波， 所述第三驱动源 Vddl为一三角形 波， 所述第四驱动源 Vmc为一高频率的方形波。 其中， 所述第四驱动源 Vmc可以为一控制时钟信号。
在本较佳实施例中， 所述薄膜晶体管 T的栅极 g上的驱动电压 V 包 括： 所述选通线 G ( M )上驱动电压 V由一高电平 VD1产生电路 VD1X及 一低电平 VD2产生电路 VD2X共同产生， 所述高电平产生电路 VD1X在高 电平结束时刻产生一电压下降沿 V，sl。p。 所述电压下降沿 V，sl。p具有负的线 性电压降或者具有负的阶梯电压降。
请参阅图 10- 12 , 第一驱动源 Vdd、 第二驱动源 Stc、 第三驱动源
Vddl、 第四驱动源 Vmc, 及输出端 VDl c及下降沿 V，sl。p的波形如图所示。 Stc和 Vmc都是一种 CLK变换后的时钟信号， 第一驱动源 Vdd的幅值大小与 选通线 G(j)上的电压信号幅值相同。 当第二驱动源 Stc为高电平时， 第一驱 动源 Vdd处于高电平， 第一电开关 SW1 闭合， 第二电开关 SW2打开， 此 时输出端 VDlc为高电平 VD1 ; 当第二驱动源 Stc为低电平时， 第一驱动 源 Vdd处于低电平， 第一电开关 SW1打开， 第二电开关 SW2受第四驱动 源 Vmc的电平的变化控制其打开或者闭合动作， 同时具有线性下降波形的 第一驱动源 Vddl电压信号经过放大器连接于第二电开关 SW2 , 第一驱动源 Vddl的信号经过放大器 Q , 并在第二电开关 SW2的控制下， 施加到输出端 VDlc。 其中采用输出端 VDlc 与低电平 VD2 合成信号来驱动选通线 G(j), 下降沿 V，sl。p的产生受到第四驱动源 Vmc的控制， 第四驱动源 Vmc在 第二驱动源 Ste处于高电平时处于低电平， 在第二驱动源 Sto由高电平到低 电平的 tx时刻内具有高的频率 f, 在这段时间内第二电开关 SW2高速的导 通与断开， 对加在其上的第三驱动源 Vddl进行抽样， 形成如图 11 所示的 下降沿 V，sl。p波形。 所述下降沿 V，sl。p波形可以根据 tx的时间长短， 以及该 时间段内的频率 f的不同参数， 获得不同的下降沿 V，sl。p波形。
所述下降沿 V，sl。p波形与第一电开关 SW1 闭合、 第二电开关 SW2打 开时的高电平共同构成选通线 G(j)的高电平 VDlc。
综上所述， 本发明液晶面板驱动电路通过电开关控制将方形波驱动电 压与具有一定斜率的三角形波合成到一起， 形成高电平结束时具有一下降 率的下降沿的驱动电压驱动薄膜晶体管的栅极， 从而减少寄生电容因放电 带来的延长薄膜晶体管导通的时间， 进而减小薄膜晶体管非导通状态下的 异常导通的可能性， 进一步提高薄膜晶体管控制的精度， 避免了液晶分子 异常偏转带来的透射率的改变和对比度异常的现象， 提高大尺寸使用该电 路的液晶显示器的质量。
以上所述， 对于本领域的普通技术人员来说， 可以根据本发明的技术 方案和技术构思作出其他各种相应的改变和变形， 而所有这些改变和变形 都应属于本发明权利要求的保护范围。

Claims

权 利 要 求
1、 一种液晶面板驱动电路， 其包括： 栅极驱动器、 源极驱动器、 多 条选通线及多条数据线， 该多条选通线和数据线界定多个像素单元， 每一 像素单元包括一薄膜晶体管、 一公共电极、 一与薄膜晶体管电性连接的像 素电极及一存储电容， 所述薄膜晶体管通过选通线及数据线分别与栅极驱 动器及源极驱动器电性连接， 所述公共电极与像素电极形成一液晶电容， 所述存储电容与该液晶电容并联连接， 所述栅极驱动器包括一驱动合成电 路， 所述驱动合成电路包括： 第一电开关、 与第一电开关电性连接的放大 器、 与第一电开关电性连接的放大器第一驱动源、 与第一电开关电性连接 的放大器第二驱动源、 电性接于放大器两接口上的第一电阻、 与放大器电 性连接的第三驱动源、 与第一电开关电性连接的第二电阻、 电性连接于第 二电阻与放大器之间的第二电开关、 与放大器电性连接的第三电阻及与第 二电开关电性连接的第四驱动源。
2、 如权利要求 1 所述的液晶面板驱动电路， 其中， 所述薄膜晶体管 包括： 一栅极、 一源极及一漏极， 所述栅极通过选通线电性连接至栅极驱 动器， 所述源极通过数据线电性连接至源极驱动器， 所述漏极与像素电极 电性连接。
3、 如权利要求 2 所述的液晶面板驱动电路， 其中， 所述第一电开关 包括： 第一、 第二及第三引脚， 所述第一引脚电性连接至第一驱动源， 所 述第二引脚电性连接至第二驱动源及放大器， 所述第三引脚电性连接至第 二电阻一端。
4、 如权利要求 3 所述的液晶面板驱动电路， 其中， 所述第二电开关 包括： 第四、 第五及第六引脚， 所述第四引脚电性连接至第二电阻的另一 端， 所述第五引脚电性连接至第四驱动源， 所述第六引脚电性连接至放大 器及第一电阻的一端。
5、 如权利要求 4 所述的液晶面板驱动电路， 其中， 所述放大器包 括： 第七、 第八及第九引脚， 所述第七引脚电性连接至第二驱动源及第一 电开关的第二引脚， 所述第八引脚电性连接至第三驱动源及第一电阻的另 一端， 所述第九引脚电性连接至第二电开关的第六引脚、 第一电阻的一端 及第三电阻。
6、 如权利要求 5 所述的液晶面板驱动电路， 其中， 所述薄膜晶体管 的栅极与第二电阻与第一电开关连接端电性连接。
7、 如权利要求 6 所述的液晶面板驱动电路， 其中， 所述第一电开关 在第二引脚被高电平控制时导通， 被低电平控制时断开； 所述第二电开关 在第五引脚被高电平控制时导通， 被低电平控制时断开。
8、 如权利要求 1 所述的液晶面板驱动电路， 其中， 所述第一驱动源 为一方形波， 所述第二驱动源为一与第一驱动源具有相同相位及周期的方 形波， 所述第三驱动源为一三角形波， 所述第四驱动源为一高频率的方形 波。
9、 一种液晶面板驱动电路， 包括： 栅极驱动器、 源极驱动器、 多条 选通线及多条数据线， 该多条选通线和数据线界定多个像素单元， 每一像 素单元包括一薄膜晶体管、 一公共电极、 一与薄膜晶体管电性连接的像素 电极及一存储电容， 所述薄膜晶体管通过选通线及数据线分别与栅极驱动 器及源极驱动器电性连接， 所述公共电极与像素电极形成一液晶电容， 所 述存储电容与该液晶电容并联连接， 所述栅极驱动器包括一驱动合成电 路， 所述驱动合成电路包括： 第一电开关、 与第一电开关电性连接的放大 器、 与第一电开关电性连接的放大器第一驱动源、 与第一电开关电性连接 的放大器第二驱动源、 电性接于放大器两接口上的第一电阻、 与放大器电 性连接的第三驱动源、 与第一电开关电性连接的第二电阻、 电性连接于第 二电阻与放大器之间的第二电开关、 与放大器电性连接的第三电阻及与第 二电开关电性连接的第四驱动源；
其中， 所述薄膜晶体管包括： 一栅极、 一源极及一漏极， 所述栅极通 过选通线电性连接至栅极驱动器， 所述源极通过数据线电性连接至源极驱 动器， 所述漏极与像素电极电性连接；
其中， 所述第一电开关包括： 第一、 第二及第三引脚， 所述第一引脚 电性连接至第一驱动源， 所述第二引脚电性连接至第二驱动源及放大器， 所述第三引脚电性连接至第二电阻一端；
其中， 所述第二电开关包括： 第四、 第五及第六引脚， 所述第四引脚 电性连接至第二电阻的另一端， 所述第五引脚电性连接至第四驱动源， 所 述第六引脚电性连接至放大器及第一电阻的一端；
其中， 所述放大器包括： 第七、 第八及第九引脚， 所述第七引脚电性 连接至第二驱动源及第一电开关的第二引脚， 所述第八引脚电性连接至第 三驱动源及第一电阻的另一端， 所述第九引脚电性连接至第二电开关的第 六引脚、 第一电阻的一端及第三电阻；
其中， 所述薄膜晶体管的栅极与第二电阻与第一电开关连接端电性连 接； 其中， 所述第一电开关在第二引脚被高电平控制时导通， 被低电平控 制时断开； 所述第二电开关在第五引脚被高电平控制时导通， 被低电平控 制时断开；
其中， 所述第一驱动源为一方形波， 所述第二驱动源为一与第一驱动 源具有相同相位及周期的方形波， 所述第三驱动源为一三角形波， 所述第 四驱动源为一高频率的方形波。
PCT/CN2012/084108 2012-10-22 2012-11-06 液晶面板驱动电路 Ceased WO2014063387A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0643833A (ja) * 1992-04-24 1994-02-18 Toshiba Corp 液晶表示装置およびその駆動方法
JPH06110035A (ja) * 1992-09-28 1994-04-22 Seiko Epson Corp 液晶表示装置の駆動方法
CN1319833A (zh) * 2000-03-28 2001-10-31 三洋电机株式会社 有源矩阵型液晶显示装置
CN1667457A (zh) * 2003-09-18 2005-09-14 夏普株式会社 显示装置及其驱动电路和显示方法
CN101300619A (zh) * 2005-11-04 2008-11-05 夏普株式会社 显示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101281498B1 (ko) * 2006-10-31 2013-07-02 삼성디스플레이 주식회사 게이트 구동회로 및 이를 갖는 표시장치
JP2009015832A (ja) * 2007-06-07 2009-01-22 Renesas Technology Corp アクセス間調停回路、半導体装置およびアクセス間調停方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0643833A (ja) * 1992-04-24 1994-02-18 Toshiba Corp 液晶表示装置およびその駆動方法
JPH06110035A (ja) * 1992-09-28 1994-04-22 Seiko Epson Corp 液晶表示装置の駆動方法
CN1319833A (zh) * 2000-03-28 2001-10-31 三洋电机株式会社 有源矩阵型液晶显示装置
CN1667457A (zh) * 2003-09-18 2005-09-14 夏普株式会社 显示装置及其驱动电路和显示方法
CN101300619A (zh) * 2005-11-04 2008-11-05 夏普株式会社 显示装置

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