WO2014056420A1 - 核间通信装置及方法 - Google Patents

核间通信装置及方法 Download PDF

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Publication number
WO2014056420A1
WO2014056420A1 PCT/CN2013/084831 CN2013084831W WO2014056420A1 WO 2014056420 A1 WO2014056420 A1 WO 2014056420A1 CN 2013084831 W CN2013084831 W CN 2013084831W WO 2014056420 A1 WO2014056420 A1 WO 2014056420A1
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Prior art keywords
message
core
read
module
mailbox module
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PCT/CN2013/084831
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English (en)
French (fr)
Inventor
王鹏
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中兴通讯股份有限公司
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Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Priority to EP13845652.0A priority Critical patent/EP2908252B1/en
Priority to KR1020157012032A priority patent/KR101951072B1/ko
Priority to JP2015535970A priority patent/JP6475625B2/ja
Priority to US14/434,245 priority patent/US9639409B2/en
Publication of WO2014056420A1 publication Critical patent/WO2014056420A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/546—Message passing systems or structures, e.g. queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/52—Indexing scheme relating to G06F9/52
    • G06F2209/521—Atomic

Definitions

  • the present invention relates to the field of high performance chip design, and in particular to an inter-core communication device and method.
  • multi-core processors are more and more widely applied to various technical fields, their advantages of powerful parallel computing capability, low power consumption and high integration are gradually accepted by the market.
  • the distinguishing feature of multicore processors is that the same task can be broken down into threads or processes running on multiple cores in parallel, and this parallelism brings significant performance improvements.
  • multi-core processors bring performance improvements, they also bring a series of problems such as frequent inter-core communication tasks and complex management of multi-core communication, and with more and more cores integrated on the same chip, this problem It has become more and more prominent.
  • inter-core communication is generally based on shared memory.
  • the patent number CN200510087321 is a patent "inter-core communication method and apparatus for multi-core processors in an embedded real-time operating system", which uses shared memory to implement a shared message pool and a message data pipeline required for inter-core communication.
  • the patent also fails to solve the problem of resource consumption and complexity increase caused by the introduction of mutually exclusive operations to ensure the reliability of inter-core communication.
  • the communication efficiency is low and the real-time performance cannot be guaranteed.
  • the existing inter-core communication technology will require more hardware resources and more complicated software processing when the number of cores increases significantly.
  • the frequency of the core, the interface structure, and the support for data structures also greatly increase the software complexity of existing inter-core communication methods, and the compatibility and reliability of heterogeneous nuclear communication procedures are insufficient. That is, the existing inter-core communication technology is insufficient in scalability and flexibility in adapting to nuclear heterogeneity and the increase in the number of cores. Therefore, the inter-core communication apparatus and method in the related art have problems of high complexity, poor real-time performance, and poor scalability in multi-core applications.
  • the present invention provides an inter-core communication apparatus and method for solving at least the problems of high complexity, poor real-time performance, and poor scalability in multi-core applications in the related art.
  • an inter-core communication apparatus including: a mailbox module, configured to store a message sent by a message sending core to a message receiving core, and notify the message receiving core to read the message; And a matching module, configured to provide a read/write interface between the mailbox module and the message receiving core and the message sending core, between the message receiving core and the message sending core that communicates with the mailbox module.
  • the inter-core communication device further includes: an arbitration module: configured to, when the plurality of cores simultaneously initiate a read/write access request for requesting the read/write message to the mailbox module, to read the plurality of reads according to a predetermined rule The write access request is arbitrated, and the plurality of read and write access requests are sequentially serially output.
  • the letter box module comprises: a bus interface unit configured to implement mutual exclusion of read and write messages by multiplexing the bus error feedback register.
  • the bus interface unit comprises: a first mutual exclusion unit, configured to implement a mutual exclusion lock function by multiplexing the bus error feedback register, and realize mutual exclusion of writing messages by the plurality of message sending cores to the letter box module And/or a second mutually exclusive unit, configured to implement a mutex lock function by multiplexing the bus error feedback register, implementing a message sending core to write a message to the mailbox module and a message receiving core to read from the mailbox module Mutual exclusion of messages.
  • the bus interface unit further comprises: a triggering subunit, configured to write a message to the mailbox module at the message sending core, or after the message receiving core reads the message from the mailbox module , triggering a state change of the bus error feedback register.
  • the method further comprises: when the plurality of cores simultaneously initiate a read/write access request for requesting the read/write message to the mailbox module, and arbitrating the plurality of read and write access requests according to a predetermined rule, The plurality of read and write access requests are serially output in sequence.
  • the mutual exclusion of the read/write message is implemented by multiplexing the bus error feedback register.
  • the mutual exclusion of the read/write message by multiplexing the bus error feedback register comprises: implementing a mutual exclusion lock function by multiplexing the bus error feedback register, so as to implement mutual message writing by the plurality of message sending cores to the letter box module. And/or, by multiplexing the bus error feedback register to implement the function of the mutex, realizing the mutual exclusion of the message sending core to the letter box module and the message receiving core reading the message from the mailbox module.
  • the message sending core writes a message to the mailbox module, or the message receiving core triggers a state change of the bus error feedback register after reading the message from the letter box module.
  • the mailbox module sends a first response message to the message sending core, where the message sending core is according to the first response message. Determining that the message sending core successfully writes a message to the mailbox module; and/or, after the message receiving core reads the message from the mailbox module, the mailbox module sends a second to the message receiving core a response message, wherein the message receiving core determines that the message receiving core read message is successful according to the second response message.
  • the method further includes: the mailbox module clearing the interrupt request.
  • an inter-core communication apparatus including: a receiving unit, configured to be in a mailbox module, configured to receive a message sent by a message sending core by using a bus adaptation module;
  • the mailbox module is configured to send an interrupt request to the message receiving core, wherein the message receiving core reads the message according to the interrupt request.
  • the mail box module is configured to store a message sent by the message sending core to the message receiving core, and notify the message receiving core to read the message; and the bus adapting module is connected to the letter box module for communication.
  • the message receiving core and the message sending core are configured to provide a read/write interface between the mail box module and the message receiving core and the message sending core, which solves the complexity of the inter-core communication device and method in the prior art.
  • FIG. 1 is a block diagram showing the structure of an inter-core communication apparatus according to an embodiment of the present invention
  • FIG. 2 is a block diagram showing a preferred configuration of an inter-core communication apparatus according to an embodiment of the present invention
  • FIG. 4 is a block diagram showing a preferred structure of a bus interface unit 32 in a letterbox module 12 in an inter-core communication device according to an embodiment of the present invention
  • FIG. 5 is a core according to an embodiment of the present invention.
  • FIG. 6 is a block diagram of a preferred structure of a letter box module 12 in an inter-core communication device according to an embodiment of the present invention;
  • FIG. 7 is an inter-core communication device according to an embodiment of the present invention.
  • Figure 3 is a flow chart of a method for communicating between cores according to an embodiment of the present invention;
  • Figure 9 is a block diagram showing the structure of an inter-core communication device according to an embodiment of the present invention;
  • FIG. 11 is a flowchart of a method for inter-core communication according to an embodiment of the present invention;
  • FIG. 12 is a flowchart of an inter-core communication method according to an embodiment of the present invention.
  • Inter block diagram of a communication device mailbox module is a block diagram inter-core communication apparatus in an embodiment of the present invention, the adaptation module according to the bus;
  • FIG. 14 is a structural block diagram of an arbitration module in an inter-core communication apparatus according to an embodiment of the present invention.
  • the inter-core communication device includes a mailbox module 12 and a bus adapter. Module 14, the apparatus will be described below.
  • the mailbox module 12 is configured to store a message sent by the message sending core to the message receiving core, and notify the message receiving core to read the message;
  • the bus adapting module 14 is connected to the letter box module 12, and is in communication with the mail box module. Between the message receiving core and the message sending core, it is set to provide a read/write interface between the mailbox module and the message receiving core and the message sending core.
  • inter-core communication device only the mailbox module and the architecture of the bus adaptation module connected between the message receiving core and the message sending core are adopted, and the shared memory is used in the related art, or a dedicated interrupt is used to cooperate with the shared memory.
  • the method requires a large number of software interactions, resulting in complicated inter-core communication steps, inefficiency and low flexibility.
  • a simple architecture inter-core communication device composed of a letter box module and a bus adaptation module is used, and the inter-core communication device itself is adopted.
  • the feedback of read and write message access and response to read and write message access significantly reduces the complexity of inter-core communication, effectively reduces communication delay, and can be realized by adding modules only, with better scalability. And can be reduced.
  • FIG. 2 is a block diagram of a preferred structure of an inter-core communication device according to an embodiment of the present invention.
  • the device includes an arbitration module 22, which includes all the modules shown in FIG. Between the mailbox module 12 and the bus adaptation module 14, configured to arbitrate the plurality of read and write access requests according to a predetermined rule when the plurality of cores simultaneously initiate a read/write access request for requesting read and write messages to the mailbox module. , the plurality of read and write access requests are serially output in sequence.
  • 3 is a block diagram of a preferred structure of a letterbox module 12 in an inter-core communication device according to an embodiment of the present invention. As shown in FIG.
  • the mailbox module 12 includes: a bus interface unit 32, which is configured to pass through The bus error feedback register is used to implement mutual exclusion of read and write messages.
  • 4 is a block diagram showing a preferred structure of a bus interface unit 32 in a letterbox module 12 in an inter-core communication device according to an embodiment of the present invention. As shown in FIG. 4, the bus interface unit 32 includes: a first mutex unit 42 and/or a The second mutually exclusive unit 44 will be described below with respect to the preferred bus interface unit.
  • the first mutex unit 42 is configured to implement a mutex lock function by multiplexing the bus error feedback register, and realize mutual exclusion of a plurality of message sending cores to write the message to the mailbox module; and/or, the second mutex unit 44, It is set to realize the mutual exclusion lock function by multiplexing the bus error feedback register, and realizes the mutual exclusion of the message sending core writing the message to the mailbox module and the message receiving core reading the message from the mailbox module.
  • 5 is a block diagram showing a preferred structure of a bus interface unit 32 in an inter-core communication device. As shown in FIG.
  • the bus interface unit 32 includes: a trigger subunit 52, which is set to The message sending core writes a message to the mailbox module, or the message receiving core triggers a state change of the bus error feedback register after reading the message from the mailbox module.
  • 6 is a block diagram of a preferred structure of a mailbox module 12 in an inter-core communication device according to an embodiment of the present invention.
  • the mailbox module 12 includes: a storage unit 62, which is configured to access an address according to a message. The above message is stored.
  • 7 is a block diagram 3 of a preferred structure of a mailbox module 12 in an inter-core communication device according to an embodiment of the present invention. As shown in FIG.
  • the mailbox module 12 includes: a notification unit 72 configured to notify the message receiving core reception by an interrupt request. Message.
  • an inter-core communication method is also provided.
  • FIG. 8 is a flowchart of a method for inter-core communication according to an embodiment of the present invention. As shown in FIG. 8, the process includes the following steps: Step S802, the mailbox module passes The bus adaptation module receives the message sent from the message sending core; in step S804, the mailbox module sends an interrupt request to the message receiving core, wherein the message receiving core reads the message according to the interrupt request.
  • the inter-core communication is realized by the combination of the letter box module and the bus adaptation module, compared with the method of using the shared memory in the related art, or the method of using the dedicated interrupt to cooperate with the shared memory, which requires a lot of software interaction, thereby causing the inter-core
  • the communication steps are complicated, inefficient, and not flexible. Not only is the process simple, but the inter-core communication can be realized only through the message read and write access, which significantly reduces the complexity of inter-core communication and effectively improves to some extent. Inter-core communication efficiency.
  • the plurality of read and write access requests may be arbitrated according to a predetermined rule, and the plurality of read and write access requests are sequentially Serial output.
  • the multiple cores may be multiple message sending cores, multiple message receiving cores, or a mixture of the two.
  • the read and write access requests are first arbitrated. To avoid confusion of inter-core communication.
  • the arbitration module can count the number of multiple cores for inter-core communication. The quantity is different and flexible.
  • the mutual exclusion of read and write messages is implemented by multiplexing the bus error feedback register.
  • the use of the bus error feedback register in the inter-core communication to achieve the mutual exclusion of the read and write messages compared with the prior art, in order to achieve the mutual exclusion function, additional mutual exclusion devices and additional mutually exclusive operation steps are required, which can not only reduce The interaction between the inter-core communication device and the external structure, and to some extent, effectively reduces the consumption of resources.
  • the multiplex bus error feedback register can better realize the mutual exclusion of read and write messages for the abnormal situations that are more likely to occur in inter-core communication.
  • the function of mutual exclusion lock is realized by multiplexing the bus error feedback register. , implementing multiple messages to send a message to the mailbox module to write a mutual exclusion; for example, by multiplexing the bus error feedback register to implement the function of the mutex, the message sending core writes the message to the mailbox module and the message receiving core reads from the mailbox module Mutual exclusion of messages.
  • the two can be combined.
  • the message sending core writes a message to the mailbox module, or after the message receiving core reads the message from the mailbox module, the change of the read/write state of the mailbox module is realized by triggering the change of the state of the bus error feedback register, thereby avoiding The loss of messages, the order of reading and writing, and the reliability of reading and writing messages.
  • the mailbox module sends a first response message to the message sending core, where the message sending core determines that the message sending core writes to the letter box module according to the first response message.
  • the message succeeds; and/or, after the message receiving core reads the message from the mailbox module, the mailbox module sends a second response message to the message receiving core, wherein the message receiving core determines the message receiving the core read message according to the second response message. success.
  • the mailbox module After determining that the message receiving core has read the message, the mailbox module automatically clears the interrupt request. When a new message is subsequently written, a new interrupt request is generated, which not only ensures the correspondence of the read/write message, but also reduces the operation steps of receiving the core clear interrupt request.
  • an inter-core communication device is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments, and has not been described again.
  • module may implement a combination of software and/or hardware of a predetermined function.
  • the apparatus described in the following embodiments is preferably implemented in hardware, software, or a combination of software and hardware, is also possible and conceivable.
  • 9 is a block diagram showing the structure of an inter-core communication apparatus according to an embodiment of the present invention. As shown in FIG. 9, the apparatus is located in a mailbox module 90, a receiving unit 92 and a transmitting unit 94, which will be described below.
  • the receiving unit 92 is configured to receive the message sent by the message sending core by using the bus adapting module; the sending unit 94 is connected to the receiving unit 92, and is configured to send an interrupt request to the message receiving core, where the message receiving core is according to the interrupt Request to read the above message.
  • the inter-core communication device has high complexity, poor real-time performance, and poor scalability in multi-core applications.
  • ICN inter-core communication network
  • the ICN includes any number of the following three types of modules: the mailbox module (Postbox) (same as the above mailbox module 12), the bus adapter module (Bus Adapter, abbreviated as BA) (same as the bus adaptation module 14 described above), and the arbitration module (Arbiter). (Same as above arbitration module 22).
  • the ICN can be applied to a hierarchical structure to meet the application scenario in which the number of cores is significantly increased and the core is heterogeneous.
  • FIG. 10 is a structural block diagram of an inter-core communication device of a multi-core chip according to an embodiment of the present invention. As shown in FIG. 10, the structure includes a mailbox. Module, bus adaptation module, arbitration module, the device will be described separately below.
  • the mailbox module (Postbox) message needs to be temporarily stored somewhere for the receiving core to read, and has a reliable mechanism for receiving the arrival of the core message.
  • the ICN provided in this embodiment includes several Postbox modules.
  • the mailbox module provides the following functions: mutually exclusive read and write messages, message storage, and notification interrupt requests.
  • the Postbox module is completed by the following units, that is, the bus module includes a plurality of Bus Interface Units (BIUs), a plurality of message storage units (RegFiles), and a plurality of interrupt generations.
  • the unit (IntGen) describes the units included in the mailbox module separately.
  • BIU unit Set to achieve exclusive access to read and write messages.
  • the BIU unit provides a read message channel for the message receiving core and a write message channel for several message sending cores.
  • BIU Unit Multiplexed Bus Error (Error)
  • the Feedback Register implements a lock completion access to the same resource (referred to as RegFiles below).
  • RegFiles unit Set to provide several unit message storage register spaces. For each Postbox, there are several sets of message storage registers for several send message channels. At the same time, according to the communication traffic determined by the application requirements, more message registers can also be set, and different message registers are distinguished by addresses.
  • IntGen unit Set to notify the receiving core of the interrupt request when a message arrives. If the receiving core detects that the message has been read, the interrupt request is automatically cleared. It can be seen that it avoids the need to additionally set the interrupt clear register operation for reading messages in the traditional inter-core communication mode.
  • Each interrupt line can be bundled with one or a group of Regfiles, so that the receiving core can enter the specific ISR (interrupt service routine) through the interrupt request number and read the message in the corresponding RegFiles.
  • the Postbox in the inter-core communication device of this embodiment has a mutually exclusive access protection function that is not available in the related art: In the traditional multi-core communication mode, multiple cores occupy the same inter-core communication resource and need to use a mutex or a spin lock to perform mutual exclusion operations.
  • the Postbox multiplexed bus Error feedback register implements a lock register to complete the exclusive access function. The operation is as follows:
  • the BIU Multiplex Error Information Feedback Register implements a lock register.
  • the lock register When the lock register is 0, it means the lock is released; when the lock register is 1, it means the lock is occupied.
  • the lock register automatically changes to 1 after the send core writes Postbox RegFiles. After that, Postbox generates an interrupt notification receiving core, and the receiving core performs a Postbox RegFiles read operation, and the lock register automatically becomes 0.
  • Postbox After that, Postbox generates an interrupt notification receiving core, and the receiving core performs a Postbox RegFiles read operation, and the lock register automatically becomes 0.
  • the first exception that is, before the receiving core performs a Postbox RegFiles read operation
  • another sending core wants to write to a Regfiles. If the message in Regfiles is modified at this time, the previous message will be lost.
  • the lock register in the Postbox in this example is 1, it indicates that the lock is in the occupied state, so the send message write operation is unsuccessful, that is, the Postbox RegFiles information is not modified; meanwhile, the lock register information 1 will be returned as an Error response message to the send message.
  • the kernel notified it that an abnormal operation was performed.
  • the core enters exception handling, which allows it to wait for several instruction cycles to continue accessing. Until the receiving core performs a normal read Postbox RegFiles operation, the lock register becomes 0, that is, the lock is released, and other transmitting cores can perform normal write operations.
  • the BIU When the second type of abnormality occurs, that is, while a core write message operation occurs while receiving the core read message, the BIU is forced to perform the order of reading first and then writing, that is, the previous message is first read, and then In order to write new messages, this ensures the reliability of inter-core communication.
  • Bus Adaptation Module (BA, Bus Adapter): Since the bus protocol between the cores for communication may be different, and the core needs to access more Postbox, the ICN in this embodiment includes several BA modules, including 1 The core read/write interface and several Postbox read/write interfaces, the BA module performs the following two functions:
  • the BA module can significantly isolate the external complex bus protocol, and the internal only uses a simple and fast data read/write protocol, which significantly reduces the hardware delay of the inter-core communication device.
  • Arbitration module A conflict occurs when there is multiple cores within a cluster that simultaneously initiate read and write access to a Postbox message.
  • the ICN in this embodiment includes a number of Arbiter modules including a number of message input interfaces and a message output interface. It is used to provide the following functions: The read and write access requests for several data channels are arbitrated according to specific principles, and the simultaneous read and write access requests are serialized. Among them, Arbiter polls and arbitrates the read and write access of messages arriving at the arbitration module at the same time, even if multiple simultaneous read and write accesses are serially output in sequence; or, priority is given to read and write access to messages arriving at the arbitration module at the same time.
  • FIG. 11 is a flowchart of a method for inter-core communication according to an embodiment of the present invention. As shown in FIG. 11, the method includes the following steps: Step S1102: Sending a message core Write a message through the BA, and determine whether the message was sent successfully according to the information returned by the BA. The write operations of each core are asynchronous and independent, and do not affect each other. If the Error Response message returned by the BA is invalid, the message is sent successfully; otherwise, the Postbox is occupied and the message is unsuccessful.
  • the sending core can delay the writing of the message after several cycles until the message is sent successfully.
  • the sending message of the sending core is sent to the Postbox having a specific address through the Arbiter or not through the Arbiter, and the Postbox generates an interrupt request (int) to the receiving message core.
  • Step S1106 The receiving core receives the interrupt and performs a message reading operation.
  • Step S1108 The message read operation request signal of the receiving core enters the ICN until it is sent to the mailbox module (Postbox) that generates the interrupt request, and reads the message sent to it, and the interrupt request of the Postbox is automatically pulled low.
  • the embodiments and preferred embodiments provided by the present invention have a natural mutual exclusion function.
  • the multi-core is not limited to the CPU (Central Processing Unit) and DSP (Digital Signal Processor) as exemplified in the implementation examples.
  • the entire ICN uses a 3-level architecture to meet the application needs of multicore (10 cores total) and nuclear heterogeneous (6DSP+4ARM).
  • the entire ICN contains 15 Postboxes, 10 BAs and 4 Arbiters.
  • the overall structure is shown in Figure 10. Three DSPs form a cluster. Two CPUs constitute one cluster, and because the data traffic is relatively small, the data path does not pass through the arbiter.
  • the ICN can select the number of three types of components according to the number of cores and the communication traffic, and the interconnection mode (for example, directly connected to Postbox without an arbiter in the implementation example), and does not affect the entire structural features and communication flow of the ICN. Extend the present and the cutability is excellent.
  • Postbox is divided into Local Postbox and B Cross Postbox. Specifically, in the present embodiment, there are the following: 10 local Postboxs responsible for inter-core communication within the DSP cluster and the DSP cluster, responsible for inter-core communication between the DSP cluster and the CPU cluster 1 local Postbox, responsible for inter-core communication between DSP clusters, 1 Cross Postbox, or 1 cross-communication between CPU clusters for inter-core communication.
  • this distributed structure can restrict certain communication traffic to the bandwidth of a specific area without any influence on other communication areas, and significantly reduce the arbitration overhead of a single arbitration module, and significantly increase the overall bandwidth efficiency of the multi-core. Reduce the communication delay of the multi-core as a whole.
  • multiple Postbox interrupt requests can be merged or logically combined to reduce the number of inter-core interrupt requests arriving at the core. It greatly increases the extensibility of ICN.
  • the specific implementation of the 3 types of modules included in the ICN is as follows -
  • the mailbox module (Postbox) message needs to be temporarily stored somewhere for the receiving core to read, and has a reliable mechanism for receiving the incoming nuclear message. Therefore, the ICN of the present invention includes a plurality of Postbox modules. It provides the following functions: Message store mutually exclusive read and write messages generate notification interrupt requests 12 is a structural block diagram of a letter box module in an inter-core communication device according to an embodiment of the present invention. As shown in FIG. 12, the mailbox module (Postbox) includes a plurality of BIU units, a plurality of RegFiles units, and a plurality of IntGen units. Among them, each functional unit is as follows:
  • BIU unit Implements exclusive access to read and write messages.
  • BUS0 is the read message channel of the receiving core to which the Postbox belongs, and BUS1 ⁇ n is the write message channel of the sending core.
  • BIU Unit Multiplexed Bus The Error Feedback Register implements a lock-complete access to the same RegFiles unit.
  • RegFiles unit Provides several unit message storage register spaces. For each Postbox, there are several sets of message storage registers for several messaging channels. At the same time, according to the communication traffic determined by the application requirements, more message registers can also be set, and different message registers are distinguished by addresses.
  • IntGen unit When a message arrives, it is responsible for generating an interrupt request to notify the receiving core. If the receiving core detects that the message has been read, the interrupt request is automatically cleared. It can be seen that it avoids the need to additionally set the interrupt clear register operation when reading messages in the traditional inter-core communication mode.
  • Each of the interrupt lines can be bundled with one or a group of Regfiles, so that the receiving core can enter the specific ISR (Interrupt Service Routine) through the interrupt request number and read the message in the corresponding RegFiles.
  • ISR Interrupt Service Routine
  • the Postbox multiplex bus error feedback register implements a lock register to complete the mutual access access function.
  • the specific implementation is as follows:
  • the BIU multiplexes the Error Information Feedback Register to implement a lock register.
  • the lock register When the lock register is 0, it means the lock is released; when the lock register is 1, it means the lock is occupied.
  • the lock register automatically changes to 1 after the send core writes Postbox RegFiles.
  • Postbox After that, Postbox generates an interrupt notification receiving core, the receiving core performs a Postbox RegFiles read operation, and the lock register automatically becomes 0; when the first exception occurs, that is, before the receiving core performs a Postbox RegFiles read operation, another sending core wants to Regfiles writes, if the message in Regfiles is modified at this time, it will cause the previous The message is missing.
  • the lock register in the Postbox of this embodiment is 1, it indicates that the lock is in the occupied state, so the sending of the message write operation is unsuccessful, that is, the Postbox RegFiles information is not modified; meanwhile, the lock register information 1 is returned to the sending core as the Error response information. Notify it that an abnormal operation has been performed.
  • the core enters exception handling, that is, it waits for several instruction cycles to continue accessing. Until the receiving core performs a normal read Postbox RegFiles operation, the lock register becomes 0, that is, the lock is released, and other transmitting cores can perform normal write operations.
  • the BIU When the second type of abnormality occurs, that is, while a core write message operation occurs while receiving the core read message, the BIU is forced to perform the order of reading first and then writing, that is, the previous message is first read, and then In order to write new messages, this ensures the reliability of inter-core communication.
  • the lock register generates the register from the device Error information, that is, there is no need to add additional mutually exclusive function units such as mutex and semaphore; if the lock operation is successful, the message sending operation is successful, and the release of the lock is a message.
  • the message request lock failure is the bus feedback Error response, that is, the mutual exclusion processing mechanism is consistent with the bus common read and write mechanism, that is, without adding additional mutual exclusion operation cycles, the programming complexity and communication delay are significantly reduced. Therefore, the apparatus and method described in the above embodiments and preferred embodiments implement mutual exclusion access protection for inter-core communication resources.
  • Bus Adaptation Module (BA, Bus Adapter): Since the bus protocol between the cores for communication may be different, and the core needs to access more Postbox, the ICN of the present invention includes several BA modules, including one The core read and write interface and several Postbox read and write interfaces complete two functions:
  • FIG. 13 is a structural block diagram of a bus adaptation module in an inter-core communication device according to an embodiment of the present invention. As shown in FIG.
  • the BA enables different output of the APB selection signal according to whether the access address of the APB matches the register address of the Postbox, thereby strobing different message paths.
  • the APB interface is readable and writable, and the core reads and writes messages to the Postbox through the APB interface.
  • FIG. 14 is a structural block diagram of an arbitration module in an inter-core communication device according to an embodiment of the present invention. As shown in FIG. 14, the arbitration module includes a plurality of message input interfaces and one message. Output Interface. It provides the following functions: Read and write access requests to several data channels are arbitrated according to specific principles, and messages read and write access requests that arrive at the same time are serialized.
  • the Arbiter polls and arbitrates the read and write access of the message to the arbitration module at the same time, even if multiple simultaneous read and write accesses are serially output in sequence; that is, between different data paths in which the message read and write request exists. Polling, that is, each time only one data path of the existing request can be strobed, after the read and write access is completed, the next data path of the existing message read and write request is strobed; and so on, until the message read and write request of all the paths is processed. .
  • the message read and write access to the arbitration module can be prioritized, even if multiple simultaneous message read and write access requests are performed in descending order of priority.
  • the steps of applying the inter-core communication method of the inter-core communication device are as follows:
  • the message core to be sent is written by the BA, and the message is sent according to the information returned by the BA.
  • the write operations of each core are asynchronous and independent, and do not affect each other. If the Error Response message returned by the BA is invalid, the message is sent successfully; otherwise, the Postbox is occupied and the message is unsuccessful. At this point, the sending core can delay the writing of the message after several cycles until the message is sent successfully.
  • the sending message of several sending cores is sent to the Postbox with a specific address through Arbiter or without Arbiter, and the Postbox generates an interrupt request to the receiving message core.
  • the receiving core receives the interrupt and performs a message read operation.
  • the message read operation request signal of the receiving core enters the ICN until it is sent to the Postbox that generates the interrupt request, and reads the message sent to it, and the interrupt request of the Postbox is automatically pulled low (the interrupt request corresponding to the read message is automatically cleared) ).
  • the DSPO enters the ISR and reads the messages in the Postbox.
  • DSP clusterO internally sends a message core DSP2 sends a message to PostboxO belonging to the destination core DSP0; DSP cluster 1 sends a message core DSP3, 4 simultaneously has a message to be sent to DSP clusterO DSPO. Therefore, it was first arbitrated by Arbiter2 inside DSP cluster 1. It is assumed that the transmitting core DSP3 obtained the arbitration right, first wrote the message to the Postbox of DSP CLUSTERO, and then sent the core DSP4 to obtain the arbitration right, and wrote the message to the DSP CLUSTERO. Postbox;
  • DSP CLUSTERO internal PostboxO and DSP CLUSTERO Postbox have interrupt request generated at the same time;
  • the DSP0 core enters the ISR. According to the priority set by the software, it is assumed that the internal PostboxO message is read first, and then the message in the Postbox of the DSP CLUSTERO is read.
  • CPU CORE0 sends a message to CPU&DSP cross Postbox via BA6, but returns ERROR message, indicating that the communication resource lock has not been released, the message has not been sent successfully; CPU CORE0 enters the waiting period and then sends the message again.
  • DSP5 processes the high priority transaction and successfully reads the first message.
  • the inter-core communication device After reset, it can work normally; when the message read/write request enters the ICN, it is completely managed by the ICN, which significantly reduces the complexity of the inter-core communication and reduces the communication delay; the inter-core communication device adopts a distributed structure, which can make Some traffic is limited to the bandwidth of a particular area without any impact on other areas of communication, and significantly reduces the arbitration overhead of a single arbitration module, thereby significantly reducing the statistical communication delay of the overall multicore; when the number of cores increases significantly, Through the foregoing embodiments and the preferred embodiments, only a corresponding number of Type 3 modules and corresponding interconnecting lines need to be added, and the interconnection manner can also be flexibly connected according to application requirements, without affecting the existing structural features and software operation steps of the ICN, and thus Excellent scalability and cutability.
  • modules or steps of the present invention can be implemented by a general-purpose computing device, which can be concentrated on a single computing device or distributed over a network composed of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device, such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein.
  • the steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps are fabricated as a single integrated circuit module.
  • the invention is not limited to any specific combination of hardware and software.
  • the above is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

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Abstract

本发明提供了一种核间通信装置及方法，该装置包括：信箱模块，设置为存储消息发送核发送给消息接收核的消息，并通知消息接收核读取所述消息；总线适配模块，连接于信箱模块与进行通信的消息接收核和消息发送核之间，设置为提供信箱模块与消息接收核和消息发送核的读写接口，通过本发明，解决了相关技术中核间通信装置和方法存在复杂度高、实时性差，以及多核应用时可扩展性差的问题，进而达到了显著减少核间通信复杂度，减少通信时延，以及具备极好的可扩展性和可裁减性的效果。

Description

核间通信装置及方法
技术领域 本发明涉及高性能芯片设计领域， 具体而言， 涉及一种核间通信装置及方法。 背景技术 随着多核处理器被越来越广泛的应用到各个技术领域， 其强大的并行计算能力， 低功耗以及高集成度的优点逐渐被市场所接受。 多核处理器的显著特征是同一个任务 可以被分解到多个内核的线程或进程上并行运行，这种并行性带来了性能的显著提升。 但是多核处理器带来性能提升的同时， 也带来了频繁的核间通信任务以及复杂的对多 核通信进行管理等一系列问题， 而且随着同一芯片上集成的核越来越多， 此问题变的 越来越突出。 因此， 高速高效的核间通信装置和方法成为多核处理器芯片的关键技术 之一。 在相关技术中，普遍基于共享内存进行核间通信。例如，专利号为 CN200510087321 的专利"嵌入式实时操作系统中多核处理器的核间通信方法及装置"， 其采用共享内存 实现核间通信所需的共享消息池和消息数据管道。 该种方法需要操作系统软件创建消 息队列， 需要建立核间通信的管道操作， 因此复杂性较高； 更关键的是为了完成对多 核共享消息内存的访问一致性需要采用自旋锁资源以及额外的申请锁释放锁等同步操 作， 这些复杂的软件交互步骤将大大降低核间通信的效率， 同时在核数量显著增加时 可靠性降低； 其分离的消息操作和中断通知机制也会导致效率下降。 此外， 基于共享 内存的方法由于核间消息必须与数据共用同一带宽， 在通信实时性上更增加了不确定 性。 为解决基于共享内存的核间通信机制的高复杂性高时延问题， 也产生了一些改进 方法。 例如， 专利号为 US20080988459的专禾 l」"Method and System for Generating and Delivering Inter-Processor Interrupts in a Multi-Core Processor and in Certain Shared Memory Multi-Processor Systems" , 其通过软件操作一组专用的中断屏蔽寄存器 (Interrupt Mask Register, 简称为 IMR) 来指定共享存储区域， 并在写操作针对所指 定的共享存储器区域时自动触发核间中断生成。 但其消息是存在共享存储区的循环缓 冲中， 仍旧需要通过软件实现的数据结构进行循环缓冲访问； 而消息通知所产生的中 断由 IMR产生。 其仍需要提前设置 IMR寄存器， 且寄存器操作与消息操作的分离以 及软件交互步骤多等因素直接导致其核间通信延迟较大， 软件编程复杂， 无法满足高 性能多核通信的需要。 同时， 该专利也未能解决为保证核间通信可靠性必须引入互斥 操作而带来的资源消耗和复杂度提升的问题。 除了上面所述现有核间通信技术通信效率低， 实时性无法保证的主要缺陷外， 现 有核间通信技术在核数量显著增加时， 其将需要更多的硬件资源和更加复杂的软件处 理步骤； 在异构多核系统中， 核的频率， 接口结构以及对数据结构的支持差异也大大 增加了现有核间通信方法的软件复杂性， 异构核通信程序的兼容性和可靠性不足。 即 现有核间通信技术在适应核异构和核数量增加时的可扩展性和灵活性不足。 因此， 在相关技术中的核间通信装置和方法存在复杂度高、 实时性差， 以及多核 应用时可扩展性差的问题。 发明内容 本发明提供了一种核间通信装置及方法， 以至少解决相关技术中核间通信装置和 方法存在复杂度高、 实时性差， 以及多核应用时可扩展性差的问题。 根据本发明的一个方面， 提供了一种核间通信装置， 包括： 信箱模块， 设置为存 储消息发送核发送给消息接收核的消息， 并通知所述消息接收核读取所述消息； 总线 适配模块， 连接于所述信箱模块与进行通信的所述消息接收核和消息发送核之间， 设 置为提供所述信箱模块与所述消息接收核和所述消息发送核的读写接口。 优选地， 该核间通信装置还包括： 仲裁模块： 设置为在多个核同时向所述信箱模 块发起用于请求读写消息的读写访问请求时， 按照预定的规则对所述多个读写访问请 求进行仲裁， 将所述多个读写访问请求依次串行输出。 优选地， 所述信箱模块包括： 总线接口单元， 设置为通过复用总线错误反馈寄存 器实现读写消息的互斥。 优选地， 所述总线接口单元包括： 第一互斥单元， 设置为通过复用所述总线错误 反馈寄存器实现互斥锁的功能， 实现多个消息发送核向所述信箱模块写消息的互斥； 和 /或， 第二互斥单元， 设置为通过复用所述总线错误反馈寄存器实现互斥锁的功能， 实现消息发送核向所述信箱模块写消息与消息接收核从所述信箱模块读消息的互斥。 优选地， 所述总线接口单元还包括： 触发子单元， 设置为在所述消息发送核向所 述信箱模块写入了消息， 或者， 所述消息接收核从所述信箱模块读取了消息之后， 触 发所述总线错误反馈寄存器的状态变化。 优选地， 所述信箱模块包括： 存储单元， 设置为根据消息访问地址对所述消息进 行存储。 优选地， 所述信箱模块包括： 通知单元， 设置为通过中断请求通知所述消息接收 核接收消息。 根据本发明的另一方面， 提供了一种核间通信方法， 包括： 信箱模块通过总线适 配模块接收来自消息发送核发送的消息； 所述信箱模块向消息接收核发送中断请求， 其中， 所述消息接收核根据所述中断请求读取所述消息。 优选地， 该方法还包括： 在多个核同时向所述信箱模块发起用于请求读写消息的 读写访问请求时， 按照预定的规则对所述多个读写访问请求进行仲裁， 将所述多个读 写访问请求依次串行输出。 优选地，在多个核同时向所述信箱模块发起用于请求读写消息的读写访问请求时， 通过复用总线错误反馈寄存器实现读写消息的互斥。 优选地， 通过复用总线错误反馈寄存器实现读写消息的互斥包括： 通过复用所述 总线错误反馈寄存器实现互斥锁的功能， 实现多个消息发送核向所述信箱模块写消息 的互斥； 和 /或， 通过复用所述总线错误反馈寄存器实现互斥锁的功能， 实现消息发送 核向所述信箱模块写消息与消息接收核从所述信箱模块读消息的互斥。 优选地， 在所述消息发送核向所述信箱模块写入了消息， 或者， 所述消息接收核 从所述信箱模块读取了消息之后， 触发所述总线错误反馈寄存器的状态变化。 优选地， 在所述消息发送核向所述信箱模块写入了消息之后， 所述信箱模块向所 述消息发送核发送第一响应消息， 其中， 所述消息发送核根据所述第一响应消息确定 所述消息发送核向所述信箱模块写入消息成功； 和 /或， 在所述消息接收核从所述信箱 模块读取了消息之后， 所述信箱模块向所述消息接收核发送第二响应消息， 其中， 所 述消息接收核根据所述第二响应消息确定所述消息接收核读取消息成功。 优选地， 在所述消息接收核读取了所述消息之后， 还包括， 所述信箱模块将所述 中断请求清除。 根据本发明的再一方面， 提供了一种核间通信装置， 包括： 接收单元， 设置为信 箱模块中， 用于通过总线适配模块接收来自消息发送核发送的消息； 发送单元， 位于 所述信箱模块中， 设置为向消息接收核发送中断请求， 其中， 所述消息接收核根据所 述中断请求读取所述消息。 通过本发明， 采用信箱模块， 设置为存储消息发送核发送给消息接收核的消息， 并通知所述消息接收核读取所述消息； 总线适配模块， 连接于所述信箱模块与进行通 信的所述消息接收核和消息发送核之间， 设置为提供所述信箱模块与所述消息接收核 和所述消息发送核的读写接口，解决了现有技术中核间通信装置和方法存在复杂度高、 实时性差， 以及多核应用时可扩展性差的问题，进而达到了显著减少核间通信复杂度， 减少通信时延， 以及具备极好的可扩展性和可裁减性的效果。 附图说明 此处所说明的附图用来提供对本发明的进一步理解， 构成本申请的一部分， 本发 明的示意性实施例及其说明用于解释本发明， 并不构成对本发明的不当限定。 在附图 中： 图 1是根据本发明实施例的核间通信装置的结构框图； 图 2是根据本发明实施例的核间通信装置的优选结构框图； 图 3是根据本发明实施例的核间通信装置中信箱模块 12的优选结构框图一； 图 4是根据本发明实施例的核间通信装置中信箱模块 12中总线接口单元 32的优 选结构框图； 图 5是根据本发明实施例的核间通信装置中总线接口单元 32的优选结构框图； 图 6是根据本发明实施例的核间通信装置中信箱模块 12的优选结构框图二； 图 7是根据本发明实施例的核间通信装置中信箱模块 12的优选结构框图三； 图 8是根据本发明实施例的核间通信方法的流程图； 图 9是根据本发明实施例的核间通信装置的结构框图； 图 10是根据本发明实施例的多核芯片的核间通信装置结构框图； 图 11是根据本发明实施例的核间通信方法的流程图； 图 12是根据本发明实施例的核间通信装置中信箱模块的结构框图； 图 13是根据本发明实施例的核间通信装置中总线适配模块的结构框图； 图 14是根据本发明实施例的核间通信装置中仲裁模块的结构框图。 具体实施方式 下文中将参考附图并结合实施例来详细说明本发明。 需要说明的是， 在不冲突的 情况下， 本申请中的实施例及实施例中的特征可以相互组合。 在本实施例中提供了一种核间通信装置， 图 1是根据本发明实施例的核间通信装 置的结构框图， 如图 1所示， 该核间通信装置包括信箱模块 12和总线适配模块 14， 下面对该装置进行说明。 信箱模块 12， 设置为存储消息发送核发送给消息接收核的消息， 并通知消息接收 核读取该消息； 总线适配模块 14， 连接于上述信箱模块 12， 并且， 处于信箱模块与进 行通信的消息接收核和消息发送核之间， 设置为提供信箱模块与消息接收核和消息发 送核的读写接口。 通过上述核间通信装置， 仅采用信箱模块以及连接于消息接收核与消息发送核之 间的总线适配模块的架构， 相对于相关技术中采用共享内存的方式， 或者， 采用专用 中断配合共享内存的方式由于需要众多软件交互， 从而导致核间通信步骤复杂， 效率 低下以及灵活性不高的问题， 采用信箱模块与总线适配模块构成的简单架构的核间通 信装置， 通过核间通信装置本身读写消息访问及响应读写消息访问的反馈， 显著地减 少了核间通信的复杂度， 有效地减少了通信时延， 同时仅靠增加模块的方式就可以实 现， 具备较佳的可扩展性及可裁减性。 图 2是根据本发明实施例的核间通信装置的优选结构框图， 如图 2所示， 该装置 除包括图 1所示的所有模块外， 还包括仲裁模块 22， 该仲裁模块 22: 连接于信箱模块 12与总线适配模块 14之间， 设置为在多个核同时向信箱模块发起用于请求读写消息 的读写访问请求时， 按照预定的规则对上述多个读写访问请求进行仲裁， 将该多个读 写访问请求依次串行输出。 图 3是根据本发明实施例的核间通信装置中信箱模块 12的优选结构框图一，如图 3所示， 该信箱模块 12包括： 总线接口单元 32， 该总线接口单元 32， 设置为通过复 用总线错误反馈寄存器实现读写消息的互斥。 图 4是根据本发明实施例的核间通信装置中信箱模块 12中总线接口单元 32的优 选结构框图， 如图 4所示， 该总线接口单元 32包括： 第一互斥单元 42和 /或第二互斥 单元 44， 下面对该优选总线接口单元进行说明。 第一互斥单元 42， 设置为通过复用总线错误反馈寄存器实现互斥锁的功能， 实现 多个消息发送核向该信箱模块写消息的互斥； 和 /或， 第二互斥单元 44， 设置为通过复 用总线错误反馈寄存器实现互斥锁的功能， 实现消息发送核向该信箱模块写消息与消 息接收核从该信箱模块读消息的互斥。 图 5是根据本发明实施例的核间通信装置中总线接口单元 32的优选结构框图，如 图 5所示， 该总线接口单元 32包括： 触发子单元 52， 该触发子单元 52， 设置为在消 息发送核向信箱模块写入了消息， 或者， 消息接收核从信箱模块读取了消息之后， 触 发总线错误反馈寄存器的状态变化。 图 6是根据本发明实施例的核间通信装置中信箱模块 12的优选结构框图二，如图 6所示， 该信箱模块 12包括： 存储单元 62， 该存储单元 62， 设置为根据消息访问地 址对上述消息进行存储。 图 7是根据本发明实施例的核间通信装置中信箱模块 12的优选结构框图三，如图 7所示， 该信箱模块 12包括： 通知单元 72， 设置为通过中断请求通知上述消息接收核 接收消息。 在本实施例中还提供了一种核间通信方法， 图 8是根据本发明实施例的核间通信 方法的流程图， 如图 8所示， 该流程包括如下步骤： 步骤 S802， 信箱模块通过总线适配模块接收来自消息发送核发送的消息； 步骤 S804， 该信箱模块向消息接收核发送中断请求， 其中， 该消息接收核根据上 述中断请求读取上述消息。 通过上述步骤， 通过信箱模块以及总线适配模块的组合实现核间通信， 相对于相 关技术中采用共享内存的方式， 或者， 采用专用中断配合共享内存的方式由于需要众 多软件交互， 从而导致核间通信步骤复杂， 效率低下以及灵活性不高的问题， 不仅流 程简单，仅通过消息读写访问本身即可实现核间通信， 显著减少了核间通信的复杂度， 而且在一定程度上有效地提高了核间通信效率。 优选地， 在多个核同时向信箱模块发起用于请求读写消息的读写访问请求时， 可 以按照预定的规则对该多个读写访问请求进行仲裁， 将上述多个读写访问请求依次串 行输出。 需要说明的是， 上述多个核可以是多个消息发送核， 也可以是多个消息接收 核， 也可以为两者的混合， 在进行读写访问之前， 对读写访问请求先进行仲裁处理， 避免核间通信的混乱， 另外， 该仲裁模块可以根据具体的进行核间通信的多个核的数 量不同而灵活选择， 例如， 当进行通信的核的数量较少时， 可以不采用， 而核的数量 较多时， 则也可以选择一个或多个仲裁模块进行处理。 在多个核同时向信箱模块发起用于请求读写消息的读写访问请求时， 通过复用总 线错误反馈寄存器实现读写消息的互斥。 利用核间通信中已有的总线错误反馈寄存器 实现读写消息的互斥， 相对于现有技术中为了实现互斥功能需要增加另外的互斥装置 和另外的互斥操作步骤， 不仅能够减少了核间通信装置与外部结构的交互， 并且在一 定程度上有效地降低了资源的消耗。 需要指出的是， 对于核间通信中较为容易出现的异常情况， 复用总线错误反馈寄 存器可以较好地实现读写消息的互斥， 例如， 通过复用总线错误反馈寄存器实现互斥 锁的功能， 实现多个消息发送核向信箱模块写消息的互斥； 又例如， 通过复用总线错 误反馈寄存器实现互斥锁的功能， 实现消息发送核向信箱模块写消息与消息接收核从 信箱模块读消息的互斥。 当然， 两者可以结合使用。 操作时， 在消息发送核向信箱模 块写入了消息， 或者， 消息接收核从信箱模块读取了消息之后， 通过触发总线错误反 馈寄存器状态的变化来实现信箱模块的读写状态的变化， 避免消息的丢失， 实现读写 的有序性， 保证读写消息的可靠性。 较优地， 在消息发送核向信箱模块写入了消息之后， 信箱模块向消息发送核发送 第一响应消息， 其中， 该消息发送核根据上述第一响应消息确定消息发送核向信箱模 块写入消息成功； 和 /或， 在消息接收核从信箱模块读取了消息之后， 信箱模块向消息 接收核发送第二响应消息， 其中， 消息接收核根据该第二响应消息确定消息接收核读 取消息成功。 在确定消息接收核读取了消息之后， 信箱模块将中断请求自动清除。 便 于后续写入新的消息时， 产生新的中断请求， 不仅保证读写消息的对应性， 而且减少 了接收核清除中断请求的操作步骤。 在本实施例中还提供了一种核间通信装置， 该装置用于实现上述实施例及优选实 施方式， 已经进行过说明的不再赘述。 如以下所使用的， 术语"模块"可以实现预定功 能的软件和 /或硬件的组合。 尽管以下实施例所描述的装置较佳地以硬件来实现， 但是 软件， 或者软件和硬件的组合的实现也是可能并被构想的。 图 9是根据本发明实施例的核间通信装置的结构框图， 如图 9所示， 该装置位于 信箱模块 90中， 接收单元 92和发送单元 94， 下面对该装置进行说明。 接收单元 92， 设置为通过总线适配模块接收来自消息发送核发送的消息； 发送单 元 94， 连接至上述接收单元 92， 设置为向消息接收核发送中断请求， 其中， 该消息接 收核根据上述中断请求读取上述消息。 为解决相关技术中的核间通信装置复杂度高， 实时性差， 以及在多核应用时的可 扩展性差等问题。 在本实施例中提供了一种新型的核间通信装置 ICN ( Inter-core Communication Network, 简称为 ICN) (在本部分为叙述方便， 将核间通信装置简写 为 ICN)， 该核间通信装置 ICN包括任意数量的以下 3类模块： 信箱模块 （Postbox) (同上述信箱模块 12)， 总线适配模块 （Bus Adapter, 简称为 BA) (同上述总线适配 模块 14)、 以及仲裁模块 （Arbiter) (同上述仲裁模块 22)。 ICN可以应用于采用层次 结构以满足核数量显著增多和核异构的应用场景，图 10是根据本发明实施例的多核芯 片的核间通信装置结构框图， 如图 10所示， 该结构包括信箱模块、 总线适配模块、 仲 裁模块， 下面对该装置分别进行说明。 ( 1 ) 信箱模块 （Postbox) 消息需要暂存在某个地方供接收核读取， 并且要具有可靠的通知接收核消息到来 的机制， 在本实施例中提供的 ICN中包括若干个 Postbox模块。 用以达到上述要求， 该信箱模块提供以下功能： 互斥的读写消息、 消息存储、 产生通知中断请求。 为实现信箱模块的上述功能， Postbox模块通过以下各个单元来完成， 即在该信箱 模块中包括若干总线接口单元 （Bus Interface Unit, 简称为 BIU)， 若干消息存储单元 (RegFiles), 以及若干中断产生单元（IntGen 下面分别对信箱模块所包括的各个单 元进行说明。
BIU单元： 设置为实现读写消息的互斥访问功能。 该 BIU单元提供一个消息接收 核的读消息通道， 和若干消息发送核的写消息通道。 BIU单元复用总线错误 （Error) 反馈寄存器实现了一个锁完成对同一资源 （即下文说的 RegFiles) 的互斥访问功能。
RegFiles单元：设置为提供若干单元消息存储寄存器空间。对于每个 Postbox来说， 有几个发送消息通道就有几组消息存储寄存器。同时根据应用需求所决定的通信流量， 也可以设置更多的消息寄存器， 不同的消息寄存器之间通过地址进行区分。
IntGen单元： 设置为当有消息到来时， 负责产生中断请求通知接收核。 若检测到 接收核将消息读走后， 中断请求自动清除。 可见， 其避免了传统核间通信方式中读取 消息还需要额外的设置中断清除寄存器的操作。 其中， 每根中断线可以与一个或一组 Regfiles单元捆绑在一起， 从而接收核可以通过中断请求编号进入特定 ISR (中断服务 程序）， 并读取对应 RegFiles中的消息。 需要说明的是， 在本实施例的核间通信装置中的 Postbox具有相关技术中所不具 备的互斥访问保护功能： 在传统的多核通信方式中， 多核占用同一个核间通信资源需要利用互斥锁或自旋 锁进行互斥操作。而 Postbox复用总线 Error反馈寄存器实现了一个锁寄存器完成了互 斥访问功能， 该操作实现如下：
BIU复用 Error信息反馈寄存器实现了一个锁寄存器。 当锁寄存器为 0， 代表锁为 释放状态； 当锁寄存器为 1， 代表锁为占用状态。 在正常情况下， 发送核写了 Postbox RegFiles后， 锁寄存器自动变为 1。 之后， Postbox产生中断通知接收核， 接收核进行 Postbox RegFiles读操作， 锁寄存器自动变为 0。 当第一种异常发生，即在接收核进行 Postbox RegFiles读操作之前又有某个发送核 想对一个 Regfiles进行写操作， 如果此时 Regfiles中的消息被修改， 则会造成之前的 消息丢失。但由于本实例中的 Postbox中的锁寄存器为 1， 表示锁处于占用状态， 故发 送消息写操作未成功， 即 Postbox RegFiles信息未被修改； 同时， 锁寄存器信息 1将作 为 Error 响应信息返回给发送核通知其进行了异常操作。 核进入异常处理， 即可以等 待若干指令周期后继续进行访问。直到当接收核进行了正常的读 Postbox RegFiles操作 之后， 锁寄存器变为 0， 即锁被释放， 其他发送核可以进行正常写操作。 当第二种异常发生， 即在接收核读取消息的同时， 发生了某个核的写消息操作， 则 BIU强制以先读后写的顺序进行， 即先保证前一个消息被读走， 然后才能写入新的 消息， 这样保证了核间通信的可靠性。
(2) 总线适配模块 （BA， Bus Adapter): 由于进行通信的核之间总线协议可能不同， 同时核需要访问的 Postbox 比较多， 故本实施例中的 ICN包括若干 BA模块， 其包括 1个核读写接口和若干个 Postbox读 写接口， 该 BA模块完成以下 2个功能：
A、 完成不同核接口总线协议向 ICN内部数据读写协议的适配；
B、 根据总线访问的 Postbox地址， 进行地址过滤， 即仅使唯一目的 Postbox的内 部接口上出现有效数据和有效控制信号。 可见， 通过 BA模块可以显著隔离外部复杂的总线协议， 内部仅采用简单快速的 数据读写协议， 显著减少了核间通信装置的硬件延迟。
(3 ) 仲裁模块 （Arbiter): 当一个 Cluster 内部有多个核同时对一个 Postbox 发起消息读写访问时将发生冲 突。 因而在本实施例中的 ICN包括若干 Arbiter模块， 其包括若干个消息输入接口和 1 个消息输出接口。 用以提供如下功能： 对若干数据通道的读写访问请求按照特定原则 进行仲裁， 即将同时到达的消息读写访问请求串行化。 其中， Arbiter对同时到达仲裁模块的消息读写访问进行轮询仲裁， 即使多个同时 到达的消息读写访问按照顺序串行输出； 或者， 对同时到达该仲裁模块的消息读写访 问进行优先级仲裁， 即使多个同时到达的消息读写访问请求按照优先级由高到低的顺 序串行输出。 在本实施例中还提供了一种核间通信方法，图 11是根据本发明实施例的核间通信 方法的流程图， 如图 11所示， 该方法包括如下步骤： 步骤 S1102,发消息核通过 BA进行写消息操作，并根据 BA返回的信息确定消息 是否发送成功。各个核的写消息操作是异步且独立的，互不影响。如果 BA返回的 Error Response信息为无效， 则消息发送成功； 反之， 表示 Postbox被占用， 写消息未成功。 此时， 发送核可以延迟若干周期后再进行写消息操作， 直到消息发送成功为止。 步骤 S1104,发送核的发送消息经过 Arbiter或不经过 Arbiter发送至具有特定地址 的 Postbox中， Postbox产生中断请求 （int) 给接收消息核。 步骤 S1106， 接收核接收到中断， 并进行消息读取操作。 步骤 S1108, 接收核的消息读操作请求信号进入 ICN直至发送到产生中断请求的 信箱模块（Postbox) 中， 并读取到发送给它的消息， 且 Postbox的中断请求自动拉低。 本发明所提供的实施例及优选实施方式具有天生的互斥功能。 即在进行核间通信 前， 无需进行额外的申请锁和释放锁的操作， 互斥完全通过对 ICN本身的读写访问和 ERROR返回机制完成， 显著减少了核间通信的复杂性， 减少了通信时延； 另外， 无需 要任何初始化步骤， ICN上电复位后即可正常工作； 当消息读写请求进入 ICN后， 完 全由 ICN自行管理， 不仅实现了自动化管理， 而且在一定程度上大大节省了资源。 采用分布式结构， 可以使某些通信流量局限在特定区域的带宽之内而不对其他通 信区域造成任何影响， 并且显著减少了单一仲裁模块的仲裁开销， 从而显著减少了多 核整体的统计通信延迟。 当核数量显著增加时， 仅需增加相应数量的 3类模块和对应的互联线， 同时互联 方式也可以根据应用需求灵活连接， 不影响 ICN的现有结构特征和软件操作步骤， 因 此具有极好的可扩展性和可裁减性。 下面结合附图 10对本发明实施例作进一步的具体说明。需要说明的是， 多核不限 于实施例子中所举的 CPU (中央处理器） 和 DSP (数字信号处理器）。 整个 ICN采用 3级结构以满足多核（一共 10个核）和核异构 （6DSP+4ARM) 的 应用需求。整个 ICN包含 15个 Postbox, 10个 BA以及 4个 Arbiter, 其整体结构如图 10所示。 3个 DSP构成一个 Cluster。 2个 CPU构成 1个 Cluster, 由于其数据流量比 较小， 数据通路未经过仲裁器。 可见， ICN可以根据核的数量和通信流量选择 3类组 件的数量， 以及互联方式 （如实施例子中不经过仲裁器， 直接连到 Postbox上）， 不影 响 ICN的整个结构特征和通信流程， 可扩展现性和可裁减性极好。 按照负责功能区域， Postbox分为 Local Postbox (本地信箱）禾 B Cross Postbox (交 叉信箱）。 具体来说， 在本实施例中存在以下几个： 负责 DSP cluster (簇） 内部和 DSP cluster (簇） 内部进行核间通信的 10个 local Postbox, 负责 DSP cluster与 CPU cluster 之间的核间通信的 1个 local Postbox, 负责 DSP cluster之间进行核间通信 1个 Cross Postbox以及或负责 CPU cluster之间进行核间通信 1个 Cross Postbox。 可见， 这种分 布式结构可以使某些通信流量局限在特定区域的带宽之内而不对其他通信区域造成任 何影响， 并且显著减少了单一仲裁模块的仲裁开销， 显著增大了多核整体带宽效率， 减少了多核整体的通信延迟。 同时， 当核数量显著增加时， 可能导致一个核接收的核 间通信中断请求过多， 此时可将多个 Postbox 的中断请求通过或逻辑进行合并从而减 少到达核的核间中断请求数量， 从而大大增加了 ICN的可扩展现性。 其中， ICN包括的 3类模块的具体实施如下-
( 1 ) 信箱模块 （Postbox) 消息需要暂存在某个地方供接收核读取， 并且要具有可靠的通知接收核消息到来 的机制， 故本发明所述 ICN包括若干 Postbox模块。 其提供如下功能： 消息存储 互斥的读写消息 产生通知中断请求 图 12是根据本发明实施例的核间通信装置中信箱模块的结构框图，如图 12所示， 该信箱模块 （Postbox)包括若干 BIU单元， 若干 RegFiles单元， 和若干 IntGen单元。 其中， 各功能单元如下：
BIU单元： 实现读写消息的互斥访问功能。 其中 BUS0为该 Postbox所属接收核的读消息通 道， BUSl~n为发送核的写消息通道。 BIU单元复用总线 Error反馈寄存器实现了一个 锁完成对同一个 RegFiles单元的互斥访问功能。
RegFiles单元： 提供若干单元消息存储寄存器空间。 对于每个 Postbox来说， 有几个发送消息通 道就有几组消息存储寄存器。 同时根据应用需求所决定的通信流量， 也可以设置更多 的消息寄存器， 不同的消息寄存器之间通过地址进行区分。
IntGen单元： 当有消息到来时， 负责产生中断请求通知接收核。若检测到接收核将消息读走后， 中断请求自动清除。 可见， 其避免了传统核间通信方式中读取消息还需要额外的设置 中断清除寄存器的操作。其中每根中断线可以与一个或一组 Regfiles单元捆绑在一起， 从而接收核可以通过中断请求编号进入特定 ISR (中断服务程序），并读取对应 RegFiles 中的消息。 其中， 需要特别强调的， 本核间通信装置中的 Postbox具有其他方案所不具备的 互斥访问保护功能。 在传统的多核通信方式中， 多核占用同一个核间通信资源需要利用互斥锁或自旋 锁进行互斥操作。而 Postbox复用总线 Error反馈寄存器实现了一个锁寄存器完成了互 斥访问功能， 其具体实现如下：
BIU复用 Error信息反馈寄存器实现了一个锁寄存器。 当锁寄存器为 0， 代表锁为 释放状态； 当锁寄存器为 1， 代表锁为占用状态。 在正常情况下， 发送核写了 Postbox RegFiles后， 锁寄存器自动变为 1。 之后， Postbox产生中断通知接收核， 接收核进行 Postbox RegFiles读操作， 锁寄存器自动变为 0; 当第一种异常发生，即在接收核进行 Postbox RegFiles读操作之前又有某个发送核 想对一个 Regfiles进行写操作， 如果此时 Regfiles中的消息被修改， 则会造成之前的 消息丢失。但由于本实施例 Postbox中的锁寄存器为 1， 表示锁处于占用状态， 故发送 消息写操作未成功， 即 Postbox RegFiles信息未被修改； 同时， 锁寄存器信息 1将作为 Error响应信息返回给发送核通知其进行了异常操作。核进入异常处理， 即等待若干指 令周期后继续进行访问。直到当接收核进行了正常的读 Postbox RegFiles操作之后，锁 寄存器变为 0， 即锁被释放， 其他发送核可以进行正常写操作。 当第二种异常发生， 即在接收核读取消息的同时， 发生了某个核的写消息操作， 则 BIU强制以先读后写的顺序进行， 即先保证前一个消息被读走， 然后才能写入新的 消息， 这样保证了核间通信的可靠性。 在实现时， 锁寄存器即从设备 Error信息产生寄存器， 即无需增加额外的如互斥 锁， 信号量那样的互斥功能单元； 申请锁操作成功即是消息发送操作成功， 释放锁成 功即是消息读取成功， 消息申请锁失败即是总线反馈 Error 响应， 即互斥处理机制与 总线通用的读写机制一致， 即无需增加额外的互斥操作周期， 显著减少了编程复杂性 和通信延迟。 因此， 上述实施例及优选实施方式所示的装置和方法实现了对核间通信 资源的互斥访问保护。 (2) 总线适配模块 （BA， Bus Adapter): 由于进行通信的核之间总线协议可能不同， 同时核需要访问的 Postbox 比较多， 故本发明所述 ICN包括若干 BA模块， 其包括 1个核读写接口和若干个 Postbox读写 接口， 其完成 2个功能：
A.完成不同核接口总线协议向 ICN内部数据读写协议的适配； B.根据总线访问的 Postbox地址， 进行地址过滤， 即仅使唯一目的 Postbox的内部 接口上出现有效数据和有效控制信号。 可见， 通过 BA模块可以显著隔离外部复杂的总线协议， 内部仅采用简单快速的 数据读写协议， 显著减少了核间通信装置的硬件延迟。 在本实施例子中， 内部外部均采用比较简单的增强外置总线（Advanced Peripheral Bus, 简称为 APB)协议， 图 13是根据本发明实施例的核间通信装置中总线适配模块 的结构框图， 如图 13所示， BA根据 APB的访问地址和 Postbox的寄存器地址是否匹 配来使能输出不同的 APB选择信号， 从而选通不同的消息通路。 该 APB接口可读可 写， 核通过 APB接口对 Postbox进行消息读写操作。
(3 ) 仲裁模块 （Arbiter) 当一个 Cluster 内部有多个核同时对一个 Postbox 发起消息读写访问时将发生冲 突。 故本发明所述 ICN包括若干 Arbiter模块， 图 14是根据本发明实施例的核间通信 装置中仲裁模块的结构框图， 如图 14所示， 该仲裁模块包括若干个消息输入接口和 1 个消息输出接口。 其提供如下功能： 对若干数据通道的读写访问请求按照特定原则进 行仲裁， 即将同时到达的消息读写访问请求串行化。 其中， Arbiter对同时到达所述仲裁模块的消息读写访问进行轮询仲裁， 即使多个 同时到达的消息读写访问按照顺序串行输出； 即对存在消息读写请求的不同数据通路 之间进行轮询， 即每次只能选通一个存在请求的数据通路， 读写访问完成后， 再选通 下一个存在消息读写请求的数据通路； 依次类推， 直至处理完所有通路的消息读写请 求。 同时， 根据模块设置的工作模式， 可以对同时到达所述仲裁模块的消息读写访问 进行优先级仲裁， 即使多个同时到达的消息读写访问请求按照优先级由高到低的顺序 进行。 应用本核间通信装置的核间通信方法步骤如下： 待发送消息核通过 BA进行写消息操作， 并根据 BA返回的信息确定消息是否发 送成功。 各个核的写消息操作是异步且独立的， 互不影响。 如果 BA 返回的 Error Response通信息为无效， 则消息发送成功； 反之， 表示 Postbox被占用， 写消息未成 功。 此时， 发送核可以延迟若干周期后再进行写消息操作， 直到消息发送成功为止。 若干发送核的发送消息经过 Arbiter 或不经过 Arbiter 发送至具有特定地址的 Postbox中， Postbox产生中断请求给接收消息核。 当互相通信的核数量较少时， 消息 读写可以不经过 Arbiter。 接收核接收到中断， 并进行消息读取操作。 接收核的消息读操作请求信号进入 ICN直至发送到产生中断请求的 Postbox中， 并读取到发送给它的消息且 Postbox 的中断请求自动拉低 （即将读取完毕消息所对应 的中断请求自动清除）。 举下面 3个例子说明本发明所述核间方法：
A: 一般应用下 CLUSTER内部消息通信过程：
1.发消息核 DSP2发送消息到属于目的核 DSP0的 PostboxO; 2. PostboxO产生中断请求给 DSPO;
3. DSPO进入 ISR， 读取 Postbox中的消息。
B.—般应用下同时有跨 CLUSTER的消息通信和 CLUSTER内部的消息通信过程：
1. DSP clusterO内部发消息核 DSP2发送消息到属于目的核 DSP0的 PostboxO; DSP cluster 1的发消息核 DSP3， 4同时有消息需要发送给 DSP clusterO DSPO。 故首先经过 了 DSP cluster 1内部的 Arbiter2进行了仲裁， 假设发送核 DSP3获得了仲裁权， 先把消 息写到了 DSP CLUSTERO的 Postbox中， 而后发送核 DSP4获得了仲裁权， 把消息写 到了 DSP CLUSTERO的 Postbox中；
2. DSP CLUSTERO内部 PostboxO和 DSP CLUSTERO的 Postbox同时有中断请求产 生；
3. DSP0核进入 ISR，根据软件设定的优先级，假设先读取了内部 PostboxO的消息， 再读取 DSP CLUSTERO的 Postbox中的消息。
C. 互斥保护机制生效时的跨 CLUSTER的核间通信过程： l.CPU CORE0经过 BA6发送了一条消息到 CPU&DSP cross Postbox; 2.CPU&DSP cross Postbox产生中断请求给 DSP5， DSP5由于同时有优先级更高的 事务未来得及处理该中断， 即未进行消息读取；
3. CPU CORE0经过 BA6又发送了一条消息到 CPU&DSP cross Postbox, 但返回 ERROR信息， 表示通信资源锁未被释放， 该消息未发送成功； CPU CORE0进入等待 周期后又再次进行消息发送操作。 4.DSP5处理完高优先级的事务， 成功读取第 1条消息。
5. CPU CORE0成功发送第 2条消息， 即返回的 ERROR信息为无效。 然后 CPU coreO成功读取了第 2条消息。 可见在进行核间通信的过程中无需额外的互斥保护机 制， 即实现了可靠的核间通信。 需要强调的是， 在实际的核间通信过程中， 以上 3种情况或更复杂的通信场景都 是可能存在的。 另外， 本发明实施例的核间通信装置所包括的上述 3个模块以及连接交互关系是 解决相关技术所存在的技术问题的关键； 本发明实施例的核间通信方法也是区别与现 有技术也是显而易见的。 上述实施例及优选实施方式具有天生的互斥功能。 即在进行 核间通信前， 无需进行额外的申请锁和释放锁的操作， 互斥完全通过对 ICN本身的读 写访问和 ERROR返回机制完成； 另外， 实施时无需要任何初始化步骤， ICN上电复 位后即可正常工作； 当消息读写请求进入 ICN后， 完全由 ICN自行管理， 从而显著减 少了核间通信的复杂性， 减少通信时延； 该核间通信装置采用分布式结构， 可以使某 些通信流量局限在特定区域的带宽之内而不对其他通信区域造成任何影响， 并且显著 减少了单一仲裁模块的仲裁开销， 从而显著减少了多核整体的统计通信延迟； 当核数 量显著增加时， 通过上述实施例及优选实施方式， 仅需增加相应数量的 3类模块和对 应的互联线， 同时互联方式也可以根据应用需求灵活连接， 不影响 ICN的现有结构特 征和软件操作步骤， 因此具有极好的可扩展性和可裁减性。 显然， 本领域的技术人员应该明白， 上述的本发明的各模块或各步骤可以用通用 的计算装置来实现， 它们可以集中在单个的计算装置上， 或者分布在多个计算装置所 组成的网络上， 可选地， 它们可以用计算装置可执行的程序代码来实现， 从而， 可以 将它们存储在存储装置中由计算装置来执行， 并且在某些情况下， 可以以不同于此处 的顺序执行所示出或描述的步骤， 或者将它们分别制作成各个集成电路模块， 或者将 它们中的多个模块或步骤制作成单个集成电路模块来实现。 这样， 本发明不限制于任 何特定的硬件和软件结合。 以上所述仅为本发明的优选实施例而已， 并不用于限制本发明， 对于本领域的技 术人员来说， 本发明可以有各种更改和变化。 凡在本发明的精神和原则之内， 所作的 任何修改、 等同替换、 改进等， 均应包含在本发明的保护范围之内。

Claims

权 利 要 求 书
1. 一种核间通信装置， 包括：
信箱模块， 设置为存储消息发送核发送给消息接收核的消息， 并通知所述 消息接收核读取所述消息；
总线适配模块， 连接于所述信箱模块与进行通信的所述消息接收核和消息 发送核之间， 设置为提供所述信箱模块与所述消息接收核和所述消息发送核的 读写接口。
2. 根据权利要求 1所述的装置， 其中， 还包括：
仲裁模块： 设置为在多个核同时向所述信箱模块发起用于请求读写消息的 读写访问请求时， 按照预定的规则对所述多个读写访问请求进行仲裁， 将所述 多个读写访问请求依次串行输出。
3. 根据权利要求 1所述的装置， 其中， 所述信箱模块包括- 总线接口单元，设置为通过复用总线错误反馈寄存器实现读写消息的互斥。
4. 根据权利要求 3所述的装置， 其中， 所述总线接口单元包括：
第一互斥单元， 设置为通过复用所述总线错误反馈寄存器实现互斥锁的功 能， 实现多个消息发送核向所述信箱模块写消息的互斥； 和 /或，
第二互斥单元， 设置为通过复用所述总线错误反馈寄存器实现互斥锁的功 能， 实现消息发送核向所述信箱模块写消息与消息接收核从所述信箱模块读消 息的互斥。
5. 根据权利要求 3或 4所述的装置， 其中， 所述总线接口单元还包括： 触发子单元，设置为在所述消息发送核向所述信箱模块写入了消息，或者， 所述消息接收核从所述信箱模块读取了消息之后， 触发所述总线错误反馈寄存 器的状态变化。
6. 根据权利要求 1所述的装置， 其中， 所述信箱模块包括：
存储单元， 设置为根据消息访问地址对所述消息进行存储。
7. 根据权利要求 1所述的装置， 其中， 所述信箱模块包括: 通知单元， 设置为通过中断请求通知所述消息接收核接收消息。
8. 一种核间通信方法， 包括：
信箱模块通过总线适配模块接收来自消息发送核发送的消息； 所述信箱模块向消息接收核发送中断请求， 其中， 所述消息接收核根据所 述中断请求读取所述消息。
9. 根据权利要求 8所述的方法， 其中， 还包括： 在多个核同时向所述信箱模块发 起用于请求读写消息的读写访问请求时， 按照预定的规则对所述多个读写访问 请求进行仲裁， 将所述多个读写访问请求依次串行输出。
10. 根据权利要求 8所述的方法， 其中， 在多个核同时向所述信箱模块发起用于请 求读写消息的读写访问请求时， 通过复用总线错误反馈寄存器实现读写消息的 互斥。
11. 根据权利要求 10所述的方法，其中，通过复用总线错误反馈寄存器实现读写消 息的互斥包括：
通过复用所述总线错误反馈寄存器实现互斥锁的功能， 实现多个消息发送 核向所述信箱模块写消息的互斥； 和 /或， 通过复用所述总线错误反馈寄存器实 现互斥锁的功能， 实现消息发送核向所述信箱模块写消息与消息接收核从所述 信箱模块读消息的互斥。
12. 根据权利要求 10或 11所述的方法， 其中， 在所述消息发送核向所述信箱模块 写入了消息， 或者， 所述消息接收核从所述信箱模块读取了消息之后， 触发所 述总线错误反馈寄存器的状态变化。
13. 根据权利要求 10或 11所述的方法， 其中，
在所述消息发送核向所述信箱模块写入了消息之后， 所述信箱模块向所述 消息发送核发送第一响应消息， 其中， 所述消息发送核根据所述第一响应消息 确定所述消息发送核向所述信箱模块写入消息成功； 和 /或，
在所述消息接收核从所述信箱模块读取了消息之后， 所述信箱模块向所述 消息接收核发送第二响应消息， 其中， 所述消息接收核根据所述第二响应消息 确定所述消息接收核读取消息成功。
14. 根据权利要求 8所述的方法， 其中， 在所述消息接收核读取了所述消息之后， 还包括， 所述信箱模块将所述中断请求清除。 一种核间通信装置， 包括：
接收单元， 位于信箱模块中， 设置为通过总线适配模块接收来自消息发送 核发送的消息；
发送单元， 位于所述信箱模块中， 设置为向消息接收核发送中断请求， 其 中， 所述消息接收核根据所述中断请求读取所述消息。
PCT/CN2013/084831 2012-10-12 2013-10-08 核间通信装置及方法 WO2014056420A1 (zh)

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