WO2014032369A1 - 一种基于纹波控制的单电感双输出开关电源 - Google Patents

一种基于纹波控制的单电感双输出开关电源 Download PDF

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Publication number
WO2014032369A1
WO2014032369A1 PCT/CN2012/085463 CN2012085463W WO2014032369A1 WO 2014032369 A1 WO2014032369 A1 WO 2014032369A1 CN 2012085463 W CN2012085463 W CN 2012085463W WO 2014032369 A1 WO2014032369 A1 WO 2014032369A1
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Prior art keywords
module
resistor
output
voltage
pmos transistor
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PCT/CN2012/085463
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English (en)
French (fr)
Inventor
孙伟锋
杨淼
徐申
钱钦松
陆生礼
时龙兴
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东南大学
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Publication of WO2014032369A1 publication Critical patent/WO2014032369A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0083—Converters characterised by their input or output configuration
    • H02M1/009—Converters characterised by their input or output configuration having two or more independently controlled outputs

Definitions

  • the invention relates to the field of switching power supplies, in particular to a single inductor multi-output switching power supply based on ripple control. Background technique
  • SIMO step-down DC-DC converters have become a hot topic in academia and industry because they reduce the use of off-chip components (especially off-chip inductors) and thus reduce the size of power modules. And the direction of development. Although it can reduce the size of the power module, there are also problems of large output ripple, low efficiency, and cross modulation. Small ripple, low cross-coupling, high efficiency, and fast transient response are the most important indicators for practical SIMO applications.
  • the prior art uses a common mode voltage to control the main loop current loop.
  • the dual output SIMO structure of the differential mode voltage control secondary loop voltage loop can reduce the cross coupling to a certain extent, but the secondary loop control method is complicated and the transient response is slow.
  • the method of reducing the output ripple by using a flying capacitor string between the two outputs will deteriorate the intermodulation effect to some extent.
  • the present invention proposes a single-inductance dual-output switching power supply (DC-DC converter) based on ripple control based on the prior art, which can simplify the control topology and improve the transient response. , reduce ripple and intermodulation coupling.
  • DC-DC converter single-inductance dual-output switching power supply
  • a single-inductance dual-output switching power supply based on ripple control comprising: a power stage module, a filtering and voltage sampling module, a secondary voltage sampling module, and a secondary ripple Control module, main voltage sampling module, main control module and driving module, power level module output connection filtering and voltage sampling module, filtering and voltage sampling module output are respectively connected to secondary voltage sampling module and main voltage sampling module, secondary
  • the output of the voltage sampling module is connected to the secondary ripple control module, and the output of the main-stage voltage sampling module is connected to the main-level control module, and the outputs of the secondary ripple control module and the main-level control module are connected to the driving module, and the output of the driving module is connected to the power level module.
  • the secondary ripple control module also outputs a ramp compensation current source I sl . Pe signal to the secondary voltage sampling module; where:
  • the power stage module includes a PMOS transistor MP1 as a main power switch transistor, an NMOS transistor MN1 as a synchronous rectifier switch transistor, a PMOS transistor MP2 and a NMOS transistor MN2 as a secondary power switch transistor, and an inductor L.
  • a source connection power supply of the PMOS transistor MP1 The voltage Vin, the drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN1 and the end of the inductor L.
  • the source of the NMOS transistor MN1 is grounded, and the other end of the inductor L is connected to the source of the PMOS transistor MP2 and the NMOS transistor MN2, respectively.
  • the filter and voltage sampling module includes a capacitor, C 2 and a resistor, R 2 , R 3 , R 4 , R 5 and R 6 , one end of the capacitor and a drain of the PMOS transistor MP2 in the power stage module, a resistor and one end of the resistor R 3 Connected together as one output voltage V, the other end of the capacitor d is connected to the other end of the resistor and one end of the resistor R 4 From and to ground, the other end of the resistor R4 and the other end of the resistor R 3 is connected as one branch sampling voltage V 1; electrode, a resistor R one end of the source capacitor C one end of the power stage module 2, the NMOS transistor MN2 is 2 and a resistor R 5 is connected together as another output voltage V 02, one end of the other end of the capacitor C and the resistor R 2 and the other end of the resistor R 2 6 and the other end connected to ground, the resistor R 6 and the other end of the resistor R 5 is connected to As another sampling voltage V 2 ;
  • Secondary voltage sampling module comprises a PMOS transistor PMOS transistor MP7 and MP8, resistors R u, Ri 2, Ri 3 , R i4 and R 15, one pair of constant current source 12 and the pair of slope compensation current source I sl.
  • resistors R u, Ri 2, Ri 3 , R i4 and R 15 are respectively connected to the sampling voltage and the sampling voltage V 2 outputted by the filtering and voltage sampling module, and the other end of the resistor R 13 is connected to the gate of the PMOS transistor MP7 and one end of the resistor R 14 .
  • the other end of the resistor R 15 is connected to the gate of the PMOS transistor MP8, the drain of the PMOS transistor MP7 is connected to the drain of the PMOS transistor MP8 and the other end of the resistor R 14 and grounded, and a pair of constant current sources 1 2 And a pair of slope compensation current sources I sl .
  • One end of the pe is connected to the power supply VDD, and one of the slopes compensates for the current source I sl .
  • pe end of the other end is connected to a resistor R 12 and the other end 12 of the output voltage V-, the other end of the source resistor R 12 and a PMOS transistor MP8 and wherein a constant current source are connected together, the other slope compensation Current source I sl .
  • the source and the other end of the pe PMOS transistor MP7 and the end of the resistor Ru is connected, the other end of the other end of the resistor R u and another constant current source 12 is connected as an output voltage V +;
  • the secondary ripple control module includes a slope compensation circuit and a comparator circuit.
  • the two input ends of the comparator circuit are respectively connected to the output voltages V+ and V_ of the secondary voltage sampling module, and the slope compensation circuit comprises a PMOS transistor MP3, a PMOS transistor MP4, and a PMOS.
  • tube MP5, MP6 and NMOS transistor PMOS transistor MN3, MN4 is NMOS transistor, NMOS transistor MN5, capacitors C 3, C 4, a resistor R 1Q, a constant current source and an inverter, with one end of a constant current source PMOS transistor MP6,
  • the source, the source of the PMOS transistor MP5, and one end of the capacitor C 4 are connected together and connected to the power supply VDD, and the other end of the constant current source is connected to the drain of the NMOS transistor MN3, the gate, and the gate of the NMOS transistor MN4.
  • source of the NMOS transistor MN3 is connected to one end of the capacitor C and the drain of the NMOS transistor MN5, the other end of the capacitor C 3 and the source of the NMOS transistor MN5 electrode 3 are grounded, the gate of NMOS transistor connected to an output terminal of the inverter MN5
  • the input end of the inverter is connected to the duty signal d 2 outputted by the comparator circuit
  • the gate of the PMOS transistor MP6 is connected to the duty signal d 2
  • the source of MP3, the gate and drain of M0S transistor MP3 are interconnected and connected with MOS
  • the gate of the transistor MP4 and the drain of the NMOS transistor MN4 are connected together, the source of the NMOS transistor MN4 is grounded through the resistor Rio, the gate of the PMOS transistor MP5 is grounded, and the drain of the PMOS transistor MP5 is connected to the source of the PMOS transistor MP4, PMOS The drain of
  • the main-stage voltage sampling module includes resistors R 7 , R 8 and R 9 , and one end of the resistor R 7 and the resistor R 8 is respectively connected to the sampling voltage and the sampling voltage V 2 , the resistor R 7 and the resistor R 8 outputted by the filtering and voltage sampling module. The other end is grounded through a resistor R 9 ;
  • the main stage control module includes a slope compensation circuit (same as the slope compensation circuit in the secondary ripple control module), an oscillator, a current detection circuit, an adder, an error amplifier, and a pulse width modulator.
  • the oscillator outputs a clock control signal to the slope compensation.
  • Circuit, slope compensation circuit output connection adder, current detection circuit input connection power stage mode The drain of the PMOS transistor MP1 and the NMOS transistor MN1 in the block, the output of the current detecting circuit is also connected to the adder, the output of the adder is connected to one input of the pulse width modulator, and the other input of the pulse width modulator is connected to the error.
  • the output of the amplifier, the negative input terminal of the error amplifier is connected to the resistor R 7 and the connection terminal of the sampling voltage V M output in the main-stage voltage sampling module, and the positive input terminal of the error amplifier is connected to the reference voltage Vref, and the pulse width modulator output main Stage duty cycle signal d 1 ;
  • the driving module is provided with a dead zone and a driving circuit (the existing circuit can be used), and the input end thereof is respectively connected to the main-stage duty-cycle signal of the pulse width modulator output in the main-level control module and the comparator circuit output in the secondary ripple control module.
  • the duty cycle signal d 2 at the output of the dead zone and the driving circuit, the driving signals PD and ND generated by the duty cycle signal ⁇ are respectively connected to the gate of the PMOS transistor MP1 and the gate of the NMOS transistor MN1 in the power stage module electrode, the signal generated by the duty cycle (1 second driving signals DP and DN are respectively connected to the gate of the NMOS transistor MN2 and the gate of the power stage module PMOS transistor MP2.
  • the main loop adopts the common mode voltage peak current mode
  • the secondary loop adopts the dual SIMO step-down DC-DC converter with differential mode voltage ripple control mode
  • the secondary loop adopts the ripple control mode.
  • the control circuit is simplified, and the main circuit adopts the peak current mode of the error amplifier without compensation, which further simplifies the control circuit and improves the transient response.
  • the secondary control loop is added. Additional slope compensation, additional slope compensation also reduces ripple.
  • Main-stage switches MP1 and MN1 are controlled by common-mode signals of two output voltages, and the secondary switches MP2 and MN2 are controlled by differential mode signals of two output voltages.
  • the main stage switch uses common mode voltage control and the secondary switch uses differential mode voltage control to reduce cross coupling.
  • the core of the ripple control structure is a high-precision high-speed comparator and a slope compensation circuit.
  • the slope compensation is superimposed on the input terminal secondary voltage sampling module of the high-precision high-speed comparator to realize ripple control.
  • the control topology of the primary loop is the peak current type control topology
  • the control topology of the secondary loop is the ripple control topology.
  • the secondary switch is controlled by the ripple of the differential mode voltage and eliminates potential subharmonic oscillations by ramp compensation, thereby reducing the ripple of the single inductor dual output switching power supply.
  • the power switch tube selects different types of power switch tubes according to the input and output voltage difference, and adopts PSM mode to improve efficiency through the segment drive and light load phases.
  • the secondary ripple control module simplifies the control topology and makes the system faster.
  • the slope compensation circuit of the main circuit can be omitted to a certain extent.
  • FIG. 1 is a block diagram of the present invention
  • Figure 2 is a general view of the circuit of the present invention
  • 3 is a circuit diagram of a secondary slope compensation circuit of the present invention
  • 4 is a circuit diagram of a secondary voltage sampling circuit of the present invention
  • FIG. 5 is a working waveform diagram of the present invention.
  • Figure 6 is a schematic diagram of the secondary slope compensation of the present invention.
  • the object of the present invention is to provide a fast response, small ripple, low cross-coupling, high efficiency single inductance dual output step-down DC-DC converter.
  • power stage module 1 filter and voltage sampling module 2, secondary voltage sampling module 3, secondary ripple control module 4, main stage voltage sampling module 5, main stage control module 6 and drive module 7.
  • Power stage module 1 output V 01 V02 to filter and voltage sampling module 2, filter and voltage sampling module 2 output, V 2 to secondary voltage sampling module 3 and main voltage sampling module 5, secondary voltage sampling module 3 output V + , V_ to secondary Ripple control module 4, main stage voltage sampling module 5 outputs V M to main stage control module 6, secondary ripple control module 4 and main stage control module 6 respectively output duty cycle signals d 2 , 4 to drive module 7,
  • the output of the drive module 7 is connected to the power stage module 1, and the secondary ripple control module 4 also outputs a ramp compensation current source I sl .
  • the pe signal is sent to the secondary voltage sampling module 3.
  • Vin is the switching power supply input voltage
  • MP1 is the input loop main stage power switch tube
  • MN1 is the main loop synchronous rectification power switch tube
  • MP2, MN2 is the secondary power tube
  • the inductor L constitutes the power stage module 1.
  • the filter capacitor for branch one is the load of branch one
  • 3 ⁇ 4 is the filter capacitor of branch two
  • R 2 is the load of branch two
  • Ri R 2 , R 3 , C 2 , R 4 , R 5 and R 6 constitutes a filtering and voltage sampling module 2.
  • R 7 , R 8 and R 9 form the main stage voltage sampling module 5, error amplifier and pulse width modulator, plus current detection, adder, oscillator and slope compensation circuit I, which constitute the main stage control module 6.
  • the slope compensation circuit II and the high speed high precision low offset comparator form a secondary ripple control module 4.
  • the slope compensation circuit II and the slope compensation circuit 1 can adopt the same circuit configuration.
  • the main stage power switch tube MP1 and the synchronous rectification power switch tube MN1 function as main loop switches, control energy input, MP1 uses a power PMOS tube, and MN1 uses a power NMOS tube.
  • the two secondary power switches MP2 and MN2 after the inductor L act as secondary switches to determine the energy distribution.
  • the two output voltages Voi and Vo 2 are obtained by sampling resistors R 3 , R4, R 5 and R 6 to obtain sampling voltages N ⁇ and V 2 , and the sampling voltages N ⁇ and V 2 are respectively transmitted to the main-stage voltage sampling module and the secondary voltage sampling.
  • the primary voltage sampling module to sample voltage ⁇ 1 and V 2 sampling process to obtain primary sampling voltage V M, V M and the reference voltage Vref is compared to generate an output voltage, the current detection circuit and a slope compensation circuit I by error amplifier
  • the current is generated by the sampling resistor to generate another voltage, which is compared by a pulse width modulator to produce a duty cycle signal 4, which generates drive signals PD and ND through the drive module.
  • the power transistor MP2 that selects the output voltage uses a power PMOS transistor
  • the power transistor MN2 that selects the output voltage uses a power NMOS transistor.
  • the power tube type that selects the output voltage can be selected based on the relationship between the two output voltage values Voi and V 02 and the power supply voltage.
  • the selection basis is: when the output voltage is less than half of the power supply voltage, the power tube selects the N-type power MOS tube, and when the output voltage is greater than half of the power supply voltage, the power tube selects the P-power MOS tube.
  • the power MOS transistor MP2 of the output voltage selects the P-type power MOS transistor.
  • the rated output voltage of Vo 2 is 1.2V, which is greater than half of the power supply voltage.
  • the power MOS transistor MN2 that selects the output voltage selects the N-type power MOS transistor.
  • the secondary control loop uses a ripple control mode with slope compensation added.
  • the secondary ramp current generated by the slope compensation circuit II is input to the secondary voltage sampling module, and the two sampling output voltages and the V 2 are generated by the secondary voltage sampling module to generate a differential mode voltage V+ and a V- input to a high-speed high-precision low offset comparison.
  • the two inputs of the device generate a secondary duty cycle signal d 2 , and the duty cycle signal d 2 generates drive signals DP and DN through a drive module (PWM).
  • the output filter capacitor and C 2 use a capacitor with a low parasitic inductance, such as a small-capacitance capacitor, or a capacitor with a low parasitic inductance made by a special process.
  • resistors R 7, R 8 and R 9 are pressed by sampling points to the voltage V M, the voltage V M is the common-mode voltage sampling voltage, V M is input to the primary control module error 6 The negative input of the amplifier.
  • the output clock of the oscillator control ramp compensation circuit II generates a ramp compensation current, and the current of the current detection power stage is superimposed and input to the pulse width modulator.
  • the sampling voltage V M generated by the main voltage sampling module is input to the negative input terminal of the error amplifier
  • the reference voltage Vref is input to the positive input terminal of the error amplifier
  • the output of the error amplifier is input to the pulse modulator
  • the pulse modulator generates the main stage.
  • the space ratio signal 4 the main stage duty ratio signal ⁇ is input to the drive module 7.
  • the two outputs V+ and V- of the secondary voltage sampling module are input to the two input terminals of the high speed high precision comparator, and the secondary slope compensation current generated by the slope compensation circuit II is input to the secondary In the stage voltage sampling module, the differential mode voltages V+ and V- are compared in a comparator to generate a duty cycle signal d 2 of the secondary circuit, and the secondary duty cycle signal d 2 is input to the drive module 7.
  • 3 is a circuit diagram of the slope compensation circuit II in the secondary ripple control module 4, II is a current source, the current source is generated by a current reference, MN3, MN4, and MN5 are NMOS transistors, and MP3, MP4, MP5, and MP6 are PMOS
  • the tube, MN5 and MP6 are MOS tube switches, the secondary duty cycle signal d 2 controls the switch tube MP6, and the secondary duty cycle signal d 2 controls the switch tube MN5 through the inverter.
  • the switch tubes MN5 and MP6 are closed, the current reference has no reference current generated, and the slope compensation circuit II does not work.
  • the secondary duty signal control switches MN5 and MP6 are disconnected, and the current reference is The current is generated, II is a constant current source, and the voltage on the capacitor C 3 rises linearly in proportion to the time when the switch tube MN5 is turned off, and the voltage on the resistor R 1Q also rises linearly in proportion to time, and the switch tube MP6 is also Disconnected, a time-proportional current flows through capacitor C 4 , and the source of the MP3 tube produces a voltage proportional to time, which in turn produces a squared current in the working path of the MP4 tube. Secondary slope compensation current I sl . Pe .
  • FIG 4 is a circuit diagram of the secondary voltage of the sampling module, a constant current source 12, current source generating a current reference, I sl.
  • Pe is the ramp current of the slope compensation circuit II
  • MP7 and MP8 are PMOS tubes
  • R 13 , R 14 and R 15 are the sampling voltage dividers of the output sampling voltages ⁇ 1 and V 2 in the secondary control module 4
  • R u and R 12 is the slope compensation current I sl .
  • pe and the constant current source 12 is converted to a voltage sampling resistor.
  • the output voltage V 2 is transmitted to the source stage of the MP8 through the source follower composed of MP8, and the voltage generated by the slope compensation current and the constant current source current flowing through the MP8 is also at the source level of the MP8, and the slope is supplemented.
  • the current sinking through resistor R 12 produces a voltage that, in combination with the two voltages described above, is sent to the negative input of a high speed, high precision, low offset comparator.
  • the output voltage is passed through the source follower of MP7 to the source stage of MP7, while the slope compensates for current I sl .
  • the voltage generated by pe and constant current source 12 through MP7 is also at the source level of MP7.
  • the constant current source flows through resistor Ru to generate a voltage. This voltage and the above two voltages are added together to be sent to high speed, high precision and low offset.
  • the positive input of the comparator is provided to generate a voltage that, in combination with the two voltages described above, is sent to the negative input of a high speed, high precision, low offset comparator.
  • the working waveform of the above control method is as shown in FIG. 5, which is the case of the branch one heavy load and the branch double load.
  • the energy required by the branch 1 is relatively large, and the duty ratio of the secondary loop is smaller than the duty ratio of the primary loop.
  • the structure of the proposed SIDO defaults to charging branch 2 first, V 02 rises, V 01 drops due to free discharge, and the ideal rising slope of inductor current is (V in -V 02 )/L, when V 02 is charged
  • the secondary duty cycle is turned over, the main stage turns to charge the branch 1, and the branch 2 is free to discharge.
  • the ideal rising slope of the inductor current is (V in -V 01 )/L, when the inductor current rises to the main stage.
  • the main circuit enters the inductor freewheeling state.
  • the branch circuit 1 continues to flow, and the branch circuit 2 continues to discharge freely.
  • the secondary loop duty ratio is greater than the primary loop duty ratio.
  • the branch 2 In the main circuit inductor current rising phase, the branch 2 is always charged, the slope is (V in -V 02 ) / L, the branch 1 is free to discharge, and in the inductor current freewheeling phase, the first branch 2 is freewheeling, branch Road 1 continues to discharge freely.
  • branch 2 When branch 2 continues to flow to the rollover point, it enters branch circuit 1 to continue the flow and branch 2 free discharge phase.
  • the inductor current drops to the main stage rollover point, it enters the next cycle.

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  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

一种基于纹波控制的单电感双输出开关电源，包括功率级模块（1）、滤波和电压采样模块（2）、次级电压采样模块（3）、次级纹波控制模块（4）、主级电压采样模块（5）、主级控制模块（6）和驱动模块（7），功率级模块（1）输出连接滤波和电压采样模块（2），滤波和电压采样模块（2）输出分别连接次级电压采样模块（3）和主级电压采样模块（5），次级电压采样模块（3）输出连接次级纹波控制模块（4），主级电压采样模块（5）连接主级控制模块（6），次级纹波控制模块（4）和主级控制模块（6）的输出均连接驱动模块（7），驱动模块（7）输出连接功率级模块（1），次级纹波控制模块（4）还输出斜坡补偿电流源（Islope）信号给次级电压采样模块（3）。

Description

一种基于紋波控制的单电感双输出开关电源 技术领域
本发明涉及开关电源领域， 尤其涉及一种基于纹波控制的单电感多输出开关电源。 背景技术
许多电子设备需要提供多个相互独立的电源， 这些电子设备要求高效的电源管理系 统。 单电感多输出 （SIMO) 降压型 DC-DC 转换器因其能减少片外元件的使用 （特别是 片外电感） 从而减小电源模块的体积， 因此成为一个学术界和产业界热点的研究和发展 方向。 虽然它能减小电源模块的体积， 但也存在着输出纹波较大， 效率偏低和交叉调制 的问题。 对于实际应用的 SIMO来说， 小纹波、 低交叉耦合、 高效率和快速瞬态响应是 最需要关注的指标。 已有技术采用共模电压控制主回路电流环， 差模电压控制次级回路 电压环的双输出 SIMO结构虽然一定程度上可以降低交叉耦合， 但是次级回路控制方法 复杂， 瞬态响应偏慢， 用飞电容串在两路输出之间来降低输出纹波的方法又会在一定程 度上恶化交调效应。
发明内容
为克服现有技术存在的缺陷， 本发明在现有技术基础上， 提出了一种基于纹波控制 的单电感双输出开关电源 （DC-DC 转换器）， 可以简化控制拓扑， 提高瞬态响应， 降低 纹波和交调耦合。
为实现上述目的， 本发明采用以下技术方案： 一种基于纹波控制的单电感双输出开 关电源， 其特征是： 包括功率级模块、 滤波和电压采样模块、 次级电压采样模块、 次级 波纹控制模块、 主级电压采样模块、 主级控制模块和驱动模块， 功率级模块输出连接滤 波和电压采样模块， 滤波和电压采样模块输出分别连接次级电压采样模块及主级电压采 样模块， 次级电压采样模块输出连接次级纹波控制模块， 主级电压采样模块输出连接主 级控制模块， 次级纹波控制模块及主级控制模块的输出均连接驱动模块， 驱动模块输出 连接功率级模块， 次级纹波控制模块还输出斜坡补偿电流源 Isl。pe信号给次级电压采样模 块； 其中：
功率级模块包括作为主功率开关管的 PMOS管 MP1、作为同步整流开关管的 NMOS 管 MN1、 作为次级功率开关管的 PMOS管 MP2及 NMOS管 MN2以及电感 L， PMOS 管 MP1的源极连接电源电压 Vin， PMOS管 MP1的漏极与 NMOS管 MN1的漏极以及电 感 L的一端连接在一起， NMOS管 MN1的源极接地， 电感 L的另一端分别连接 PMOS 管 MP2的源极及 NMOS管 MN2的漏极；
滤波和电压采样模块包括电容 、 C2及电阻 、 R2、 R3、 R4、 R5和 R6， 电容 的一端与功率级模块中 PMOS管 MP2的漏极、电阻 以及电阻 R3的一端连接在一起作 为一路输出电压 V ， 电容 d的另一端与电阻 的另一端以及电阻 R4的一端连接在一 起并接地， 电阻 R4的另一端与电阻 R3的另一端连接作为一路采样电压 V1 ; 电容 C2的一 端与功率级模块中 NMOS管 MN2的源极、 电阻 R2以及电阻 R5的一端连接在一起作为 另一路输出电压 V02， 电容 C2的另一端与电阻 R2的另一端以及电阻 R6的一端连接在一 起并接地， 电阻 R6的另一端与电阻 R5的另一端连接作为另一路采样电压 V2;
次级电压采样模块包括 PMOS管 MP7和 PMOS管 MP8、 电阻 Ru、 Ri2、 Ri3、 Ri4 和 R15、 一对恒流电流源 12及一对斜坡补偿电流源 Isl。pe， 电阻 R13及电阻 R15的一端分别 连接滤波和电压采样模块输出的采样电压 及采样电压 V2， 电阻 R13的另一端与 PMOS 管 MP7的栅极以及电阻 R14的一端连接在一起，电阻 R15的另一端与 PMOS管 MP8的栅 极连接， PMOS管 MP7的漏极与 PMOS管 MP8的漏极以及电阻 R14的另一端连接在一 起并接地， 一对恒流电流源 12及一对斜坡补偿电流源 Isl。pe的一端连接电源 VDD,其中一 个斜坡补偿电流源 Isl。pe的另一端与电阻 R12的一端连接作为输出电压 V—, 电阻 R12的另 一端与 PMOS管 MP8的源极以及其中一个恒流电流源 12的另一端连接在一起， 另一个 斜坡补偿电流源 Isl。pe的另一端与 PMOS管 MP7的源极以及电阻 Ru的一端连接在一起， 电阻 Ru的另一端与另一个恒流电流源 12的另一端连接作为输出电压 V+;
次级波纹控制模块包括斜坡补偿电路和比较器电路， 比较器电路的两个输入端分别 连接次级电压采样模块的输出电压 V+及 V—, 斜坡补偿电路包括 PMOS管 MP3、 PMOS 管 MP4、 PMOS管 MP5 、 PMOS管 MP6以及 NMOS管 MN3、 NMOS管 MN4、 NMOS 管 MN5、 电容 C3、 C4、 电阻 R1Q、恒流电流源 和反相器，恒流电流源 的一端与 PMOS 管 MP6的源极、 PMOS管 MP5的源极以及电容 C4的一端连接在一起并连接电源 VDD, 恒流电流源 的另一端与 NMOS管 MN3的漏极、 栅极以及 NMOS管 MN4的栅极连接 在一起， NMOS管 MN3的源极连接电容 C3的一端和 NMOS管 MN5的漏极， 电容 C3 的另一端及 NMOS管 MN5的源极均接地， NMOS管 MN5的栅极连接反相器的输出端， 反相器的输入端连接比较器电路输出的占空比信号 d2， PMOS管 MP6的栅极连接占空比 信号 d2， PMOS管 MP6的漏极连接电容 C4的另一端及 M0S管 MP3的源极， M0S管 MP3的栅极与漏极互连并与 M0S管 MP4的栅极及 NMOS管 MN4的漏极连接在一起， NMOS管 MN4的源极通过电阻 Rio接地， PMOS管 MP5的栅极接地， PMOS管 MP5的 漏极连接 PMOS管 MP4的源极， PMOS管 MP4的漏极作为斜坡补偿电路的输出， 输出 斜坡补偿电流源 Isl。pe信号给次级电压采样模块；
主级电压采样模块包括电阻 R7、 R8和 R9， 电阻 R7及电阻 R8的一端分别连接滤波和 电压采样模块输出的采样电压 及采样电压 V2， 电阻 R7及电阻 R8的另一端通过电阻 R9接地；
主级控制模块包括斜坡补偿电路（与次级波纹控制模块中的斜坡补偿电路相同）、振 荡器、 电流检测电路、 叠加器、 误差放大器和脉冲宽度调制器， 振荡器输出时钟控制信 号给斜坡补偿电路， 斜坡补偿电路输出连接叠加器， 电流检测电路的输入连接功率级模 块中 PMOS管 MP1和 NMOS管 MN1的的漏极， 电流检测电路的输出亦连接至叠加器， 叠加器的输出连接脉冲宽度调制器的一个输入端， 脉冲宽度调制器的另一个输入端连接 误差放大器的输出， 误差放大器的负输入端连接主级电压采样模块中作为采样电压 VM 输出的电阻 R7、 及 的连接端， 误差放大器正输入端连接基准电压 Vref， 接脉冲宽 度调制器输出主级占空比信号 d1 ;
驱动模块设有死区和驱动电路（可采用现有电路）， 其输入端分别连接主级控制模块 中脉冲宽度调制器输出的主级占空比信号 及次级波纹控制模块中比较器电路输出的占 空比信号 d2， 在死区和驱动电路的输出端， 由占空比信号 ^产生的驱动信号 PD和 ND 分别连接到功率级模块中 PMOS管 MP1的栅极及 NMOS管 MN1的栅极，由占空比信号 (12产生的驱动信号 DP和 DN分别连接到功率级模块中 PMOS管 MP2的栅极及 NMOS 管 MN2的栅极。
本发明的优点及显著效果：
( 1 )主环路采用共模电压峰值电流模式， 次级环路采用差模电压纹波控制模式的双路 SIMO降压 DC-DC转换器， 次级回路采用纹波控制模式。 为了提高瞬态响应， 简化了控 制电路， 主回路采用误差放大器无补偿的峰值电流模式， 进一步简化了控制电路， 同时 也提高了瞬态响应； 为了使主次回路稳定， 次级控制回路加入了额外的斜坡补偿， 额外 的斜坡补偿同时也降低了纹波。
(2)主级开关 MP1和 MN1通过两路输出电压的共模信号控制， 次级开关管 MP2和 MN2通过两路输出电压的差模信号控制。 主级开关采用共模电压控制， 次级开关采用差 模电压控制可减小交叉耦合。
(3)纹波控制型结构的核心在于一个高精度高速的比较器和一个斜坡补偿电路 ， 斜 坡补偿叠加到高精度高速比较器的输入端次级电压采样模块实现纹波控制。
(4) 主回路的控制拓扑为峰值电流型控制拓扑， 次级回路的控制拓扑为纹波控制型 拓扑。 次级开关采用差模电压的纹波进行控制， 并通过斜坡补偿消除了潜在的次谐波振 荡， 从而减小了单电感双输出开关电源的纹波。
(5) 功率开关管根据输入输出电压差选择不同类型的功率开关管， 并通过分段驱动 和轻载阶段采用 PSM模式来提高效率。
(6) 次级纹波控制模块简化了控制拓扑， 使系统响应速度变快。
(7) 由于次级纹波控制模块采用了斜坡补偿， 所以主级回路的斜坡补偿电路在一定 程度上也可以省去。
附图说明
图 1为本发明的方框图；
图 2为本发明的电路总图；
图 3为本发明的次级斜坡补偿电路的电路图； 图 4为本发明的次级电压采样电路图；
图 5为本发明的工作波形图；
图 6为本发明次级斜坡补偿的原理图。
具体实施方式
参看图 1， 本发明目的是提供一个快速响应、 小纹波、低交叉耦合、 高效率的单电感 双输出降压型 DC-DC转换器。 包括功率级模块 1、 滤波和电压采样模块 2、 次级电压采 样模块 3、 次级波纹控制模块 4、 主级电压采样模块 5、 主级控制模块 6和驱动模块 7.功 率级模块 1输出 V01 V02至滤波和电压采样模块 2， 滤波和电压采样模块 2输出 、 V2分别至次级电压采样模块 3及主级电压采样模块 5，次级电压采样模块 3输出 V+、 V_ 至次级纹波控制模块 4， 主级电压采样模块 5输出 VM至主级控制模块 6， 次级纹波控制 模块 4及主级控制模块 6分别输出占空比信号 d2、 4至驱动模块 7， 驱动模块 7输出连 接功率级模块 1， 次级纹波控制模块 4还输出斜坡补偿电流源 Isl。pe信号给次级电压采样 模块 3。
如图 2所示， Vin为开关电源输入电压， MP1为输入回路主级功率开关管， MN1为 主环路同步整流功率开关管， MP2、 MN2为次级功率管， MP1、 MN1、 MP2、 MN2和电 感 L组成了功率级模块 1。 为支路一的滤波电容， 为支路一的负载， ¾为支路二 的滤波电容， R2为支路二的负载， 、 Ri R2、 R3、 C2、 R4、 R5和 R6组成了滤波和电 压采样模块 2。 R7、 R8、 R9组成主级电压采样模块 5， 误差放大器和脉冲宽度调制器， 加 上电流检测、 叠加器、 振荡器和斜坡补偿电路 I， 组成了主级控制模块 6。 斜坡补偿电路 II和高速高精度低失调比较器， 组成了次级纹波控制模块 4。斜坡补偿电路 II与斜坡补偿 电路 I可采用结构相同的电路结构。
在功率级模块 1中， 主级功率开关管 MP1和同步整流功率开关管 MN1作为主环路 开关， 控制能量的输入， MP1使用功率 PMOS管， MN1使用功率 NMOS管。 电感 L之 后的两个次级功率开关管 MP2和 MN2作为次级开关， 决定能量的分配。 两路输出电压 Voi和 Vo2通过采样电阻 R3,R4,R5和 R6得到采样电压 N\和 V2，采样电压 N\和 V2分别传 递到主级电压采样模块和次级电压采样模块， 主级电压采样模块对采样电压 ¥1和 V2进 行采样处理得到主级采样电压 VM， VM和基准电压 Vref 通过误差放大器进行比较产生输 出电压， 电流检测电路和斜坡补偿电路 I的电流通过采样电阻产生另外一个电压， 这两 个电压通过脉冲宽度调制器进行比较产生占空比信号 4， 占空比信号 ^通过驱动模块产 生驱动信号 PD和 ND。 选择输出电压的功率管 MP2使用功率 PMOS管， 选择输出电压 的功率管 MN2使用功率 NMOS管。 选择输出电压的功率管类型可根据两路输出电压值 Voi和 V02与电源电压的关系来选择。其选择依据是：当输出电压小于电源电压的一半时， 功率管选择 N型功率 MOS管， 当输出电压大于电源电压的一半时， 功率管选择 P功率 MOS管。 例如当电源为 3.3V， VQ1的额定输出电压为 1.8V, 大于电源电压的一半， 选择 输出电压的功率 MOS管 MP2就选择 P型功率 MOS管， Vo2的额定输出电压为 1.2V, 大于电源电压的一半， 选择输出电压的功率 MOS管 MN2就选择 N型功率 MOS管。
次级控制环路采用添加了斜坡补偿的纹波控制模式。 斜坡补偿电路 II产生的二次斜 坡电流输入到次级电压采样模块， 两路采样输出电压 ¥工和 V2通过次级电压采样模块产 生差模电压 V+和 V-输入到高速高精度低失调比较器的两个输入端，产生次级占空比信号 d2， 占空比信号 d2通过驱动模块 （PWM) 产生驱动信号 DP和 DN。
在滤波和电压采样模块 2中， 输出滤波电容 和 C2使用低寄生电感的电容， 如体 积小的电容， 或者采用特殊工艺制作的低寄生电感的电容。
在主级电压采样模块 5 中， 电阻 R7、 R8和 R9通过分压采样到电压 VM， 这个电压 VM为共模电压采样电压， VM输入到主级控制模块 6中的误差放大器的负输入端。
在主级控制模块 6 中， 振荡器的输出时钟控制斜坡补偿电路 II产生斜坡补偿电流， 电流检测功率级的电流， 这两个电流叠加并输入到脉冲宽度调制器中。 同时， 主级电压 采样模块产生的采样电压 VM输入到误差放大器的负输入端， 基准电压 Vref输入到误差 放大器正输入端， 误差放大器的输出输入到脉冲调制器， 脉冲调制器产生主级占空比信 号 4， 主级占空比信号 ^输入到驱动模块 7中。
在次级纹波控制模块 4中，次级电压采样模块的两路输出 V+和 V-输入到高速高精度 比较器的两个输入端， 斜坡补偿电路 II产生的二次斜坡补偿电流输入到次级电压采样模 块中， 差模电压 V+和 V-在比较器中进行比较， 产生次回路的占空比信号 d2， 次级占空 比信号 d2输入到驱动模块 7中。
图 3为次级纹波控制模块 4中的斜坡补偿电路 II的电路示意图， II为电流源， 电流 源由电流基准产生， MN3、 MN4和 MN5为 NMOS管， MP3、 MP4、 MP5和 MP6为 PMOS 管， MN5和 MP6为 MOS管开关， 次级占空比信号 d2控制开关管 MP6, 次级占空比信 号 d2通过反相器控制开关管 MN5。初始状态时， 开关管 MN5和 MP6闭合， 电流基准无 基准电流产生， 斜坡补偿电路 II不工作， 当整个开关电源工作的时候， 次级占空比信号 控制开关管 MN5和 MP6断开， 电流基准产生电流， II为恒流源， 电容 C3上的电压在开 关管 MN5断开时会与时间成比例线性上升，电阻 R1Q上的电压也与时间成比例线性上升， 此时开关管 MP6也断开， 一个与时间成比例的电流流经电容 C4， MP3管的源端产生一 个与时间成比例的电压，进而在 MP4管的工作通路上产生一个与时间成平方关系的电流， 即为二次斜坡补偿电流 Isl。pe。
图 4为次级电压采样模块的电路示意图， 12为恒流电流源， 电流源由电流基准产生， Isl。pe为斜坡补偿电路 II的斜坡电流， MP7和 MP8为 PMOS管， R13、 R14和 R15为次级控 制模块 4中的输出采样电压 ¥1和 V2的采样分压电阻， Ru和 R12为把斜坡补偿电流 Isl。pe 和恒流源 12转化为电压的采样电阻。输出电压 V2经过 MP8构成的源随器传递到 MP8的 源级， 同时斜坡补偿电流和恒流源电流流经 MP8产生的电压也在 MP8的源级， 斜坡补 偿电流流经电阻 R12产生了一个电压， 这个电压和上述的两个电压加起来被送到高速高 精度低失调的比较器的负输入端。输出电压 经过 MP7构成的源随器传递到 MP7的源 级， 同时斜坡补偿电流 Isl。pe和恒流源电流 12经 MP7产生的电压也在 MP7的源级， 恒流 源流经电阻 Ru产生了一个电压，这个电压和上述的两个电压加起来被送到高速高精度低 失调的比较器的正输入端。
上述控制方式的工作波形如图 5所示， 分别为支路一重载和支路二重载的情况。 在支路 1重载的情况下， 如图 5 (a) 所示， 根据能量分配的原理， 支路 1需要的能 量比较大， 次级回路占空比小于主级回路占空比。 我们提出的 SIDO 的结构默认先给支 路 2充电， V02上升， V01由于自由放电而下降，此时电感电流理想的上升斜率为 (Vin-V02)/L, 当 V02充电到次级占空比翻转点， 主级转而给支路 1充电， 支路 2自由放电， 此时电感 电流理想的上升斜率为 (Vin-V01)/L,当电感电流上升到主级占空比翻转点， 主级回路进入 电感续流状态， 此时支路 1续流， 支路 2继续自由放电。
在支路 2重载的情况下， 如图 5 (b) 所示， 次级回路占空比大于主级回路占空比。 在主级回路电感电流上升阶段，一直给支路 2充电，斜率为 (Vin-V02)/L，支路 1 自由放电， 而在电感电流续流阶段， 首先支路 2续流， 支路 1继续自由放电， 当支路 2续流到翻转 点， 进入支路 1续流而支路 2自由放电阶段， 当电感电流下降到主级翻转点， 进入下一 个周期。
这种控制方式的核心和需要解决的问题在于， 在支路 2重载的情况下， 如何使次级占空 比自由切换。 如图 6所示。
由于自由放电的斜率远小于电感电流续流的斜率， 这导致了主级占空比切换后， 纹 波控制模块的两个比较因子 V2和 kV^法出现交点，从而使次级占空比无法切换。为了解 决这个问题， 我们采样支路 2输出电压¥2到纹波控制模块的时候，人为叠加了一个斜坡补 偿电路， 使支路 2在续流阶段采样到纹波控制模块的电压为上升的电压， 从而与另外一个 比较因子出现交点， 实现次级占空比切换。 同时由于次级斜坡补偿会影响到 SIDO结构的 两路输出电压， 所以采用二次斜坡补偿。

Claims

权利要求书
1、 一种基于纹波控制的单电感双输出开关电源， 其特征是： 包括功率级模块、 滤波 和电压采样模块、 次级电压采样模块、 次级波纹控制模块、 主级电压采样模块、 主级控 制模块和驱动模块， 功率级模块输出连接滤波和电压采样模块， 滤波和电压采样模块输 出分别连接次级电压采样模块及主级电压采样模块， 次级电压采样模块输出连接次级纹 波控制模块， 主级电压采样模块输出连接主级控制模块， 次级纹波控制模块及主级控制 模块的输出均连接驱动模块， 驱动模块输出连接功率级模块， 次级纹波控制模块还输出 斜坡补偿电流源 Isl。pe信号给次级电压采样模块； 其中：
功率级模块包括作为主功率开关管的 PMOS管 MP1、 作为同步整流开关管的 NMOS 管 MN1、 作为次级功率开关管的 PMOS管 MP2及 NMOS管 MN2以及电感 L， PMOS管 MPl的源极连接电源电压 Vin， PMOS管 MPl的漏极与 NMOS管 MN1的漏极以及电感 L的一端连接在一起， NMOS管 MN1 的源极接地， 电感 L的另一端分别连接 PMOS管 MP2的源极及 NMOS管 MN2的漏极；
滤波和电压采样模块包括电容 C^ C2及电阻 、 R2、 R3、 、 和 ， 电容 的 一端与功率级模块中 PMOS管 MP2的漏极、 电阻 以及电阻 R3的一端连接在一起作为 一路输出电压 V01， 电容 d的另一端与电阻 的另一端以及电阻 R4的一端连接在一起 并接地， 电阻 的另一端与电阻 的另一端连接作为一路采样电压 V1 ; 电容 C2的一端 与功率级模块中 NMOS管 MN2的源极、 电阻 R2以及电阻 R5的一端连接在一起作为另一 路输出电压 V02， 电容 C2的另一端与电阻 R2的另一端以及电阻 R6的一端连接在一起并 接地， 电阻 R6的另一端与电阻 R5的另一端连接作为另一路采样电压 V2;
次级电压采样模块包括 PMOS管 MP7和 PMOS管 MP8、 电阻 Ru、 Ri2、 Ri3、 Ri4和 Ris 一对恒流电流源 12及一对斜坡补偿电流源 Isl。pe， 电阻 R13及电阻 R15的一端分别连接 滤波和电压采样模块输出的采样电压 及采样电压 V2， 电阻 R13的另一端与 PMOS管 MP7的栅极以及电阻 R14的一端连接在一起， 电阻 R15的另一端与 PMOS管 MP8的栅极 连接， PMOS管 MP7的漏极与 PMOS管 MP8的漏极以及电阻 R14的另一端连接在一起并 接地， 一对恒流电流源 12及一对斜坡补偿电流源 Isl。pe的一端连接电源 VDD， 其中一个斜 坡补偿电流源 Isl。pe的另一端与电阻 R12的一端连接作为输出电压 V—, 电阻 R12的另一端 与 PMOS管 MP8的源极以及其中一个恒流电流源 12的另一端连接在一起， 另一个斜坡补 偿电流源 Islope的另一端与 PMOS管 MP7的源极以及电阻 Ru的一端连接在一起， 电阻 Rii的另一端与另一个恒流电流源 12的另一端连接作为输出电压 V+;
次级波纹控制模块包括斜坡补偿电路和比较器电路， 比较器电路的两个输入端分别 连接次级电压采样模块的输出电压 V+及 V—, 斜坡补偿电路包括 PMOS管 MP3、 PMOS 管 MP4、 PMOS管 MP5 、 PMOS管 MP6以及 NMOS管 MN3、 NMOS管 MN4、 NMOS 管 MN5、 电容 C3、 C4、 电阻 R1Q、 恒流电流源 和反相器， 恒流电流源 的一端与 PMOS管 MP6的源极、 PMOS管 MP5的源极以及电容 C4的一端连接在一起并连接电源 VDD, 恒流电流源 的另一端与 NM0S管 MN3的漏极、 栅极以及 NM0S管 MN4的栅 极连接在一起， NM0S管 MN3的源极连接电容 C3的一端和 NM0S管 MN5的漏极， 电 容 C3的另一端及 NM0S管 MN5的源极均接地， NM0S管 MN5的栅极连接反相器的输 出端， 反相器的输入端连接比较器电路输出的占空比信号 d2， PMOS管 MP6的栅极连接 占空比信号 d2， PMOS管 MP6的漏极连接电容 C4的另一端及 M0S管 MP3的源极， M0S管 MP3的栅极与漏极互连并与 M0S管 MP4的栅极及 NM0S管 MN4的漏极连接 在一起， NM0S管 MN4的源极通过电阻 R1Q接地， PMOS管 MP5的栅极接地， PMOS管 MP5的漏极连接 PMOS管 MP4的源极， PMOS管 MP4的漏极作为斜坡补偿电路的输 出， 输出斜坡补偿电流源 Isl。pe信号给次级电压采样模块；
主级电压采样模块包括电阻 R7、 R8和 R9， 电阻 R7及电阻 R8的一端分别连接滤波和 电压采样模块输出的采样电压 及采样电压 V2， 电阻 R7及电阻 R8的另一端通过电阻 R9 接地；
主级控制模块包括斜坡补偿电路、 振荡器、 电流检测电路、 叠加器、 误差放大器和 脉冲宽度调制器， 振荡器输出时钟控制信号给斜坡补偿电路， 斜坡补偿电路输出连接加 法器， 电流检测电路的输入连接功率级模块中 PMOS管 MP1和 NM0S管 MN1 的的漏 极， 电流检测电路的输出亦连接至叠加器， 叠加器的输出连接脉冲宽度调制器的一个输 入端， 脉冲宽度调制器的另一个输入端连接误差放大器的输出， 误差放大器的负输入端 连接主级电压采样模块中作为采样电压 VM输出的电阻 R7、 R8及 R9的连接端， 误差放大 器正输入端连接基准电压 Vref， 接脉冲宽度调制器输出主级占空比信号 d1 ;
驱动模块设有死区和驱动电路， 其输入端分别连接主级控制模块中脉冲宽度调制器 输出的主级占空比信号 4及次级波纹控制模块中比较器电路输出的占空比信号 d2， 在死 区和驱动电路的输出端， 由占空比信号 ^产生的驱动信号 PD和 ND分别连接到功率级模 块中 PMOS管 MP1 的栅极及 NMOS管 MN1 的栅极， 由占空比信号（12产生的驱动信号 DP和 DN分别连接到功率级模块中 PMOS管 MP2的栅极及 NMOS管 MN2的栅极。
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