WO2014026306A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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WO2014026306A1
WO2014026306A1 PCT/CN2012/001377 CN2012001377W WO2014026306A1 WO 2014026306 A1 WO2014026306 A1 WO 2014026306A1 CN 2012001377 W CN2012001377 W CN 2012001377W WO 2014026306 A1 WO2014026306 A1 WO 2014026306A1
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semiconductor device
source
substrate
region
gesn
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French (fr)
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马小龙
殷华湘
付作振
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/211—Gated diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/021—Manufacture or treatment of gated diodes, e.g. field-controlled diodes [FCD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0277—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming conductor-insulator-semiconductor or Schottky barrier source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/165—Tunnel injectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
    • H10P34/40—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
    • H10P34/42—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation with electromagnetic radiation, e.g. laser annealing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions

Definitions

  • the present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly to a tunneling field effect transistor (TFET) having a GeSn alloy as a source and a method of fabricating the same.
  • TFET tunneling field effect transistor
  • the critical parameters of the device such as the threshold voltage
  • the advantages of reduced power consumption and increased integration promote the overall performance of the device.
  • the driving ability of the device is limited by the conventional silicon material process, the carrier mobility is low, and the device driving capability is insufficient. Therefore, high mobility channel devices have important application backgrounds in the future.
  • GeSn alloy which has a high carrier mobility and can adjust the energy band structure of the alloy by adjusting the Sn content, so it is widely used in advanced CMOS devices and optoelectronic devices. in.
  • TFET tunneling field effect transistor
  • an object of the present invention is to provide a TFET having a GeSn stress region and a method for fabricating the same, which overcomes the defects of the above conventional process, effectively improves the on-state current Ion and the switch current ratio Ion/Ioff of the TFET, that is, increases the driving. The ability to effectively reduce power consumption.
  • the above object of the present invention is achieved by providing a semiconductor device including a substrate, a gate stack structure on a substrate, a source/drain region in a substrate on both sides of the gate stack structure, and a source-drain region in the substrate.
  • the channel region is characterized in that: the source region in the source and drain regions comprises a GeSn alloy, and optionally a tunneling dielectric layer is further included between the GeSn alloy and the channel region of the source region.
  • the channel region comprises Si and/or SiGe.
  • the forbidden band width of the GeSn alloy is adjusted by controlling the Sn content.
  • the Sn content in the GeSn alloy is more than 0 and less than 30%.
  • the source and drain regions further include an elevated source and drain region of the same material.
  • the tunnel dielectric layer comprises silicon oxide, silicon nitride, silicon oxynitride, high k materials, and combinations thereof.
  • the source and drain regions further comprise a metallized source/drain contact layer.
  • the source region and the drain region have different conductivity types, and the channel region is intrinsically undoped.
  • the present invention also provides a method of fabricating a semiconductor device, comprising: forming a gate stack structure on a substrate; forming a drain region in a substrate on one side of the gate stack structure; and a substrate on the other side of the gate stack structure The source region of the GeSn material is formed.
  • the forbidden band width of the GeSn alloy is adjusted by controlling the Sn content.
  • the Sn content in the GeSn alloy is more than 0 and less than 30%.
  • the method for forming a source region of a GeSn material shield includes: etching a substrate of the source region, selectively epitaxially growing, and depositing a GeSn alloy.
  • the method for forming a source region of a GeSn material comprises: injecting a precursor into a substrate on the other side of the gate stack structure; and rapidly annealing the laser to cause the precursor to react to form a GeSn alloy to form a source region.
  • the step of implanting the precursor further comprises: performing amorphization ion implantation to form an amorphization region in the substrate; and injecting Sn in the amorphization region.
  • the ions implanted by the amorphized ions include Ge, B, Ga, In, and combinations thereof.
  • the implantation dose of Sn is 1 10 15 ⁇ 1 X 10 17 cm - 2 .
  • a protective layer is formed on the precursor before the laser is rapidly annealed.
  • the laser single-pulse time lns ⁇ lus in the laser rapid annealing process the number of pulses is
  • a tunneling dielectric layer is further formed between the source region and the channel, and the forming step specifically includes: etching the substrate on the other side of the gate stack structure to form a source trench, in the source trench A tunneling dielectric film is deposited, and a GeSn alloy is formed on the tunnel dielectric layer film to form a source region.
  • a GeSn alloy having a narrow band gap is formed by implanting a precursor and then rapidly annealing the laser, thereby effectively improving the on-state current of the TFET, and has an important application prospect in high performance and low power consumption applications.
  • 1 to 3 are schematic cross-sectional views showing respective steps of a method of fabricating a semiconductor device in accordance with a first embodiment of the present invention
  • 4A and 4B are schematic cross-sectional views showing a method of fabricating a semiconductor device in accordance with a second embodiment of the present invention.
  • Figure 5 is a schematic cross-sectional view of a final semiconductor device fabricated in accordance with the present invention. detailed description
  • a conventional MOSFET device structure having a GeSn stress source drain region is formed.
  • a gate stack structure 2 and a gate spacer 3 are formed on a substrate 1, and a drain region 1 D is formed in the substrate 1 on the side of the gate stack structure.
  • a substrate 1 is provided which may be a bulk Si, a SOL body Ge, GeOI, SiGe, GeSb, or a III-V or II-VI compound semiconductor substrate such as GaAs, GaN, InP, InSb or the like. Further, it may be a transparent substrate such as glass, plastic or resin. In order to be compatible with existing CMOS processes for large scale digital integrated circuit fabrication, the substrate 1 is preferably a bulk Si (monocrystalline silicon wafer), SOI wafer.
  • a shallow trench is first etched in the substrate 1, and then a fill oxide (for example, silicon oxide) is deposited in the shallow trench by conventional methods such as rapid thermal oxidation (RTO), LPCVD, PECVD HDPCVD to form shallow trench isolation (STI) 1A.
  • RTO rapid thermal oxidation
  • LPCVD LPCVD
  • PECVD HDPCVD shallow trench isolation
  • the substrate region surrounded by the STI 1A constitutes the active region of the device.
  • a buried layer (not shown) is formed in the active region surrounded by the STI 1A, and the buried layer is used to enhance the stress applied to the channel region by the source/drain region or to enhance the stress of the channel region itself, thereby further improving the current carrying current.
  • the buried material is a material having a lattice constant between the substrate Si and a later source/drain region GeSn, such as SiGe.
  • the method of forming the buried layer may be optionally depositing a buffer layer on the substrate 1, epitaxially growing a SiGe buried layer on the substrate/buffer layer, and optionally epitaxially growing a Si or Ge top layer on the buried layer.
  • the method of forming the buried layer may also be to implant Ge ions into the Si substrate to a certain depth, and then anneal to cause the implanted dopant ions to react with the substrate to form a SiGe buried layer.
  • the distance between the buried layer and the surface of the substrate 1, that is, the depth of the buried layer, is set by controlling the epitaxy or the implantation process parameters according to the stress distribution of the channel region, and the buried layer depth is, for example, 10 to 30 nm.
  • the gate insulating layer 2A, the gate conductive layer 2B are sequentially deposited on the substrate 1 by conventional methods such as LPCVD, PECVD, HDPCVD MOCVD, MBE, ALD, evaporation, sputtering, etc., and then etched to form a gate stack structure 2A/ 2B.
  • the gate stack structure will remain, and the gate insulating layer 2A is a high-k material including, but not limited to, nitrides (eg, SiN, A1N, TiN), metal oxides (mainly subgroups and lanthanides).
  • Metal element oxides such as A1 2 0 3 , Ta 2 0 5 , Ti0 2 , ZnO, Zr0 2 , Hf0 2 , Ce0 2 , Y 2 0 3 , La 2 0 3 ), perovskite phase oxides (eg PbZr) x Ti 1-x 0 3 ( PZT ) , Ba x Sr 1-x Ti0 3 ( BST ) ) ;
  • the gate conductive layer 2B is a metal and/or a metal nitride, wherein the metal includes Al, Ti, Cu, Mo, W, Ta, metal nitrides include TiN, TaN.
  • the gate stack structure at this time is a dummy gate stack structure, which will be removed in a subsequent process
  • the gate insulating layer 2A includes silicon oxide, silicon oxynitride
  • the gate conductive layer 2B is polysilicon or amorphous. silicon.
  • the thickness of the layer 2A is, for example, 1 to 5 nm
  • the thickness of the layer 2B is, for example, 10 to 100 nm.
  • a shield material such as silicon nitride, silicon oxynitride, diamond-like amorphous carbon (DLC) is deposited on the substrate 1 and the gate stack structure 2A/2B by conventional methods such as PECVD, HDPCVD, etc., and is etched to form a gate.
  • Side wall 3 a shield material such as silicon nitride, silicon oxynitride, diamond-like amorphous carbon (DLC) is deposited on the substrate 1 and the gate stack structure 2A/2B by conventional methods such as PECVD, HDPCVD, etc.
  • the drain region ion implantation is performed, and a drain region 1D having a first doping type, for example, a drain region of n+, is formed in the substrate 1 of the gate stack structure 2A/2B-side (left or right side).
  • the type of doped ions may be P, As, N, etc., and the doping amount and implantation energy are appropriately set according to the junction depth control and the doping concentration.
  • a tunnel dielectric layer is also formed between the source region and the substrate (channel).
  • the forming step specifically includes: etching the source region, depositing a tunneling dielectric film.
  • the substrate 1 on the other side of the gate stack structure 2 is photolithographically/etched to form a source region trench 1 S T .
  • the tunneling dielectric layer 4 is deposited in the source trench 1 ST by LPCVD, PECVD, HDPCVD, MBE, ALD, etc., and the material thereof may be silicon oxide, silicon nitride, silicon oxynitride, high-k material, and combinations thereof.
  • the ground is a laminated structure of the above various materials.
  • the thickness of the tunnel dielectric layer 4 is selected in accordance with device performance requirements, for example, l ⁇ 10 nm.
  • a source region 1S is formed.
  • the source region IS is selectively epitaxially grown in the source trench 1 ST by PECVD, HDPCVD, MBE, ALD, etc., and the precursor contains at least Ge and Sn elements, and the source region 1 S is GeSn. Alloy material.
  • the thickness of the alloy layer and the content of Sn (atomic number ratio) in the Ge 1-x Sn x alloy can be controlled by controlling process parameters such as the raw material gas, the flow rate of the solid, and the pressure and temperature in the reaction chamber. Preferably, 0 ⁇ x ⁇ 0.3.
  • the in-situ doping is performed synchronously when epitaxially growing the GeSn alloy such that the source region 1 S has a second doping type different from the drain region 1D doping type, for example, p+.
  • the substrate 1 (constituting the channel region) may be an undoped intrinsic substrate 1 or a second doping type having light doping, such as p -.
  • FIG. 4A and 4B illustrate another embodiment of the present invention in which a source region 1 S of a GeSn alloy is formed by implanting a precursor (Fig. 4A) followed by laser annealing (Fig. 4B).
  • a precursor Fig. 4A
  • Fig. 4B laser annealing
  • epitaxial growth in the source trench 1 ST or C VD deposition of Si, SiGe, etc. are the same as the material of the substrate 1.
  • the above deposition methods may be PECVD, HDPCVD, MBE, ALD, or the like.
  • Doping implantation is performed, and the precursor is implanted into the source region 1 S of the gate side wall 3 side by using the gate spacer 3 as a mask to form a doped region 1 Sd of the precursor.
  • Amorphous ion implantation is first performed.
  • the implantation energy is, for example, 10 to 200 KeV, and the implantation dose is, for example, 1 X 10 15 to 1 X 10 17 cm_ 2 .
  • the implanted ions are Ge.
  • the implanted Ge ions destroy the crystal lattice in a certain region (for example, 10-20 nm from the surface) of the substrate 1 and the source region of the source region 1 S to be formed, and amorphize it to form an amorphization region. (not shown) to facilitate further ion implantation later, and to form an alloy upon annealing.
  • impurity ions such as Ga, In, etc. are further implanted in the amorphization region to adjust the conductivity type and concentration of the source and drain regions.
  • the amorphized implanted ions are impurity ions such as B, Ga, and In
  • the source-drain region conductivity type and concentration are also adjusted while amorphizing, so that the above-described impurity implantation for adjusting the source-drain conductivity type and concentration is not additionally performed.
  • Sn is implanted in the amorphization region.
  • the implantation energy is, for example, 20 to 200 keV
  • the implantation dose is, for example, 1 X 10 15 to 1 X 10 17 cm - 2 and preferably 1 X 10 16 cnT 2 .
  • at least a doping ion of Ge and Sn is contained in the amorphization region to serve as a precursor, thereby constituting a doped region 1Sd of the precursor.
  • impurity ions such as B, Ga, and In may be implanted after the Sn is implanted.
  • a protective layer (not shown) is formed on the precursor doped region I Sd .
  • a method such as PECVD, LPCVD, or the like is used to lower the deposition temperature to form a low temperature protective layer, that is, a low temperature deposition protective layer such as low temperature silicon oxide (LTO), and a deposition temperature of, for example, lower than 400 ° C to prevent Ge and Sn from reacting in advance.
  • a spin coating, screen printing, spray coating, or the like, a glass material such as PSG or BPSG, or a resin material such as a photoresist may be used to form a protective layer for avoiding excessive laser processing and damaging the material.
  • the protective layer can also be omitted.
  • laser rapid annealing is performed so that Ge in the doped region I Sd of the precursor reacts with Sn to form GeSn, thereby constituting the source region 1S of GeSn. ⁇ irradiating the precursor doped region I Sd with a laser pulse, so that the surface of the doped region I Sd containing at least two precursors of Ge and Sn is rapidly warmed and melted and reacted with each other, and is the same as the substrate 1 during cooling.
  • the lattice constant of the material introduces compressive strain along the carrier transport direction to increase the mobility of the carriers.
  • GeSn alloy can also reduce the source-drain contact resistance of the device.
  • the laser rapid annealing process the laser single pulse time Ins ⁇ lus, the number of pulses is 1 ⁇ 100, and the energy density is 100mJ / cm 2 ⁇ lJ / cm 2 .
  • the thickness of the alloy layer and the content of Sn in the Ge 1-x Sn x alloy (atomic ratio) can be controlled.
  • the existing front gate or back gate process can be continued to complete the MOSFET fabrication.
  • the epitaxially homogenous or heterogeneous but high-mobility material source/drain regions 5 are formed, and a metal silicide is formed on the G e S n source/drain region 1 S / 1 D / 5 .
  • the source and drain of the metal halide metallize the contact layer 6 to further reduce the source-drain contact resistance.
  • An interlayer dielectric layer (ILD) 7 of low k material is deposited over the entire device.
  • the source and drain contact holes are formed by etching the ILD7 until the source/drain metallized contact layer 6 is exposed, and metal such as ⁇ , Cu, Al, Mo, and metal nitride such as TiN and TaN are deposited in the contact hole to form the source/drain contact plug 8.
  • metal such as ⁇ , Cu, Al, Mo, and metal nitride such as TiN and TaN are deposited in the contact hole to form the source/drain contact plug 8.
  • the gate stack structure in the structure shown in FIG. 5 is the gate insulating layer 2A and the gate conductive layer 2B which are stacked in parallel in the front gate process, it is also applicable to the gate gate process, that is, the gate insulating layer.
  • Layer 2 A surrounds the bottom surface of the gate conductive layer 2B and the side surface (not shown in FIG. 5) in the gate trench.
  • a semiconductor device in accordance with a first embodiment of the present invention includes a substrate, a gate stack structure on the substrate, source and drain regions in the substrate on both sides of the gate stack structure, and trenches between source and drain regions in the substrate
  • the track region is characterized in that the source region in the source and drain regions comprises a GeSn alloy, and optionally a tunneling dielectric layer is further included between the GeSn alloy and the channel region of the source region. Further, the channel region includes Si or SiGe.
  • a GeSn alloy having a narrow band gap is formed by implanting a precursor and then rapidly annealing the laser, thereby effectively improving the on-state current of the TFET, and has an important application prospect in high performance and low power consumption applications.

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明公开了一种半导体器件，包括衬底、衬底上的栅极堆叠结构、栅极堆叠结构两侧衬底中的源漏区、衬底中源漏区之间的沟道区，其特征在于：源漏区中的源区包括GeSn合金，并且源区的GeSn合金与沟道区之间可选地还包括隧穿介质层。依照本发明的半导体器件及其制造方法，通过选择性外延或者注入前驱物然后激光快速退火，形成了具有窄带隙的GeSn合金，有效提高了TFET的开态电流，在高性能低功耗应用中具有重要应用前景。

Description

半导体器件及其制造方法 优先权要求
本申请要求了 2012年 8月 16日提交的、 申请号为 201210293525.X、 发明名称为 "半导体器件及其制造方法" 的中国专利申请的优先权， 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及半导体集成电路制造领域， 更具体地， 涉及一种具有 GeSn合金作为源极的隧穿场效应晶体管 （TFET )及其制造方法。 背景技术
随着集成电路工艺持续发展， 特别是器件尺寸不断等比例缩减， 器件的各个关键参数例如阈值电压等也随之减小， 功耗减小、 集成度 提高这些优点促进了器件整体性能提高。 然而与此同时， 器件的驱动 能力却受制于传统的硅材料工艺的限制， 载流子迁移率较低， 面临了 器件驱动能力相比而言不足的问题。 因此， 高迁移率沟道器件在未来 具有重要应用背景。
现有的高迁移率沟道器件通常是采用 Si1-xGex或 Si1-xCx来作为应力 源漏区向 Si的沟道区施加应力，或者直接采用这些材料作为衬底和沟道 区。 在 Si1-xGex中引入压应变能够进一步提高空穴的迁移率， 相应地在 在 Si1-xCx中引入张应变能够进一步提高电子的迁移率。 然而， 这两种材 料晶格常数与 Si差别仍不够大， 能够提供的应变有限， 难以应用在需要 更高驱动能力的器件中。
一种可选的替代材料是 GeSn合金， 该薄膜具有 ^[艮高的载流子迁移 率， 并且可以通过调节 Sn的含量调节合金的能带结构， 因此广泛应用 于先进的 CMOS器件和光电子器件中。
然而传统的 GeSn合金需要用分子束外延或者 CVD, 目前仍不成熟 或者与 CMOS不兼容。 此外， 由于 Sn在 Ge中的平衡固溶度非常的低， 因此用常规的方法很难得到 Sn的含量大于 1 %的 Ge 1-xSnx。
此外， 其他高迁移率材料， 诸如 GaAs、 InSb等也存在类似问题， 难以与 Si基的 CMOS工艺兼容。 另一方面， 常规 MOSFET的沟道长度缩减时， 漏电流随之上升。 特 别是在 30nm以下工艺中， 器件的漏电流显著增大， 使得整个器件的功 耗难以遏制地上升。 降低器件功耗的一种途径是采用新型的隧穿场效 应晶体管 （TFET ) 结构， 通过在源极与沟道区之间增加隧穿介质层， 有效降低了漏电流， 大大降低了芯片功耗。 然而， 当尺寸持续缩减到 22nm以下时， 现有的普通 TFET驱动电流较常规 MOSFET驱动电流低 3 ~ 4个数量级， 这使得无法兼顾功耗减低与提高驱动能力， 器件的整 体性能提升有限。 发明内容
有鉴于此， 本发明的目的在于提供一种具有 GeSn应力区的 TFET及 其制造方法， 克服上述传统工艺的缺陷， 有效提高 TFET的开态电流 Ion 和开关电流比 Ion/Ioff , 也即提高驱动能力的同时还能有效降低功耗。
实现本发明的上述目的， 是通过提供一种半导体器件， 包括村底、 衬底上的栅极堆叠结构、 栅极堆叠结构两側衬底中的源漏区、 衬底中 源漏区之间的沟道区， 其特征在于： 源漏区中的源区包括 GeSn合金， 并且源区的 GeSn合金与沟道区之间可选地还包括隧穿介质层。
其中， 沟道区包括 Si和 /或 SiGe。
其中， 通过控制 Sn含量来调节 GeSn合金的禁带宽度。
其中， GeSn合金中 Sn含量大于 0并且小于 30 %。
其中， 可选地， 源漏区上还包括材质相同的提升源漏区。
其中， 可选地， 隧穿介质层包括氧化硅、 氮化硅、 氮氧化硅、 高 k 材料及其组合。
其中， 源漏区上还包括金属化源漏接触层。
其中， 源区与漏区导电类型不同， 沟道区为本征未掺杂的。
本发明还提供了一种半导体器件制造方法， 包括： 在衬底上形成 栅极堆叠结构； 在栅极堆叠结构一侧的村底中形成漏区； 在栅极堆叠 结构另一侧的衬底中形成 GeSn材质的源区。
其中， 通过控制 Sn含量来调节 GeSn合金的禁带宽度。
其中， GeSn合金中 Sn含量大于 0并且小于 30 %。
其中， 形成 GeSn材盾的源区的方法包括： 刻蚀源区的衬底， 选择 性外延生长、 淀积 GeSn合金。 其中， 形成 GeSn材质的源区的方法包括： 在栅极堆叠结构另一侧 的村底中注入前驱物； 激光快速退火， 使得前驱物反应形成 GeSn合金， 构成源区。
其中， 注入前驱物的步骤进一步包括： 执行非晶化离子注入， 在 衬底中形成非晶化区； 在非晶化区中注入 Sn。
其中， 非晶化离子注入的离子包括 Ge、 B、 Ga、 In及其组合。
其中， Sn的注入剂量为 1 1015 ~ 1 X 1017cm-2。
其中， 在注入前驱物之后、 在激光快速退火之前， 在前驱物上形 成保护层。.
其中， 激光快速退火工艺中激光单脉冲时间 lns ~ lus, 脉沖个数为
1 ~ 100, 能量密度为 100mJ/cm2 ~ U/cm2。
其中， 可选地在源区与沟道之间还形成隧穿介质层， 其形成步骤 具体包括： 刻蚀栅极堆叠结构另一侧的衬底形成源极沟槽， 在源极沟 槽中沉积隧穿介质薄膜， 在隧穿介质层薄膜上形成 GeSn合金而构成源 区。
依照本发明的半导体器件及其制造方法， 通过注入前驱物然后激 光快速退火， 形成了具有窄带隙的 GeSn合金， 有效提高了 TFET的开态 电流， 在高性能低功耗应用中具有重要应用前景。 - 附图说明
以下参照附图来详细说明本发明的技术方案， 其中：
图 1至图 3为根据本发明第一实施例的半导体器件制造方法各步骤 的剖面示意图；
图 4A以及 4B为根据本发明第二实施例的半导体器件制造方法的剖 面示意图； 以及
图 5为根据本发明制造的最终半导体器件的剖面示意图。 具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案 的特征及其技术效果。 需要指出的是， 类似的附图标记表示类似的结 构， 本申请中所用的术语 "第一" 、 "第二，， 、 "上" 、 "下" 、 "厚" 、 "薄" 等等可用于修饰各种器件结构。 这些修饰除非特别说明并非暗 示所修饰器件结构的空间、 次序或层级关系。
根据本发明第一实施例， 参照图 1至图 3 , 形成了具有 GeSn应力源 漏区的常规 MOSFET器件结构。
首先参照图 1， 在衬底 1上形成栅极堆叠结构 2和栅极侧墙 3 , 在栅 极堆叠结构 2—侧的衬底 1中注入形成漏区 1 D。
提供衬底 1 , 其可以是体 Si、 SOL 体 Ge、 GeOI 、 SiGe、 GeSb, 也可以是 III-V族或者 II-VI族化合物半导体衬底，例如 GaAs、 GaN、 InP、 InSb等等。 此外， 也可以是玻璃、 塑料、 树脂等透明基板。 为了与现有 的 CMOS工艺兼容以应用于大规模数字集成电路制造， 衬底 1优选地为 体 Si (单晶硅晶片） 、 SOI晶片。
在衬底 1中先刻蚀形成浅沟槽， 然后采用快速热氧化 （RTO ) 、 LPCVD、 PECVD HDPCVD等常规方法， 在浅沟槽中沉积填充氧化物 (例如氧化硅）从而形成浅沟槽隔离 （STI ) 1A。 STI 1A包围的衬底区 域即构成器件的有源区。
优选地， 在 STI 1A包围的有源区内形成埋层 （未示出） ， 埋层用 于增强源漏区向沟道区施加的应力或者增强沟道区自身的应力， 从而 进一步提高载流子迁移率。埋层材质是晶格常数介于衬底 Si与稍后的源 漏区 GeSn之间的材料， 例如是 SiGe。 形成埋层的方法可以是可选地在 衬底 1上沉积緩沖层、 在衬底 /緩冲层上外延生长 SiGe埋层、 以及可选地 在埋层上再外延生长 Si或者 Ge顶层。 此外， 形成埋层的方法还可以是 将 Ge离子注入到 Si衬底中一定深度， 随后退火使得注入的掺杂离子与 衬底反应形成 SiGe埋层。 埋层与衬底 1表面的距离也即埋层深度， 依照 沟道区应力分布需要而通过控制外延或者注入工艺参数而设定， 埋层 深度例如是 10 ~ 30nm。
通过 LPCVD、 PECVD、 HDPCVD MOCVD、 MBE、 ALD、 蒸发、 溅射等常规方法， 在衬底 1上依次沉积栅极绝缘层 2A、 栅极导电层 2B, 并随后刻蚀形成栅极堆叠结构 2A/2B。 在前栅工艺中， 栅极堆叠结构将 一直保留， 栅极绝缘层 2A是高 k材料， 包括但不限于氮化物（例如 SiN、 A1N、 TiN ) 、 金属氧化物 （主要为副族和镧系金属元素氧化物， 例如 A1203、 Ta205、 Ti02、 ZnO、 Zr02、 Hf02、 Ce02、 Y203、 La203 ) 、 钙 钛矿相氧化物 （例如 PbZrxTi1-x03 ( PZT ) 、 BaxSr1-xTi03 ( BST ) ) ； 栅极导电层 2B是金属和 /或金属氮化物， 其中金属包括 Al、 Ti、 Cu、 Mo、 W、 Ta, 金属氮化物包括 TiN、 TaN。 在后栅工艺中， 此时的栅极堆叠 结构是假栅极堆叠结构， 在后续工艺中将去除， 栅极绝缘层 2A包括氧 化硅、氮氧化硅，栅极导电层 2B是多晶硅、非晶硅。层 2A厚度例如是 1 ~ 5nm , 层 2B厚度例如是 10 ~ 100nm。
优选地， 在衬底 1以及栅极堆叠结构 2A/2B上通过 PECVD、 HDPCVD等常规方法沉积氮化硅、氮氧化硅、类金刚石无定形碳（DLC ) 等介盾材料并刻蚀形成栅极侧墙 3。
执行漏区离子注入， 在栅极堆叠结构 2A/2B—側（左侧或者右侧均 可）的衬底 1中形成具有第一掺杂类型的漏区 1D， 例如为 n+的漏区。 掺 杂离子的种类可以是 P、 As、 N等， 掺杂剂量和注入能量依照结深控制 以及掺杂浓度需要而合理设定。
可选地， 参照图 2， 在源区与衬底（沟道）之间还形成隧穿介质层。 其形成步骤具体包括： 刻蚀源区， 沉积隧穿介质薄膜。 具体地， 光刻 / 刻蚀栅极堆叠结构 2另一侧的衬底 1，形成源区沟槽 1 S T。在源区沟槽 1 S T 中通过 LPCVD、 PECVD, HDPCVD, MBE、 ALD等方法沉积隧穿介质 层 4 , 其材质可以是氧化硅、 氮化硅、 氮氧化硅、 高 k材料及其组合， 优选地为上述多种材料的层叠结构。 隧穿介质层 4的厚度依照器件性能 需要而选定， 例如是 l ~ 10nm。
参照图 3以及图 4A至图 4B， 形成源区 1S。
其中图 3对应于本发明一个实施例，其中选择性外延生长 GeSn合金 材料的源区 1 S。 在该步骤中， 通过 PECVD、 HDPCVD, MBE、 ALD等 方法在源区沟槽 1 ST中选择性外延生长源区 IS , 其前驱物中至少包含 Ge以及 Sn元素， 形成的源区 1 S为 GeSn合金材质。 通过控制前驱物例如 原料气、 固体的配比流速以及反应室内压强和温度等工艺参数， 可以 控制合金层的厚度以及 Ge1-xSnx合金中 Sn的含量 （原子数目比） 。 优选 地， 0<x<0.3。 优选地， 在外延生长 GeSn合金时同步进行原位掺杂， 使 得源区 1 S具有不同于漏区 1D掺杂类型的第二掺杂类型， 例如为 p+。 与 之对应的， 提供衬底 1 (构成沟道区） 时可以是未掺杂的本征衬底 1 , 也可以是具有轻掺杂的第二掺杂类型， 例如 p -。
图 4A以及图 4B示出了本发明另一实施例，其中通过注入前驱物（图 4A ) , 之后激光退火处理（图 4B ) , 形成 GeSn合金的源区 1 S。 首先在 源区沟槽 1 ST中外延生长或者 C VD沉积 Si、 SiGe等与衬底 1材质相同的 材料， 以用作源区基材。 以上这些沉积方法可以是 PECVD、 HDPCVD、 MBE、 ALD等。 执行掺杂注入， 以栅极侧墙 3为掩模， 在栅极侧墙 3— 侧的源区 1 S中注入前驱物， 形成前驱物的掺杂区 1 Sd。
首先执行非晶化离子注入（PAI ) 。 注入能量例如是 10 ~ 200KeV, 注入剂量例如是 1 X 1015 ~ 1 X 1017cm_2。 当衬底 1及其源区基材 I S为 Si 时， 注入离子是 Ge。 注入的 Ge离子破坏了待形成源漏区的衬底 1及其源 区基材 1 S表面一定区域（例如距离表面 10 ~ 20nm ) 内的晶格， 使其非 晶化而构成非晶化区 （未示出） ， 以利于稍后进一步离子注入、 以及 退火时反应形成合金。
优选地， 非晶化离子注入之前和 /或之后， 进一步在非晶化区中注 入 Ga、 In等杂质离子， 以调整源漏区导电类型和浓度。
此外， 当衬底 1及其源区基材 1 S为 SiGe或者是含有 SiGe埋层的 Si时 (也即衬底本身含有 Ge ) , 非晶化注入离子是 B、 Ga、 In等杂质离子， 在非晶化的同时也调整源漏区导电类型和浓度， 因此不再额外地执行 上述调节源漏导电类型和浓度的杂质注入。
非晶化离子注入之后，在非晶化区中注入 Sn。注入能量例如是 20 ~ 200KeV, 注入剂量例如是 1 X 1015 ~ 1 X 1017cm-2并优选 1 X 1016cnT2。 至 此， 非晶化区中至少包含了 Ge和 Sn两种掺杂离子以用作前驱物， 从而 构成了前驱物的掺杂区 lSd。
此外， 也可以在注入 Sn之后再注入 B、 Ga、 In等杂质离子。
优选地， 在前驱物掺杂区 I Sd上形成保护层 （未示出） 。 例如采用 PECVD, LPCVD等方法并且降低沉积温度从而形成低温保护层， 也即 低温沉积保护层， 例如低温氧化硅（LTO ) , 沉积温度例如低于 400°C 以避免此时 Ge与 Sn提前反应。 或者通过旋涂、 丝网印刷、 喷涂等方法， 采用 PSG、 BPSG等玻璃材料， 甚至可以是光刻胶等树脂材料来形成保 护层， 用于避免稍后的激光处理过度而损坏材料。 自然， 如果能良好 调整激光处理参数， 保护层也可以省略。
然后， 参照图 4B , 执行激光快速退火， 使得前驱物的掺杂区 I Sd 中 Ge与 Sn反应形成 GeSn， 从而构成 GeSn的源区 1S。 釆用激光脉冲照射 前驱物掺杂区 I Sd, 使得至少包含 Ge与 Sn这两种前驱物的掺杂区 I Sd表 面快速升温融化并且相互反应， 并且在冷却的过程中以相同于衬底 1和 /或 SiGe埋层的晶向结晶， 最终形成 Ge1-xSnx合金， 其晶格常数大于沟道 材料的晶格常数， 沿载流子输运方向引入压应变， 提高载流子的迁移 率。 此外， GeSn合金也可以减小器件的源漏接触电阻。 激光快速退火 工艺中激光单脉沖时间 Ins ~ lus， 脉沖个数为 1 ~ 100， 能量密度为 100mJ/cm2 ~ lJ/cm2。 调节上述激光脉冲参数， 可以控制合金层的厚度 以及 Ge1-xSnx合金中 Sn的含量 （原子数目比） 。 优选地， 0<x<0.3。
此后， 参照图 5 , 可以继续采用现有的前栅或者后栅工艺， 完成 MOSFET制造。 例如在源漏区 1S/1D上再次外延同质或者异质但是均为 高迁移率材料的提升源漏区 5 , 在 G e S n源漏区 1 S / 1 D / 5上形成金属硅化 物或者金属锗化物的源漏金属化接触层 6 , 以进一步减小源漏接触电 阻。 在整个器件上沉积低 k材料的层间介质层（ILD ) 7。 刻蚀 ILD7形成 源漏接触孔， 直至暴露源漏金属化接触层 6, 在接触孔中沉积\ 、 Cu、 Al、 Mo等金属以及 TiN、 TaN等金属氮化物而形成源漏接触塞 8。 值得 注意的是， 虽然图 5所示结构中栅极堆叠结构为前栅工艺中平行层叠的 栅极绝缘层 2A与栅极导电层 2B, 但是也可以适用于后栅工艺， 也即栅 极绝缘层 2 A在栅极沟槽中包围栅极导电层 2B的底面以及侧面（图 5中未 示出） 。
由此， 依照本发明第一实施例的半导体器件包括衬底、 衬底上的 栅极堆叠结构、 栅极堆叠结构两侧衬底中的源漏区、 衬底中源漏区之 间的沟道区， 其特征在于源漏区中的源区包括 GeSn合金， 并且源区的 GeSn合金与沟道区之间可选地还包括隧穿介质层。 此外， 沟道区包括 Si或者 SiGe。
依照本发明的半导体器件及其制造方法， 通过注入前驱物然后激 光快速退火， 形成了具有窄带隙的 GeSn合金， 有效提高了 TFET的开态 电流， 在高性能低功耗应用中具有重要应用前景。
尽管已参照一个或多个示例性实施例说明本发明， 本领域技术人 员可以知晓无需脱离本发明范围而对形成器件结构的方法做出各种合 适的改变和等价方式。 此外， 由所公开的教导可做出许多可能适于特 定情形或材料的修改而不脱离本发明范围。 因此， 本发明的目的不在 于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例， 而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实 施例。

Claims

权 利 要 求
1. 一种半导体器件， 包括衬底、 衬底上的栅极堆叠结构、 栅极堆 叠结构两侧衬底中的源漏区、 衬底中源漏区之间的沟道区， 其特征在 于： 源漏区中的源区包括 GeSn合金， 并且源区的 GeSn合金与沟道区之 间可选地还包括隧穿介质层。
2. 如权利要求 1的半导体器件， 其中， 沟道区包括 Si和 /或 SiGe。
3. 如权利要求 1的半导体器件，其中，通过控制 Sn含量来调节 GeSn 合金的禁带宽度。
4. 如权利要求 3的半导体器件， 其中， GeSn合金中 Sn含量大于 0并 且小于 30 %。
5. 如权利要求 1的半导体器件， 其中， 可选地， 源漏区上还包括材 质相同的提升源漏区。
6. 如权利要求 1的半导体器件， 其中， 可选地， 隧穿介质层包括氧 化硅、 氮化硅、 氮氧化硅、 高 k材料及其组合。
7. 如权利要求 1的半导体器件， 其中， 源漏区上还包括金属化源漏 接触层。
8. 如权利要求 1的半导体器件， 其中， 源区与漏区导电类型不同， 沟道区为本征未掺杂的。
9. 一种半导体器件制造方法， 包括：
在衬底上形成栅极堆叠结构；
在栅极堆叠结构一侧的衬底中形成漏区；
在栅极堆叠结构另一侧的衬底中形成 GeSn材质的源区。
10. 如权利要求 9的半导体器件制造方法， 其中， 通过控制 Sn含量 来调节 GeSn合金的禁带宽度。
1 1. 如权利要求 10的半导体器件制造方法， 其中， GeSn合金中 Sn 含量大于 0并且小于 30 %。
12. 如权利要求 9的半导体器件制造方法， 其中， 形成 GeSn材盾的 源区的方法包括： 刻蚀源区的衬底， 选择性外延生长、 淀积 GeSn合金。
13. 如权利要求 9的半导体器件制造方法， 其中， 形成 GeSn材质的 源区的方法包括： 在栅极堆叠结构另一侧的衬底中注入前驱物； 激光 快速退火， 使得前驱物反应形成 GeSn合金， 构成源区。
14. 如权利要求 13的半导体器件制造方法， 其中， 注入前驱物的步 骤进一步包括：
执行非晶化离子注入， 在衬底中形成非晶化区；
在非晶化区中注入 Sn。
15. 如权利要求 14的半导体器件制造方法， 其中， 非晶化离子注入 的离子包括 Ge、 B、 Ga、 In及其组合。
16. 如权利要求 14的半导体器件制造方法， 其中， Sn的注入剂量为 1 X 1015 ~ 1 X 1017cm-2。
17. 如权利要求 13的半导体器件制造方法， 其中， 在注入前驱物之 后、 在激光快速退火之前， 在前驱物上形成保护层。
18. 如权利要求 13的半导体器件制造方法， 其中， 激光快速退火工 艺中激光单脉冲时间 Ins ~ lus , 脉冲个数为 1 ~ 100， 能量密度为 lOOmJ/cm2 ~ lJ/cm2。
19. 如权利要求 9的半导体器件制造方法， 其中， 可选地在源区与 沟道之间还形成隧穿介质层， 其形成步骤具体包括： 刻蚀栅极堆叠结 构另一侧的衬底形成源极沟槽， 在源极沟槽中沉积隧穿介质薄膜， 在 隧穿介质层薄膜上形成 GeSn合金而构成源区。
PCT/CN2012/001377 2012-08-16 2012-10-12 半导体器件及其制造方法 Ceased WO2014026306A1 (zh)

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