WO2014015624A1 - Substrat de réseau à plat, capteur et procédé de fabrication d'un substrat de réseau à plat - Google Patents

Substrat de réseau à plat, capteur et procédé de fabrication d'un substrat de réseau à plat Download PDF

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Publication number
WO2014015624A1
WO2014015624A1 PCT/CN2012/086500 CN2012086500W WO2014015624A1 WO 2014015624 A1 WO2014015624 A1 WO 2014015624A1 CN 2012086500 W CN2012086500 W CN 2012086500W WO 2014015624 A1 WO2014015624 A1 WO 2014015624A1
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WO
WIPO (PCT)
Prior art keywords
layer
substrate
gate
transparent conductive
gate insulating
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Application number
PCT/CN2012/086500
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English (en)
Chinese (zh)
Inventor
徐少颖
谢振宇
陈旭
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北京京东方光电科技有限公司
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Publication of WO2014015624A1 publication Critical patent/WO2014015624A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • Embodiments of the present invention relate to thin film field effect transistor (TFT) fabrication techniques and sensor fabrication techniques, and more particularly to a method of fabricating a planar array substrate, a sensor, and a planar array substrate.
  • TFT thin film field effect transistor
  • TFT flat panel X-ray sensors have broad application prospects in the medical market.
  • the manufacturing process of an amorphous silicon TFT flat panel X-ray sensor usually requires about 10 mask processes, and the process of the TFT array generally includes 4 to 6 mask processes.
  • a method for manufacturing an amorphous silicon TFT panel X-ray sensor includes the following steps:
  • Step 1 as shown in FIG. 1, in the first masking process, a gate and gate scan line 11 is formed on the substrate 10;
  • Step 2 as shown in FIG. 2, in the second mask process, a gate insulating layer 12 is formed on the substrate 10 and the formed gate and gate scan lines 11, and then over the gate insulating layer 12 and a corresponding region, forming an active layer 13;
  • Step 3 as shown in FIG. 3, in the third masking process, the gate of the peripheral region of the substrate 10 and the gate insulating layer 12 on the gate scan line 11 are peeled off to expose the gate of the peripheral region of the substrate 10 and Gate scan line 11;
  • Step 4 as shown in FIG. 4, in the fourth masking process, the source/drain electrode layer is formed over the active layer 13, including the source 14 and the drain 15; forming a common over the portion of the gate insulating layer 12. Electrode line 16;
  • Step 5 as shown in FIG. 5, in the fifth masking process, over the active layer 13, the source/drain electrode layer and the common electrode line 16, a passivation layer 17 covering substantially the entire substrate area is formed, the passivation Layer 17 has vias that expose a portion of common electrode line 16;
  • Step 6 as shown in FIG. 6, in the sixth mask process, an indium tin oxide (ITO) mask process, forming an ITO conductive layer 18 over the exposed common electrode line 16 and a portion of the passivation layer 17;
  • ITO indium tin oxide
  • Step 7 as shown in FIG. 7, in the seventh mask process, the first ITO insulating mask is performed. a process of forming an ITO insulating layer 19 over the passivation layer 17 and the ITO conductive layer 18; and forming a via hole exposing a portion of the source electrode 14;
  • Step 8 as shown in Figure 8, in the eighth mask process, a second ITO mask process, on the ITO insulating layer 19 and the vias on the source 14 to form a second ITO conductive layer 20;
  • Step 9 as shown in FIG. 9, in the ninth masking process, in addition to the vias on the source 14, in the region above the ITO insulating layer 19 and above the second ITO conductive layer 20, forming a resin layer 21;
  • Step 10 as shown in FIG. 10, in the tenth masking process, a third ITO mask process is performed to form a third ITO conductive layer 22 to cover the via holes on the resin layer 21 and the source electrode 14.
  • a flat panel array substrate including:
  • a gate and a gate scan line located above the substrate
  • a gate insulating layer over the gate and gate scan lines, an active layer above the gate insulating layer and corresponding to the gate region, and a first transparent conductive layer above the active layer and over the gate insulating layer;
  • a drain and a data line above the active layer and corresponding to the gate region a source above the active layer and corresponding to the gate region and the first transparent conductive layer above the active layer, located above the gate insulating layer and corresponding a common electrode line of the non-gate region;
  • a second transparent conductive layer located above a portion of the passivation layer and above the common electrode line;
  • the resin layer is provided with a through hole penetrating the via hole of the passivation layer at a position corresponding to the source;
  • a third transparent conductive layer located above the resin layer and the via.
  • a method for fabricating a planar array substrate including: Forming a gate and a gate scan line on the substrate;
  • a third transparent conductive layer located above the resin layer and the via hole is formed on the substrate on which the resin layer is formed.
  • a common electrode line in the same layer as the source, the drain, and the data scan line is used as a storage capacitor plate, and a total of seven mask processes are performed to complete the sensor.
  • the manufacturing process of the flat panel array substrate can reduce the number of reticle used, increase the equipment throughput, and improve the product yield.
  • FIG. 1 is a schematic cross-sectional view of a substrate after a first masking process in the prior art
  • FIG. 2 is a schematic cross-sectional view of a substrate after a second masking process in the prior art
  • FIG. 3 is a schematic cross-sectional view of a substrate after a third masking process in the prior art
  • FIG. 4 is a schematic cross-sectional view of a substrate after a fourth masking process in the prior art
  • FIG. 5 is a schematic cross-sectional view of a substrate after a fifth mask process in the prior art
  • FIG. 6 is a schematic cross-sectional view of a substrate after a sixth masking process in the prior art
  • FIG. 7 is a schematic cross-sectional view of a substrate after a seventh mask process in the prior art
  • 8 is a schematic cross-sectional view of a substrate after an eighth masking process in the prior art
  • FIG. 9 is a schematic cross-sectional view of a substrate after a ninth masking process in the prior art.
  • Figure 10 is a schematic cross-sectional view showing a TFT flat panel X-ray sensor in the prior art
  • FIG. 11 is a schematic cross-sectional view of a flat panel array substrate according to an embodiment of the present invention.
  • FIG. 12 is a schematic cross-sectional view of a substrate after a first masking process according to an embodiment of the present invention
  • FIG. 13 is a cross-sectional view of a substrate after a second masking process according to an embodiment of the present invention
  • FIG. 15 is a schematic cross-sectional view of a substrate after a fourth masking process according to an embodiment of the present invention
  • FIG. 16 is a fifth embodiment of a method according to an embodiment of the present invention.
  • FIG. 17 is a schematic cross-sectional view of a substrate after a sixth masking process according to an embodiment of the present invention.
  • the senor may be an X-ray sensor or other type of sensor, such as a sensor that transmits by photoelectric conversion.
  • a sensor that transmits by photoelectric conversion may be formed identically.
  • the flat panel array substrate includes:
  • the passivation layer may include two portions The first portion 26 of the passivation layer is located above the active layer 13, the source 14, the drain and the data line 25, and the second portion 27 of the passivation layer is located above the first transparent conductive layer 24 corresponding to the non-gate region and the gate insulating layer 12 above;
  • the resin layer is provided with a through hole penetrating through the via hole of the passivation layer at a position corresponding to the source;
  • the resin layer may include two parts, located in the blunt a first portion 29 of the resin layer above the first portion 26 of the layer and above the source 14, a second portion 30 of the resin layer over the source 14, above the second transparent conductive layer 28 and above the second portion 27 of the passivation layer;
  • the third transparent conductive layer is located above the resin layer and the through hole; in one embodiment, the third transparent conductive layer 31 is located above the first portion 29 of the resin layer, above the second portion 30 of the resin layer, and above the via.
  • the present invention also provides a sensor comprising the above-described flat panel array substrate.
  • a method of fabricating the above described planar array substrate comprising the steps of:
  • Step 101 forming a gate and a gate scan line on the substrate
  • a gate metal film is deposited on the substrate 10, and a photoresist is spin-coated on the gate metal film, and a first mask process is performed, that is, a spin-on photoresist is processed by using a mask. Exposing and developing; then etching the substrate 10 to etch away the gate metal film on the substrate 10 except for the gate and gate scan lines 11; and then graying the remaining photoresist on the substrate 10. The photoresist on the substrate 10 where the gate and gate scan lines 11 are formed is removed. As shown in FIG. 12, after the photoresist is removed, the gate and gate scan lines 11 are formed on the substrate 10.
  • the material of the gate and gate scan lines 11 may be a single metal layer such as molybdenum, aluminum, tungsten, titanium, copper, or a composite metal layer composed of at least two of the above metals, and a gate.
  • the thickness of the gate scanning line 11 is, for example, 100 nm to 500 nm.
  • Step 102 forming a gate insulating layer, an active layer and a first transparent conductive layer on the substrate forming the gate and the gate scan line; Specifically, on the substrate 10 formed in step 101, a gate insulating layer film, an active layer film, an ohmic contact layer film, and a transparent conductive film are continuously deposited, and then a layer of photoresist is spin-coated on the uppermost film, and the first step is performed.
  • a secondary mask process that is, exposing and developing the spin-coated photoresist by using a mask; then etching the substrate 10 to etch away the upper surface of the gate insulating layer 12 of the substrate 10, except for forming the active layer 13, ohmic contact a thin film of the layer 23 and other regions outside the first transparent conductive layer 24; then, the remaining photoresist on the substrate 10 is ashed, and the active layer 13, the ohmic contact layer 23 and the first transparent conductive layer 24 are formed on the substrate 10. The photoresist is removed from the area. As shown in FIG.
  • a gate insulating layer 12, an active layer 13, an ohmic contact layer 23, and a first transparent conductive layer 24 are formed on the substrate 10 on which the gate and gate scan lines 11 are formed;
  • the gate insulating layer 12 is located above the gate and gate scan lines 11, the active layer 13 is located above the gate insulating layer 12 and corresponds to the gate region, and the ohmic contact layer 23 is located above the active layer 13; the first transparent conductive layer 24 is located Above the ohmic contact layer 23 and above the gate insulating layer 12. More specifically, the gate insulating layer 12 substantially covers the entire area of the substrate (including the gate and gate scan lines 11 and the exposed portions of the substrate 10 in FIG.
  • the active layer 13 is disposed on the gate of the gate insulating layer 12.
  • the ohmic contact layer 23 is disposed on the active layer 13 and has an opening to form a channel of the thin film transistor;
  • the first transparent conductive layer 24 is disposed on a portion of the surface of the ohmic contact layer 23 and Extending and cutting off the surface of the gate insulating layer 12, a portion of the gate insulating layer 12 is left to form the common electrode described below.
  • the ohmic contact layer 23 is optional, and the purpose thereof is to reduce the contact resistance between the active layer 13 and the source 14 and the drain 15. Therefore, in another embodiment, the ohmic contact layer can also be removed.
  • the material of the gate insulating layer 12 may be an insulating material such as silicon nitride or silicon oxide, and the thickness of the gate insulating layer 12 is, for example, 250 nm to 600 nm; the material of the active layer 13 is amorphous silicon.
  • the amorphous silicon also known as amorphous silicon, is a form of elemental silicon.
  • the amorphous silicon has a brown-black or gray-black microcrystal.
  • the silicon element in the amorphous silicon does not have a complete diamond unit cell, and the purity is not high.
  • the melting point, density, and hardness of the amorphous silicon are also significantly lower than that of the crystalline silicon;
  • the thickness of the active layer 13 is, for example, 30 nm to 300 nm;
  • the material of the ohmic contact layer 23 is phosphorus-doped amorphous silicon, and the thickness of the ohmic contact layer 23 is, for example, 30nm ⁇ 100nm;
  • the thickness of the first transparent conductive layer 24 is, for example, 30 nm to 120 nm; here, a non-metal film such as an active layer film and an ohmic contact layer film may be deposited by chemical deposition, and the deposited transparent conductive film may be amorphous or polycrystalline. of.
  • Step 103 forming a drain
  • a metal film is deposited on the substrate 10 formed in step 102, and then a layer of photoresist is spin-coated on the metal film, and a third mask process is performed, that is, spin coating by using a mask.
  • the photoresist is exposed and developed, and then the substrate 10 is etched to etch away the metal thin film on the substrate 10 except the drain and the data line 15, the source 14 and the common electrode line 16, and then on the substrate 10.
  • the photoresist is ashed to remove the photoresist on the substrate 10 where the drain and data lines 15, the source 14 and the common electrode line 16 are formed. As shown in FIG.
  • the drain and data lines 25, the source electrode 14, and the common electrode line 16 are formed on the substrate 10 on which the gate insulating layer 12, the active layer 13, and the first transparent conductive layer 24 are formed.
  • the drain and data lines 25 are located above the active layer 13 and corresponding to the gate region
  • the source 14 is located above the active layer 13 and corresponds to the gate region
  • the first transparent conductive layer 24 is also located above the active layer 13.
  • the common electrode line 16 is located above the gate insulating layer 12.
  • the drain and data lines 25 are disposed on the ohmic contact layer 23 on the left side of the opening of the contact layer 23; the source 14 is disposed on the ohmic contact layer 23 on the right side of the opening and extends to the first transparent conductive layer 24, at the downward extending portion of the conductive layer 24; the common electrode line 16 is disposed on the portion of the gate insulating layer 12 that is not covered by the first transparent conductive layer 24.
  • the drain and data lines 15, the source 14 and the common electrode line 16 are formed by depositing a metal thin film on the substrate 10, and performing one exposure, development, and etching simultaneously, thereby forming a drain.
  • the data line 15, the source 14 and the common electrode line 16 are made of the same material and thickness.
  • the material may be a single metal layer such as molybdenum, aluminum, tungsten, titanium or copper, or a composite metal layer composed of at least two of the above metals.
  • the thickness of the single metal layer or the composite metal layer is, for example, 100 nm to 500 nm.
  • Step 104 forming a passivation layer and a via hole in the passivation layer for exposing the source on the substrate on which the drain and the data line, the source, and the common electrode line are formed, the passivation layer covering the entire substrate Above the surface other than the common electrode line;
  • a passivation layer film is deposited on the substrate 10 formed in step 103, and then a photoresist is spin-coated on the passivation layer film, and a fourth mask process is performed, that is, a mask is used.
  • the spin-coated photoresist is subjected to exposure and development; then, the substrate 10 is etched, the substrate 10 is etched away, and a passivation film is formed other than the passivation layer, and then the photoresist on the substrate 10 is applied. Ashing, the photoresist on the substrate 10 forming the passivation layer region is removed. As shown in FIG.
  • passivation is formed on the substrate 10 on which the drain and data lines 15, the source 14 and the common electrode line 16 are formed.
  • a passivation layer comprising a first portion 26 and a second portion 27; wherein the first portion 26 of the passivation layer is over the active layer 12, the source 14, the drain and the data line 25, and the second portion 27 of the passivation layer is located
  • a via hole is disposed over the first transparent conductive layer 24 corresponding to the non-gate region and above the gate insulating layer 12 at a position corresponding to the source of the passivation layer; more specifically, the first portion 26 of the passivation layer is covered by the drain a drain and a data line 15, a source 14 and an opening of the active layer 23 for forming a thin film transistor channel; the second portion 27 of the passivation layer overlying the first transparent conductive layer 24 and the gate insulating layer 12, but The common electrode line 16 is covered.
  • the material of the passivation layer is commonly used silicon nitride or silicon oxide, and the thickness of the first portion 26 of the passivation layer and the second portion 27 of the passivation layer is, for example, 150 nm to 2500 nm.
  • Step 105 forming a second transparent conductive layer above the part of the passivation layer and above the common electrode line on the substrate forming the passivation layer and the via hole;
  • a transparent conductive film is deposited on the substrate 10 formed in step 104, and then a layer of photoresist is spin-coated on the transparent conductive film, and a fifth mask process is performed, that is, using a mask to rotate
  • the coated photoresist is exposed and developed; then, the substrate 10 is etched, the transparent conductive film on the substrate 10 is removed, except for the transparent conductive layer, and then the photoresist on the substrate 10 is ashed.
  • the photoresist on the substrate 10 where the transparent conductive layer region is formed is removed. As shown in FIG.
  • a second transparent conductive layer 28 is formed on the substrate 10 on which the passivation layer and the via are formed; wherein the second transparent conductive layer 28 is located in the second portion of the passivation layer of the substrate 10. Above 27 and above the common electrode line 16. More specifically, the second transparent conductive layer 28 is flat and covers the common electrode line 16 and the second portion 27 of the passivation layer adjacent thereto.
  • the material of the second transparent conductive layer 28 is a transparent conductive material such as ITO, ruthenium or iridium, and the thickness of the second transparent conductive layer 28 is, for example, 30 nm to 120 nm.
  • Step 106 on the substrate forming the second transparent conductive layer, forming a resin layer covering the entire substrate, the resin layer is provided with a through hole penetrating the via hole of the passivation layer at a position corresponding to the source ;
  • a resin film is further deposited on the substrate 10 formed in step 105, and then a photoresist is spin-coated on the resin film, and a sixth mask process is performed, that is, spin coating by using a mask.
  • the photoresist is exposed and developed; then, the substrate 10 is etched, the resin film is removed from the substrate 10 except for the resin layer, and then the photoresist on the substrate 10 is ashed, and the substrate 10 is etched.
  • the photoresist forming the resin layer region is removed.
  • a resin layer is formed on the substrate 10 on which the second transparent conductive layer 28 is formed, and the resin layer has a through hole communicating with the via hole of the passivation layer, that is, the through hole penetrates the passivation layer and the resin layer.
  • the resin layer is divided into two portions by a via hole: a first portion 29 is above the first portion 26 of the passivation layer and above the source 14, and a second portion 30 of the resin layer is above the source 14, above the second transparent conductive layer 28, and passivated. Above the second portion 27 of the layer.
  • the resin layer may be a photosensitive resin layer or a non-photosensitive resin layer, and the thickness of the resin layer first portion 29 and the resin layer second portion 30 is, for example, 1 ⁇ m to 4 ⁇ m.
  • Step 107 forming a third transparent conductive layer over the resin layer and the via hole on the substrate on which the resin layer is formed;
  • a transparent conductive film is deposited on the substrate 10 of the first portion 29 of the resin layer and the second portion 30 of the resin layer in step 106, and then a layer of photoresist is spin-coated on the transparent conductive film.
  • Seven mask processes that is, exposing and developing the spin-coated photoresist by using a mask; then etching the substrate 10 to etch away the film above the substrate 10 except for the third transparent conductive layer, and then The photoresist on the substrate 10 is ashed, and the photoresist on the substrate 10 forming the third transparent conductive layer region is removed. As shown in FIG.
  • a third transparent conductive layer 31 is formed on the substrate 10 on which the resin layer is formed; wherein the third transparent conductive layer 31 covers the first portion 29 of the resin layer and the second portion of the resin layer. Above 30 and above the via. More specifically, the third transparent conductive layer 31 covers the first portion 29 of the resin layer, the second portion 30 of the resin layer, the inner wall of the via, and the exposed surface of the source in the via.
  • the material of the third transparent conductive layer 31 is a transparent conductive material such as ⁇ , ⁇ , ⁇ , and the thickness of the third transparent conductive layer 31 is, for example, 30 nm to 120 nm.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un substrat de réseau à plat, consistant à : former une ligne de grille et de balayage de grille (1) sur un substrat (10) ; former une couche d'isolation de grille (12), une couche active (13) et une première couche conductrice transparente (24) sur le substrat (10) sur lequel a été formée la ligne de grille et de balayage de grille (1) ; former une ligne de drain et de données (25), une source (14) et une ligne d'électrode commune (16) sur le substrat (10) sur lequel ont été formées la couche d'isolation de grille (12), la couche active (13) et la première couche conductrice transparente (24) ; former des couches de passivation (26) (27) et un trou d'interconnexion sur le substrat (10) sur lequel ont été formées la ligne de drain et de données (25), la source (14) et la ligne d'électrode commune (16) ; former, sur le substrat (10) sur lequel ont été formés les couches de passivation et le trou d'interconnexion, une deuxième couche conductrice transparente (28) dont une partie est située sur les couches de passivation et la ligne d'électrode commune (16) ; former des couches de résine (29) et (30) sur le substrat (10) sur lequel a été formée la deuxième couche conductrice transparente (28) ; et former une troisième couche conductrice transparente (31) sur le substrat (10) sur lequel ont été formées les couches de résine. L'invention concerne en outre un substrat de réseau à plat et un capteur. Les solutions techniques apportées par la présente invention permettent de réduire le nombre de masques utilisés et d'augmenter la productivité des dispositifs.
PCT/CN2012/086500 2012-07-27 2012-12-13 Substrat de réseau à plat, capteur et procédé de fabrication d'un substrat de réseau à plat WO2014015624A1 (fr)

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CN201210265470.1A CN103579219B (zh) 2012-07-27 2012-07-27 一种平板阵列基板、传感器及平板阵列基板的制造方法
CN201210265470.1 2012-07-27

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CN103887235B (zh) * 2014-03-10 2016-06-29 京东方科技集团股份有限公司 一种阵列基板及其制造方法、显示装置
CN103928400A (zh) * 2014-03-31 2014-07-16 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN104617102B (zh) * 2014-12-31 2017-11-03 深圳市华星光电技术有限公司 阵列基板及阵列基板制造方法
CN105093256B (zh) 2015-06-29 2017-12-01 京东方科技集团股份有限公司 一种射线检测基板及其制造方法和射线探测器
CN105448936B (zh) * 2016-01-04 2019-07-23 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN107564922B (zh) 2017-09-19 2020-03-13 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN111223879B (zh) * 2020-02-28 2022-10-18 京东方科技集团股份有限公司 一种显示基板及其制造方法、显示装置

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