WO2014015624A1 - Flatbed array substrate, sensor, and method for manufacturing flatbed array substrate - Google Patents

Flatbed array substrate, sensor, and method for manufacturing flatbed array substrate Download PDF

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Publication number
WO2014015624A1
WO2014015624A1 PCT/CN2012/086500 CN2012086500W WO2014015624A1 WO 2014015624 A1 WO2014015624 A1 WO 2014015624A1 CN 2012086500 W CN2012086500 W CN 2012086500W WO 2014015624 A1 WO2014015624 A1 WO 2014015624A1
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WIPO (PCT)
Prior art keywords
layer
substrate
gate
transparent conductive
gate insulating
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PCT/CN2012/086500
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French (fr)
Chinese (zh)
Inventor
徐少颖
谢振宇
陈旭
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北京京东方光电科技有限公司
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Publication of WO2014015624A1 publication Critical patent/WO2014015624A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • Embodiments of the present invention relate to thin film field effect transistor (TFT) fabrication techniques and sensor fabrication techniques, and more particularly to a method of fabricating a planar array substrate, a sensor, and a planar array substrate.
  • TFT thin film field effect transistor
  • TFT flat panel X-ray sensors have broad application prospects in the medical market.
  • the manufacturing process of an amorphous silicon TFT flat panel X-ray sensor usually requires about 10 mask processes, and the process of the TFT array generally includes 4 to 6 mask processes.
  • a method for manufacturing an amorphous silicon TFT panel X-ray sensor includes the following steps:
  • Step 1 as shown in FIG. 1, in the first masking process, a gate and gate scan line 11 is formed on the substrate 10;
  • Step 2 as shown in FIG. 2, in the second mask process, a gate insulating layer 12 is formed on the substrate 10 and the formed gate and gate scan lines 11, and then over the gate insulating layer 12 and a corresponding region, forming an active layer 13;
  • Step 3 as shown in FIG. 3, in the third masking process, the gate of the peripheral region of the substrate 10 and the gate insulating layer 12 on the gate scan line 11 are peeled off to expose the gate of the peripheral region of the substrate 10 and Gate scan line 11;
  • Step 4 as shown in FIG. 4, in the fourth masking process, the source/drain electrode layer is formed over the active layer 13, including the source 14 and the drain 15; forming a common over the portion of the gate insulating layer 12. Electrode line 16;
  • Step 5 as shown in FIG. 5, in the fifth masking process, over the active layer 13, the source/drain electrode layer and the common electrode line 16, a passivation layer 17 covering substantially the entire substrate area is formed, the passivation Layer 17 has vias that expose a portion of common electrode line 16;
  • Step 6 as shown in FIG. 6, in the sixth mask process, an indium tin oxide (ITO) mask process, forming an ITO conductive layer 18 over the exposed common electrode line 16 and a portion of the passivation layer 17;
  • ITO indium tin oxide
  • Step 7 as shown in FIG. 7, in the seventh mask process, the first ITO insulating mask is performed. a process of forming an ITO insulating layer 19 over the passivation layer 17 and the ITO conductive layer 18; and forming a via hole exposing a portion of the source electrode 14;
  • Step 8 as shown in Figure 8, in the eighth mask process, a second ITO mask process, on the ITO insulating layer 19 and the vias on the source 14 to form a second ITO conductive layer 20;
  • Step 9 as shown in FIG. 9, in the ninth masking process, in addition to the vias on the source 14, in the region above the ITO insulating layer 19 and above the second ITO conductive layer 20, forming a resin layer 21;
  • Step 10 as shown in FIG. 10, in the tenth masking process, a third ITO mask process is performed to form a third ITO conductive layer 22 to cover the via holes on the resin layer 21 and the source electrode 14.
  • a flat panel array substrate including:
  • a gate and a gate scan line located above the substrate
  • a gate insulating layer over the gate and gate scan lines, an active layer above the gate insulating layer and corresponding to the gate region, and a first transparent conductive layer above the active layer and over the gate insulating layer;
  • a drain and a data line above the active layer and corresponding to the gate region a source above the active layer and corresponding to the gate region and the first transparent conductive layer above the active layer, located above the gate insulating layer and corresponding a common electrode line of the non-gate region;
  • a second transparent conductive layer located above a portion of the passivation layer and above the common electrode line;
  • the resin layer is provided with a through hole penetrating the via hole of the passivation layer at a position corresponding to the source;
  • a third transparent conductive layer located above the resin layer and the via.
  • a method for fabricating a planar array substrate including: Forming a gate and a gate scan line on the substrate;
  • a third transparent conductive layer located above the resin layer and the via hole is formed on the substrate on which the resin layer is formed.
  • a common electrode line in the same layer as the source, the drain, and the data scan line is used as a storage capacitor plate, and a total of seven mask processes are performed to complete the sensor.
  • the manufacturing process of the flat panel array substrate can reduce the number of reticle used, increase the equipment throughput, and improve the product yield.
  • FIG. 1 is a schematic cross-sectional view of a substrate after a first masking process in the prior art
  • FIG. 2 is a schematic cross-sectional view of a substrate after a second masking process in the prior art
  • FIG. 3 is a schematic cross-sectional view of a substrate after a third masking process in the prior art
  • FIG. 4 is a schematic cross-sectional view of a substrate after a fourth masking process in the prior art
  • FIG. 5 is a schematic cross-sectional view of a substrate after a fifth mask process in the prior art
  • FIG. 6 is a schematic cross-sectional view of a substrate after a sixth masking process in the prior art
  • FIG. 7 is a schematic cross-sectional view of a substrate after a seventh mask process in the prior art
  • 8 is a schematic cross-sectional view of a substrate after an eighth masking process in the prior art
  • FIG. 9 is a schematic cross-sectional view of a substrate after a ninth masking process in the prior art.
  • Figure 10 is a schematic cross-sectional view showing a TFT flat panel X-ray sensor in the prior art
  • FIG. 11 is a schematic cross-sectional view of a flat panel array substrate according to an embodiment of the present invention.
  • FIG. 12 is a schematic cross-sectional view of a substrate after a first masking process according to an embodiment of the present invention
  • FIG. 13 is a cross-sectional view of a substrate after a second masking process according to an embodiment of the present invention
  • FIG. 15 is a schematic cross-sectional view of a substrate after a fourth masking process according to an embodiment of the present invention
  • FIG. 16 is a fifth embodiment of a method according to an embodiment of the present invention.
  • FIG. 17 is a schematic cross-sectional view of a substrate after a sixth masking process according to an embodiment of the present invention.
  • the senor may be an X-ray sensor or other type of sensor, such as a sensor that transmits by photoelectric conversion.
  • a sensor that transmits by photoelectric conversion may be formed identically.
  • the flat panel array substrate includes:
  • the passivation layer may include two portions The first portion 26 of the passivation layer is located above the active layer 13, the source 14, the drain and the data line 25, and the second portion 27 of the passivation layer is located above the first transparent conductive layer 24 corresponding to the non-gate region and the gate insulating layer 12 above;
  • the resin layer is provided with a through hole penetrating through the via hole of the passivation layer at a position corresponding to the source;
  • the resin layer may include two parts, located in the blunt a first portion 29 of the resin layer above the first portion 26 of the layer and above the source 14, a second portion 30 of the resin layer over the source 14, above the second transparent conductive layer 28 and above the second portion 27 of the passivation layer;
  • the third transparent conductive layer is located above the resin layer and the through hole; in one embodiment, the third transparent conductive layer 31 is located above the first portion 29 of the resin layer, above the second portion 30 of the resin layer, and above the via.
  • the present invention also provides a sensor comprising the above-described flat panel array substrate.
  • a method of fabricating the above described planar array substrate comprising the steps of:
  • Step 101 forming a gate and a gate scan line on the substrate
  • a gate metal film is deposited on the substrate 10, and a photoresist is spin-coated on the gate metal film, and a first mask process is performed, that is, a spin-on photoresist is processed by using a mask. Exposing and developing; then etching the substrate 10 to etch away the gate metal film on the substrate 10 except for the gate and gate scan lines 11; and then graying the remaining photoresist on the substrate 10. The photoresist on the substrate 10 where the gate and gate scan lines 11 are formed is removed. As shown in FIG. 12, after the photoresist is removed, the gate and gate scan lines 11 are formed on the substrate 10.
  • the material of the gate and gate scan lines 11 may be a single metal layer such as molybdenum, aluminum, tungsten, titanium, copper, or a composite metal layer composed of at least two of the above metals, and a gate.
  • the thickness of the gate scanning line 11 is, for example, 100 nm to 500 nm.
  • Step 102 forming a gate insulating layer, an active layer and a first transparent conductive layer on the substrate forming the gate and the gate scan line; Specifically, on the substrate 10 formed in step 101, a gate insulating layer film, an active layer film, an ohmic contact layer film, and a transparent conductive film are continuously deposited, and then a layer of photoresist is spin-coated on the uppermost film, and the first step is performed.
  • a secondary mask process that is, exposing and developing the spin-coated photoresist by using a mask; then etching the substrate 10 to etch away the upper surface of the gate insulating layer 12 of the substrate 10, except for forming the active layer 13, ohmic contact a thin film of the layer 23 and other regions outside the first transparent conductive layer 24; then, the remaining photoresist on the substrate 10 is ashed, and the active layer 13, the ohmic contact layer 23 and the first transparent conductive layer 24 are formed on the substrate 10. The photoresist is removed from the area. As shown in FIG.
  • a gate insulating layer 12, an active layer 13, an ohmic contact layer 23, and a first transparent conductive layer 24 are formed on the substrate 10 on which the gate and gate scan lines 11 are formed;
  • the gate insulating layer 12 is located above the gate and gate scan lines 11, the active layer 13 is located above the gate insulating layer 12 and corresponds to the gate region, and the ohmic contact layer 23 is located above the active layer 13; the first transparent conductive layer 24 is located Above the ohmic contact layer 23 and above the gate insulating layer 12. More specifically, the gate insulating layer 12 substantially covers the entire area of the substrate (including the gate and gate scan lines 11 and the exposed portions of the substrate 10 in FIG.
  • the active layer 13 is disposed on the gate of the gate insulating layer 12.
  • the ohmic contact layer 23 is disposed on the active layer 13 and has an opening to form a channel of the thin film transistor;
  • the first transparent conductive layer 24 is disposed on a portion of the surface of the ohmic contact layer 23 and Extending and cutting off the surface of the gate insulating layer 12, a portion of the gate insulating layer 12 is left to form the common electrode described below.
  • the ohmic contact layer 23 is optional, and the purpose thereof is to reduce the contact resistance between the active layer 13 and the source 14 and the drain 15. Therefore, in another embodiment, the ohmic contact layer can also be removed.
  • the material of the gate insulating layer 12 may be an insulating material such as silicon nitride or silicon oxide, and the thickness of the gate insulating layer 12 is, for example, 250 nm to 600 nm; the material of the active layer 13 is amorphous silicon.
  • the amorphous silicon also known as amorphous silicon, is a form of elemental silicon.
  • the amorphous silicon has a brown-black or gray-black microcrystal.
  • the silicon element in the amorphous silicon does not have a complete diamond unit cell, and the purity is not high.
  • the melting point, density, and hardness of the amorphous silicon are also significantly lower than that of the crystalline silicon;
  • the thickness of the active layer 13 is, for example, 30 nm to 300 nm;
  • the material of the ohmic contact layer 23 is phosphorus-doped amorphous silicon, and the thickness of the ohmic contact layer 23 is, for example, 30nm ⁇ 100nm;
  • the thickness of the first transparent conductive layer 24 is, for example, 30 nm to 120 nm; here, a non-metal film such as an active layer film and an ohmic contact layer film may be deposited by chemical deposition, and the deposited transparent conductive film may be amorphous or polycrystalline. of.
  • Step 103 forming a drain
  • a metal film is deposited on the substrate 10 formed in step 102, and then a layer of photoresist is spin-coated on the metal film, and a third mask process is performed, that is, spin coating by using a mask.
  • the photoresist is exposed and developed, and then the substrate 10 is etched to etch away the metal thin film on the substrate 10 except the drain and the data line 15, the source 14 and the common electrode line 16, and then on the substrate 10.
  • the photoresist is ashed to remove the photoresist on the substrate 10 where the drain and data lines 15, the source 14 and the common electrode line 16 are formed. As shown in FIG.
  • the drain and data lines 25, the source electrode 14, and the common electrode line 16 are formed on the substrate 10 on which the gate insulating layer 12, the active layer 13, and the first transparent conductive layer 24 are formed.
  • the drain and data lines 25 are located above the active layer 13 and corresponding to the gate region
  • the source 14 is located above the active layer 13 and corresponds to the gate region
  • the first transparent conductive layer 24 is also located above the active layer 13.
  • the common electrode line 16 is located above the gate insulating layer 12.
  • the drain and data lines 25 are disposed on the ohmic contact layer 23 on the left side of the opening of the contact layer 23; the source 14 is disposed on the ohmic contact layer 23 on the right side of the opening and extends to the first transparent conductive layer 24, at the downward extending portion of the conductive layer 24; the common electrode line 16 is disposed on the portion of the gate insulating layer 12 that is not covered by the first transparent conductive layer 24.
  • the drain and data lines 15, the source 14 and the common electrode line 16 are formed by depositing a metal thin film on the substrate 10, and performing one exposure, development, and etching simultaneously, thereby forming a drain.
  • the data line 15, the source 14 and the common electrode line 16 are made of the same material and thickness.
  • the material may be a single metal layer such as molybdenum, aluminum, tungsten, titanium or copper, or a composite metal layer composed of at least two of the above metals.
  • the thickness of the single metal layer or the composite metal layer is, for example, 100 nm to 500 nm.
  • Step 104 forming a passivation layer and a via hole in the passivation layer for exposing the source on the substrate on which the drain and the data line, the source, and the common electrode line are formed, the passivation layer covering the entire substrate Above the surface other than the common electrode line;
  • a passivation layer film is deposited on the substrate 10 formed in step 103, and then a photoresist is spin-coated on the passivation layer film, and a fourth mask process is performed, that is, a mask is used.
  • the spin-coated photoresist is subjected to exposure and development; then, the substrate 10 is etched, the substrate 10 is etched away, and a passivation film is formed other than the passivation layer, and then the photoresist on the substrate 10 is applied. Ashing, the photoresist on the substrate 10 forming the passivation layer region is removed. As shown in FIG.
  • passivation is formed on the substrate 10 on which the drain and data lines 15, the source 14 and the common electrode line 16 are formed.
  • a passivation layer comprising a first portion 26 and a second portion 27; wherein the first portion 26 of the passivation layer is over the active layer 12, the source 14, the drain and the data line 25, and the second portion 27 of the passivation layer is located
  • a via hole is disposed over the first transparent conductive layer 24 corresponding to the non-gate region and above the gate insulating layer 12 at a position corresponding to the source of the passivation layer; more specifically, the first portion 26 of the passivation layer is covered by the drain a drain and a data line 15, a source 14 and an opening of the active layer 23 for forming a thin film transistor channel; the second portion 27 of the passivation layer overlying the first transparent conductive layer 24 and the gate insulating layer 12, but The common electrode line 16 is covered.
  • the material of the passivation layer is commonly used silicon nitride or silicon oxide, and the thickness of the first portion 26 of the passivation layer and the second portion 27 of the passivation layer is, for example, 150 nm to 2500 nm.
  • Step 105 forming a second transparent conductive layer above the part of the passivation layer and above the common electrode line on the substrate forming the passivation layer and the via hole;
  • a transparent conductive film is deposited on the substrate 10 formed in step 104, and then a layer of photoresist is spin-coated on the transparent conductive film, and a fifth mask process is performed, that is, using a mask to rotate
  • the coated photoresist is exposed and developed; then, the substrate 10 is etched, the transparent conductive film on the substrate 10 is removed, except for the transparent conductive layer, and then the photoresist on the substrate 10 is ashed.
  • the photoresist on the substrate 10 where the transparent conductive layer region is formed is removed. As shown in FIG.
  • a second transparent conductive layer 28 is formed on the substrate 10 on which the passivation layer and the via are formed; wherein the second transparent conductive layer 28 is located in the second portion of the passivation layer of the substrate 10. Above 27 and above the common electrode line 16. More specifically, the second transparent conductive layer 28 is flat and covers the common electrode line 16 and the second portion 27 of the passivation layer adjacent thereto.
  • the material of the second transparent conductive layer 28 is a transparent conductive material such as ITO, ruthenium or iridium, and the thickness of the second transparent conductive layer 28 is, for example, 30 nm to 120 nm.
  • Step 106 on the substrate forming the second transparent conductive layer, forming a resin layer covering the entire substrate, the resin layer is provided with a through hole penetrating the via hole of the passivation layer at a position corresponding to the source ;
  • a resin film is further deposited on the substrate 10 formed in step 105, and then a photoresist is spin-coated on the resin film, and a sixth mask process is performed, that is, spin coating by using a mask.
  • the photoresist is exposed and developed; then, the substrate 10 is etched, the resin film is removed from the substrate 10 except for the resin layer, and then the photoresist on the substrate 10 is ashed, and the substrate 10 is etched.
  • the photoresist forming the resin layer region is removed.
  • a resin layer is formed on the substrate 10 on which the second transparent conductive layer 28 is formed, and the resin layer has a through hole communicating with the via hole of the passivation layer, that is, the through hole penetrates the passivation layer and the resin layer.
  • the resin layer is divided into two portions by a via hole: a first portion 29 is above the first portion 26 of the passivation layer and above the source 14, and a second portion 30 of the resin layer is above the source 14, above the second transparent conductive layer 28, and passivated. Above the second portion 27 of the layer.
  • the resin layer may be a photosensitive resin layer or a non-photosensitive resin layer, and the thickness of the resin layer first portion 29 and the resin layer second portion 30 is, for example, 1 ⁇ m to 4 ⁇ m.
  • Step 107 forming a third transparent conductive layer over the resin layer and the via hole on the substrate on which the resin layer is formed;
  • a transparent conductive film is deposited on the substrate 10 of the first portion 29 of the resin layer and the second portion 30 of the resin layer in step 106, and then a layer of photoresist is spin-coated on the transparent conductive film.
  • Seven mask processes that is, exposing and developing the spin-coated photoresist by using a mask; then etching the substrate 10 to etch away the film above the substrate 10 except for the third transparent conductive layer, and then The photoresist on the substrate 10 is ashed, and the photoresist on the substrate 10 forming the third transparent conductive layer region is removed. As shown in FIG.
  • a third transparent conductive layer 31 is formed on the substrate 10 on which the resin layer is formed; wherein the third transparent conductive layer 31 covers the first portion 29 of the resin layer and the second portion of the resin layer. Above 30 and above the via. More specifically, the third transparent conductive layer 31 covers the first portion 29 of the resin layer, the second portion 30 of the resin layer, the inner wall of the via, and the exposed surface of the source in the via.
  • the material of the third transparent conductive layer 31 is a transparent conductive material such as ⁇ , ⁇ , ⁇ , and the thickness of the third transparent conductive layer 31 is, for example, 30 nm to 120 nm.

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Abstract

A method for manufacturing a flatbed array substrate comprises: forming a gate and gate scan line (1) on a substrate (10); forming a gate insulating layer (12), an active layer (13), and a first transparent conducting layer (24) on the substrate (10) formed with the gate and gate scan line (1); forming a drain and data line (25), a source (14), and a common electrode line (16) on the substrate (10) formed with the gate insulating layer (12), the active layer (13), and the first transparent conducting layer (24); forming passivation layers (26) and (27) and a via hole on the substrate (10) formed with the drain and data line (25), the source (14), and the common electrode line (16); forming, on the substrate (10) formed with the passivation layers and the via hole, a second transparent conducting layer (28) with a part located on the passivation layers and the common electrode line (16); forming resin layers (29) and (30) on the substrate (10) formed with the second transparent conducting layer (28); and forming a third transparent conducting layer (31) on the substrate (10) formed with the resin layers. Further provided are a flatbed array substrate and a sensor. The technical solutions of the present invention can reduce the number of used masks and increase the device productivity.

Description

平板阵列基板、 传感器及平板阵列基板的制造方法 技术领域  Method for manufacturing flat panel array substrate, sensor and flat panel array substrate
本发明的实施例涉及薄膜场效应晶体管 （TFT )制造技术和传感器制造 技术， 尤其涉及一种平板阵列基板、 传感器及平板阵列基板的制造方法。 背景技术  Embodiments of the present invention relate to thin film field effect transistor (TFT) fabrication techniques and sensor fabrication techniques, and more particularly to a method of fabricating a planar array substrate, a sensor, and a planar array substrate. Background technique
TFT平板 X射线传感器在医疗市场中具有很广泛的应用前景。但是目前， 非晶硅 TFT平板 X射线传感器的制造工艺， 通常需要 10次左右掩模工艺， TFT阵列的工艺过程一般包括 4至 6次掩模工艺。  TFT flat panel X-ray sensors have broad application prospects in the medical market. However, at present, the manufacturing process of an amorphous silicon TFT flat panel X-ray sensor usually requires about 10 mask processes, and the process of the TFT array generally includes 4 to 6 mask processes.
参照图 1至图 10, 在现有技术中， 非晶硅 TFT平板 X射线传感器的制 造方法包括如下步骤：  Referring to FIGS. 1 through 10, in the prior art, a method for manufacturing an amorphous silicon TFT panel X-ray sensor includes the following steps:
步骤 1 , 如图 1所示， 第一次掩模工艺中， 在基板 10上形成栅极及栅极 扫描线 11;  Step 1, as shown in FIG. 1, in the first masking process, a gate and gate scan line 11 is formed on the substrate 10;
步骤 2, 如图 2所示， 第二次掩模工艺中， 在基板 10和形成的栅极及栅 极扫描线 11上形成栅绝缘层 12,然后在所述栅绝缘层 12上方且与栅极相对 应的区域， 形成有源层 13;  Step 2, as shown in FIG. 2, in the second mask process, a gate insulating layer 12 is formed on the substrate 10 and the formed gate and gate scan lines 11, and then over the gate insulating layer 12 and a corresponding region, forming an active layer 13;
步骤 3, 如图 3所示， 第三次掩模工艺中， 将基板 10的周边区域的栅极 及栅极扫描线 11上的栅绝缘层 12剥离，露出基板 10的周边区域的栅极及栅 极扫描线 11;  Step 3, as shown in FIG. 3, in the third masking process, the gate of the peripheral region of the substrate 10 and the gate insulating layer 12 on the gate scan line 11 are peeled off to expose the gate of the peripheral region of the substrate 10 and Gate scan line 11;
步骤 4, 如图 4所示， 第四次掩模工艺中， 在有源层 13上方形成所述源 /漏电极层， 包括源极 14和漏极 15; 在部分栅绝缘层 12上方形成公共电极 线 16;  Step 4, as shown in FIG. 4, in the fourth masking process, the source/drain electrode layer is formed over the active layer 13, including the source 14 and the drain 15; forming a common over the portion of the gate insulating layer 12. Electrode line 16;
步骤 5, 如图 5所示， 第五次掩模工艺中， 在有源层 13、 源 /漏电极层和 公共电极线 16上方， 形成基本覆盖整个基板面积的钝化层 17, 该钝化层 17 具有使一部分公共电极线 16暴露的过孔；  Step 5, as shown in FIG. 5, in the fifth masking process, over the active layer 13, the source/drain electrode layer and the common electrode line 16, a passivation layer 17 covering substantially the entire substrate area is formed, the passivation Layer 17 has vias that expose a portion of common electrode line 16;
步骤 6, 如图 6所示， 在第六次掩模工艺中， 进行铟锡氧化物（ ITO )掩 模过程，在暴露的公共电极线 16和一部分钝化层 17上方形成 ITO导电层 18;  Step 6, as shown in FIG. 6, in the sixth mask process, an indium tin oxide (ITO) mask process, forming an ITO conductive layer 18 over the exposed common electrode line 16 and a portion of the passivation layer 17;
步骤 7, 如图 7所示， 在第七次掩模工艺中， 进行第一次 ITO绝缘掩膜 过程， 在钝化层 17和 ITO导电层 18上方形成 ITO绝缘层 19; 并形成使一 部分源极 14暴露的过孔； Step 7, as shown in FIG. 7, in the seventh mask process, the first ITO insulating mask is performed. a process of forming an ITO insulating layer 19 over the passivation layer 17 and the ITO conductive layer 18; and forming a via hole exposing a portion of the source electrode 14;
步骤 8, 如图 8所示， 在第八次掩模工艺中， 进行第二次 ITO掩膜过程， 在 ITO绝缘层 19和源极 14上的过孔上， 形成第二 ITO导电层 20;  Step 8, as shown in Figure 8, in the eighth mask process, a second ITO mask process, on the ITO insulating layer 19 and the vias on the source 14 to form a second ITO conductive layer 20;
步骤 9, 如图 9所示， 在第九次掩模工艺中， 除源极 14上的过孔以外， 在 ITO绝缘层 19上方及第二 ITO导电层 20上方的区域， 形成树脂层 21;  Step 9, as shown in FIG. 9, in the ninth masking process, in addition to the vias on the source 14, in the region above the ITO insulating layer 19 and above the second ITO conductive layer 20, forming a resin layer 21;
步骤 10, 如图 10所示， 在第十次掩模工艺中， 进行第三次 ITO掩膜过 程， 形成第三 ITO导电层 22以覆盖树脂层 21和源极 14上的过孔。  Step 10, as shown in FIG. 10, in the tenth masking process, a third ITO mask process is performed to form a third ITO conductive layer 22 to cover the via holes on the resin layer 21 and the source electrode 14.
因此， 目前非晶硅 TFT平板 X射线传感器通常需要 10次掩模工艺才能 完成， 制造过程十分复杂， 且成本较高。 发明内容  Therefore, the current amorphous silicon TFT panel X-ray sensor usually requires 10 mask processes to complete, and the manufacturing process is complicated and costly. Summary of the invention
因此， 本发明的目的在于提供一种平板阵列基板、 传感器及平板阵列基 板的制造方法， 能够降低使用的掩模版数量， 提高设备产能。  Accordingly, it is an object of the present invention to provide a method of manufacturing a flat panel array substrate, a sensor, and a flat panel array substrate, which can reduce the number of reticle used and increase the equipment throughput.
为达到上述目的， 本发明的技术方案是这样实现的：  In order to achieve the above object, the technical solution of the present invention is achieved as follows:
根据本发明的第一方面， 提供一种平板阵列基板， 包括：  According to a first aspect of the present invention, a flat panel array substrate is provided, including:
基板；  Substrate
位于基板上方的栅极及栅极扫描线；  a gate and a gate scan line located above the substrate;
位于栅极及栅极扫描线上方的栅绝缘层， 位于栅绝缘层上方且对应栅极 区域的有源层， 位于有源层上方和栅绝缘层上方的第一透明导电层；  a gate insulating layer over the gate and gate scan lines, an active layer above the gate insulating layer and corresponding to the gate region, and a first transparent conductive layer above the active layer and over the gate insulating layer;
位于有源层上方且对应栅极区域的漏极及数据线， 位于有源层上方且对 应栅极区域以及有源层上方的第一透明导电层上方的源极， 位于栅绝缘层上 方且对应非栅极区域的公共电极线；  a drain and a data line above the active layer and corresponding to the gate region, a source above the active layer and corresponding to the gate region and the first transparent conductive layer above the active layer, located above the gate insulating layer and corresponding a common electrode line of the non-gate region;
覆盖在整个基板上方除公共电极线外的表面上的钝化层， 所述钝化层中 设置有用以暴露出源极的过孔；  Covering a passivation layer on a surface of the entire substrate except the common electrode line, wherein the passivation layer is provided with a via hole for exposing the source;
位于一部分钝化层上方及公共电极线上方的第二透明导电层；  a second transparent conductive layer located above a portion of the passivation layer and above the common electrode line;
覆盖于整个基板上方的树脂层， 该树脂层在对应源极的位置上设置有与 钝化层的所述过孔相贯穿的通孔；  Covering a resin layer over the entire substrate, the resin layer is provided with a through hole penetrating the via hole of the passivation layer at a position corresponding to the source;
位于树脂层及通孔上方的第三透明导电层。  a third transparent conductive layer located above the resin layer and the via.
根据本发明的第二方面， 还提供一种平板阵列基板的制作方法， 包括： 在基板上形成栅极及栅极扫描线； According to a second aspect of the present invention, a method for fabricating a planar array substrate is provided, including: Forming a gate and a gate scan line on the substrate;
在形成栅极及栅极扫描线的基板上， 形成栅绝缘层、 有源层和第一透明 导电层；  Forming a gate insulating layer, an active layer, and a first transparent conductive layer on the substrate forming the gate and the gate scan line;
在形成栅绝缘层、 有源层和第一透明导电层的基板上， 形成漏极及数据 线、 源极、 公共电极线；  Forming a drain and a data line, a source, and a common electrode line on the substrate on which the gate insulating layer, the active layer, and the first transparent conductive layer are formed;
在形成漏极及数据线、 源极、 公共电极线的基板上， 形成钝化层及位于 钝化层中的用以暴露出源极的过孔， 该钝化层覆盖在整个基板上方除公共电 极线外的表面上；  Forming a passivation layer and a via hole in the passivation layer for exposing the source on the substrate on which the drain and the data line, the source, and the common electrode line are formed, the passivation layer covering the entire substrate except the common On the surface outside the electrode line;
在形成钝化层及过孔的基板上， 形成位于一部分钝化层上方及公共电极 线上方的第二透明导电层；  Forming a second transparent conductive layer over the portion of the passivation layer and over the common electrode line on the substrate on which the passivation layer and the via are formed;
在形成第二透明导电层的基板上， 形成覆盖于整个基板上方的树脂层， 该树脂层在对应源极的位置上设置有与钝化层的所述过孔相贯穿的通孔； 以 及  Forming a resin layer over the entire substrate on the substrate forming the second transparent conductive layer, the resin layer being provided with a through hole penetrating the via hole of the passivation layer at a position corresponding to the source;
在形成树脂层的基板上，形成位于树脂层及通孔上方的第三透明导电层。 本发明实施例提供的平板阵列基板的制造方法中， 将与源极、 漏极及数 据扫描线位于同层的公共电极线作为存储电容极板， 总共进行七次掩模工艺 即可完成传感器中平板阵列基板的制造工艺， 因此， 能够降低使用的掩模版 数量， 提高设备产能， 提高产品良品率。 附图说明  On the substrate on which the resin layer is formed, a third transparent conductive layer located above the resin layer and the via hole is formed. In the method for manufacturing a planar array substrate provided by the embodiment of the present invention, a common electrode line in the same layer as the source, the drain, and the data scan line is used as a storage capacitor plate, and a total of seven mask processes are performed to complete the sensor. The manufacturing process of the flat panel array substrate can reduce the number of reticle used, increase the equipment throughput, and improve the product yield. DRAWINGS
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。  In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, and are not intended to limit the present invention. .
图 1是现有技术中第一次掩模工艺后基板的截面示意图；  1 is a schematic cross-sectional view of a substrate after a first masking process in the prior art;
图 2是现有技术中第二次掩模工艺后基板的截面示意图；  2 is a schematic cross-sectional view of a substrate after a second masking process in the prior art;
图 3是现有技术中第三次掩模工艺后基板的截面示意图；  3 is a schematic cross-sectional view of a substrate after a third masking process in the prior art;
图 4是现有技术中第四次掩模工艺后基板的截面示意图；  4 is a schematic cross-sectional view of a substrate after a fourth masking process in the prior art;
图 5是现有技术中第五次掩模工艺后基板的截面示意图；  5 is a schematic cross-sectional view of a substrate after a fifth mask process in the prior art;
图 6是现有技术中第六次掩模工艺后基板的截面示意图；  6 is a schematic cross-sectional view of a substrate after a sixth masking process in the prior art;
图 7是现有技术中第七次掩模工艺后基板的截面示意图； 图 8是现有技术中第八次掩模工艺后基板的截面示意图； 7 is a schematic cross-sectional view of a substrate after a seventh mask process in the prior art; 8 is a schematic cross-sectional view of a substrate after an eighth masking process in the prior art;
图 9是现有技术中第九次掩模工艺后基板的截面示意图； 9 is a schematic cross-sectional view of a substrate after a ninth masking process in the prior art;
图 10是现有技术中 TFT平板 X射线传感器的截面示意图； Figure 10 is a schematic cross-sectional view showing a TFT flat panel X-ray sensor in the prior art;
图 11是本发明实施例中平板阵列基板的截面示意图； 11 is a schematic cross-sectional view of a flat panel array substrate according to an embodiment of the present invention;
图 12是根据本发明实施例的方法第一次掩模工艺后基板的截面示意图; 图 13是根据本发明实施例的方法第二次掩模工艺后基板的截面示意图; 图 14是根据本发明实施例的方法第三次掩模工艺后基板的截面示意图; 图 15是根据本发明实施例的方法第四次掩模工艺后基板的截面示意图; 图 16是根据本发明实施例的方法第五次掩模工艺后基板的截面示意图; 图 17是根据本发明实施例的方法第六次掩模工艺后基板的截面示意图。 附图标记说明： 12 is a schematic cross-sectional view of a substrate after a first masking process according to an embodiment of the present invention; FIG. 13 is a cross-sectional view of a substrate after a second masking process according to an embodiment of the present invention; FIG. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 15 is a schematic cross-sectional view of a substrate after a fourth masking process according to an embodiment of the present invention; FIG. 16 is a fifth embodiment of a method according to an embodiment of the present invention. FIG. 17 is a schematic cross-sectional view of a substrate after a sixth masking process according to an embodiment of the present invention. FIG. Description of the reference signs:
10 基板  10 substrate
11 栅极及栅极扫描:  11 gate and gate scan:
12 栅绝缘层  12 gate insulation
13 有源层  13 active layer
14 源极  14 source
15 漏极  15 drain
16 公共电极线  16 common electrode line
17 钝化层  17 passivation layer
18 第一 ITO导电层  18 first ITO conductive layer
19 ITO绝缘层  19 ITO insulation
20 第二 ITO导电层  20 second ITO conductive layer
21 树脂层  21 resin layer
22 第三 ITO导电层  22 third ITO conductive layer
23 欧姆接触层  23 ohm contact layer
24 第一透明导电层  24 first transparent conductive layer
25 漏极及数据线  25 drain and data lines
26 钝化层第一部分  26 Passivation layer first part
27 钝化层第二部分 28: 第二透明导电层 27 Passivation layer part two 28: second transparent conductive layer
29: 树脂层第一部分  29: The first part of the resin layer
30: 树脂层第二部分  30: The second part of the resin layer
31 : 第三透明导电层 具体实施方式  31: third transparent conductive layer
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。  The technical solutions of the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings of the embodiments of the present invention. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的术语 "连接" 并非限定于物理的或者机械的连接， 而是可 以包括电性的连接， 不管是直接的还是间接的。 "上方" 、 "上" 、 "下" 、 "左" 、 "右" 等仅用于表示相对位置关系， 当被描述对象的绝对位置改变 后， 则该相对位置关系也相应地改变。  Unless otherwise defined, technical terms or scientific terms used herein shall be of the ordinary meaning understood by those of ordinary skill in the art to which the invention pertains. The term "connected" as used in the specification and claims of the present invention is not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Top", "Up", "Bottom", "Left", "Right", etc. are only used to indicate the relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship is also changed accordingly.
在本发明以下实施例中， 传感器可以是 X射线传感器， 也可以是其他类 型的传感器， 例如通过光电转换进行传输的传感器。 在下面的描述和图示中 针对单个感测单元进行， 其他感测单元可以同样地形成。  In the following embodiments of the invention, the sensor may be an X-ray sensor or other type of sensor, such as a sensor that transmits by photoelectric conversion. In the following description and illustration, for a single sensing unit, other sensing units may be formed identically.
图 11是根据本发明一个实施例的平板阵列基板的截面示意图， 如图 11 所示， 该平板阵列基板包括：  11 is a schematic cross-sectional view of a flat panel array substrate according to an embodiment of the present invention. As shown in FIG. 11, the flat panel array substrate includes:
基板 10;  Substrate 10;
位于基板 10上方的栅极及栅极扫描线 11 ;  a gate and a gate scan line 11 above the substrate 10;
位于栅极及栅极扫描线 11上方的栅绝缘层 12,位于栅绝缘层 12上方且 对应栅极区域的有源层 13 , 位于有源层 13上方的欧姆接触层 23 , 位于欧姆 接触层 23上方和栅绝缘层 12上方的第一透明导电层 24;  a gate insulating layer 12 over the gate and gate scan lines 11 , an active layer 13 above the gate insulating layer 12 and corresponding to the gate region, and an ohmic contact layer 23 above the active layer 13 on the ohmic contact layer 23 a first transparent conductive layer 24 above and above the gate insulating layer 12;
位于有源层 13上方且对应栅极区域的漏极及数据线 25 , 位于有源层 13 上方且对应栅极区域以及有源层 13 上方的第一透明导电层 24 上方的源极 14, 位于栅绝缘层 12上方且对应非栅极区域的公共电极线 16; 覆盖在整个基板上方除公共电极线 16外的表面上的钝化层，所述钝化层 中设置有暴露出源极的过孔； 在一个实施例中， 该钝化层可包括两个部分， 钝化层第一部分 26位于有源层 13、 源极 14、 漏极及数据线 25上方，钝化层 第二部分 27位于对应非栅极区域的第一透明导电层 24上方及栅绝缘层 12 上方； a drain and a data line 25 located above the active layer 13 and corresponding to the gate region, located above the active layer 13 and corresponding to the gate region and the source 14 above the first transparent conductive layer 24 above the active layer 13 a common electrode line 16 above the gate insulating layer 12 and corresponding to the non-gate region; Covering a passivation layer on the surface of the entire substrate except the common electrode line 16 in which a via hole exposing the source is disposed; in one embodiment, the passivation layer may include two portions The first portion 26 of the passivation layer is located above the active layer 13, the source 14, the drain and the data line 25, and the second portion 27 of the passivation layer is located above the first transparent conductive layer 24 corresponding to the non-gate region and the gate insulating layer 12 above;
位于钝化层第二部分 27 上方及公共电极线 16 上方的第二透明导电层 a second transparent conductive layer over the second portion 27 of the passivation layer and over the common electrode line 16
28; 28;
覆盖于整个基板上方的树脂层， 该树脂层在对应源极的位置上设置有与 钝化层的过孔相贯穿的通孔； 在一个实施例中， 该树脂层可包括两部分， 位 于钝化层第一部分 26上方及源极 14上方的树脂层第一部分 29,位于源极 14 上方、 第二透明导电层 28上方及钝化层第二部分 27上方的树脂层第二部分 30;  Covering a resin layer over the entire substrate, the resin layer is provided with a through hole penetrating through the via hole of the passivation layer at a position corresponding to the source; in one embodiment, the resin layer may include two parts, located in the blunt a first portion 29 of the resin layer above the first portion 26 of the layer and above the source 14, a second portion 30 of the resin layer over the source 14, above the second transparent conductive layer 28 and above the second portion 27 of the passivation layer;
位于树脂层及通孔上方的第三透明导电层； 在一个实施例中， 所述第三 透明导电层 31位于树脂层第一部分 29上方、树脂层第二部分 30上方及通孔 上方。  The third transparent conductive layer is located above the resin layer and the through hole; in one embodiment, the third transparent conductive layer 31 is located above the first portion 29 of the resin layer, above the second portion 30 of the resin layer, and above the via.
本发明还提供一种传感器， 该传感器包括上述平板阵列基板。  The present invention also provides a sensor comprising the above-described flat panel array substrate.
根据本发明的另一个实施例， 提供一种制造上述平板阵列基板的方法， 该方法包括以下步骤：  In accordance with another embodiment of the present invention, a method of fabricating the above described planar array substrate is provided, the method comprising the steps of:
步骤 101 , 在基板上形成栅极及栅极扫描线；  Step 101, forming a gate and a gate scan line on the substrate;
具体的，在基板 10上沉积一层栅极金属薄膜，在该栅极金属薄膜上旋涂 一层光刻胶， 并进行第一次掩模工艺， 即利用掩模板对旋涂的光刻胶进行曝 光显影； 然后对基板 10进行刻蚀， 刻蚀掉基板 10上除形成栅极及栅极扫描 线 11外其他区域的栅极金属薄膜； 然后对基板 10上的剩余的光刻胶进行灰 化，将基板 10上形成栅极及栅极扫描线 11区域的光刻胶去除。如图 12所示， 去除光刻胶后， 在基板 10上形成栅极及栅极扫描线 11。  Specifically, a gate metal film is deposited on the substrate 10, and a photoresist is spin-coated on the gate metal film, and a first mask process is performed, that is, a spin-on photoresist is processed by using a mask. Exposing and developing; then etching the substrate 10 to etch away the gate metal film on the substrate 10 except for the gate and gate scan lines 11; and then graying the remaining photoresist on the substrate 10. The photoresist on the substrate 10 where the gate and gate scan lines 11 are formed is removed. As shown in FIG. 12, after the photoresist is removed, the gate and gate scan lines 11 are formed on the substrate 10.
本发明的实施例中，栅极及栅极扫描线 11的材料可以是诸如钼、铝、钨、 钛、 铜等单金属层， 也可以是至少两个上述金属组成的复合金属层， 栅极及 栅极扫描线 11的厚度例如为 100nm~500nm。  In the embodiment of the present invention, the material of the gate and gate scan lines 11 may be a single metal layer such as molybdenum, aluminum, tungsten, titanium, copper, or a composite metal layer composed of at least two of the above metals, and a gate. The thickness of the gate scanning line 11 is, for example, 100 nm to 500 nm.
步骤 102, 在形成栅极及栅极扫描线的基板上， 形成栅绝缘层、 有源层 和第一透明导电层； 具体的，在步骤 101形成的基板 10上， 连续沉积栅绝缘层薄膜、有源层 薄膜、 欧姆接触层薄膜和透明导电薄膜， 然后在最上层薄膜上旋涂一层光刻 胶， 并进行第二次掩模工艺， 即利用掩模板对旋涂的光刻胶进行曝光显影； 然后对基板 10进行刻蚀，刻蚀掉基板 10的栅绝缘层 12上方，除形成有源层 13、 欧姆接触层 23及第一透明导电层 24外其他区域的薄膜； 然后对基板 10 上剩余的光刻胶进行灰化， 将基板 10上形成有源层 13、 欧姆接触层 23和第 一透明导电层 24区域的光刻胶去除。 如图 13所示， 去除光刻胶后， 在形成 栅极及栅极扫描线 11的基板 10上形成栅绝缘层 12、有源层 13、欧姆接触层 23和第一透明导电层 24;其中，栅绝缘层 12位于栅极及栅极扫描线 11上方， 有源层 13位于栅绝缘层 12上方且对应栅极区域，欧姆接触层 23位于有源层 13上方； 第一透明导电层 24位于欧姆接触层 23上方及栅绝缘层 12上方。 更具体地，栅绝缘层 12基本覆盖了基板的整个区域（包括栅极及栅极扫描线 11和图 12中基板 10的暴露部分 )上； 有源层 13设置在栅绝缘层 12的与栅 极相对一侧的区域上； 欧姆接触层 23设置在有源层 13上且具有一个开口， 以形成薄膜晶体管的沟道， ； 第一透明导电层 24设置在欧姆接触层 23的一 部分表面上且延伸并截止在栅绝缘层 12的表面上， 留下一部分栅绝缘层 12 用以形成下面描述的公共电极。需要说明的是，上述欧姆接触层 23为可选的， 其目的是降低有源层 13与源极 14、 漏极 15之间的接触电阻的大小。 因此， 在另一个实施例中， 也可以去掉欧姆接触层。 Step 102, forming a gate insulating layer, an active layer and a first transparent conductive layer on the substrate forming the gate and the gate scan line; Specifically, on the substrate 10 formed in step 101, a gate insulating layer film, an active layer film, an ohmic contact layer film, and a transparent conductive film are continuously deposited, and then a layer of photoresist is spin-coated on the uppermost film, and the first step is performed. a secondary mask process, that is, exposing and developing the spin-coated photoresist by using a mask; then etching the substrate 10 to etch away the upper surface of the gate insulating layer 12 of the substrate 10, except for forming the active layer 13, ohmic contact a thin film of the layer 23 and other regions outside the first transparent conductive layer 24; then, the remaining photoresist on the substrate 10 is ashed, and the active layer 13, the ohmic contact layer 23 and the first transparent conductive layer 24 are formed on the substrate 10. The photoresist is removed from the area. As shown in FIG. 13, after the photoresist is removed, a gate insulating layer 12, an active layer 13, an ohmic contact layer 23, and a first transparent conductive layer 24 are formed on the substrate 10 on which the gate and gate scan lines 11 are formed; The gate insulating layer 12 is located above the gate and gate scan lines 11, the active layer 13 is located above the gate insulating layer 12 and corresponds to the gate region, and the ohmic contact layer 23 is located above the active layer 13; the first transparent conductive layer 24 is located Above the ohmic contact layer 23 and above the gate insulating layer 12. More specifically, the gate insulating layer 12 substantially covers the entire area of the substrate (including the gate and gate scan lines 11 and the exposed portions of the substrate 10 in FIG. 12); the active layer 13 is disposed on the gate of the gate insulating layer 12. On the opposite side of the region; the ohmic contact layer 23 is disposed on the active layer 13 and has an opening to form a channel of the thin film transistor; the first transparent conductive layer 24 is disposed on a portion of the surface of the ohmic contact layer 23 and Extending and cutting off the surface of the gate insulating layer 12, a portion of the gate insulating layer 12 is left to form the common electrode described below. It should be noted that the ohmic contact layer 23 is optional, and the purpose thereof is to reduce the contact resistance between the active layer 13 and the source 14 and the drain 15. Therefore, in another embodiment, the ohmic contact layer can also be removed.
本发明的实施例中，栅绝缘层 12的材料可以是例如氮化硅或氧化硅等的 绝缘材料，栅绝缘层 12的厚度例如为 250nm~600nm; 有源层 13的材料为非 晶硅， 该非晶硅又称无定形硅， 是单质硅的一种形态， 非晶硅具有棕黑色或 灰黑色的微晶体， 非晶硅中的硅元素不具有完整的金刚石晶胞， 纯度不高， 非晶硅的熔点、 密度和硬度也明显低于晶体硅； 有源层 13 的厚度例如为 30nm~300nm; 欧姆接触层 23的材料是掺磷非晶硅， 欧姆接触层 23的厚度 例如为 30nm~100nm; 第一透明导电层 24的材料为例如 ITO、 或氧化辞铟 ( ΙΖΟ, InxZnyOz ) 、 或氧化辞铝（ZAO, ZnxAlyOz )等透明导电材料， 第一 透明导电层 24的厚度例如为 30nm~120nm; 这里， 可以釆用化学沉积法沉积 有源层薄膜和欧姆接触层薄膜等非金属薄膜， 所沉积的透明导电薄膜可以是 非晶的或多晶的。 步骤 103 , 在形成栅绝缘层、 有源层和第一透明导电层的基板上， 形成 漏极及数据线、 源极、 公共电极线； In the embodiment of the present invention, the material of the gate insulating layer 12 may be an insulating material such as silicon nitride or silicon oxide, and the thickness of the gate insulating layer 12 is, for example, 250 nm to 600 nm; the material of the active layer 13 is amorphous silicon. The amorphous silicon, also known as amorphous silicon, is a form of elemental silicon. The amorphous silicon has a brown-black or gray-black microcrystal. The silicon element in the amorphous silicon does not have a complete diamond unit cell, and the purity is not high. The melting point, density, and hardness of the amorphous silicon are also significantly lower than that of the crystalline silicon; the thickness of the active layer 13 is, for example, 30 nm to 300 nm; the material of the ohmic contact layer 23 is phosphorus-doped amorphous silicon, and the thickness of the ohmic contact layer 23 is, for example, 30nm ~ 100nm; transparent conductive material of the first layer 24, for example, ITO, or indium oxide speech (ΙΖΟ, in x Zn y O z), speech, or aluminum oxide (ZAO, Zn x Al y O z) transparent conductive material, The thickness of the first transparent conductive layer 24 is, for example, 30 nm to 120 nm; here, a non-metal film such as an active layer film and an ohmic contact layer film may be deposited by chemical deposition, and the deposited transparent conductive film may be amorphous or polycrystalline. of. Step 103, forming a drain and a data line, a source, and a common electrode line on the substrate on which the gate insulating layer, the active layer, and the first transparent conductive layer are formed;
具体的，在步骤 102形成的基板 10上，再沉积一层金属薄膜， 然后在该 金属薄膜上旋涂一层光刻胶， 并进行第三次掩模工艺， 即利用掩模板对旋涂 的光刻胶进行曝光显影， 然后对基板 10进行刻蚀， 刻蚀掉基板 10上除形成 漏极及数据线 15、 源极 14、 公共电极线 16外其他区域的金属薄膜， 然后对 基板 10上的光刻胶进行灰化， 将基板 10上形成漏极及数据线 15、 源极 14、 公共电极线 16区域的光刻胶去除。 如图 14所示， 去除光刻胶后， 在形成栅 绝缘层 12、 有源层 13和第一透明导电层 24的基板 10上形成漏极及数据线 25、 源极 14、 公共电极线 16; 其中， 漏极及数据线 25位于有源层 13上方且 对应栅极区域， 源极 14位于有源层 13上方且对应栅极区域， 还位于有源层 13上方的第一透明导电层 24上， 公共电极线 16位于栅绝缘层 12上方。 更 具体地， 漏极及数据线 25设置于接触层 23的开口左侧的欧姆接触层 23上； 源极 14设置于该开口右侧的欧姆接触层 23上，并延伸到第一透明导电层 24 上， 截止于导电层 24的向下延伸部分处； 公共电极线 16设置在栅绝缘层 12 的没有被第一透明导电层 24所覆盖的那部分上。  Specifically, a metal film is deposited on the substrate 10 formed in step 102, and then a layer of photoresist is spin-coated on the metal film, and a third mask process is performed, that is, spin coating by using a mask. The photoresist is exposed and developed, and then the substrate 10 is etched to etch away the metal thin film on the substrate 10 except the drain and the data line 15, the source 14 and the common electrode line 16, and then on the substrate 10. The photoresist is ashed to remove the photoresist on the substrate 10 where the drain and data lines 15, the source 14 and the common electrode line 16 are formed. As shown in FIG. 14, after the photoresist is removed, the drain and data lines 25, the source electrode 14, and the common electrode line 16 are formed on the substrate 10 on which the gate insulating layer 12, the active layer 13, and the first transparent conductive layer 24 are formed. Wherein the drain and data lines 25 are located above the active layer 13 and corresponding to the gate region, the source 14 is located above the active layer 13 and corresponds to the gate region, and the first transparent conductive layer 24 is also located above the active layer 13. Above, the common electrode line 16 is located above the gate insulating layer 12. More specifically, the drain and data lines 25 are disposed on the ohmic contact layer 23 on the left side of the opening of the contact layer 23; the source 14 is disposed on the ohmic contact layer 23 on the right side of the opening and extends to the first transparent conductive layer 24, at the downward extending portion of the conductive layer 24; the common electrode line 16 is disposed on the portion of the gate insulating layer 12 that is not covered by the first transparent conductive layer 24.
本发明的实施例中， 漏极及数据线 15、 源极 14、 公共电极线 16是在基 板 10上沉积金属薄膜后，并进行一次曝光、显影、刻蚀后同时形成的， 因此， 漏极及数据线 15、 源极 14、 公共电极线 16的材料和厚度相同， 材料可以是 诸如钼、 铝、 钨、 钛、 铜等单金属层， 也可以是至少两个上述金属组成的复 合金属层， 单金属层或复合金属层的厚度例如为 100nm~500nm。  In the embodiment of the present invention, the drain and data lines 15, the source 14 and the common electrode line 16 are formed by depositing a metal thin film on the substrate 10, and performing one exposure, development, and etching simultaneously, thereby forming a drain. And the data line 15, the source 14 and the common electrode line 16 are made of the same material and thickness. The material may be a single metal layer such as molybdenum, aluminum, tungsten, titanium or copper, or a composite metal layer composed of at least two of the above metals. The thickness of the single metal layer or the composite metal layer is, for example, 100 nm to 500 nm.
步骤 104, 在形成漏极及数据线、 源极、 公共电极线的基板上， 形成钝 化层及位于钝化层中的用以暴露出源极的过孔， 该钝化层覆盖在整个基板上 方除公共电极线外的表面上；  Step 104, forming a passivation layer and a via hole in the passivation layer for exposing the source on the substrate on which the drain and the data line, the source, and the common electrode line are formed, the passivation layer covering the entire substrate Above the surface other than the common electrode line;
具体的，在步骤 103形成的基板 10上，再沉积一层钝化层薄膜， 然后在 该钝化层薄膜上旋涂一层光刻胶， 并进行第四次掩模工艺， 即利用掩模板对 旋涂的光刻胶进行曝光显影； 然后对基板 10进行刻蚀，刻蚀掉基板 10上方， 除形成钝化层外其他区域的钝化层薄膜， 然后对基板 10 上的光刻胶进行灰 化， 将基板 10上形成钝化层区域的光刻胶去除。 如图 15所示， 去除光刻胶 后， 在形成漏极及数据线 15、 源极 14、公共电极线 16的基板 10上形成钝化 层， 该钝化层包括第一部分 26和第二部分 27; 其中， 钝化层第一部分 26位 于有源层 12、 源极 14、 漏极及数据线 25上方，钝化层第二部分 27位于对应 非栅极区域的第一透明导电层 24上方及栅绝缘层 12上方， 在钝化层的与源 极相对应的位置上设置过孔； 更具体地，钝化层第一部分 26覆盖在漏极及数 据线 15、 源极 14以及用以形成薄膜晶体管沟道的有源层 23的开口上； 钝化 层第二部分 27覆盖在第一透明导电层 24及栅绝缘层 12上，但没覆盖公共电 极线 16。 Specifically, a passivation layer film is deposited on the substrate 10 formed in step 103, and then a photoresist is spin-coated on the passivation layer film, and a fourth mask process is performed, that is, a mask is used. The spin-coated photoresist is subjected to exposure and development; then, the substrate 10 is etched, the substrate 10 is etched away, and a passivation film is formed other than the passivation layer, and then the photoresist on the substrate 10 is applied. Ashing, the photoresist on the substrate 10 forming the passivation layer region is removed. As shown in FIG. 15, after the photoresist is removed, passivation is formed on the substrate 10 on which the drain and data lines 15, the source 14 and the common electrode line 16 are formed. a passivation layer comprising a first portion 26 and a second portion 27; wherein the first portion 26 of the passivation layer is over the active layer 12, the source 14, the drain and the data line 25, and the second portion 27 of the passivation layer is located A via hole is disposed over the first transparent conductive layer 24 corresponding to the non-gate region and above the gate insulating layer 12 at a position corresponding to the source of the passivation layer; more specifically, the first portion 26 of the passivation layer is covered by the drain a drain and a data line 15, a source 14 and an opening of the active layer 23 for forming a thin film transistor channel; the second portion 27 of the passivation layer overlying the first transparent conductive layer 24 and the gate insulating layer 12, but The common electrode line 16 is covered.
本发明的实施例中， 钝化层的材料为常用的氮化硅或氧化硅， 钝化层第 一部分 26与钝化层第二部分 27的厚度例如为 150nm~2500nm。  In an embodiment of the invention, the material of the passivation layer is commonly used silicon nitride or silicon oxide, and the thickness of the first portion 26 of the passivation layer and the second portion 27 of the passivation layer is, for example, 150 nm to 2500 nm.
步骤 105 , 在形成钝化层及过孔的基板上， 形成位于一部分钝化层上方 及公共电极线上方的第二透明导电层；  Step 105, forming a second transparent conductive layer above the part of the passivation layer and above the common electrode line on the substrate forming the passivation layer and the via hole;
具体的，在步骤 104形成的基板 10上，再沉积一层透明导电薄膜， 然后 在该透明导电薄膜上旋涂一层光刻胶， 并进行第五次掩模工艺， 即利用掩模 板对旋涂的光刻胶进行曝光显影； 然后对基板 10进行刻蚀， 刻蚀掉基板 10 上方，除形成透明导电层外其他区域的透明导电薄膜，然后对基板 10上的光 刻胶进行灰化， 将基板 10上形成透明导电层区域的光刻胶去除。 如图 16所 示， 去除光刻胶后， 在形成钝化层及过孔的基板 10 上形成第二透明导电层 28; 其中，第二透明导电层 28位于基板 10的钝化层第二部分 27上方及公共 电极线 16上方。 更具体地， 第二透明导电层 28为平坦的， 其覆盖在公共电 极线 16及与之相邻的钝化层第二部分 27上。  Specifically, a transparent conductive film is deposited on the substrate 10 formed in step 104, and then a layer of photoresist is spin-coated on the transparent conductive film, and a fifth mask process is performed, that is, using a mask to rotate The coated photoresist is exposed and developed; then, the substrate 10 is etched, the transparent conductive film on the substrate 10 is removed, except for the transparent conductive layer, and then the photoresist on the substrate 10 is ashed. The photoresist on the substrate 10 where the transparent conductive layer region is formed is removed. As shown in FIG. 16, after the photoresist is removed, a second transparent conductive layer 28 is formed on the substrate 10 on which the passivation layer and the via are formed; wherein the second transparent conductive layer 28 is located in the second portion of the passivation layer of the substrate 10. Above 27 and above the common electrode line 16. More specifically, the second transparent conductive layer 28 is flat and covers the common electrode line 16 and the second portion 27 of the passivation layer adjacent thereto.
本发明的实施例中， 第二透明导电层 28的材料为诸如 ITO、 ΙΖΟ、 ΖΑΟ 等透明导电材料， 第二透明导电层 28的厚度例如为 30nm~120nm。  In the embodiment of the present invention, the material of the second transparent conductive layer 28 is a transparent conductive material such as ITO, ruthenium or iridium, and the thickness of the second transparent conductive layer 28 is, for example, 30 nm to 120 nm.
步骤 106, 在形成第二透明导电层的基板上， 形成覆盖于整个基板上方 的树脂层， 该树脂层在对应源极的位置上设置有与钝化层的所述过孔相贯穿 的通孔；  Step 106, on the substrate forming the second transparent conductive layer, forming a resin layer covering the entire substrate, the resin layer is provided with a through hole penetrating the via hole of the passivation layer at a position corresponding to the source ;
具体的，在步骤 105形成的基板 10上，再沉积一层树脂薄膜， 然后在该 树脂薄膜上旋涂一层光刻胶， 并进行第六次掩模工艺， 即利用掩模板对旋涂 的光刻胶进行曝光显影； 然后对基板 10进行刻蚀， 刻蚀掉基板 10上方， 除 形成树脂层外其他区域的树脂薄膜，然后对基板 10上的光刻胶进行灰化，将 基板 10上形成树脂层区域的光刻胶去除。 如图 17所示， 去除光刻胶后， 在 形成第二透明导电层 28的基板 10上形成树脂层， 树脂层具有一个通孔， 与 钝化层的过孔相连通， 也就是说， 该通孔贯穿钝化层和树脂层。 该树脂层被 通孔分成两个部分：第一部分 29位于钝化层第一部分 26上方及源极 14上方， 树脂层第二部分 30位于源极 14上方、第二透明导电层 28上方及钝化层第二 部分 27上方。 Specifically, a resin film is further deposited on the substrate 10 formed in step 105, and then a photoresist is spin-coated on the resin film, and a sixth mask process is performed, that is, spin coating by using a mask. The photoresist is exposed and developed; then, the substrate 10 is etched, the resin film is removed from the substrate 10 except for the resin layer, and then the photoresist on the substrate 10 is ashed, and the substrate 10 is etched. The photoresist forming the resin layer region is removed. As shown in Figure 17, after removing the photoresist, A resin layer is formed on the substrate 10 on which the second transparent conductive layer 28 is formed, and the resin layer has a through hole communicating with the via hole of the passivation layer, that is, the through hole penetrates the passivation layer and the resin layer. The resin layer is divided into two portions by a via hole: a first portion 29 is above the first portion 26 of the passivation layer and above the source 14, and a second portion 30 of the resin layer is above the source 14, above the second transparent conductive layer 28, and passivated. Above the second portion 27 of the layer.
本发明的实施例中， 树脂层可以为感光树脂层或非感光树脂层， 树脂层 第一部分 29和树脂层第二部分 30的厚度例如为 1μπι~4μπι。  In the embodiment of the present invention, the resin layer may be a photosensitive resin layer or a non-photosensitive resin layer, and the thickness of the resin layer first portion 29 and the resin layer second portion 30 is, for example, 1 μm to 4 μm.
步骤 107, 在形成树脂层的基板上， 形成位于树脂层及通孔上方的第三 透明导电层；  Step 107, forming a third transparent conductive layer over the resin layer and the via hole on the substrate on which the resin layer is formed;
具体的， 在步骤 106形成树脂层第一部分 29和树脂层第二部分 30的基 板 10上，再沉积一层透明导电薄膜，然后在该透明导电薄膜上旋涂一层光刻 胶， 并进行第七次掩模工艺， 即利用掩模板对旋涂的光刻胶进行曝光显影； 然后对基板 10进行刻蚀， 刻蚀掉基板 10上方， 除形成第三透明导电层外其 他区域的薄膜， 然后对基板 10上的光刻胶进行灰化， 将基板 10上形成第三 透明导电层区域的光刻胶去除。如图 11所示， 剥离光刻胶后，在形成树脂层 的基板 10上形成第三透明导电层 31 ; 其中， 第三透明导电层 31覆盖在树脂 层第一部分 29上方、 树脂层第二部分 30上方及过孔上方。 更具体地， 第三 透明导电层 31覆盖于树脂层第一部分 29、 树脂层第二部分 30、 过孔的内壁 及过孔中源极的暴露表面上。  Specifically, a transparent conductive film is deposited on the substrate 10 of the first portion 29 of the resin layer and the second portion 30 of the resin layer in step 106, and then a layer of photoresist is spin-coated on the transparent conductive film. Seven mask processes, that is, exposing and developing the spin-coated photoresist by using a mask; then etching the substrate 10 to etch away the film above the substrate 10 except for the third transparent conductive layer, and then The photoresist on the substrate 10 is ashed, and the photoresist on the substrate 10 forming the third transparent conductive layer region is removed. As shown in FIG. 11, after the photoresist is stripped, a third transparent conductive layer 31 is formed on the substrate 10 on which the resin layer is formed; wherein the third transparent conductive layer 31 covers the first portion 29 of the resin layer and the second portion of the resin layer. Above 30 and above the via. More specifically, the third transparent conductive layer 31 covers the first portion 29 of the resin layer, the second portion 30 of the resin layer, the inner wall of the via, and the exposed surface of the source in the via.
本发明的实施例中， 第三透明导电层 31的材料为诸如 ΙΤΟ、 ΙΖΟ、 ΖΑΟ 等透明导电材料， 第三透明导电层 31的厚度例如为 30nm~120nm。  In the embodiment of the present invention, the material of the third transparent conductive layer 31 is a transparent conductive material such as ΙΤΟ, ΙΖΟ, ΖΑΟ, and the thickness of the third transparent conductive layer 31 is, for example, 30 nm to 120 nm.
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。  The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.

Claims

权利要求书 claims
1、 一种平板阵列基板， 包括： 1. A flat panel array substrate, including:
基板； substrate;
位于基板上方的栅极及栅极扫描线； Gate electrodes and gate scan lines located above the substrate;
位于栅极及栅极扫描线上方的栅绝缘层， 位于栅绝缘层上方且对应栅极 区域的有源层， 位于有源层上方和栅绝缘层上方的第一透明导电层； A gate insulating layer located above the gate electrode and the gate scanning line, an active layer located above the gate insulating layer and corresponding to the gate region, a first transparent conductive layer located above the active layer and above the gate insulating layer;
位于有源层上方且对应栅极区域的漏极及数据线， 位于有源层上方且对 应栅极区域以及有源层上方的第一透明导电层上方的源极， 位于栅绝缘层上 方且对应非栅极区域的公共电极线； The drain electrode and the data line located above the active layer and corresponding to the gate region, the source electrode located above the active layer and corresponding to the gate region and the first transparent conductive layer above the active layer, the source electrode located above the gate insulating layer and corresponding to Common electrode lines in non-gate areas;
覆盖在整个基板上方除公共电极线外的表面上的钝化层， 所述钝化层中 设置有用以暴露出源极的过孔； A passivation layer covering the entire surface of the substrate except for the common electrode line, with via holes provided in the passivation layer to expose the source;
位于一部分钝化层上方及公共电极线上方的第二透明导电层； 覆盖于整个基板上方的树脂层， 该树脂层在对应源极的位置上设置有与 钝化层的所述过孔相贯穿的通孔； 和 a second transparent conductive layer located above a portion of the passivation layer and above the common electrode line; a resin layer covering the entire substrate, the resin layer is provided with the via hole penetrating the passivation layer at a position corresponding to the source electrode through holes; and
位于树脂层及通孔上方的第三透明导电层。 The third transparent conductive layer is located above the resin layer and the through hole.
2、根据权利要求 1所述的平板阵列基板，还包括设置在有源层表面上的 欧姆接触层。 2. The flat array substrate according to claim 1, further comprising an ohmic contact layer disposed on the surface of the active layer.
3、根据权利要求 2所述的平板阵列基板， 其中， 所述第一透明导电层设 置在欧姆接触层的一部分表面上且延伸并截止在栅绝缘层的表面上。 3. The flat array substrate according to claim 2, wherein the first transparent conductive layer is disposed on a part of the surface of the ohmic contact layer and extends and stops on the surface of the gate insulating layer.
4、 根据权利要求 1-3中任一项所述的平板阵列基板， 其中， 所述钝化层 包括第一部分和第二部分， 其中所述钝化层第一部分位于有源层、 源极、 漏 极及数据线的上方， 钝化层第二部分位于对应非栅极区域的第一透明导电层 及栅绝缘层的上方。 4. The flat array substrate according to any one of claims 1 to 3, wherein the passivation layer includes a first part and a second part, wherein the first part of the passivation layer is located on the active layer, the source electrode, Above the drain electrode and the data line, the second part of the passivation layer is located above the first transparent conductive layer and the gate insulating layer corresponding to the non-gate area.
5、 根据权利要求 1-4中任一项所述的平板阵列基板， 其中， 所述树脂层 包括第一部分和第二部分， 其中树脂层第一部分覆盖在钝化层第一部分上， 所述树脂层第二部分覆盖在第二透明导电层上。 5. The flat panel array substrate according to any one of claims 1 to 4, wherein the resin layer includes a first part and a second part, wherein the first part of the resin layer covers the first part of the passivation layer, and the resin The second portion of the layer overlies the second transparent conductive layer.
6、 根据权利要求 1-5中任一项所述的平板阵列基板， 其中， 所述通孔贯 穿所述钝化层和树脂层， 以暴露出源极。 6. The flat array substrate according to any one of claims 1 to 5, wherein the through hole penetrates the passivation layer and the resin layer to expose the source electrode.
7、 一种传感器， 包括权利要求 1-6中任一项所述的平板阵列基板。 7. A sensor, comprising the flat array substrate according to any one of claims 1-6.
8、 一种平板阵列基板的制作方法， 包括： 8. A method for manufacturing a flat array substrate, including:
在基板上形成栅极及栅极扫描线； Form gate electrodes and gate scan lines on the substrate;
在形成栅极及栅极扫描线的基板上， 形成栅绝缘层、 有源层和第一透明 导电层； Form a gate insulating layer, an active layer and a first transparent conductive layer on the substrate where the gate electrode and the gate scanning line are formed;
在形成栅绝缘层、 有源层和第一透明导电层的基板上， 形成漏极及数据 线、 源极、 公共电极线； On the substrate on which the gate insulating layer, the active layer and the first transparent conductive layer are formed, the drain electrode, data line, source electrode and common electrode line are formed;
在形成漏极及数据线、 源极、 公共电极线的基板上， 形成钝化层及位于 钝化层中的用以暴露出源极的过孔， 该钝化层覆盖在整个基板上方除公共电 极线外的表面上； On the substrate where the drain, data lines, source, and common electrode lines are formed, a passivation layer and a via hole located in the passivation layer to expose the source are formed. The passivation layer covers the entire substrate except for the common electrode. On the surface outside the electrode wire;
在形成钝化层及过孔的基板上， 形成位于一部分钝化层上方及公共电极 线上方的第二透明导电层； On the substrate where the passivation layer and the via hole are formed, a second transparent conductive layer is formed above a portion of the passivation layer and above the common electrode line;
在形成第二透明导电层的基板上， 形成覆盖于整个基板上方的树脂层， 该树脂层在对应源极的位置上设置有与钝化层的所述过孔相贯穿的通孔； 以 及 On the substrate on which the second transparent conductive layer is formed, a resin layer covering the entire substrate is formed, and the resin layer is provided with a through hole penetrating the via hole of the passivation layer at a position corresponding to the source electrode; and
在形成树脂层的基板上，形成位于树脂层及通孔上方的第三透明导电层。 On the substrate on which the resin layer is formed, a third transparent conductive layer is formed above the resin layer and the through hole.
9、根据权利要求 8所述的方法， 还包括： 在形成所述栅绝缘层、有源层 和第一透明导电层时， 形成有源层上的欧姆接触层。 9. The method of claim 8, further comprising: forming an ohmic contact layer on the active layer when forming the gate insulating layer, the active layer and the first transparent conductive layer.
10、 根据权利要求 9所述的方法， 其中， 所述第一透明导电层设置在欧 姆接触层的一部分表面上， 且延伸并截止在栅绝缘层的表面上。 10. The method according to claim 9, wherein the first transparent conductive layer is disposed on a part of the surface of the ohmic contact layer, and extends and stops on the surface of the gate insulating layer.
11、 根据权利要求 8-10中任一项所述的方法， 其中， 所述钝化层包括第 一部分和第二部分， 其中所述钝化层第一部分位于有源层、 源极、 漏极及数 据线的上方， 钝化层第二部分位于对应非栅极区域的第一透明导电层及栅绝 缘层的上方。 11. The method according to any one of claims 8 to 10, wherein the passivation layer includes a first part and a second part, wherein the first part of the passivation layer is located on the active layer, the source electrode, and the drain electrode. and above the data lines, the second part of the passivation layer is located above the first transparent conductive layer and the gate insulating layer corresponding to the non-gate area.
12、 根据权利要求 8-11中任一项所述的方法， 其中， 所述树脂层包括第 一部分和第二部分， 其中树脂层第一部分覆盖在钝化层第一部分上， 所述树 脂层第二部分覆盖在第二透明导电层上。 12. The method according to any one of claims 8 to 11, wherein the resin layer includes a first part and a second part, wherein the first part of the resin layer covers the first part of the passivation layer, and the third part of the resin layer The two parts cover the second transparent conductive layer.
13、 根据权利要求 8-12中任一项所述的方法， 其中， 所述通孔贯穿所述 钝化层和树脂层， 以暴露出源极。 13. The method according to any one of claims 8-12, wherein the through hole penetrates the passivation layer and the resin layer to expose the source electrode.
14、 根据权利要求 8-13中任一项所述的方法， 其中， 所述在形成栅极及 栅极扫描线的基板上， 形成栅绝缘层、 有源层和第一透明导电层包括： 在形成栅极及栅极扫描线的基板上， 连续沉积栅绝缘层薄膜、 有源层薄 膜和透明导电薄膜， 并进行一次掩模工艺， 从而形成栅绝缘层、 有源层和第 一透明导电层。 14. The method according to any one of claims 8 to 13, wherein forming the gate insulating layer, the active layer and the first transparent conductive layer on the substrate on which the gate electrode and the gate scanning line are formed includes: On the substrate where the gate electrode and gate scanning line are formed, the gate insulating layer film, the active layer film and the transparent conductive film are continuously deposited, and a mask process is performed to form the gate insulating layer, the active layer and the first transparent conductive film. layer.
15、根据权利要求 8-14中任一项所述的方法，其中，所述漏极及数据线、 源极、公共电极线通过沉积一层金属薄膜后，经过一次掩膜工艺而一起形成。 15. The method according to any one of claims 8 to 14, wherein the drain electrode, data line, source electrode, and common electrode line are formed together by depositing a layer of metal film and then undergoing a masking process.
16、 根据权利要求 8-15中任一项所述的方法， 其中， 所述栅极及栅极扫 描线为由钼、 铝、 钨、 钛或铜制成的单层， 或由钼、 铝、 钨、 钛、 铜中的至 少两个金属制成的多层， 该单层或多层的厚度为 100nm~500nm。 16. The method according to any one of claims 8 to 15, wherein the gate electrode and the gate scanning line are a single layer made of molybdenum, aluminum, tungsten, titanium or copper, or are made of molybdenum, aluminum A multi-layer made of at least two metals among tungsten, titanium and copper, and the thickness of the single layer or multi-layer is 100nm~500nm.
17、 根据权利要求 8-16中任一项所述的方法， 其中， 所述栅绝缘层由氮 化硅或氧化硅制成， 厚度为 250nm~600nm。 17. The method according to any one of claims 8-16, wherein the gate insulating layer is made of silicon nitride or silicon oxide, and has a thickness of 250nm~600nm.
18、 根据权利要求 8-17中任一项所述的方法， 其中， 所述有源层由非晶 硅制成， 厚度为 30nm~300nm。 18. The method according to any one of claims 8-17, wherein the active layer is made of amorphous silicon and has a thickness of 30nm~300nm.
19、 根据权利要求 8-18中任一项所述的方法， 其中， 所述欧姆接触层由 掺磚非晶硅制成， 厚度为 30nm~100nm。 19. The method according to any one of claims 8-18, wherein the ohmic contact layer is made of brick-doped amorphous silicon and has a thickness of 30nm~100nm.
20、 根据权利要求 8-19中任一项所述的方法， 其中， 所述第一透明导电 层、 第二透明导电层和第三透明导电层由铟锡氧化物、 或氧化辞铟、 或氧化 辞铝制成， 厚度为 30nm~120nm。 20. The method according to any one of claims 8 to 19, wherein the first transparent conductive layer, the second transparent conductive layer and the third transparent conductive layer are made of indium tin oxide, or indium oxide, or Made of aluminum oxide, with a thickness of 30nm~120nm.
21、 根据权利要求 8-20中任一项所述的方法， 其中， 所述钝化层由氮化 硅或氧化硅制成， 厚度为 150nm~2500nm。 21. The method according to any one of claims 8-20, wherein the passivation layer is made of silicon nitride or silicon oxide, and has a thickness of 150nm~2500nm.
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