CN103579219A - Planar array substrate, sensor and manufacturing method of planar array substrate - Google Patents
Planar array substrate, sensor and manufacturing method of planar array substrate Download PDFInfo
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- CN103579219A CN103579219A CN201210265470.1A CN201210265470A CN103579219A CN 103579219 A CN103579219 A CN 103579219A CN 201210265470 A CN201210265470 A CN 201210265470A CN 103579219 A CN103579219 A CN 103579219A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
Abstract
The invention discloses a manufacturing method of a planar array substrate. The manufacturing method of the planar array substrate comprises the steps that a grid electrode and a grid electrode scanning line are formed on the substrate, a grid insulating layer, an active layer and a first transparent conducting layer are formed on the substrate where the grid electrode and the grid electrode scanning line are formed, a drain electrode, a data line, a source electrode and a public electrode layer are formed on the substrate where the grid insulating layer, the active layer and the first transparent conducting layer are formed, a first passivation layer, a second passivation layer and a via hole are formed on the substrate where the drain electrode, the data line, the source electrode and the public electrode layer are formed, a second transparent conducting layer is formed on the substrate where the first passivation layer, the second passivation layer and the via hole are formed, a first resin layer and a second resin layer are formed on the substrate where the second transparent conducting layer is formed, and a third transparent conducting layer is formed on the substrate where the first resin layer and the second resin layer are formed. The invention further provides the planar array substrate and a senor. According to the planar array substrate, the sensor and the manufacturing method of the planar array substrate, the number of used masks can be reduced and the capacity of equipment is improved.
Description
Technical field
The present invention relates to Thin Film Transistor (TFT) (TFT, Thin Film Transistor) manufacturing technology and transducer manufacturing technology, relate in particular to the manufacture method of a kind of flat plate array substrate, transducer and flat plate array substrate.
Background technology
In the < < major technologies and equipment autonomous innovation guidance list > > that in December, 2009,15 the Ministry of Industry and Information Technology, the Ministry of Science and Technology, the Ministry of Finance, State Assets Administration Committee promulgated, project 12.3.5 is " product newly developed " by " non-crystalline silicon tft X-ray plane transducer " project verification.Four ministries and commissions are thought in medical market, the non-crystalline silicon tft X-ray plane capacity sensor approximately 18,000,000,000 of township hospital (approximately 60,000), if the mortality according to 10 years, the magnitude of recruitment of later annual non-crystalline silicon tft X-ray plane transducer in market is 1,800,000,000, so TFT X-ray plane transducer has unprecedented application prospect.
But, current domestic technology and the manufacturing process that there is no this respect, the production market of non-crystalline silicon tft X-ray plane transducer is by external oligopoly.At present, the manufacturing process of non-crystalline silicon tft X-ray plane transducer, needs left and right masking process conventionally 10 times, and the technical process of tft array generally comprises masking process 4 to 6 times.
At present, the manufacture of non-crystalline silicon tft X-ray plane transducer mainly comprises the steps:
Step 1 as shown in Figure 1, in masking process, forms grid and controlling grid scan line 11 for the first time on substrate 10;
Step 2 as shown in Figure 2, for the second time in masking process, forms gate insulation layer 12 on substrate 10 and the grid forming and controlling grid scan line 11, then above described gate insulation layer 12 and the region corresponding with area of grid, forms active layer 13;
Step 3, as shown in Figure 3, in masking process, peels off the gate insulation layer 12 on the grid of the neighboring area of substrate 10 and controlling grid scan line 11 for the third time, exposes grid and the controlling grid scan line 11 of the neighboring area of substrate 10;
Step 4 as shown in Figure 4, in the 4th masking process, forms described source/drain electrode layer and comprises source electrode 14 and drain electrode 15 above active layer 13; Above described gate insulation layer 12, form common electrode layer 16;
Step 5, as shown in Figure 5, in the 5th masking process, above active layer 13, source-drain electrode layer and common electrode layer 16, forms passivation layer 17;
Step 6, as shown in Figure 6, in the 6th masking process, carries out nano indium tin metal oxide (ITO, Indium Tin Oxides) mask process for the first time, above common electrode layer 16 and passivation layer 17, forms ITO conductive layer 18;
Step 7, as shown in Figure 7, in the 7th masking process, carries out the mask of ITO insulation for the first time process, on passivation layer 17 and ITO conductive layer 18 upper stratas, forms ITO insulating barrier 19; On source electrode 14, form a via hole;
Step 8, as shown in Figure 8, in the 8th masking process, carries out ITO mask process for the second time, on ITO insulating barrier 19 and via hole, forms the 2nd ITO conductive layer 20;
Step 9, as shown in Figure 9, in the 9th masking process, in the region except via hole above ITO insulating barrier 19 and above the 2nd ITO conductive layer 20, forms resin bed 21;
Therefore, non-crystalline silicon tft X-ray plane transducer needs 10 masking process just can complete conventionally at present, and manufacture process is very complicated, and cost is higher.
Summary of the invention
In view of this, main purpose of the present invention is to provide the manufacture method of a kind of flat plate array substrate, transducer and flat plate array substrate, can reduce the mask plate quantity of use, improves equipment capacity.
For achieving the above object, technical scheme of the present invention is achieved in that
The invention provides a kind of flat plate array substrate, comprising:
Substrate;
Be positioned at grid and the controlling grid scan line of substrate top;
Be positioned at the gate insulation layer of grid and controlling grid scan line top, be positioned at the active layer of gate insulation layer top and corresponding area of grid, be positioned at the ohmic contact layer of active layer top, be positioned at the first transparency conducting layer of ohmic contact layer top and gate insulation layer top;
Be positioned at drain electrode and the data wire of active layer top and corresponding area of grid, be positioned at the source electrode of the first transparency conducting layer top of active layer top and corresponding area of grid and active layer top, be positioned at the common electrode layer of gate insulation layer top and corresponding non-area of grid;
Be positioned at the first passivation layer of active layer, source electrode, drain electrode and data wire top, be positioned at the first transparency conducting layer top of corresponding non-area of grid and the second passivation layer of gate insulation layer top, between the first passivation layer and the second passivation layer, have via hole;
Be positioned at the second transparency conducting layer of the second passivation layer top and public electrode top;
Be positioned at the first resin bed of the first passivation layer top and source electrode top, be positioned at the second resin bed of source electrode top, the second transparency conducting layer top and the second passivation layer top;
Be positioned at the 3rd transparency conducting layer of the first resin bed top, the second resin bed top and via hole top.
The present invention also provides a kind of transducer, and this transducer comprises above-mentioned flat plate array substrate.
The present invention also provides a kind of manufacture method of flat plate array substrate, comprising:
On substrate, form grid and controlling grid scan line;
Forming on the substrate of grid and controlling grid scan line, form gate insulation layer, active layer and the first transparency conducting layer;
Forming on the substrate of gate insulation layer, active layer and the first transparency conducting layer, form drain electrode and data wire, source electrode, common electrode layer;
Forming on the substrate of drain electrode and data wire, source electrode, common electrode layer, form the first passivation layer, the second passivation layer and via hole;
Forming on the substrate of the first passivation layer, the second passivation layer and via hole, form the second transparency conducting layer;
Forming on the substrate of the second transparency conducting layer, form the first resin bed and the second resin bed;
Forming on the substrate of the first resin bed and the second resin bed, form the 3rd transparency conducting layer.
In said method, described formation on the substrate of grid and controlling grid scan line, formation gate insulation layer, active layer and the first transparency conducting layer are:
Forming on the substrate of grid and controlling grid scan line, successive sedimentation gate insulation layer film, active layer film and transparent conductive film, and carry out masking process for the second time, form gate insulation layer, active layer and the first transparency conducting layer.
In said method, the method also comprises:
When described formation gate insulation layer, active layer and the first transparency conducting layer, form ohmic contact layer simultaneously.
In said method,
The material of described grid and controlling grid scan line is the single metal layers such as molybdenum, aluminium, tungsten, titanium, copper, or is at least two complex metal layers that metal forms in molybdenum, aluminium, tungsten, titanium, copper;
The thickness of described grid and controlling grid scan line is 100nm～500nm.
In said method,
The material of described gate insulation layer is silicon nitride or silica;
The thickness of described gate insulation layer is 250nm～600nm.
In said method,
The material of described active layer is amorphous silicon;
The thickness of described active layer 13 is 30nm～300nm.
In said method,
The material of ohmic contact layer is phosphorus-doped amorphous silicon;
The thickness of described ohmic contact layer is 30nm～100nm.
In said method,
The material of described the first transparency conducting layer, the second transparency conducting layer and the 3rd transparency conducting layer is nano indium tin metal oxide (ITO) or indium zinc oxide (IZO) or zinc oxide aluminum (ZAO);
The thickness of described the first transparency conducting layer, the second transparency conducting layer and the 3rd transparency conducting layer is 30nm～120nm.
In said method,
Described drain electrode and data wire, source electrode, common electrode layer deposit after layer of metal film on substrate, carry out forming after single exposure development treatment, etching processing simultaneously;
The material of described drain electrode and data wire, source electrode and common electrode layer is the single metal layers such as molybdenum, aluminium, tungsten, titanium, copper, or is at least two complex metal layers that metal forms in molybdenum, aluminium, tungsten, titanium, copper;
The thickness of described drain electrode and data wire, source electrode and common electrode layer is 100nm～500nm.
In said method,
The material of described the first passivation layer and the second passivation layer is silicon nitride or silica;
The thickness of described the first passivation layer and the second passivation layer is 150nm～2500nm.
In said method,
The material of described the first passivation layer and the second passivation layer is silicon nitride or silica;
The thickness of described the first passivation layer and the second passivation layer is 150nm～2500nm.
The manufacture method of flat plate array substrate provided by the invention, transducer and flat plate array substrate forms grid and controlling grid scan line on substrate; Forming on the substrate of grid and controlling grid scan line, form gate insulation layer, active layer and the first transparency conducting layer; Forming on the substrate of gate insulation layer, active layer and the first transparency conducting layer, form drain electrode and data wire, source electrode, common electrode layer; Forming on the substrate of drain electrode and data wire, source electrode, common electrode layer, form the first passivation layer, the second passivation layer and via hole; Forming on the substrate of the first passivation layer, the second passivation layer and via hole, form the second transparency conducting layer; Forming on the substrate of the second transparency conducting layer, form the first resin bed and the second resin bed; Forming on the substrate of the first resin bed and the second resin bed, form the 3rd transparency conducting layer; So, using the same layer metal level common electrode layer with source electrode, drain electrode and data scanning line as storage capacitance pole plate, altogether carry out seven masking process and can complete the manufacturing process of transducer middle plateform array base palte, therefore, can reduce the mask plate quantity of use, improve equipment capacity, improve product yields
Accompanying drawing explanation
Fig. 1 is the schematic cross-section of masking process metacoxal plate for the first time in prior art;
Fig. 2 is the schematic cross-section of masking process metacoxal plate for the second time in prior art;
Fig. 3 is the schematic cross-section of masking process metacoxal plate for the third time in prior art;
Fig. 4 is the schematic cross-section of the 4th masking process metacoxal plate in prior art;
Fig. 5 is the schematic cross-section of the 5th masking process metacoxal plate in prior art;
Fig. 6 is the schematic cross-section of the 6th masking process metacoxal plate in prior art;
Fig. 7 is the schematic cross-section of the 7th masking process metacoxal plate in prior art;
Fig. 8 is the schematic cross-section of the 8th masking process metacoxal plate in prior art;
Fig. 9 is the schematic cross-section of the 9th masking process metacoxal plate in prior art;
Figure 10 is the schematic cross-section of TFT X-ray plane transducer in prior art;
Figure 11 is the schematic cross-section of middle plateform array base palte of the present invention;
Figure 12 is the schematic flow sheet that the present invention realizes the manufacture method of flat plate array substrate;
Figure 13 is the schematic cross-section of masking process metacoxal plate for the first time in the present invention;
Figure 14 is the schematic cross-section of masking process metacoxal plate for the second time in the present invention;
Figure 15 is the schematic cross-section of masking process metacoxal plate for the third time in the present invention;
Figure 16 is the schematic cross-section of the 4th masking process metacoxal plate in the present invention;
Figure 17 is the schematic cross-section of the 5th masking process metacoxal plate in the present invention;
Figure 18 is the schematic cross-section of the 6th masking process metacoxal plate in the present invention.
Description of reference numerals:
10: substrate
11: grid and controlling grid scan line
12: gate insulation layer
13: active layer
14: source electrode
15: drain electrode
16: common electrode layer
17: passivation layer
18: the ITO conductive layers
19:ITO insulating barrier
20: the two ITO conductive layers
21: resin bed
22: the three ITO conductive layers
23: ohmic contact layer
24: the first transparency conducting layers
25: drain electrode and data wire
26: the first passivation layers
27: the second passivation layers
28: the second transparency conducting layers
29: the first resin beds
30: the second resin beds
31: the three transparency conducting layers
Embodiment
Basic thought of the present invention is: on substrate, form grid and controlling grid scan line; Forming on the substrate of grid and controlling grid scan line, form gate insulation layer, active layer and the first transparency conducting layer; Forming on the substrate of gate insulation layer, active layer and the first transparency conducting layer, form drain electrode and data wire, source electrode, common electrode layer; Forming on the substrate of drain electrode and data wire, source electrode, common electrode layer, form the first passivation layer, the second passivation layer and via hole; Forming on the substrate of the first passivation layer, the second passivation layer and via hole, form the second transparency conducting layer; Forming on the substrate of the second transparency conducting layer, form the first resin bed and the second resin bed; Forming on the substrate of the first resin bed and the second resin bed, form the 3rd transparency conducting layer.
Below by drawings and the specific embodiments, the present invention is described in further detail again.
The utility model provides a kind of flat plate array substrate, and Figure 11 is the schematic cross-section of middle plateform array base palte of the present invention, and as shown in figure 11, this flat plate array substrate comprises:
Be positioned at grid and the controlling grid scan line 11 of substrate 10 tops;
Be positioned at the gate insulation layer 12 of grid and controlling grid scan line 11 tops, be positioned at the active layer 13 of gate insulation layer 12 tops and corresponding area of grid, be positioned at the ohmic contact layer 23 of active layer 13 tops, be positioned at the first transparency conducting layer 24 of ohmic contact layer 23 tops and gate insulation layer 12 tops;
Be positioned at drain electrode and the data wire 25 of active layer 13 tops and corresponding area of grid, be positioned at the source electrode 14 of the first transparency conducting layer 24 tops of active layer 13 tops and corresponding area of grid and active layer 13 tops, be positioned at the common electrode layer 16 of gate insulation layer 12 tops and corresponding non-area of grid;
Be positioned at the first passivation layer 26 of active layer 13, source electrode 14, drain electrode and data wire 25 tops, be positioned between the first transparency conducting layer 24 tops of corresponding non-area of grid and the second passivation layer 27, the first passivation layers 26 of gate insulation layer 12 tops and the second passivation layer 27 and have via hole;
Be positioned at the second transparency conducting layer 28 of the second passivation layer 27 tops and common electrode layer 16 tops;
Be positioned at the first resin bed 29 of the first passivation layer 26 tops and source electrode 14 tops, be positioned at the second resin bed 30 of source electrode 14 tops, the second transparency conducting layer 28 tops and the second passivation layer 27 tops;
Be positioned at the 3rd transparency conducting layer 31 of the first resin bed 29 tops, the second resin bed 30 tops and via hole top.
The present invention also provides a kind of transducer, and this transducer comprises above-mentioned flat plate array substrate.
For realizing above-mentioned flat plate array substrate, the present invention also provides a kind of manufacture method of flat plate array substrate, and Figure 12 is the schematic flow sheet that the present invention realizes the manufacture method of flat plate array substrate, and as shown in figure 12, the method comprises the following steps:
Step 1201 forms grid and controlling grid scan line on substrate;
Concrete, on substrate 10, deposit one deck gate metal film, spin coating one deck photoresist on this gate metal film, and carry out masking process for the first time, utilize mask plate to carry out exposure imaging processing to the photoresist of spin coating; Then substrate 10 is carried out to etching processing, etch away on substrate 10 the gate metal film in other regions except forming grid and controlling grid scan line 11; Then the remaining photoresist on substrate 10 is carried out to ashing processing, the photoresist that forms grid and controlling grid scan line 11 regions on substrate 10 is removed; As shown in figure 13, remove after photoresist, on substrate 10, form grid and controlling grid scan line 11;
Wherein, the material of grid and controlling grid scan line 11 can be the single metal layers such as molybdenum, aluminium, tungsten, titanium, copper, can be also the complex metal layers that wherein at least two metals form, and the thickness of grid and controlling grid scan line 11 is 100nm～500nm.
Step 1202, forming on the substrate of grid and controlling grid scan line, forms gate insulation layer, active layer and the first transparency conducting layer;
Concrete, in step 1201, form on the substrate 10 of grid and controlling grid scan line 11, successive sedimentation gate insulation layer film, active layer film, ohmic contact layer film and transparent conductive film, then spin coating one deck photoresist on the superiors' film, and carry out masking process for the second time, utilize mask plate to carry out exposure imaging processing to the photoresist of spin coating; Then substrate 10 is carried out to etching processing, etch away gate insulation layer 12 tops of substrate 10, the film in other regions except forming active layer 13, ohmic contact layer 23 and the first transparency conducting layer 24; Then remaining photoresist on substrate 10 is carried out to ashing processing, the photoresist that forms active layer 13, ohmic contact layer 23 and the first transparency conducting layer 24 regions on substrate 10 is removed; As shown in figure 14, remove after photoresist, on the substrate 10 that forms grid and controlling grid scan line 11, form gate insulation layer 12, active layer 13, ohmic contact layer 23 and the first transparency conducting layer 24; Wherein, gate insulation layer 12 is positioned at grid and controlling grid scan line 11 tops, and active layer 13 is positioned at gate insulation layer 12 tops and corresponding area of grid, and ohmic contact layer 23 is positioned at active layer 13 tops; The first transparency conducting layer 24 is positioned at ohmic contact layer 23 tops and gate insulation layer 12 tops; It should be noted that, above-mentioned ohmic contact layer 23 is optional formation, can only on the substrate 10 that forms grid and controlling grid scan line 11, form gate insulation layer 12, active layer 13 and the first transparency conducting layer 24, also can on the substrate 10 that forms grid and controlling grid scan line 11, form gate insulation layer 12, active layer 13, ohmic contact layer 23 and the first transparency conducting layer 24, ohmic contact layer 23 is for reducing the size of active layer 13 and source electrode 14, the contact resistance between 15 that drains;
Wherein, the material of gate insulation layer 12 can be the insulating material such as silicon nitride or silica, and the thickness of gate insulation layer 12 is 250nm～600nm; The material of active layer 13 is amorphous silicon, this amorphous silicon claims again amorphous silicon, it is a kind of form of elemental silicon, amorphous silicon has the microcrystal of brownish black or grey black, element silicon in amorphous silicon does not have complete diamond structure cell, purity is not high, and the fusing point of amorphous silicon, density and hardness are also starkly lower than crystalline silicon; The thickness of active layer 13 is 30nm～300nm; The material of ohmic contact layer 23 is phosphorus-doped amorphous silicon, and the thickness of ohmic contact layer 23 is 30nm～100nm; The material of the first transparency conducting layer 24 is the transparent conductive materials such as ITO or indium zinc oxide (IZO, InxZnyOz) or zinc oxide aluminum (ZAO, ZnxAlyOz), and the thickness of the first transparency conducting layer 24 is 30nm～120nm; Here, can adopt chemical deposition method to deposit the nonmetal films such as active layer film and ohmic contact layer film, adopt non-crystal type or polycrystalline mode deposit transparent conductive film.
Step 1203, forming on the substrate of gate insulation layer, active layer and the first transparency conducting layer, forms drain electrode and data wire, source electrode, common electrode layer;
Concrete, in step 1202, form gate insulation layer 12, on the substrate 10 of active layer 13 and the first transparency conducting layer 24, deposit again layer of metal film, then spin coating one deck photoresist on this metallic film, and carry out masking process for the third time, utilize mask plate to carry out exposure imaging processing to the photoresist of spin coating, then substrate 10 is carried out to etching processing, etch away on substrate 10 except forming drain electrode and data wire 15, source electrode 14, the metallic film in common electrode layer 16 outer other regions, then the photoresist on substrate 10 is carried out to ashing processing, drain electrode and data wire 15 will be formed on substrate 10, source electrode 14, the photoresist in common electrode layer 16 regions is removed, as shown in figure 15, remove after photoresist, on the substrate 10 that forms gate insulation layer 12, active layer 13 and the first transparency conducting layer 24, form drain electrode and data wire 25, source electrode 14, common electrode layer 16, wherein, drain electrode and data wire 25 are positioned at active layer 13 tops and corresponding area of grid, source electrode 14 is positioned at active layer 13 tops and corresponding area of grid, is also positioned on the first transparency conducting layer 24 of active layer 13 tops, and common electrode layer 16 is positioned at gate insulation layer 12 tops and corresponding non-area of grid,
Wherein, drain electrode and data wire 15, source electrode 14, common electrode layer 16 are on substrate 10 after depositing metal films, and carry out forming after single exposure development treatment, etching processing simultaneously, therefore, the material of drain electrode and data wire 15, source electrode 14, common electrode layer 16 is identical with thickness, material can be the single metal layers such as molybdenum, aluminium, tungsten, titanium, copper, can be also the complex metal layers that wherein at least two metals form, and thickness is 100nm～500nm.
Step 1204, forming on the substrate of drain electrode and data wire, source electrode, common electrode layer, forms the first passivation layer, the second passivation layer and via hole;
Concrete, in step 1203, form on the substrate 10 of drain electrode and data wire 15, source electrode 14, common electrode layer 16, deposit again one deck passivation layer film, then spin coating one deck photoresist on this passivation layer film, and carry out masking process the 4th time, utilize mask plate to carry out exposure imaging processing to the photoresist of spin coating; Then substrate 10 is carried out to etching processing, etch away substrate 10 tops, except forming passivation layer, the passivation layer film in other regions, then carries out ashing processing to the photoresist on substrate 10, and the photoresist that forms passivation layer region on substrate 10 is removed; As shown in figure 16, remove after photoresist, on 16 substrates 10 that form drain electrode and data wire 15, source electrode 14, common electrode layer, form the first passivation layer 26 and the second passivation layer 27; Wherein, the first passivation layer 26 is positioned at active layer 12, source electrode 14, drain electrode and data wire 25 tops, the second passivation layer 27 is positioned at the first transparency conducting layer 24 tops and gate insulation layer 12 tops of corresponding non-area of grid, and has via hole between the first passivation layer 26 and the second passivation layer 27;
Wherein, the material of the first passivation layer 26 and the second passivation layer 27 is conventional silicon nitride or silica, and the thickness of the first passivation layer 26 and the second passivation layer 27 is 150nm～2500nm.
Step 1205, forming on the substrate of the first passivation layer, the second passivation layer and via hole, forms the second transparency conducting layer;
Concrete, in step 1204, form on the substrate 10 of the first passivation layer 26, the second passivation layer 27 and via hole, deposit again layer of transparent conductive film, then spin coating one deck photoresist on this transparent conductive film, and carry out masking process the 5th time, utilize mask plate to carry out exposure imaging processing to the photoresist of spin coating; Then substrate 10 is carried out to etching processing, etch away substrate 10 tops, except forming transparency conducting layer, the transparent conductive film in other regions, then carries out ashing processing to the photoresist on substrate 10, and the photoresist that forms electrically conducting transparent layer region on substrate 10 is removed; As shown in figure 17, remove after photoresist, on the substrate 10 that forms the first passivation layer 26, the second passivation layer 27 and via hole, form the second transparency conducting layer 28; Wherein, the second transparency conducting layer 28 is positioned at the second passivation layer 27 tops and common electrode layer 16 tops of substrate 10;
Wherein, the material of the second transparency conducting layer 28 is the transparent conductive materials such as ITO, IZO, ZAO, and the thickness of the second transparency conducting layer 28 is 30nm～120nm.
Step 1206, forming on the substrate of the second transparency conducting layer, forms the first resin bed and the second resin bed;
Concrete, in step 1205, form on the substrate 10 of the second transparency conducting layer 28, then deposit layer of transparent conductive film, then spin coating one deck photoresist on this transparent conductive film, and carry out masking process the 6th time, utilize mask plate to carry out exposure imaging processing to the photoresist of spin coating; Then substrate 10 is carried out to etching processing, etch away substrate 10 tops, except forming resin bed, the resin bed film in other regions, then carries out ashing processing to the photoresist on substrate 10, and the photoresist that forms resin bed region on substrate 10 is removed; As shown in figure 18, remove after photoresist, on the substrate 10 that forms the second transparency conducting layer 28, form the first resin bed 29 and the second resin bed 30; Wherein, the first resin bed 29 is positioned at the first passivation layer 26 tops and source electrode 14 tops, and the second resin bed 30 is positioned at source electrode 14 tops, the second transparency conducting layer 28 tops and the second passivation layer 27 tops;
Wherein, the first resin bed 29 and the second resin bed 30 can be photosensitive resin layer or non-sense resin bed, and the thickness of the first resin bed 29 and the second resin bed 30 is 1 μ m～4 μ m.
Step 1207, forming on the substrate of the first resin bed and the second resin bed, forms the 3rd transparency conducting layer;
Concrete, in step 1206, form on the substrate 10 of the first resin bed 29 and the second resin bed 30, deposit again layer of transparent conductive film, then spin coating one deck photoresist on this transparent conductive film, and carry out masking process the 7th time, utilize mask plate to carry out exposure imaging processing to the photoresist of spin coating; Then substrate 10 is carried out to etching processing, etch away substrate 10 tops, except forming transparency conducting layer, the film in other regions, then carries out ashing processing to the photoresist on substrate 10, and the photoresist that forms electrically conducting transparent layer region on substrate 10 is removed; As shown in figure 11, after stripping photoresist, on the substrate 10 that forms the first resin bed 29 and the second resin bed 30, form the 3rd transparency conducting layer 31; Wherein, the 3rd transparency conducting layer 31 is positioned at the first resin bed 29 tops, the second resin bed 30 tops and via hole top;
Wherein, the material of the 3rd transparency conducting layer 31 is the transparent conductive materials such as ITO, IZO, ZAO, and the thickness of the 3rd transparency conducting layer 31 is 30nm～120nm.
The above, be only preferred embodiment of the present invention, is not intended to limit protection scope of the present invention, all any modifications of doing within the spirit and principles in the present invention, is equal to and replaces and improvement etc., within all should being included in protection scope of the present invention.
Claims (13)
1. a flat plate array substrate, is characterized in that, this flat plate array substrate comprises:
Substrate;
Be positioned at grid and the controlling grid scan line of substrate top;
Be positioned at the gate insulation layer of grid and controlling grid scan line top, be positioned at the active layer of gate insulation layer top and corresponding area of grid, be positioned at the ohmic contact layer of active layer top, be positioned at the first transparency conducting layer of ohmic contact layer top and gate insulation layer top;
Be positioned at drain electrode and the data wire of active layer top and corresponding area of grid, be positioned at the source electrode of the first transparency conducting layer top of active layer top and corresponding area of grid and active layer top, be positioned at the common electrode layer of gate insulation layer top and corresponding non-area of grid;
Be positioned at the first passivation layer of active layer, source electrode, drain electrode and data wire top, be positioned at the first transparency conducting layer top of corresponding non-area of grid and the second passivation layer of gate insulation layer top, between the first passivation layer and the second passivation layer, have via hole;
Be positioned at the second transparency conducting layer of the second passivation layer top and public electrode top;
Be positioned at the first resin bed of the first passivation layer top and source electrode top, be positioned at the second resin bed of source electrode top, the second transparency conducting layer top and the second passivation layer top;
Be positioned at the 3rd transparency conducting layer of the first resin bed top, the second resin bed top and via hole top.
2. a transducer, is characterized in that, this transducer comprises flat plate array substrate claimed in claim 1.
3. a manufacture method for flat plate array substrate, is characterized in that, the method comprises:
On substrate, form grid and controlling grid scan line;
Forming on the substrate of grid and controlling grid scan line, form gate insulation layer, active layer and the first transparency conducting layer;
Forming on the substrate of gate insulation layer, active layer and the first transparency conducting layer, form drain electrode and data wire, source electrode, common electrode layer;
Forming on the substrate of drain electrode and data wire, source electrode, common electrode layer, form the first passivation layer, the second passivation layer and via hole;
Forming on the substrate of the first passivation layer, the second passivation layer and via hole, form the second transparency conducting layer;
Forming on the substrate of the second transparency conducting layer, form the first resin bed and the second resin bed;
Forming on the substrate of the first resin bed and the second resin bed, form the 3rd transparency conducting layer.
4. method according to claim 3, is characterized in that, described formation on the substrate of grid and controlling grid scan line, and formation gate insulation layer, active layer and the first transparency conducting layer are:
Forming on the substrate of grid and controlling grid scan line, successive sedimentation gate insulation layer film, active layer film and transparent conductive film, and carry out masking process for the second time, form gate insulation layer, active layer and the first transparency conducting layer.
5. according to the method described in claim 3 or 4, it is characterized in that, the method also comprises:
When described formation gate insulation layer, active layer and the first transparency conducting layer, form ohmic contact layer simultaneously.
6. method according to claim 3, is characterized in that,
The material of described grid and controlling grid scan line is the single metal layers such as molybdenum, aluminium, tungsten, titanium, copper, or is at least two complex metal layers that metal forms in molybdenum, aluminium, tungsten, titanium, copper;
The thickness of described grid and controlling grid scan line is 100nm～500nm.
7. according to the method described in claim 3 or 4, it is characterized in that,
The material of described gate insulation layer is silicon nitride or silica;
The thickness of described gate insulation layer is 250nm～600nm.
8. according to the method described in claim 3 or 4, it is characterized in that,
The material of described active layer is amorphous silicon;
The thickness of described active layer 13 is 30nm～300nm.
9. method according to claim 5, is characterized in that,
The material of ohmic contact layer is phosphorus-doped amorphous silicon;
The thickness of described ohmic contact layer is 30nm～100nm.
10. method according to claim 3, is characterized in that,
The material of described the first transparency conducting layer, the second transparency conducting layer and the 3rd transparency conducting layer is nano indium tin metal oxide (ITO) or indium zinc oxide (IZO) or zinc oxide aluminum (ZAO);
The thickness of described the first transparency conducting layer, the second transparency conducting layer and the 3rd transparency conducting layer is 30nm～120nm.
11. methods according to claim 3, is characterized in that,
Described drain electrode and data wire, source electrode, common electrode layer deposit after layer of metal film on substrate, carry out forming after single exposure development treatment, etching processing simultaneously;
The material of described drain electrode and data wire, source electrode and common electrode layer is the single metal layers such as molybdenum, aluminium, tungsten, titanium, copper, or is at least two complex metal layers that metal forms in molybdenum, aluminium, tungsten, titanium, copper;
The thickness of described drain electrode and data wire, source electrode and common electrode layer is 100nm～500nm.
12. methods according to claim 3, is characterized in that,
The material of described the first passivation layer and the second passivation layer is silicon nitride or silica;
The thickness of described the first passivation layer and the second passivation layer is 150nm～2500nm.
13. methods according to claim 3, is characterized in that,
The material of described the first passivation layer and the second passivation layer is silicon nitride or silica;
The thickness of described the first passivation layer and the second passivation layer is 150nm～2500nm.
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| CN201210265470.1A CN103579219B (en) | 2012-07-27 | 2012-07-27 | The manufacture method of a kind of flat plate array substrate, transducer and flat plate array substrate |
| PCT/CN2012/086500 WO2014015624A1 (en) | 2012-07-27 | 2012-12-13 | Flatbed array substrate, sensor, and method for manufacturing flatbed array substrate |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103887235A (en) * | 2014-03-10 | 2014-06-25 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate, and display device |
| CN103928400A (en) * | 2014-03-31 | 2014-07-16 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN104617102A (en) * | 2014-12-31 | 2015-05-13 | 深圳市华星光电技术有限公司 | Array substrate and manufacturing method thereof |
| CN105448936A (en) * | 2016-01-04 | 2016-03-30 | 京东方科技集团股份有限公司 | Array base plate and preparing method thereof, display device |
| WO2017000458A1 (en) * | 2015-06-29 | 2017-01-05 | 京东方科技集团股份有限公司 | Ray detection substrate and manufacturing method therefor, ray detector |
| CN107564922A (en) * | 2017-09-19 | 2018-01-09 | 京东方科技集团股份有限公司 | Array base palte and its manufacture method, display device |
| CN111223879A (en) * | 2020-02-28 | 2020-06-02 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101656232A (en) * | 2008-08-19 | 2010-02-24 | 北京京东方光电科技有限公司 | Method for manufacturing thin film transistor array substrate |
| CN102148195A (en) * | 2010-04-26 | 2011-08-10 | 北京京东方光电科技有限公司 | TFT-LCD (thin film transistor-liquid crystal display) array substrate and manufacturing method thereof |
| CN102419499A (en) * | 2010-09-28 | 2012-04-18 | 株式会社日立显示器 | Liquid crystal display device |
| CN102566179A (en) * | 2010-11-26 | 2012-07-11 | 乐金显示有限公司 | Method for fabricating liquid crystal display device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070082644A (en) * | 2006-02-17 | 2007-08-22 | 삼성전자주식회사 | Thin film transistor panel and display device |
| US20110085121A1 (en) * | 2009-10-08 | 2011-04-14 | Hydis Technologies Co., Ltd. | Fringe Field Switching Mode Liquid Crystal Display Device and Method of Fabricating the Same |
-
2012
- 2012-07-27 CN CN201210265470.1A patent/CN103579219B/en active Active
- 2012-12-13 WO PCT/CN2012/086500 patent/WO2014015624A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101656232A (en) * | 2008-08-19 | 2010-02-24 | 北京京东方光电科技有限公司 | Method for manufacturing thin film transistor array substrate |
| CN102148195A (en) * | 2010-04-26 | 2011-08-10 | 北京京东方光电科技有限公司 | TFT-LCD (thin film transistor-liquid crystal display) array substrate and manufacturing method thereof |
| CN102419499A (en) * | 2010-09-28 | 2012-04-18 | 株式会社日立显示器 | Liquid crystal display device |
| CN102566179A (en) * | 2010-11-26 | 2012-07-11 | 乐金显示有限公司 | Method for fabricating liquid crystal display device |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103887235A (en) * | 2014-03-10 | 2014-06-25 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate, and display device |
| CN103887235B (en) * | 2014-03-10 | 2016-06-29 | 京东方科技集团股份有限公司 | A kind of array base palte and manufacture method, display device |
| CN103928400A (en) * | 2014-03-31 | 2014-07-16 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| US10014329B2 (en) | 2014-03-31 | 2018-07-03 | Boe Technology Group Co., Ltd. | Array substrate with thin film transistor and method of manufacturing the same |
| CN104617102B (en) * | 2014-12-31 | 2017-11-03 | 深圳市华星光电技术有限公司 | Array base palte and manufacturing method of array base plate |
| CN104617102A (en) * | 2014-12-31 | 2015-05-13 | 深圳市华星光电技术有限公司 | Array substrate and manufacturing method thereof |
| US10043846B2 (en) | 2015-06-29 | 2018-08-07 | Boe Technology Group Co., Ltd. | Radiographic detection substrate and manufacture method thereof, radiographic detection device |
| WO2017000458A1 (en) * | 2015-06-29 | 2017-01-05 | 京东方科技集团股份有限公司 | Ray detection substrate and manufacturing method therefor, ray detector |
| CN105448936A (en) * | 2016-01-04 | 2016-03-30 | 京东方科技集团股份有限公司 | Array base plate and preparing method thereof, display device |
| CN105448936B (en) * | 2016-01-04 | 2019-07-23 | 京东方科技集团股份有限公司 | A kind of array substrate and preparation method thereof, display device |
| CN107564922A (en) * | 2017-09-19 | 2018-01-09 | 京东方科技集团股份有限公司 | Array base palte and its manufacture method, display device |
| US10534233B2 (en) | 2017-09-19 | 2020-01-14 | Boe Technology Group Co., Ltd. | Array substrate, method for manufacturing the same, display device |
| CN111223879A (en) * | 2020-02-28 | 2020-06-02 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
| CN111223879B (en) * | 2020-02-28 | 2022-10-18 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
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| Publication number | Publication date |
|---|---|
| WO2014015624A1 (en) | 2014-01-30 |
| CN103579219B (en) | 2016-03-16 |
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