CN202796954U - Planar array substrate and sensor - Google Patents
Planar array substrate and sensor Download PDFInfo
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- CN202796954U CN202796954U CN 201220370699 CN201220370699U CN202796954U CN 202796954 U CN202796954 U CN 202796954U CN 201220370699 CN201220370699 CN 201220370699 CN 201220370699 U CN201220370699 U CN 201220370699U CN 202796954 U CN202796954 U CN 202796954U
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Abstract
The utility model discloses a planar array substrate and a sensor. The planar array substrate comprises the components as following: a substrate and a grid electrode and a grid electrode scan line over the substrate; a grid insulation layer over the grid electrode and the grid electrode scan line; a first active layer arranged over the grid insulation layer and corresponding to a grid electrode area; a source/drain electrode layer arranged over the first active layer and corresponding to the grid electrode area; a second active layer arranged over the grid insulation layer and corresponding to a non-grid electrode area; a common electrode layer over the second active layer; a first active layer and a first passivation layer over the source/drain electrode layer; a second active layer and a second passivation layer over the grid insulation layer; a through hole between the first passivation layer and the second passivation layer; the second passivation layer and a first transparent conducting layer over the through hole; the first passivation layer and a resin layer over the first transparent conducting layer; and the resin layer and a second transparent conducting layer on a through hole zone. According to the technology scheme provided in the utility model, the number of applied mask layers is reduced, and production power of equipment is raised.
Description
Technical field
The utility model relates to Thin Film Transistor (TFT) (TFT, Thin Film Transistor) manufacturing technology and transducer manufacturing technology, relates in particular to a kind of flat plate array substrate and transducer.
Background technology
In " major technologies and equipment autonomous innovation guidance list " that on December 15th, 2009, the Ministry of Industry and Information Technology, the Ministry of Science and Technology, the Ministry of Finance, State Assets Administration Committee promulgated, project 12.3.5 is " product newly developed " with " non-crystalline silicon tft X-ray plane transducer " project verification.Four ministries and commissions are thought in the medical market, the non-crystalline silicon tft X-ray plane capacity sensor about 18,000,000,000 of township hospital (about 60,000), if the mortality according to 10 years, the magnitude of recruitment of later annual non-crystalline silicon tft X-ray plane transducer in market is 1,800,000,000, so TFT X-ray plane transducer has unprecedented application prospect.
But, present domestic technology and the manufacturing process that does not have this respect, the production market of non-crystalline silicon tft X-ray plane transducer is by external oligopoly.At present, the manufacturing process of non-crystalline silicon tft X-ray plane transducer needs left and right sides masking process usually 10 times, and the technical process of tft array generally comprises masking process 4 to 6 times.
At present, the manufacturing of non-crystalline silicon tft X-ray plane transducer mainly comprises the steps:
Step 1 as shown in Figure 1, in the masking process, forms grid and controlling grid scan line 11 at substrate 10 for the first time;
Step 2 as shown in Figure 2, for the second time in the masking process, forms gate insulation layers 12 at substrate 10 and the grid that forms and controlling grid scan line 11, then above described gate insulation layer 12 and the zone corresponding with area of grid, forms active layer 13;
Step 3 as shown in Figure 3, for the third time in the masking process, is peeled off the grid of the neighboring area of substrate 10 and the gate insulation layer 12 on the controlling grid scan line 11, exposes grid and the controlling grid scan line 11 of the neighboring area of substrate 10;
Step 4 as shown in Figure 4, in the 4th masking process, forms described source/drain electrode layer and comprises source electrode 14 and drain electrode 15 above active layer 13; Above described gate insulation layer 12, form common electrode layer 16;
Step 5 as shown in Figure 5, in the 5th masking process, above active layer 13, source-drain electrode layer and common electrode layer 16, forms passivation layer 17;
Step 6 as shown in Figure 6, in the 6th masking process, is carried out the nano indium tin metal oxide first time (ITO, Indium Tin Oxides) mask process, above common electrode layer 16 and passivation layer 17, forms ITO conductive layer 18;
Step 7 as shown in Figure 7, in the 7th masking process, is carried out ITO insulation first time mask process, on passivation layer 17 and ITO conductive layer 18 upper stratas, forms ITO insulating barrier 19; Form a via hole at source electrode 14;
Step 8 as shown in Figure 8, in the 8th masking process, is carried out the ITO mask process second time, on ITO insulating barrier 19 and via hole, forms the 2nd ITO conductive layer 20;
Step 9, as shown in Figure 9, in the 9th masking process, above the ITO insulating barrier 19, and the 2nd ITO conductive layer 20 above zone except via hole, formation resin bed 21;
Therefore, non-crystalline silicon tft X-ray plane transducer needs 10 masking process just can finish usually at present, and manufacture process is very complicated, and cost is higher.
The utility model content
In view of this, main purpose of the present utility model is to provide a kind of flat plate array substrate and transducer, can reduce the mask plate quantity of use, improves equipment capacity.
For achieving the above object, the technical solution of the utility model is achieved in that
The utility model provides a kind of flat plate array substrate, comprising:
Grid and the controlling grid scan line of substrate and described substrate top;
The gate insulation layer of described grid and controlling grid scan line top, above described gate insulation layer and the first active layer of corresponding area of grid, source/the drain electrode layer of described the first active layer top and corresponding area of grid, and the second active layer of described gate insulation layer top and corresponding non-area of grid, the common electrode layer of described the second active layer top;
The first passivation layer of described the first active layer and described source/drain electrode layer top, the second passivation layer of described the second active layer and gate insulation layer top, the via hole between described the first passivation layer and described the second passivation layer;
The first transparency conducting layer of described the second passivation layer and described via hole top;
The resin bed of described the first passivation layer and described the first transparency conducting layer top;
The second transparency conducting layer on described resin bed and the described via area.
In the above-mentioned flat plate array substrate, the material of described grid and controlling grid scan line is the single metal layer of molybdenum, aluminium, tungsten, titanium, copper, or is at least two complex metal layers that metal forms in molybdenum, aluminium, tungsten, titanium, the copper;
The thickness of described grid and controlling grid scan line is 100nm～500nm.
In the above-mentioned flat plate array substrate, the material of described source/drain electrode layer and described common electrode layer is the single metal layers such as molybdenum, aluminium, tungsten, titanium, copper, or is at least two complex metal layers that metal forms in molybdenum, aluminium, tungsten, titanium, the copper;
The thickness of described source/drain electrode layer and described common electrode layer is 100nm～500nm.
In the above-mentioned flat plate array substrate, the material of described gate insulation layer is insulating material;
Described insulating material is silicon nitride or silica;
The thickness of described gate insulation layer is 250nm～600nm.
In the above-mentioned flat plate array substrate, the material of described the first active layer and described the second active layer is amorphous silicon;
The thickness of described the first active layer and described the second active layer is 30nm～300nm.
In the above-mentioned flat plate array substrate, the material of described the first passivation layer and described the second passivation layer is silicon nitride or silica;
The thickness of described the first passivation layer and described the second passivation layer is 150nm～2500nm.
In the above-mentioned flat plate array substrate, the material of described the first transparency conducting layer is transparent conductive material;
Described transparent conductive material is ITO or IZO or ZAO;
The thickness of the first transparency conducting layer is 30nm～120nm.
In the above-mentioned flat plate array substrate, the material of described resin bed is photosensitive material or non-photosensitive material;
The thickness of described resin bed is 1 μ m～4 μ m.
In the above-mentioned flat plate array substrate, the material of described the second transparency conducting layer is transparent conductive material;
Described transparent conductive material is ITO or IZO or ZAO;
The thickness of described the second transparency conducting layer is 30nm～120nm.
The utility model also provides a kind of transducer, and this transducer comprises above-mentioned flat plate array substrate.
Flat plate array substrate and transducer that the utility model provides, grid and the controlling grid scan line of substrate and described substrate top; The gate insulation layer of described grid and controlling grid scan line top, above described gate insulation layer and the first active layer of corresponding area of grid, source/the drain electrode layer of described the first active layer top and corresponding area of grid, and the second active layer of described gate insulation layer top and corresponding non-area of grid, the common electrode layer of described the second active layer top; The first passivation layer of described the first active layer and described source/drain electrode layer top, the second passivation layer of described the second active layer and gate insulation layer top, the via hole between described the first passivation layer and described the second passivation layer; The first transparency conducting layer of described the second passivation layer and described via hole top; The resin bed of described the first passivation layer and described the first transparency conducting layer top; The second transparency conducting layer on described resin bed and the described via area, so, will with the same layer metal level common electrode layer of source/drain electrode layer as the storage capacitance pole plate, altogether carry out six masking process and can finish the manufacturing process of transducer middle plateform array base palte, therefore, can reduce the mask plate quantity of use, improve equipment capacity, improve the product yields.
Description of drawings
Fig. 1 is the schematic cross-section of masking process metacoxal plate for the first time in the prior art;
Fig. 2 is the schematic cross-section of masking process metacoxal plate for the second time in the prior art;
Fig. 3 is the schematic cross-section of masking process metacoxal plate for the third time in the prior art;
Fig. 4 is the schematic cross-section of the 4th masking process metacoxal plate in the prior art;
Fig. 5 is the schematic cross-section of the 5th masking process metacoxal plate in the prior art;
Fig. 6 is the schematic cross-section of the 6th masking process metacoxal plate in the prior art;
Fig. 7 is the schematic cross-section of the 7th masking process metacoxal plate in the prior art;
Fig. 8 is the schematic cross-section of the 8th masking process metacoxal plate in the prior art;
Fig. 9 is the schematic cross-section of the 9th masking process metacoxal plate in the prior art;
Figure 10 is the schematic cross-section of TFT X-ray plane transducer in the prior art;
Figure 11 is the schematic cross-section of the utility model flat plate array substrate;
Figure 12 is for the first time schematic cross-section of masking process metacoxal plate of the utility model;
Figure 13 is for the second time schematic cross-section of masking process metacoxal plate of the utility model;
Figure 14 is for the third time schematic cross-section of masking process metacoxal plate of the utility model;
Figure 15 is the schematic cross-section of the 4th masking process metacoxal plate of the utility model;
Figure 16 is the schematic cross-section of the 5th masking process metacoxal plate of the utility model.
Description of reference numerals:
10: substrate
11: grid and controlling grid scan line
12: gate insulation layer
13: active layer
14: source electrode
15: drain electrode
16: common electrode layer
17: passivation layer
The 18:ITO conductive layer
The 19:ITO insulating barrier
20: the two ITO conductive layers
21: resin bed
22: the three ITO conductive layers
23: the first active layers
24: the second active layers
25: the first passivation layers
26: the second passivation layers
27: the first transparency conducting layers
28: the second transparency conducting layers
Embodiment
Below by drawings and the specific embodiments the utility model is described in further detail again.
The utility model provides a kind of flat plate array substrate, and Figure 11 is the schematic cross-section of the utility model flat plate array substrate, and as shown in figure 11, this flat plate array substrate comprises:
The grid of substrate 10 and substrate 10 tops and controlling grid scan line 11;
The gate insulation layer 12 of grid and controlling grid scan line 11 tops, above gate insulation layer 12 and the first active layer 23 of corresponding area of grid, source/the drain electrode layer of the first active layer 23 tops and corresponding area of grid (comprising source electrode 14 and drain electrode 15), and the common electrode layer 16 of the second active layer 24, the second active layers 24 tops of gate insulation layer 12 tops and corresponding non-area of grid;
The first passivation layer 25 of the first active layer 23 of corresponding area of grid and source/drain electrode layer top, the second passivation layer 26, the first passivation layers 25 of the second active layer 24 of corresponding non-area of grid and gate insulation layer 12 tops and the via hole between the second passivation layer 26;
The first transparency conducting layer 27 of the second passivation layer 26 and via hole top;
The resin bed 21 of the first passivation layer 25 and the first transparency conducting layer 27 tops;
The second transparency conducting layer 28 on resin bed 21 and the via area.
Wherein, the material of grid and controlling grid scan line 11 can be the single metal layers such as molybdenum, aluminium, tungsten, titanium, copper, also can be the complex metal layers that form of at least two metals wherein, and the thickness of grid and controlling grid scan line 11 is 100nm～500nm;
The material of source/drain electrode layer can be the single metal layers such as molybdenum, aluminium, tungsten, titanium, copper, also can be the complex metal layers that form of at least two metals wherein, and the thickness of source/drain electrode layer is 100nm～500nm; The material of gate insulation layer 12 can be the insulating material such as silicon nitride or silica, and the thickness of gate insulation layer 12 is 250nm～600nm; The material of the first active layer 23 and the second active layer 24 is amorphous silicon, this amorphous silicon claims again amorphous silicon, it is a kind of form of elemental silicon, amorphous silicon has the microcrystal of brownish black or grey black, element silicon in the amorphous silicon does not have complete diamond structure cell, purity is not high, and the fusing point of amorphous silicon, density and hardness also are starkly lower than crystalline silicon; The thickness of the first active layer 23 and the second active layer 24 is 30nm～300nm; The material of common electrode layer 16 can be the single metal layers such as molybdenum, aluminium, tungsten, titanium, copper, also can be the complex metal layers that form of at least two metals wherein, and the thickness of common electrode layer 16 is 100nm～500nm;
The material of the first passivation layer 25 and the second passivation layer 26 is silicon nitride or silica commonly used, and the thickness of the first passivation layer 25 and the second passivation layer 26 is 150nm～2500nm;
The material of the first transparency conducting layer 27 is ITO or the transparent conductive materials such as indium zinc oxide (IZO, InxZnyOz) or zinc oxide aluminum (ZAO, ZnxAlyOz), and the thickness of the first transparency conducting layer 27 is 30nm～120nm;
The material of the second transparency conducting layer 28 is the transparent conductive materials such as ITO, IZO, ZAO, and the thickness of the second transparency conducting layer 28 is 30nm～120nm.
The first transparency conducting layer 27 and the second transparency conducting layer 28 all utilize transparent conductive material, the first transparency conducting layer 27 is used for and the common electrode layer 16 common storage capacitances that form, the second transparency conducting layer 28 is collecting electrode, is used for receiving the electronics that X ray inductive material coating produces.
The utility model also provides a kind of transducer, and this transducer comprises above-mentioned flat plate array substrate.
The technological process of making flat plate array substrate shown in Figure 11 comprises:
Step 1 as shown in figure 12, in first time masking process, forms grid and controlling grid scan line 11 above substrate 10.
Step 2, as shown in figure 13, in second time masking process, above grid and controlling grid scan line 11, form gate insulation layer 12, above gate insulation layer 12 and corresponding area of grid form the first active layer 23, above the first active layer 23 and corresponding area of grid form source/drain electrode layer, this source/drain electrode layer comprises source electrode 14 and drain electrode 15); Above gate insulation layer 12 and corresponding non-area of grid form the second active layer 24, above the second active layer 24, form common electrode layer 16.
Step 3, as shown in figure 14, in masking process for the third time, above the first active layer 23 of corresponding area of grid and source/drain electrode layer, form the first passivation layer 25, forming the second passivation layer 26 above the second active layer 24 of the non-area of grid of correspondence and gate insulation layer 12, is via hole between described the first passivation layer 25 and the second passivation layer 26.
Step 4 as shown in figure 15, in the 4th masking process, forms the first transparency conducting layer 27 above the second passivation layer 26 and via hole.
Step 5 as shown in figure 16, in the 5th masking process, forms resin bed 21 above the first passivation layer 25 and the first transparency conducting layer 27.
Step 6 as shown in figure 11, in the 6th masking process, forms the second transparency conducting layer 28 at resin bed 21 and via area, finishes the making flow process of flat plate array substrate.
The above; it only is preferred embodiment of the present utility model; be not be used to limiting protection range of the present utility model, all any modifications of within spirit of the present utility model and principle, doing, be equal to and replace and improvement etc., all should be included within the protection range of the present utility model.
Claims (10)
1. a flat plate array substrate is characterized in that, this flat plate array substrate comprises:
Grid and the controlling grid scan line of substrate and described substrate top;
The gate insulation layer of described grid and controlling grid scan line top, above described gate insulation layer and the first active layer of corresponding area of grid, source/the drain electrode layer of described the first active layer top and corresponding area of grid, and the second active layer of described gate insulation layer top and corresponding non-area of grid, the common electrode layer of described the second active layer top;
The first passivation layer of described the first active layer and described source/drain electrode layer top, the second passivation layer of described the second active layer and gate insulation layer top, the via hole between described the first passivation layer and described the second passivation layer;
The first transparency conducting layer of described the second passivation layer and described via hole top;
The resin bed of described the first passivation layer and described the first transparency conducting layer top;
The second transparency conducting layer on described resin bed and the described via area.
2. flat plate array substrate according to claim 1 is characterized in that,
The material of described grid and controlling grid scan line is the single metal layer of molybdenum, aluminium, tungsten, titanium, copper, or is at least two complex metal layers that metal forms in molybdenum, aluminium, tungsten, titanium, the copper;
The thickness of described grid and controlling grid scan line is 100nm～500nm.
3. flat plate array substrate according to claim 1 is characterized in that,
The material of described source/drain electrode layer and described common electrode layer is the single metal layers such as molybdenum, aluminium, tungsten, titanium, copper, or is at least two complex metal layers that metal forms in molybdenum, aluminium, tungsten, titanium, the copper;
The thickness of described source/drain electrode layer and described common electrode layer is 100nm～500nm.
4. flat plate array substrate according to claim 1 is characterized in that,
The material of described gate insulation layer is insulating material;
Described insulating material is silicon nitride or silica;
The thickness of described gate insulation layer is 250nm～600nm.
5. flat plate array substrate according to claim 1 is characterized in that,
The material of described the first active layer and described the second active layer is amorphous silicon;
The thickness of described the first active layer and described the second active layer is 30nm～300nm.
6. flat plate array substrate according to claim 1 is characterized in that,
The material of described the first passivation layer and described the second passivation layer is silicon nitride or silica;
The thickness of described the first passivation layer and described the second passivation layer is 150nm～2500nm.
7. flat plate array substrate according to claim 1 is characterized in that,
The material of described the first transparency conducting layer is transparent conductive material;
Described transparent conductive material is ITO or IZO or ZAO;
The thickness of the first transparency conducting layer is 30nm～120nm.
8. flat plate array substrate according to claim 1 is characterized in that,
The material of described resin bed is photosensitive material or non-photosensitive material;
The thickness of described resin bed is 1 μ m～4 μ m.
9. flat plate array substrate according to claim 1 is characterized in that,
The material of described the second transparency conducting layer is transparent conductive material;
Described transparent conductive material is ITO or IZO or ZAO;
The thickness of described the second transparency conducting layer is 30nm～120nm.
10. a transducer is characterized in that, this transducer comprises each described flat plate array substrate of claim 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN 201220370699 CN202796954U (en) | 2012-07-27 | 2012-07-27 | Planar array substrate and sensor |
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|---|---|---|---|
| CN 201220370699 CN202796954U (en) | 2012-07-27 | 2012-07-27 | Planar array substrate and sensor |
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| CN202796954U true CN202796954U (en) | 2013-03-13 |
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| CN 201220370699 Expired - Lifetime CN202796954U (en) | 2012-07-27 | 2012-07-27 | Planar array substrate and sensor |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106371253A (en) * | 2016-08-26 | 2017-02-01 | 武汉华星光电技术有限公司 | Array substrate, liquid crystal display panel and manufacturing method |
| WO2017177618A1 (en) * | 2016-04-15 | 2017-10-19 | 京东方科技集团股份有限公司 | Sensor and manufacturing method therefor, and electronic device |
-
2012
- 2012-07-27 CN CN 201220370699 patent/CN202796954U/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017177618A1 (en) * | 2016-04-15 | 2017-10-19 | 京东方科技集团股份有限公司 | Sensor and manufacturing method therefor, and electronic device |
| US10269837B2 (en) | 2016-04-15 | 2019-04-23 | Boe Technology Group Co., Ltd. | Sensor, manufacturing method thereof and electronic device |
| RU2710383C1 (en) * | 2016-04-15 | 2019-12-26 | Боэ Текнолоджи Груп Ко., Лтд. | Sensor, manufacturing method thereof and electronic device |
| CN106371253A (en) * | 2016-08-26 | 2017-02-01 | 武汉华星光电技术有限公司 | Array substrate, liquid crystal display panel and manufacturing method |
| WO2018035973A1 (en) * | 2016-08-26 | 2018-03-01 | 武汉华星光电技术有限公司 | Array substrate, liquid crystal display panel, and manufacturing method |
| US10114259B2 (en) | 2016-08-26 | 2018-10-30 | Wuhan China Star Optoelectronics Technology Co., Ltd | Array substrate, liquid crystal display panel and manufacturing method |
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Legal Events
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| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY Effective date: 20150626 Owner name: JINGDONGFANG SCIENCE AND TECHNOLOGY GROUP CO., LTD Free format text: FORMER OWNER: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY CO., LTD. Effective date: 20150626 |
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Effective date of registration: 20150626 Address after: 100015 Jiuxianqiao Road, Beijing, No. 10, No. Patentee after: BOE TECHNOLOGY GROUP Co.,Ltd. Patentee after: BEIJING BOE OPTOELECTRONICS TECHNOLOGY Co.,Ltd. Address before: 100176 Beijing city in Western Daxing District economic and Technological Development Zone, Road No. 8 Patentee before: BEIJING BOE OPTOELECTRONICS TECHNOLOGY Co.,Ltd. |
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Granted publication date: 20130313 |