CN106784013A - A kind of thin film transistor (TFT), array base palte and display device - Google Patents
A kind of thin film transistor (TFT), array base palte and display device Download PDFInfo
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- CN106784013A CN106784013A CN201611071426.1A CN201611071426A CN106784013A CN 106784013 A CN106784013 A CN 106784013A CN 201611071426 A CN201611071426 A CN 201611071426A CN 106784013 A CN106784013 A CN 106784013A
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- 239000010409 thin film Substances 0.000 title claims abstract description 35
- 229910052751 metal Inorganic materials 0.000 claims abstract description 108
- 239000002184 metal Substances 0.000 claims abstract description 108
- 230000004888 barrier function Effects 0.000 claims abstract description 96
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 26
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 26
- 150000004767 nitrides Chemical class 0.000 claims abstract description 26
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 6
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 20
- 229910010282 TiON Inorganic materials 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 239000010408 film Substances 0.000 abstract description 47
- 239000000853 adhesive Substances 0.000 abstract description 18
- 230000001070 adhesive effect Effects 0.000 abstract description 18
- 239000000463 material Substances 0.000 abstract description 17
- 239000010949 copper Substances 0.000 description 132
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 15
- 239000000758 substrate Substances 0.000 description 15
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 15
- 239000012212 insulator Substances 0.000 description 13
- 238000002161 passivation Methods 0.000 description 10
- MEYZYGMYMLNUHJ-UHFFFAOYSA-N tunicamycin Natural products CC(C)CCCCCCCCCC=CC(=O)NC1C(O)C(O)C(CC(O)C2OC(C(O)C2O)N3C=CC(=O)NC3=O)OC1OC4OC(CO)C(O)C(O)C4NC(=O)C MEYZYGMYMLNUHJ-UHFFFAOYSA-N 0.000 description 10
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 9
- 239000011787 zinc oxide Substances 0.000 description 9
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- AKJVMGQSGCSQBU-UHFFFAOYSA-N zinc azanidylidenezinc Chemical compound [Zn++].[N-]=[Zn].[N-]=[Zn] AKJVMGQSGCSQBU-UHFFFAOYSA-N 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000012528 membrane Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 239000004821 Contact adhesive Substances 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910000765 intermetallic Inorganic materials 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- 150000003752 zinc compounds Chemical class 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 description 1
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides a kind of thin film transistor (TFT), array base palte and display device, the thin film transistor (TFT) includes Cu wiring layers, the Cu wiring layers include gate electrode and/or source-drain electrode, an at least surface of the Cu wiring layers is provided with Cu barrier layers, and the Cu barrier layers are using any one or more formation in metal oxide, metal nitride and metal oxynitride.In the embodiment of the present invention, Cu barrier layers are set in Cu wiring layers upper surface and/or lower surface, are spread up and/or down with the Cu for preventing Cu wiring layers.And, the conductive energy of material used using Cu barrier layers does not influence the normal work of Cu wiring layers, in addition, the material adhesive force of those types is preferable, by increasing capacitance it is possible to increase the adhesive force between Cu wiring layers and other film layers.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of thin film transistor (TFT), array base palte and display device.
Background technology
In display technology field, with becoming increasingly popular for large scale and driving frequency product high, low-resistance Cu (copper)
Layout techniques more and more attract attention, and each panel vendor has carried out Cu technological development one after another, to lift production capacity and yield,
Gate electrode, grid line, source electrode and drain electrode and data wire in array base palte etc. are made for example with Cu.However, Cu is connected up
The contact poor adhesive force that layer there is a problem of with glass substrate and active layer, meanwhile, Cu is under certain conditions as certain
At a temperature of, can spread up or down, for example, when gate electrode is made using Cu, Cu is possible to that gate insulator can be expanded to
(GI), or even active layer, so as to have a strong impact on device property.
The content of the invention
In view of this, the present invention provides a kind of thin film transistor (TFT), array base palte and display device, to solve existing Cu cloth
Line layer contact poor adhesive force and the easily problem of diffusion.
In order to solve the above technical problems, the present invention provides a kind of thin film transistor (TFT), including Cu wiring layers, the Cu wiring layers
Including gate electrode and/or source-drain electrode, an at least surface of the Cu wiring layers is provided with Cu barrier layers, and the Cu barrier layers are adopted
Formed with any one or more in metal oxide, metal nitride and metal oxynitride.
Preferably, the metal oxide includes：TiO and ZnO.
Preferably, the metal nitride includes：TiN and ZnN.
Preferably, the metal oxynitride includes：TiON, TiNO, ZnON and ZnNO.
Preferably, the thickness on the Cu barrier layers is 50-1000A.
The present invention also provides a kind of array base palte, including Cu wiring layers, and the Cu wiring layers include barrier metal layer and/or source
Leakage metal level, an at least surface of the Cu wiring layers is provided with Cu barrier layers, and the Cu barrier layers use metal oxide, gold
Any one or more formation in category nitride and metal oxynitride.
Preferably, the metal oxide includes：TiO and ZnO.
Preferably, the metal nitride includes：TiN and ZnN.
Preferably, the metal oxynitride includes：TiON, TiNO, ZnON and ZnNO.
Preferably, the thickness on the Cu barrier layers is 50-1000A.
The present invention also provides a kind of display device, including above-mentioned array base palte.
Above-mentioned technical proposal of the invention has the beneficial effect that：
In the embodiment of the present invention, Cu barrier layers are set in Cu wiring layers upper surface and/or lower surface, to prevent Cu wiring layers
Cu spread up and/or down.And, the conductive energy of material used using Cu barrier layers does not influence Cu wiring layers
Normal work, in addition, the material adhesive force of those types is preferable, by increasing capacitance it is possible to increase attached between Cu wiring layers and other film layers
Put forth effort.
Brief description of the drawings
Fig. 1 is the structural representation of the array base palte of one embodiment of the invention.
Specific embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
Accompanying drawing, the technical scheme to the embodiment of the present invention is clearly and completely described.Obviously, described embodiment is this hair
Bright a part of embodiment, rather than whole embodiments.Based on described embodiments of the invention, ordinary skill
The every other embodiment that personnel are obtained, belongs to the scope of protection of the invention.
Unless otherwise defined, technical term used herein or scientific terminology should be in art of the present invention and have
The ordinary meaning that the personage of general technical ability is understood.Used in present patent application specification and claims " the
One ", " second " and similar word are not offered as any order, quantity or importance, and are used only to distinguish different
Part.Equally, the similar word such as " one " or " " does not indicate that quantity is limited yet, but expression has at least one.
The similar word such as " connection " or " connected " is not limited to physics or machinery connection, and can be including electrical
Connection, either directly still indirectly." on ", D score, "left", "right" etc. be only used for representing relative position relation, work as quilt
After the absolute position of description object changes, then the relative position relation also correspondingly changes.
To solve the problems, such as the contact poor adhesive force of the Cu wiring layers in existing thin film transistor (TFT) and easily diffusion, the present invention is real
Apply example and a kind of thin film transistor (TFT), including Cu wiring layers are provided, the Cu wiring layers include gate electrode and/or source-drain electrode, wherein,
An at least surface of the Cu wiring layers is provided with Cu barrier layers, and the Cu barrier layers use metal oxide, metal nitride
With any one or more formation in metal oxynitride.
The Cu wiring layers are made using Cu metals or Cu alloys.
Metal oxide, metal nitride and metal oxynitride are conductive, and contact adhesive force is preferable.
(refer to a table of the underlay substrate away from thin film transistor (TFT) in Cu wiring layers upper surface in the embodiment of the present invention
Face) and/or lower surface (referring to a surface of the underlay substrate near thin film transistor (TFT)) setting Cu barrier layers, to prevent Cu cloth
The Cu of line layer spreads up and/or down.
And, formed using any one or more material in metal oxide, metal nitride and metal oxynitride,
The conductive energy of material of those types, the normal work of Cu wiring layers is not influenceed, in addition, the material of those types is attached
Put forth effort preferably, by increasing capacitance it is possible to increase the adhesive force between Cu wiring layers and other film layers of thin film transistor (TFT).
Preferably, two surfaces of the Cu wiring layers are respectively provided with Cu barrier layers.
Preferably, the figure on the Cu barrier layers is identical with the figure of the Cu wiring layers, to ensure that residence is completely covered
State Cu wiring layers.Certainly, the size of the figure on the Cu barrier layers can also be more than the size of the figure of the Cu wiring layers.
Preferably, the metal oxide includes：TiO (titanium oxide) and ZnO (zinc oxide).
Preferably, the metal nitride includes：TiN (titanium nitride) and ZnN (zinc nitride).
Preferably, the metal oxynitride includes：TiON (titanium oxynitrides), TiNO (titanium oxynitride), ZnON (nitrogen oxidations
Zinc) and ZnNO (oxynitriding zinc).
Above-mentioned given example is titanium, zinc compound, certainly, in some other embodiment of the invention, is also not excluded for
Using other kinds of metallic compound.
The film layer setting on the Cu barrier layers can include following several：
1) Cu barrier layers are individual layer film layer structure.
The individual layer film layer mechanism is formed using one of metal oxide, metal nitride or metal oxynitride；Or
Person
The individual layer film layer mechanism is using any two kinds or three in metal oxide, metal nitride and metal oxynitride
Material is planted to be mixed to form.
2) Cu barrier layers are stratified film structure.
So-called stratified film structure is at least two-layer film layer structure.
The stratified film structure includes following several situations again：
21) the multiple film layers in the stratified film structure are by by metal oxide, metal nitride or metal oxynitride
Thing is formed.
I.e. multiple film layers are formed by by metal oxide；Or
Multiple film layers are formed by by metal nitride；Or
Multiple film layers are formed by by metal oxynitride.
When multiple film layers by metal oxide by forming, multiple film layers can be different types of metal oxidation
Thing, such as Cu barrier layers include two-layer film layer structure, wherein tunic layer is formed using TiO, another tunic layer uses ZnO shapes
Into.Certainly, the metal oxide of same type can also be included in multiple film layers, such as Cu barrier layers include trilamellar membrane layer
Structure, wherein ground floor film layer is formed using TiO, and second layer film layer is formed using ZnO, and third layer film layer is formed using TiO.
Likewise, when multiple film layers by metal nitride by forming, multiple film layers can be different types of gold
Category nitride, can also include the metal nitride of same type in multiple film layers.
When multiple film layers by metal oxynitride by forming, multiple film layers can be different types of metal nitrogen oxygen
Compound, can also include the metal oxynitride of same type in multiple film layers.
22) the multiple film layers in the stratified film structure use metal oxide, metal nitride and metal oxynitride
In different types of material formed.
For example, Cu barrier layers include two-layer film layer structure, wherein tunic layer is formed using TiO, another tunic layer is used
TiN is formed.Again for example, Cu barrier layers include trilamellar membrane Rotating fields, wherein tunic layer is formed using TiO, tunic layer is used
TiN is formed, and tunic layer is formed using TiON.
23) at least there are two film layers in the multiple film layers in the stratified film structure, two film layers use metal oxygen
The material of the identical type in compound, metal nitride and metal oxynitride.
For example, Cu barrier layers include trilamellar membrane Rotating fields, wherein tunic layer is formed using TiO, tunic layer uses TiN
Formed, tunic layer is formed using ZnO, and TiO and ZnO belongs to the material of identical type, equal metal oxide.Again for example, Cu
Barrier layer includes trilamellar membrane Rotating fields, and wherein ground floor film layer is formed using TiO, and second layer film layer is formed using TiN, third layer
Film layer is formed using TiO, and ground floor film layer and third layer film layer are formed using TiO.
24) in the multiple film layers in the stratified film structure, at least in the presence of a film layer, the film layer is aoxidized using metal
It is mixed to form for any two or three in thing, metal nitride and metal oxynitride.
Thin film transistor (TFT) in the embodiment of the present invention can be top gate type thin film transistor, or bottom gate thin film is brilliant
Body pipe.
Effect to Cu barrier layers so that thin film transistor (TFT) is as top gate type thin film transistor as an example below is illustrated.
When the Cu wiring layers in above-described embodiment are gate electrode, Cu barrier layers can be set in the upper surface of gate electrode,
Prevent the Cu in gate electrode from being spread to gate insulator and active layer direction.Simultaneously, additionally it is possible to increase gate electrode and gate insulator
Adhesive force between layer.Now, the Cu barrier layers are properly termed as cap layers.
Furthermore it is also possible to the lower surface in gate electrode sets Cu barrier layers, the Cu in gate electrode is prevented to thin film transistor (TFT)
Underlay substrate (usually glass substrate) direction diffusion.Simultaneously, additionally it is possible to increase the attachment between gate electrode and underlay substrate
Power.Now, the Cu barrier layers are properly termed as buffer layers
When the Cu wiring layers in above-described embodiment are source electrode and drain electrode, can be in source electrode and the upper table of drain electrode
Face sets Cu barrier layers.
Furthermore it is also possible to the lower surface in source electrode and drain electrode sets Cu barrier layers, in preventing source electrode and drain electrode
Cu to active layer direction spread.Simultaneously, additionally it is possible to increase the adhesive force between source electrode and drain electrode and active layer.Now,
The Cu barrier layers are properly termed as buffer layers.
The thickness on the Cu barrier layers in the embodiment of the present invention can be 50-1000A (angstrom), preferably 100-800A, thickness
Degree set it is too thin if, the lack of homogeneity of forming thin film is unfavorable for the performance of Cu barrier functions；It is too thick that thickness is set
Words, influence the resistance of Cu wiring layers, while also increasing the cost of material.
The thin film transistor (TFT) of the embodiment of the present invention can be ESL types thin film transistor (TFT), or BCE types it is thin
Film transistor.
The embodiment of the present invention also provides a kind of array base palte, including Cu wiring layers, and the Cu wiring layers include barrier metal layer
And/or Source and drain metal level, an at least surface of the Cu wiring layers is provided with Cu barrier layers, and the Cu barrier layers use metal oxygen
Any one or more formation in compound, metal nitride and metal oxynitride.
Wherein, barrier metal layer includes gate electrode and/or grid line.
Source and drain metal level includes source-drain electrode and/or data wire.
The Cu wiring layers are made using Cu metals or Cu alloys.
Metal oxide, metal nitride and metal oxynitride are conductive, and contact adhesive force is preferable.
In the embodiment of the present invention, Cu wiring layers upper surface (referring to a surface of the underlay substrate away from array base palte)
And/or lower surface (referring to a surface of the underlay substrate near array base palte) sets Cu barrier layers, to prevent Cu wiring layers
Cu spread up and/or down.
And, formed using any one or more material in metal oxide, metal nitride and metal oxynitride,
The conductive energy of material of those types, the normal work of Cu wiring layers is not influenceed, in addition, the material of those types is attached
Put forth effort preferably, by increasing capacitance it is possible to increase the adhesive force between Cu wiring layers and other film layers of array base palte.
Preferably, two surfaces of the Cu wiring layers are respectively provided with Cu barrier layers.
Preferably, the figure on the Cu barrier layers is identical with the figure of the Cu wiring layers, to ensure that residence is completely covered
State Cu wiring layers.Certainly, the size of the figure on the Cu barrier layers can also be more than the size of the figure of the Cu wiring layers, only
If guarantee covers all Cu wiring layers.
Preferably, the metal oxide includes：TiO and ZnO.
Preferably, the metal nitride includes：TiN and ZnN.
Preferably, the metal oxynitride includes：TiON, TiNO, ZnON and ZnNO.
Above-mentioned given example is titanium, zinc compound, certainly, in some other embodiment of the invention, is also not excluded for
Using other kinds of metallic compound.
Likewise, the film layer on the Cu barrier layers is set described in the embodiment that can include above-mentioned thin film transistor (TFT)
1) with 2) two kinds of situations, it is not repeated.
The thickness on the Cu barrier layers in the embodiment of the present invention can be 50-1000A, and preferably 100-800A, thickness sets
Put it is too thin if, the lack of homogeneity of forming thin film is unfavorable for the performance of Cu barrier functions；Thickness set it is too thick if,
The resistance of Cu wiring layers is influenceed, while also increasing the cost of material.
Thin film transistor (TFT) in the array base palte of the embodiment of the present invention can be top gate type thin film transistor, or bottom
Gate type thin film transistor.
Effect to Cu barrier layers so that thin film transistor (TFT) is as top gate type thin film transistor as an example below is illustrated.
When the Cu wiring layers in above-described embodiment are gate electrode and grid line (i.e. barrier metal layer), can be in barrier metal layer
Upper surface sets Cu barrier layers, prevents the Cu in barrier metal layer from being spread to gate insulator and active layer direction.Simultaneously, additionally it is possible to
Increase the adhesive force between barrier metal layer and gate insulator.Furthermore it is also possible to reduce when passivation layer is etched to barrier metal layer
Oxidation or the influence of over etching.Now, the Cu barrier layers are properly termed as cap layers.
Furthermore it is also possible to the lower surface in barrier metal layer sets Cu barrier layers, the Cu in barrier metal layer is prevented to array base
Underlay substrate (usually glass substrate) direction diffusion of plate.Simultaneously, additionally it is possible to increase between barrier metal layer and underlay substrate
Adhesive force.Now, the Cu barrier layers are properly termed as buffer layers.
When the Cu wiring layers in above-described embodiment are source electrode, drain electrode and data wire (Source and drain metal level), Ke Yi
The upper surface of Source and drain metal level sets Cu barrier layers, prevents the Cu in Source and drain metal level from being spread to passivation layer (PVX) direction.Together
When, additionally it is possible to increase the adhesive force between Source and drain metal level and passivation layer.Furthermore it is also possible to reduce when passivation layer is etched to source and drain
The oxidation of metal level or the influence of over etching.Now, the Cu barrier layers are properly termed as cap layers.
Furthermore it is also possible to the lower surface in Source and drain metal level sets Cu barrier layers, Cu in Source and drain metal level is prevented to having
Active layer and gate insulator direction are spread.Simultaneously, additionally it is possible to increase between Source and drain metal level and active layer and gate insulator
Adhesive force.Now, the Cu barrier layers are properly termed as buffer layers.
In one embodiment of this invention the active layer of thin film transistor (TFT) be active layer of metal oxide, such as active layer by
IGZO materials are formed, and the passivation layer above the thin film transistor (TFT) with active layer of metal oxide is generally formed using silica,
Cu metals are easier to diffuse in silica, thus, in the array base palte of this type, to prevent the Cu in Source and drain metal level
PVX is diffused to, it is necessary to set Cu barrier layers between Source and drain metal level and PVX.
Fig. 1 is refer to, Fig. 1 is the structural representation of the array base palte in one embodiment of the invention, and the array base palte includes：
Underlay substrate 101；
First Cu barrier layers 102；
Barrier metal layer, including gate electrode 103 and grid line (not shown), a Cu barrier layers 102 are located at the He of underlay substrate 101
Between barrier metal layer, the figure with barrier metal layer is identical；
2nd Cu barrier layers 104, the 2nd Cu barrier layers 104 are located at barrier metal layer upper surface, the figure phase with barrier metal layer
Together；
Gate insulator 105；
Active layer 106；
3rd Cu barrier layers 107；
Source and drain metal level, including source-drain electrode 108 and data wire (not shown), the 3rd Cu barrier layers 107 are located at source and drain electricity
Between pole 108 and active layer 106, and between data wire and gate insulator 105, the 3rd Cu barrier layers 107 and source and drain metal
The figure of layer is identical；
4th Cu barrier layers 109, it is identical with the figure of Source and drain metal level positioned at Source and drain metal level top；
Passivation layer 110.
In the embodiment of the present invention, the first Cu barrier layers 102 are set in the lower surface of barrier metal layer, in preventing barrier metal layer
Cu spreads to the direction of underlay substrate 101.Simultaneously, additionally it is possible to increase the adhesive force between barrier metal layer and underlay substrate 101.Together
When, in the upper surface of barrier metal layer, the 2nd Cu barrier layers 104 are set, the Cu in barrier metal layer is prevented to the He of gate insulator 105
Spread in the direction of active layer 106.Simultaneously, additionally it is possible to increase the adhesive force between barrier metal layer and gate insulator 105.In addition, also
Oxidation or the influence of over etching to barrier metal layer when passivation layer 110 is etched can be reduced.
The 3rd Cu barrier layers 107 are set in the lower surface of Source and drain metal level, the Cu in Source and drain metal level is prevented to active layer
106 and the direction of gate insulator 105 diffusion.Simultaneously, additionally it is possible to increase Source and drain metal level and active layer 106 and gate insulator
Adhesive force between 105.Meanwhile, in the upper surface of Source and drain metal level sets the 4th Cu barrier layers 109, prevents Source and drain metal level
Cu to the direction of passivation layer 110 spread.Simultaneously, additionally it is possible to increase the adhesive force between Source and drain metal level and passivation layer 110.Separately
Outward, oxidation or the influence of over etching to Source and drain metal level when passivation layer 110 is etched can also be reduced.
The embodiment of the present invention also provides a kind of display device, including above-mentioned array base palte.
The above is the preferred embodiment of the present invention, it is noted that for those skilled in the art
For, on the premise of principle of the present invention is not departed from, some improvements and modifications can also be made, these improvements and modifications
Should be regarded as protection scope of the present invention.
Claims (10)
1. a kind of thin film transistor (TFT), including Cu wiring layer, the Cu wiring layers include gate electrode and/or source-drain electrode, its feature
It is that an at least surface of the Cu wiring layers is provided with Cu barrier layers, and the Cu barrier layers use metal oxide, metal nitrogen
Any one or more formation in compound and metal oxynitride.
2. thin film transistor (TFT) according to claim 1, it is characterised in that the metal oxide includes：TiO and ZnO.
3. thin film transistor (TFT) according to claim 1, it is characterised in that the metal nitride includes：TiN and ZnN.
4. thin film transistor (TFT) according to claim 1, it is characterised in that the metal oxynitride includes：TiON、
TiNO, ZnON and ZnNO.
5. thin film transistor (TFT) according to claim 1, it is characterised in that the thickness on the Cu barrier layers is 50-1000A.
6. a kind of array base palte, including Cu wiring layer, the Cu wiring layers include barrier metal layer and/or Source and drain metal level, and it is special
Levy and be, an at least surface of the Cu wiring layers is provided with Cu barrier layers, and the Cu barrier layers use metal oxide, metal
Any one or more formation in nitride and metal oxynitride.
7. array base palte according to claim 6, it is characterised in that the metal oxide includes：TiO and ZnO.
8. array base palte according to claim 6, it is characterised in that the metal nitride includes：TiN and ZnN.
9. array base palte according to claim 6, it is characterised in that the metal oxynitride includes：TiON、TiNO、
ZnON and ZnNO.
10. a kind of display device, including the array base palte as described in claim any one of 1-6.
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Application publication date: 20170531 |