WO2014006695A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2014006695A1 WO2014006695A1 PCT/JP2012/067018 JP2012067018W WO2014006695A1 WO 2014006695 A1 WO2014006695 A1 WO 2014006695A1 JP 2012067018 W JP2012067018 W JP 2012067018W WO 2014006695 A1 WO2014006695 A1 WO 2014006695A1
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- 229910001385 heavy metal Inorganic materials 0.000 claims abstract description 155
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/221—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities of killers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Definitions
- the present invention relates to a semiconductor device.
- FIG. 18 is a diagram shown for explaining a conventional semiconductor device 900.
- 18A is a cross-sectional view schematically illustrating a conventional semiconductor device 900
- FIG. 18B is a diagram illustrating a state in which the depletion layer 960 extends when a reverse bias is applied to the conventional semiconductor device 900. is there.
- 18 is a cross-sectional view schematically showing a conventional semiconductor device 900.
- each element is appropriately deformed and the dimensions and intervals of each element are not necessarily accurate. It is not drawn. The same applies to the following drawings.
- the conventional semiconductor device 900 includes an n + type semiconductor layer 912 and an n ⁇ type semiconductor layer 914.
- a barrier metal layer 930 that is formed on the surface of 920 and forms a Schottky junction with the n ⁇ type semiconductor layer 914 and an ohmic junction with the p + type diffusion region 920.
- reference numeral 940 indicates an anode electrode layer
- reference numeral 950 indicates a cathode electrode layer.
- the conventional semiconductor device 900 has a structure in which the barrier metal layer 930 is formed on the surfaces of the n ⁇ type semiconductor layer 914 and the p + type diffusion region 920 (that is, the JBS structure). As shown in (b), the entire surface of the n ⁇ type semiconductor layer 914 is pinched off by the depletion layer 960 extending from the interface between the n ⁇ type semiconductor layer 914 and the p + type diffusion region 920 to the n ⁇ type semiconductor layer 914 side. As a result, the reverse breakdown voltage VR can be increased, and the leakage current IR can be decreased.
- the conventional semiconductor device 900 has the following problems. 19 and 20 are diagrams for explaining the problems in the conventional semiconductor device 900.
- FIG. 19 In the conventional semiconductor device 900, when the forward drop voltage VF is lowered or the reverse recovery time trr is shortened, the formation area ratio of the p + -type diffusion region 920 is reduced (see FIG. 19). , by widening the spacing between the p + -type diffusion region 920 to reduce the formation area ratio of the p + -type diffusion region 920), n -. or higher n-type impurity concentration in the -type semiconductor layer 914 (FIG. 20), the n ⁇ type semiconductor layer 914 needs to be thinned.
- FIG. 19 and FIG. As shown, since the entire surface of the n ⁇ type semiconductor layer 914 is difficult to pinch off during reverse bias, the forward drop voltage VF can be lowered or reversed while maintaining a high reverse breakdown voltage VR and a low leakage current IR. There is a problem that it is actually not easy to shorten the recovery time trr. Further, in the conventional semiconductor device 900, when the n ⁇ type semiconductor layer 914 is thinned, there is a problem that the reverse breakdown voltage VR is lowered.
- the present invention has been made to solve the above-described problems.
- the forward drop voltage VF is lowered or the reverse recovery time trr is shortened while maintaining a high reverse breakdown voltage VR and a low leakage current IR.
- An object of the present invention is to provide a semiconductor device that can be used.
- a semiconductor device of the present invention includes a first conductivity type first semiconductor layer and a first conductivity type second semiconductor layer containing a first conductivity type impurity at a concentration lower than that of the first semiconductor layer.
- a semiconductor substrate having a structure in which the first semiconductor layer and the second semiconductor layer are stacked in this order; and a first conductivity type impurity selectively formed on a surface of the second semiconductor layer.
- the semiconductor substrate includes the second semiconductor layer. Wherein the heavy metal is diffused so that the concentration in terms is the highest.
- the depth position on the surface of the second semiconductor layer is D1
- the depth position in the deepest portion of the high concentration diffusion region is D2, which is deeper than the depth position D2.
- a depth position shallower than the boundary surface between the first semiconductor layer and the second semiconductor layer is D3
- a depth position at the boundary surface between the first semiconductor layer and the second semiconductor layer is D4.
- the depth position D3 is preferably a depth position where the tail current can be controlled when the switch is turned off.
- the concentration of the heavy metal at the depth position D2 is preferably higher than the concentration of the heavy metal at the depth position D3.
- the concentration of the heavy metal at the depth position D1 is preferably higher than the concentration of the heavy metal at the depth position D5.
- the heavy metal is diffused from the surface side of the first semiconductor layer.
- the concentration of the heavy metal on the surface of the second semiconductor layer is preferably higher than the concentration of the heavy metal on the surface of the high concentration diffusion region.
- the concentration of the heavy metal on the surface of the high concentration diffusion region is higher than the concentration of the heavy metal on the surface of the second semiconductor layer.
- the heavy metal is preferably platinum.
- the semiconductor device of the present invention since it has a structure in which a barrier metal layer is formed on the surface of the second semiconductor layer and the high-concentration diffusion region (that is, a JBS structure), the second semiconductor layer and the high-concentration are at the time of reverse bias. Since the entire surface of the second semiconductor layer is pinched off by the depletion layer extending from the boundary surface with the diffusion region to the second semiconductor layer side, the reverse breakdown voltage VR can be increased, and the leakage current IR is decreased. It becomes possible.
- the semiconductor device of the present invention since the heavy metal is diffused in the semiconductor substrate so that the concentration becomes the highest on the surface of the second semiconductor layer, the pseudo is near the surface of the second semiconductor layer.
- the depletion layer extends as in the case where the concentration of the first conductivity type impurity is reduced.
- the semiconductor device of the present invention since the entire surface of the second semiconductor layer is easily pinched off during reverse bias (see FIG. 1C described later), a high reverse breakdown voltage VR and a low leakage current are obtained. With the IR maintained, the forward voltage drop VF can be made lower and the reverse recovery time trr can be made shorter than in the case of the conventional semiconductor device 900.
- the semiconductor device of the present invention can reduce the forward drop voltage VF and shorten the reverse recovery time trr while maintaining a high reverse breakdown voltage VR and a low leakage current IR. It becomes.
- the reverse breakdown voltage VR can be increased, the second semiconductor layer can be thinned. From this viewpoint, the forward voltage drop VF is reduced. Or the reverse recovery time trr can be shortened.
- the heavy metal is diffused so as to have the highest concentration on the surface of the second semiconductor layer, so that the carrier annihilation rate is increased on the surface of the second semiconductor layer.
- the carrier annihilation rate is not so high, so that noise at the time of switching off is low (see FIG. 15 described later), and soft recovery characteristics are excellent. It becomes a semiconductor device.
- FIG. 1 is a diagram for explaining a semiconductor device 100 according to a first embodiment. It is a figure shown in order to demonstrate a mode that the density
- FIG. 6 is a diagram for explaining the semiconductor device manufacturing method according to the first embodiment.
- FIG. 6 is a diagram for explaining the semiconductor device manufacturing method according to the first embodiment.
- FIG. 10 is a view for explaining the method for manufacturing the semiconductor device in the first modification of the first embodiment.
- FIG. 10 is a view for explaining the method for manufacturing the semiconductor device according to the second modification of the first embodiment.
- FIG. 6 is a diagram for explaining a semiconductor device 100b according to a second modification of the first embodiment.
- FIG. 6 is a diagram for explaining a semiconductor device 100c according to a third modification of the first embodiment.
- FIG. 6 is a diagram for explaining a semiconductor device 102 according to a second embodiment.
- FIG. 10 is a view for explaining the method for manufacturing the semiconductor device in the second embodiment.
- FIG. 6 is a diagram for explaining a semiconductor device 104 according to a third embodiment.
- FIG. 6 is a view for explaining a method for manufacturing a semiconductor device in a third embodiment.
- FIG. 6 is a diagram for explaining a semiconductor device 106 according to a fourth embodiment.
- FIG. 10 is a diagram showing a heavy metal concentration distribution and a carrier annihilation rate distribution in a semiconductor device 106 according to the fourth embodiment.
- FIG. 10 is a diagram showing a heavy metal concentration distribution and a carrier annihilation rate distribution in a semiconductor device 106 according to the fourth embodiment.
- FIG. 6 is a diagram for explaining current response characteristics when a switch is turned off in a semiconductor device 106 according to a fourth embodiment. It is a figure which shows the response characteristic at the time of switch-off in the test example 1.
- FIG. It is a figure which shows the electrostatic capacitance in Test Example 2.
- FIG. It is a figure shown in order to demonstrate the problem in the conventional semiconductor device 900.
- FIG. It is a figure shown in order to demonstrate the problem in the conventional semiconductor device 900.
- FIG. It is a figure shown in order to demonstrate the problem in the conventional semiconductor device 900.
- FIG. It is a figure shown in order to demonstrate the problem in the conventional semiconductor device 900.
- FIG. 1 is a diagram for explaining the semiconductor device 100 according to the first embodiment.
- 1A is a cross-sectional view of the semiconductor device 100
- FIG. 1B is a diagram showing a concentration distribution of heavy metal (platinum) in the semiconductor substrate 110
- FIG. 1C is a reverse bias applied to the semiconductor device 100. It is a figure which shows a mode that the depletion layer 160 is extended when giving.
- the semiconductor device 100 includes an n + type semiconductor layer (first conductivity type first semiconductor layer) 112 and an n type impurity (concentration lower than that of the n + type semiconductor layer).
- An n ⁇ type semiconductor layer (first conductivity type second semiconductor layer) 114 containing a first conductivity type impurity), and an n + type semiconductor layer 112 and an n ⁇ type semiconductor layer 114 are stacked in this order.
- the concentration of the n-type impurity which is selectively formed on the surface of the semiconductor substrate 110 having the above structure and the n ⁇ -type semiconductor layer 114 and contains the p-type impurity (second conductivity type impurity) in the n ⁇ -type semiconductor layer 114 p + -type diffusion region containing a higher concentration than the (second conductivity type high concentration diffusion region) 120, n - formed type semiconductor layer 114 and the p + -type diffusion region 120 on the surface, n - -type semiconductor forming a Schottky junction with the layer 114, p + -type And a barrier metal layer 130 which forms an ohmic junction with the diffuser region 120.
- heavy metal is diffused in the semiconductor substrate 110 so that the concentration is highest on the surface of the n ⁇ -type semiconductor layer 114.
- the heavy metal is diffused so as to have the highest concentration on the surface of the n ⁇ -type semiconductor layer” means “the concentration on the surface of the n ⁇ -type semiconductor layer in the n ⁇ -type semiconductor layer”. Means that heavy metals are diffused so that is the highest.
- the concentration of heavy metal is higher on the surface of the n ⁇ type semiconductor layer than on the surface of the n + type semiconductor layer.
- the depth position on the surface of the n ⁇ type semiconductor layer 114 is D1
- the depth position on the boundary surface between the n + type semiconductor layer 112 and the n ⁇ type semiconductor layer 114 is D4
- the n + type semiconductor layer 112 When the depth position on the surface is D5, the heavy metal concentration at the depth position D1 is higher than the heavy metal concentration at the depth position D4.
- the heavy metal concentration at the depth position D1 is higher than the heavy metal concentration at the depth position D5.
- the “depth position” mentioned above refers to the depth position from the surface of the n ⁇ -type semiconductor layer 114.
- reference numeral 140 indicates an anode electrode layer
- reference numeral 150 indicates a cathode electrode layer.
- the surface on the side where the anode electrode layer 140 is formed is the first main surface
- the surface on the side where the cathode electrode layer 150 is formed is the second main surface.
- the thickness of the semiconductor substrate 110 is 400 ⁇ m, for example.
- the thickness of the n + type semiconductor layer 112 is, for example, 350 ⁇ m, and the impurity concentration in the n + type semiconductor layer 112 is, for example, 1 ⁇ 10 19 cm ⁇ 3 .
- the thickness of the n ⁇ type semiconductor layer 114 is, for example, 50 ⁇ m, and the impurity concentration in the n ⁇ type semiconductor layer 114 is, for example, 1 ⁇ 10 14 cm ⁇ 3 .
- the depth of the p + type diffusion region 120 is, for example, 5 ⁇ m, and the surface impurity concentration of the p + type diffusion region 120 is, for example, 1 ⁇ 10 16 to 1 ⁇ 10 19 cm ⁇ 3 .
- the p + -type diffusion region 120 has a circular shape when seen in a plan view, and has a diameter of 10 ⁇ m, for example. Further, each p + type diffusion region 120 is arranged at, for example, a hexagonal apex position in plan view. Further, the ratio of the area where the p + -type diffusion region 120 is formed to the total area of the active region is, for example, 40%.
- the barrier metal layer 130 is made of aluminum, for example.
- the thickness of the barrier metal layer 130 is, for example, 1 ⁇ m.
- the anode electrode layer 140 is made of, for example, aluminum.
- the thickness of the anode electrode layer 140 is, for example, 5 ⁇ m.
- the cathode electrode 150 is made of nickel, for example.
- the thickness of the cathode electrode layer 150 is 2 ⁇ m, for example.
- platinum as a heavy metal is diffused so as to have a maximum concentration on the surface on the n ⁇ -type semiconductor layer 114 side, as shown in FIG.
- platinum for example, is diffused as a heavy metal from the surface side of the n + -type semiconductor layer 112 (see FIGS. 3D and 4A described later).
- the semiconductor device 100 According to the semiconductor device 100 according to the first embodiment, a structure in which the barrier metal layer 130 is formed on the surfaces of the n ⁇ type semiconductor layer 114 and the p + type diffusion region 120 (ie, because having a JBS structure), at the time of reverse bias, n - -type semiconductor layer 114 and the n from the boundary surface between the p + -type diffusion region 120 - n by -type semiconductor layer 114 depletion layer extending side 160 - the surface of the type semiconductor layer 114 Since the entire region is pinched off, the reverse breakdown voltage VR can be increased, and the leak current IR can be decreased.
- the reverse breakdown voltage VR can be increased, and the leak current IR can be decreased.
- the heavy metal platinum
- the depletion layer 160 extends in the same manner as when the concentration of the n-type impurity is artificially reduced.
- FIG. 2 is a diagram for explaining how the concentration of the n-type impurity is artificially lowered when heavy metal (platinum) is diffused.
- FIG. 2A is a diagram showing a pseudo n-type impurity concentration when heavy metal (platinum) is diffused
- FIG. 2B is an n-type when heavy metal (platinum) is not diffused. It is a figure which shows the density
- n when a reverse bias - since the entire surface of the type semiconductor layer 114 is easily pinched off, p + -type diffusion region The formation area ratio of 120 is reduced (see FIGS. 18 and 19 of the prior art), or the n-type impurity concentration in the n ⁇ -type semiconductor layer 114 is increased (see FIGS. 18 and 20 of the prior art). This also prevents the reverse breakdown voltage VR from being lowered and the leakage current IR from being raised.
- the forward voltage drop VF is made lower than in the case of the conventional semiconductor device 900 while maintaining the high reverse breakdown voltage VR and the low leakage current IR,
- the reverse recovery time trr can be shortened.
- the semiconductor device 100 can reduce the forward drop voltage VF or shorten the reverse recovery time trr while maintaining a high reverse breakdown voltage VR and a low leakage current IR.
- Semiconductor device can reduce the forward drop voltage VF or shorten the reverse recovery time trr while maintaining a high reverse breakdown voltage VR and a low leakage current IR.
- the reverse breakdown voltage VR can be increased, the n ⁇ -type semiconductor layer 114 can be thinned. It is possible to reduce the voltage drop VF and shorten the reverse recovery time trr.
- FIGS. 4 (a) to 4 (d) are process diagrams.
- the semiconductor device manufacturing method includes a semiconductor substrate preparation step, a p + -type diffusion region formation step (high concentration diffusion region formation step), and a heavy metal diffusion source layer formation step.
- it demonstrates in order of a process.
- the semiconductor substrate preparation step includes an n + type semiconductor layer 112 and an n ⁇ type semiconductor layer 114 grown on the n + type semiconductor layer 112 by an epitaxial growth method, as shown in FIG. And a semiconductor substrate 110 having a structure in which an n + type semiconductor layer 112 and an n ⁇ type semiconductor layer 114 are stacked in this order.
- a silicon substrate having a thickness of, for example, 400 ⁇ m is used as the semiconductor substrate 110.
- the thickness of the n + type semiconductor layer 112 is, for example, 350 ⁇ m, and the impurity concentration in the n + type semiconductor layer 112 is, for example, 1 ⁇ 10 19 cm ⁇ 3 .
- the thickness of the n ⁇ type semiconductor layer 114 is, for example, 50 ⁇ m, and the impurity concentration in the n ⁇ type semiconductor layer 114 is, for example, 1 ⁇ 10 14 cm ⁇ 3 .
- p + type diffusion region forming step (high concentration diffusion region forming step)
- the n ⁇ type semiconductor layer 114 contains p type impurities on the surface of the n ⁇ type semiconductor layer 114. This is a step of selectively forming the p + -type diffusion region 120 contained at a concentration higher than the impurity concentration.
- a silicon oxide film mask M1 having a thickness of, for example, 800 nm is formed on the surface of the n ⁇ type semiconductor layer 114 (first main surface side surface).
- a p-type impurity for example, boron
- An impurity introduction region 120 ′ is formed.
- the semiconductor substrate 110 is subjected to a heat treatment (for example, 1000 ° C.) to activate the p-type impurity, thereby forming a p + -type diffusion region 120 as shown in FIG.
- the depth of the p + type diffusion region 120 is, for example, 5 ⁇ m, and the surface impurity concentration of the p + type diffusion region 120 is, for example, 1 ⁇ 10 16 to 1 ⁇ 10 19 cm ⁇ 3 .
- the p + -type diffusion region 120 has a circular shape when seen in a plan view, and has a diameter of 10 ⁇ m, for example. Further, each p + type diffusion region 120 is arranged at, for example, a hexagonal apex position in plan view. Further, the ratio of the area for forming the p + -type diffusion region 120 to the total area of the active region is, for example, 40%.
- the heavy metal diffusion source layer formation step is a step of forming the heavy metal diffusion source layer 116 on the surface of the semiconductor substrate 100 on the n + type semiconductor layer 112 side.
- the oxide film (not shown) and the mask M1 formed on both surfaces of the semiconductor substrate 100 in the p + type diffusion region forming step are removed. Thereafter, a silicon oxide film mask M 2 having a thickness of 2 ⁇ m, for example, is formed on the n ⁇ -type semiconductor layer 114 side of the semiconductor substrate 100. Thereafter, as shown in FIG. 3D, a heavy metal diffusion source layer 116 is formed on the surface of the semiconductor substrate 100 on the n + type semiconductor layer 112 side by spinner coating with a heavy metal diffusion source layer forming coating solution.
- the heavy metal diffusion source layer forming coating solution a silicon oxide film coating forming coating solution in which a silicon compound and an additive (diffusion platinum impurity, glassy forming agent, organic binder) are dissolved in an alcoholic organic solvent is used.
- the mask M2 may be formed from above the mask M1 without removing the mask M1.
- the heavy metal diffusion step is a step of diffusing heavy metal (platinum) from the heavy metal diffusion source layer 116 into the semiconductor substrate 110 by performing a heat treatment on the semiconductor substrate 110.
- the concentration distribution of heavy metal along the depth direction of the semiconductor substrate 110 after the heavy metal diffusion step is the first main surface (surface of the n ⁇ type semiconductor layer 114) and the second main surface (n + type semiconductor) of the semiconductor substrate 110.
- n ⁇ type semiconductor layer 112 On the surface of the layer 112, a U-shaped distribution with a high concentration is obtained. Therefore, in the n ⁇ type semiconductor layer 114, the concentration of heavy metal (platinum) is maximized on the surface of the n ⁇ type semiconductor layer 114.
- the mask M2 on the n ⁇ -type semiconductor layer 114 side and the oxidized alteration layer of the heavy metal diffusion source layer 116 on the n + -type semiconductor layer 112 side in the semiconductor substrate 100 are removed by hydrofluoric acid etching (see FIG. 4B). .
- a Schottky junction is formed between the n ⁇ type semiconductor layer 114 and the n ⁇ type semiconductor layer 114 on the surfaces of the n ⁇ type semiconductor layer 114 and the p + type diffusion region 120, and p + type. This is a step of forming a barrier metal layer 130 that forms an ohmic junction with the diffusion region 120 (see FIG. 4C).
- the material of the barrier metal layer 130 is, for example, aluminum, and the thickness of the barrier metal layer 130 is, for example, 1 ⁇ m.
- Anode electrode layer forming step is a step of forming the anode electrode layer 140 above the barrier metal layer 130.
- An anode electrode layer 140 made of aluminum is formed on the surface of the electrode layer made of the barrier metal layer 130 (see FIG. 4C).
- the thickness of the anode electrode layer 140 is, for example, 5 ⁇ m.
- the cathode electrode layer formation step is a step of forming the cathode electrode layer 150 on the surface of the n + type semiconductor layer 112.
- the thickness of the cathode electrode layer 150 is 2 ⁇ m, for example.
- the semiconductor device 100 according to the first embodiment can be manufactured by performing the semiconductor device manufacturing method according to the first embodiment including the steps as described above.
- FIG. 5 is a view for explaining the semiconductor device manufacturing method according to the first modification of the first embodiment.
- FIG. 5A to FIG. 5D are process diagrams.
- the steps after the heavy metal diffusion source layer forming step are the semiconductor device according to the first embodiment. Therefore, the drawings corresponding to FIGS. 3D to 4D are omitted.
- the manufacturing method of the semiconductor device in the first modification of the first embodiment basically includes the same steps as the manufacturing method of the semiconductor device in the first embodiment, but the type of the semiconductor substrate to be prepared first is different. That is, in the method for manufacturing a semiconductor device according to Modification 1, as shown in FIG. 5A, a semiconductor substrate 110 made of an n ⁇ type semiconductor layer 114 is prepared as a semiconductor substrate. Therefore, a p-type impurity (for example, boron) is introduced into the surface of the n ⁇ -type semiconductor layer 114 by a method such as an ion implantation method or a deposition method to form a p-type impurity introduction region 120 ′ (see FIG. 5B).
- a p-type impurity for example, boron
- an n-type impurity for example, phosphorus
- an n-type impurity introduction region 112 ′ is introduced into the surface (second main surface side surface) of the n ⁇ -type semiconductor layer 114 to form an n-type impurity introduction region 112 ′ (see FIG. 5C).
- Heat treatment for example, 1000 ° C.
- the semiconductor substrate 110 to activate the p-type impurity and the n-type impurity, and as shown in FIG. 5D, the p + -type diffusion region 120 and the n + -type semiconductor layer 112 are activated.
- the formation depth of the n + type semiconductor layer 112 is, for example, 5 ⁇ m.
- the semiconductor device 100a (not shown) according to the first modification of the first embodiment having the same configuration as that of the semiconductor device 100 according to the first embodiment can be manufactured.
- FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the second modification of the first embodiment.
- 6A and 6B are process diagrams.
- FIG. 7 is a view for explaining the semiconductor device 100b according to the second modification of the first embodiment.
- FIG. 7A is a cross-sectional view of the semiconductor device 100b
- FIG. 7B is a diagram showing the concentration distribution of heavy metal (platinum) in the semiconductor substrate 110.
- FIG. in the semiconductor device manufacturing method according to the second modification of the first embodiment the steps prior to the heavy metal diffusion source layer forming step (see FIGS. 3A to 3D) and the barrier metal layer forming step. Since the subsequent steps (see FIGS. 4B to 5D) are the same as those in the method of manufacturing the semiconductor device according to the first embodiment, the corresponding drawings are not shown.
- the manufacturing method of the semiconductor device in Modification 2 of Embodiment 1 basically includes the same steps as the manufacturing method of the semiconductor device in Embodiment 1, but the heavy metal diffusion step (see FIG. 6A) is performed. Then, the semiconductor device manufacturing method according to the first embodiment is different in that it further includes a step of thinning the n + -type semiconductor layer 112 (see FIG. 6B).
- the method for manufacturing a semiconductor device according to the second modification of the first embodiment further includes a step of thinning the n + type semiconductor layer 112 by CMP after performing the heavy metal diffusion step.
- the thickness of the n + type semiconductor layer 112 is, for example, 5 ⁇ m.
- the concentration of heavy metal (platinum) on the surface of the n + -type semiconductor layer 112 is lower than that in the semiconductor device 100 according to the first embodiment.
- FIG. 8 is a view for explaining the semiconductor device 100c according to the third modification of the first embodiment.
- the semiconductor device 100c according to the third modification of the first embodiment basically has the same configuration as the semiconductor device 100 according to the first embodiment, but is different from the semiconductor device 100 according to the first embodiment on the first main surface side.
- the configuration is different. That is, in the semiconductor device 100c according to the modified example 3, the barrier metal layer 132 formed on the first main surface side also serves as the anode electrode layer (see FIG. 8).
- the barrier metal layer 132 is made of, for example, aluminum.
- the thickness of the barrier metal layer 132 is, for example, 6 ⁇ m.
- the semiconductor device 100c according to the third modification of the first embodiment having such a configuration is also included in the semiconductor device of the present invention as in the case of the semiconductor device 100 according to the first embodiment.
- FIG. 9 is a diagram for explaining the semiconductor device 102 according to the second embodiment.
- FIG. 9A is a cross-sectional view of the semiconductor device 102
- FIG. 9B is a diagram showing the concentration distribution of heavy metal (platinum) in the semiconductor substrate 110.
- the semiconductor device 102 according to the second embodiment basically has the same configuration as that of the semiconductor device 100 according to the first embodiment, but the concentration distribution of heavy metal (platinum) in the semiconductor substrate 110 is different from that of the semiconductor device 100. Different. That is, in the semiconductor device 102 according to the second embodiment, as shown in FIG. 9, unlike the case where the concentration distribution of heavy metals (platinum) in the semiconductor substrate 110 is a semiconductor device 100, n - surface type semiconductor layer 114
- the concentration of heavy metal (platinum) in FIG. 9B is the concentration of heavy metal (platinum) on the surface of the p + type diffusion region 120 (in FIG. 9B, the two-dot chain line). (See curve by).
- the semiconductor device 102 according to the second embodiment differs from the semiconductor device 100 according to the first embodiment in the concentration distribution of heavy metal (platinum) in the semiconductor substrate 110, but the semiconductor device 100 according to the first embodiment.
- it has a structure in which a barrier metal layer 130 is formed on the surfaces of the n ⁇ type semiconductor layer 114 and the p + type diffusion region 120 (that is, a JBS structure). Since the heavy metal (platinum) is diffused so as to have the highest concentration on the surface of the n ⁇ -type semiconductor layer 114, the forward voltage drop VF is lowered while maintaining the high reverse breakdown voltage VR and the low leakage current IR. Or the reverse recovery time trr can be shortened.
- the reverse breakdown voltage VR can be increased, the n ⁇ -type semiconductor layer 114 can be thinned. It is possible to reduce the voltage drop VF and shorten the reverse recovery time trr.
- the concentration of heavy metal (platinum) on the surface of the n ⁇ -type semiconductor layer 114 is higher than the concentration of heavy metal (platinum) on the surface of the p + -type diffusion region 120.
- the depletion layer extends earlier than when the semiconductor device 100 according to the first embodiment is applied (from when a low voltage is applied). Therefore, according to the semiconductor device 102 according to the second embodiment, the entire surface of the n ⁇ -type semiconductor layer 114 is more easily pinched off at the time of reverse bias, so that the reverse breakdown voltage VR can be further increased. Become.
- the semiconductor device 102 according to the second embodiment has the same configuration as that of the semiconductor device 100 according to the first embodiment except for the concentration distribution of heavy metal (platinum) in the semiconductor substrate 110, the semiconductor device 102 according to the first embodiment.
- the semiconductor device 100 has a corresponding effect among the effects of the semiconductor device 100.
- FIG. 10 is a view for explaining the method for manufacturing the semiconductor device according to the second embodiment.
- FIG. 10A to FIG. 10D are process diagrams.
- the steps up to the p + -type diffusion region formation step see FIGS. 3A to 3C
- the steps after the heavy metal diffusion step FIG. 4 (b) to FIG. 4 (d) are the same as those in the method of manufacturing the semiconductor device according to the first embodiment, and therefore FIG. 3 (a) to FIG. 3 (c) and FIG. 4 (b) to FIG.
- the illustration corresponding to FIG. 4D is omitted.
- the manufacturing method of the semiconductor device in the second embodiment basically includes the same steps as the manufacturing method of the semiconductor device in the first embodiment, but the semiconductor substrate is formed between the p + -type diffusion region forming step and the heavy metal diffusion step.
- 110 further includes a second heavy metal diffusion source layer forming step of forming a second heavy metal diffusion source layer 118 on the surface on the n ⁇ type semiconductor layer 114 side in 110 (particularly the surface of the n ⁇ type semiconductor layer 114).
- the n ⁇ type semiconductor layer 114 and the p + type diffusion region 120 are included.
- a second heavy metal diffusion source layer 118 (for example, a platinum layer formed by vapor deposition or sputtering) 118 is formed on the surface of the n ⁇ type semiconductor layer 114 (see FIGS. 10B to 10C).
- reference numeral M3 denotes a silicon oxide film mask having a thickness of 2 ⁇ m, for example.
- the semiconductor device 102 according to the second embodiment can be manufactured by such a method.
- FIG. 11 is a diagram for explaining the semiconductor device 104 according to the third embodiment.
- FIG. 11A is a cross-sectional view of the semiconductor device 104
- FIG. 11B is a diagram showing the concentration distribution of heavy metal (platinum) in the semiconductor substrate 110.
- FIG. 11A is a cross-sectional view of the semiconductor device 104
- FIG. 11B is a diagram showing the concentration distribution of heavy metal (platinum) in the semiconductor substrate 110.
- the semiconductor device 104 according to the third embodiment basically has the same configuration as that of the semiconductor device 100 according to the first embodiment, but the concentration distribution of heavy metal (platinum) in the semiconductor substrate 110 is different from that of the semiconductor device 100. Different. That is, in the semiconductor device 104 according to the third embodiment, as shown in FIG. 11, unlike the case where the concentration distribution of heavy metals (platinum) in the semiconductor substrate 110 is a semiconductor device 100, the surface of the p + -type diffusion region 120
- the concentration of heavy metal (platinum) in FIG. 11 is the concentration of heavy metal (platinum) on the surface of the n ⁇ -type semiconductor layer 114 (in FIG. 11B, the one-dot chain line). (See curve by).
- the semiconductor device 104 according to the third embodiment differs from the semiconductor device 100 according to the first embodiment in the concentration distribution of heavy metal (platinum) in the semiconductor substrate 110, but the semiconductor device 100 according to the first embodiment.
- it has a structure in which a barrier metal layer 130 is formed on the surfaces of the n ⁇ type semiconductor layer 114 and the p + type diffusion region 120 (that is, a JBS structure). Since the heavy metal (platinum) is diffused so as to have the highest concentration on the surface of the n ⁇ -type semiconductor layer 114, the forward voltage drop VF is lowered while maintaining the high reverse breakdown voltage VR and the low leakage current IR. Or the reverse recovery time trr can be shortened.
- the reverse breakdown voltage VR can be increased, the n ⁇ type semiconductor layer 114 can be thinned, and also from this viewpoint, the forward direction It is possible to reduce the voltage drop VF and shorten the reverse recovery time trr.
- the carrier annihilation rate is increased, whereas the carrier annihilation rate is not so high at the bottom of the n ⁇ -type semiconductor layer 114 (near the interface with the n + -type semiconductor layer 112). It becomes a semiconductor device with excellent soft recovery characteristics.
- the concentration of heavy metal (platinum) on the surface of the p + type diffusion region 120 is higher than the concentration of heavy metal (platinum) on the surface of the n ⁇ type semiconductor layer 114. It is possible to increase the speed at which minority carriers disappear when the switch is turned off. For this reason, according to the semiconductor device 104 according to the third embodiment, the reverse recovery time trr can be further shortened.
- the semiconductor device 104 according to the third embodiment has the same configuration as that of the semiconductor device 100 according to the first embodiment except for the concentration distribution of heavy metal (platinum) in the semiconductor substrate 110, the semiconductor device 104 according to the first embodiment.
- the semiconductor device 100 has a corresponding effect among the effects of the semiconductor device 100.
- FIG. 12 is a view for explaining the method for manufacturing the semiconductor device according to the third embodiment.
- 12A to 12D are process diagrams.
- the steps up to the p + -type diffusion region forming step see FIGS. 3A to 3C
- the steps after the heavy metal diffusion step FIG. 4 (b) to FIG. 4 (d)
- FIG. 3 (a) to FIG. 3 (c) and FIG. 4 (b) Illustrations corresponding to FIG. 4D are omitted.
- the manufacturing method of the semiconductor device in the third embodiment basically includes the same steps as the manufacturing method of the semiconductor device in the first embodiment, but the semiconductor substrate is formed between the p + -type diffusion region forming step and the heavy metal diffusion step.
- 110 further includes a second heavy metal diffusion source layer forming step of forming a second heavy metal diffusion source layer on the surface of 110 on the n ⁇ type semiconductor layer 114 side (particularly the surface of the p + type diffusion region 120).
- the n ⁇ type semiconductor layer 114 and the p + type diffusion region 120 are included.
- a second heavy metal diffusion source layer 118 (for example, a platinum layer formed by vapor deposition or sputtering) 118 is formed on the surface of the p + type diffusion region 120 (see FIGS. 12B to 12C).
- reference numeral M4 denotes a silicon oxide film mask having a thickness of 2 ⁇ m, for example.
- the semiconductor device 104 according to the third embodiment can be manufactured by such a method.
- FIG. 13 is a view for explaining the semiconductor device 106 according to the fourth embodiment.
- 13A is a cross-sectional view of the semiconductor device 106
- FIG. 13B is a diagram showing a concentration distribution of heavy metal (platinum) in the semiconductor substrate 110
- FIG. 13C is a reverse bias applied to the semiconductor device 106. It is a figure which shows a mode that the depletion layer 160 is extended when giving.
- FIG. 14 is a diagram illustrating a heavy metal (platinum) concentration distribution and a carrier annihilation rate distribution in the semiconductor device 106 according to the fourth embodiment.
- FIG. 14A is a diagram showing a concentration distribution of heavy metal (platinum), and FIG. 14B is a diagram showing a carrier annihilation rate distribution.
- FIG. 15 is a diagram illustrating current response characteristics when the semiconductor device 106 according to the fourth embodiment is switched off.
- FIG. 15A is a diagram showing the entire current response characteristic, and
- FIG. 15B is an enlarged view of FIG. 15A.
- a symbol a indicates a tail current
- a symbol b indicates a reverse recovery time trr
- a symbol c indicates noise generated when the switch is turned off.
- the semiconductor device 106 according to the fourth embodiment basically has the same configuration as that of the semiconductor device 100 according to the first embodiment, but the concentration distribution of heavy metal (platinum) in the semiconductor substrate 110 is different from that of the semiconductor device 100. Different.
- the depth position on the surface of the n ⁇ type semiconductor layer 114 is D1
- the depth at the deepest portion of the p + type diffusion region 120 is shown.
- the depth position is D2, the depth position deeper than the depth position D2 and shallower than the boundary surface between the n + -type semiconductor layer 112 and the n ⁇ -type semiconductor layer 114 is D3, and the n + -type semiconductor layer 112 and
- the concentration of heavy metal (platinum) at the depth position D4 is It is higher than the concentration of heavy metal (platinum) at the position D3.
- the concentration of heavy metal (platinum) at the depth position D2 is higher than the concentration of heavy metal (platinum) at the depth position D3.
- the depth position D3 is a depth position (for example, a depth position 10 ⁇ m shallower than the depth position D4) at which the tail current can be controlled when the switch is turned off.
- the thickness of the semiconductor substrate 110 is 400 ⁇ m, for example.
- the thickness of the n + type semiconductor layer 112 is, for example, 340 ⁇ m, and the impurity concentration in the n + type semiconductor layer 112 is, for example, 1 ⁇ 10 19 cm ⁇ 3 .
- the thickness of the n ⁇ type semiconductor layer 114 is 55 ⁇ m or more (for example, 60 ⁇ m), and the impurity concentration in the n ⁇ type semiconductor layer 114 is, for example, 1 ⁇ 10 14 cm ⁇ 3 .
- the semiconductor device 106 according to the fourth embodiment differs from the semiconductor device 100 according to the first embodiment in the concentration distribution of heavy metal (platinum) in the semiconductor substrate 110, but the semiconductor device 100 according to the first embodiment.
- it has a structure in which a barrier metal layer 130 is formed on the surfaces of the n ⁇ type semiconductor layer 114 and the p + type diffusion region 120 (that is, a JBS structure). Since the heavy metal (platinum) is diffused so as to have the highest concentration on the surface of the n ⁇ -type semiconductor layer 114, the forward voltage drop VF is lowered while maintaining the high reverse breakdown voltage VR and the low leakage current IR. Or the reverse recovery time trr can be shortened.
- the reverse breakdown voltage VR can be increased, the n ⁇ -type semiconductor layer 114 can be thinned. It is possible to reduce the voltage drop VF and shorten the reverse recovery time trr.
- the heavy metal (platinum) is diffused so as to have the highest concentration on the surface of the n ⁇ type semiconductor layer 114 (see FIG. 14A).
- the carrier annihilation rate is increased on the surface of the n ⁇ type semiconductor layer 114, whereas the carrier annihilation rate is not so high at the bottom of the n ⁇ type semiconductor layer 114 (near the interface with the n + type semiconductor layer 112). (See FIG. 14B.)
- the noise at the time of switch-off is reduced, and the semiconductor device is excellent in soft recovery characteristics.
- the concentration of heavy metal (platinum) at the depth position D4 is higher than the concentration of heavy metal (platinum) at the depth position D3 (see FIG. 14A).
- the carrier annihilation speed at the depth position D4 is faster than the carrier annihilation speed at the depth position D3, as shown in FIG. 15, the tail current is reduced and the waste of power is reduced.
- the concentration of heavy metal (platinum) at the depth position D2 is higher than the concentration of heavy metal (platinum) at the depth position D3. Since the carrier annihilation speed in platinum) is faster than the carrier annihilation speed at the depth position D3, the overall recovery speed is increased, and the reverse recovery time trr can be shortened (see symbol b in FIG. 15). ). On the other hand, since the concentration of heavy metal (platinum) at the depth position D3 is lower than the concentration of heavy metal (platinum) at the depth position D2, the noise at the time of switching off is reduced, and the semiconductor device having excellent soft recovery characteristics become.
- the semiconductor device 106 according to the fourth embodiment can reduce the forward drop voltage VF or shorten the reverse recovery time trr while maintaining a high reverse breakdown voltage VR and a low leakage current IR. Further, it becomes a semiconductor device that is power-saving and has excellent soft recovery characteristics.
- the current change rate (di / dt in the return slope of the leak current IR (see d in FIG. 16A described later)) and the voltage change rate (dV / dt (refer to reference sign e in FIG. 16B described later) can be loosened (refer to current response characteristics and voltage response characteristics indicated by reference signs S1 to S3 in FIG. 16).
- the peak value of the leakage current IR and the integrated value (charge amount) Qrr of the leakage current IR can be significantly reduced by optimizing the conditions of the heavy metal diffusion process. (Refer to a current characteristic indicated by S1 in FIG. 16 described later.)
- the semiconductor device 106 according to the fourth embodiment has the same configuration as that of the semiconductor device 100 according to the first embodiment except for the concentration distribution of heavy metal (platinum) in the semiconductor substrate 110, the semiconductor device 106 according to the first embodiment.
- the semiconductor device 100 has a corresponding effect among the effects of the semiconductor device 100.
- the semiconductor device 106 according to the fourth embodiment is basically manufactured by a semiconductor device manufacturing method (semiconductor device manufacturing method according to the fourth embodiment) including the same steps as the semiconductor device manufacturing method according to the first embodiment. Is possible.
- the thickness of the n + type semiconductor layer 112 is, for example, 340 ⁇ m
- the thickness of the n ⁇ type semiconductor layer 114 is for example, a semiconductor substrate having a thickness of 60 ⁇ m is used.
- the concentration of heavy metal (platinum) at the depth position D4 is higher than the concentration of heavy metal (platinum) at the depth position D3, and the concentration of heavy metal (platinum) at the depth position D2 is higher.
- the semiconductor device 106 according to the fourth embodiment can be manufactured so as to be higher than the concentration of heavy metal (platinum) at the depth position D3 (see FIG. 13).
- Test Example 1 is a test example for showing that the semiconductor device of the present invention is a semiconductor device excellent in soft recovery characteristics.
- Sample Preparation Basically, semiconductor devices having the same structure as the semiconductor device according to Embodiment 4 were used as Samples 1 to 3 (Examples). However, Sample 1 was subjected to the heavy metal diffusion step at 880 ° C., Sample 2 was subjected to the heavy metal diffusion step at 850 ° C., and Sample 3 was subjected to the heavy metal diffusion step at 820 ° C. Sample 4 (Comparative Example) was irradiated with an electron beam instead of diffusing heavy metal as a lifetime killer.
- Test method The recovery characteristics (current response characteristics and voltage response characteristics) when the switch is turned off so that the forward current IF decreases at a rate of 500 A / ⁇ s from the forward bias state in which the forward current IF of 10 A flows is the reverse voltage. Measurement was performed until VR reached 300V. The measurement was performed using a di / dt method reverse recovery waveform test apparatus.
- FIG. 16 is a diagram illustrating response characteristics when the switch is turned off in Test Example 1.
- FIG. 16A is a diagram showing current response characteristics when the switch is off
- FIG. 16B is a diagram showing voltage response characteristics when the switch is off.
- reference numeral S1 indicates a voltage response characteristic for the sample 1
- reference numeral S2 indicates a voltage response characteristic for the sample 2
- reference numeral S3 indicates a voltage response characteristic for the sample 3
- reference numeral S4 indicates a voltage for the sample 4. Response characteristics are shown.
- Samples 1 to 3 have soft recovery characteristics superior to those of Sample 4 (Comparative Example).
- Sample 1 subjected to the heavy metal diffusion process at 880 ° C. has a shorter reverse recovery time trr and superior soft recovery characteristics with reduced noise than Sample 3 subjected to the heavy metal diffusion process at 820 ° C. It was.
- Test Example 2 is a test example for showing that the semiconductor device of the present invention is a semiconductor device that is pinched off at a low voltage.
- Sample 5 a semiconductor device having the same structure as that of the semiconductor device according to Embodiment 4 was used as Sample 5 (Example).
- Sample 6 Comparative Example having the same structure as Sample 5 and having no heavy metal (platinum) introduced therein was used.
- FIG. 17 is a diagram showing the capacitance in Test Example 2.
- reference numeral S ⁇ b> 5 indicates the electrostatic capacity of the sample 5
- reference numeral S ⁇ b> 6 indicates the electrostatic capacity of the sample 6.
- platinum is used as the heavy metal, but the present invention is not limited to this.
- a metal material other than platinum for example, gold may be used.
- the heavy metal diffusion source layer is formed using the heavy metal diffusion source layer forming coating solution comprising the silicon oxide film coating forming coating solution.
- the present invention is not limited to this. is not.
- a heavy metal diffusion source layer may be formed using a heavy metal diffusion source layer forming coating solution different from the silicon oxide film coating forming coating solution, or a heavy metal diffusion source layer comprising a heavy metal film by vapor deposition or sputtering. May be formed.
- aluminum is used as the material for the barrier metal, but the present invention is not limited to this.
- a metal material other than aluminum eg, molybdenum, titanium, platinum, etc. may be used.
- the semiconductor substrate 110 having a structure in which the n + type semiconductor layer 112 and the n ⁇ type semiconductor layer 114 are directly stacked is used, but the present invention is limited to this. It is not a thing.
- a semiconductor substrate 110 in which another semiconductor layer (for example, an n ⁇ type semiconductor layer, an n type semiconductor layer, etc.) exists between the n + type semiconductor layer 112 and the n ⁇ type semiconductor layer 114 may be used. .
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Abstract
Description
A.実施形態1に係る半導体装置100
図1は、実施形態1に係る半導体装置100を説明するために示す図である。図1(a)は半導体装置100の断面図であり、図1(b)は半導体基体110における重金属(白金)の濃度分布を示す図であり、図1(c)は半導体装置100に逆バイアスを与えたときに空乏層160が延びる様子を示す図である。
実施形態1に係る半導体装置100によれば、n-型半導体層114及びp+型拡散領域120の表面上にバリアメタル層130が形成された構造(すなわちJBS構造)を有するため、逆バイアス時には、n-型半導体層114とp+型拡散領域120との境界面からn-型半導体層114側に延びる空乏層160によりn-型半導体層114の表面全域がピンチオフすることから、逆方向耐圧VRを高くすることが可能となり、また、リーク電流IRを低くすることが可能となる。
実施形態1に係る半導体装置100は、以下に示す半導体装置の製造方法によって製造することが可能である。図3及び図4は、実施形態1における半導体装置の製造方法を説明するために示す図である。図3(a)~図3(d)及び図4(a)~図4(d)は各工程図である。
半導体基体準備工程は、図3(a)に示すように、n+型半導体層112と、当該n+型半導体層112上にエピタキシャル成長法によって成長させたn-型半導体層114とを有し、n+型半導体層112及びn-型半導体層114とがこの順序で積層された構造を有する半導体基体110を準備する工程である。半導体基体110としては、厚さが例えば400μmのシリコン基板を用いる。n+型半導体層112の厚さは例えば350μmであり、n+型半導体層112における不純物濃度は例えば1×1019cm-3である。n-型半導体層114の厚さは例えば50μmであり、n-型半導体層114における不純物濃度は例えば1×1014cm-3である。
p+型拡散領域形成工程は、図3(b)及び図3(c)に示すように、n-型半導体層114の表面に、p型不純物をn-型半導体層114が含有するn型不純物の濃度よりも高い濃度で含有するp+型拡散領域120を選択的に形成する工程である。
重金属拡散源層形成工程は、半導体基体100におけるn+型半導体層112側の表面に重金属拡散源層116を形成する工程である。
重金属拡散工程は、半導体基体110に熱処理を施すことにより、重金属拡散源層116から半導体基体110中に重金属(白金)を拡散させる工程である。重金属拡散工程後における重金属の、半導体基体110の深さ方向に沿った濃度分布は、半導体基体110の第1主面(n-型半導体層114の表面)及び第2主面(n+型半導体層112の表面)において、濃度が高くなるようなU字状の分布となる。従って、n-型半導体層114においては、n-型半導体層114の表面において重金属(白金)の濃度が極大となる。
バリアメタル層形成工程は、n-型半導体層114及びp+型拡散領域120の表面上に、n-型半導体層114との間でショットキー接合を形成し、p+型拡散領域120との間でオーミック接合を形成するバリアメタル層130を形成する工程である(図4(c)参照。)。
アノード電極層形成工程は、バリアメタル層130の上方にアノード電極層140を形成する工程である。
カソード電極層形成工程は、n+型半導体層112の表面にカソード電極層150を形成する工程である。
図5は、実施形態1の変形例1における半導体装置の製造方法を説明するために示す図である。図5(a)~図5(d)は各工程図である。なお、実施形態1の変形例1における半導体装置の製造方法においては、重金属拡散源層形成工程から後の工程(図3(d)~図4(d)参照。)が実施形態1における半導体装置の製造方法の場合と同様であるため、図3(d)~図4(d)に対応する図面の図示は省略する。
すなわち、変形例1における半導体装置の製造方法においては、図5(a)に示すように、半導体基体として、n-型半導体層114からなる半導体基体110を準備する。従って、イオン注入法やデポジション法などの方法によりp型不純物(例えばボロン)をn-型半導体層114の表面に導入しp型不純物導入領域120’を形成し(図5(b)参照。)、さらにはn型不純物(例えばリン)をn-型半導体層114の表面(第2主面側表面)に導入しn型不純物導入領域112’を形成した後(図5(c)参照。)、半導体基板110に熱処理(例えば1000℃)を施してp型不純物及びn型不純物を活性化して、図5(d)に示すように、p+型拡散領域120及びn+型半導体層112を形成する。n+型半導体層112の形成深さは例えば5μmとする。
図6は、実施形態1の変形例2における半導体装置の製造方法を説明するために示す図である。図6(a)及び図6(b)は各工程図である。図7は、実施形態1の変形例2に係る半導体装置100bを説明するために示す図である。図7(a)は半導体装置100bの断面図であり、図7(b)は半導体基体110における重金属(白金)の濃度分布を示す図である。なお、実施形態1の変形例2における半導体装置の製造方法においては、重金属拡散源層形成工程よりも前の工程(図3(a)~図3(d)参照。)及びバリアメタル層形成工程から後の工程(図4(b)~図5(d)参照。)が実施形態1における半導体装置の製造方法の場合と同様であるため、これらに対応する図面の図示は省略する。
図8は、実施形態1の変形例3に係る半導体装置100cを説明するために示す図である。
実施形態1の変形例3に係る半導体装置100cは、基本的には実施形態1に係る半導体装置100と同様の構成を有するが、実施形態1に係る半導体装置100とは第1主面側の構成が異なる。
すなわち、変形例3に係る半導体装置100cは、第1主面側に形成されているバリアメタル層132がアノード電極層をも兼ねている(図8参照。)。バリアメタル層132は例えばアルミニウムからなる。バリアメタル層132の厚さは例えば6μmである。
A.実施形態2に係る半導体装置102
図9は、実施形態2に係る半導体装置102を説明するために示す図である。図9(a)は半導体装置102の断面図であり、図9(b)は半導体基体110における重金属(白金)の濃度分布を示す図である。
すなわち、実施形態2に係る半導体装置102においては、図9に示すように、半導体基体110中の重金属(白金)の濃度分布が半導体装置100の場合とは異なり、n-型半導体層114の表面における重金属(白金)の濃度(図9(b)中、一点鎖線による曲線参照。)が、p+型拡散領域120の表面における重金属(白金)の濃度(図9(b)中、二点鎖線による曲線参照。)よりも高い。
実施形態2における半導体装置102は、以下に示す半導体装置の製造方法(実施形態2における半導体装置の製造方法)によって製造することが可能である。
図10は、実施形態2における半導体装置の製造方法を説明するために示す図である。図10(a)~図10(d)は各工程図である。なお、実施形態2における半導体装置の製造方法においては、p+型拡散領域形成工程までの工程(図3(a)~図3(c)参照。)及び重金属拡散工程よりも後の工程(図4(b)~図4(d)参照。)が、実施形態1における半導体装置の製造方法の場合と同様であるため、図3(a)~図3(c)及び図4(b)~図4(d)に対応する図面の図示は省略する。
A.実施形態3に係る半導体装置104
図11は、実施形態3に係る半導体装置104を説明するために示す図である。図11(a)は半導体装置104の断面図であり、図11(b)は半導体基体110における重金属(白金)の濃度分布を示す図である。
すなわち、実施形態3に係る半導体装置104においては、図11に示すように、半導体基体110中の重金属(白金)の濃度分布が半導体装置100の場合とは異なり、p+型拡散領域120の表面における重金属(白金)の濃度(図11(b)中、二点鎖線による曲線参照。)が、n-型半導体層114の表面における重金属(白金)の濃度(図11(b)中、一点鎖線による曲線参照。)よりも高い。
実施形態3における半導体装置104は、以下に示す半導体装置の製造方法(実施形態3における半導体装置の製造方法)によって製造することが可能である。
図12は、実施形態3における半導体装置の製造方法を説明するために示す図である。図12(a)~図12(d)は各工程図である。なお、実施形態3における半導体装置の製造方法においては、p+型拡散領域形成工程までの工程(図3(a)~図3(c)参照。)及び重金属拡散工程よりも後の工程(図4(b)~図4(d)参照。)が、実施形態1に係る半導体装置の製造方法の場合と同様であるため、図3(a)~図3(c)及び図4(b)~図4(d)に対応する図面の図示は省略する。
A.実施形態4に係る半導体装置106
図13は、実施形態4に係る半導体装置106を説明するために示す図である。図13(a)は半導体装置106の断面図であり、図13(b)は半導体基体110における重金属(白金)の濃度分布を示す図であり、図13(c)は半導体装置106に逆バイアスを与えたときに空乏層160が延びる様子を示す図である。
図14は、実施形態4に係る半導体装置106における重金属(白金)の濃度分布及びキャリア消滅速度分布を示す図である。図14(a)は重金属(白金)の濃度分布を示す図であり、図14(b)はキャリア消滅速度分布を示す図である。
図15は、実施形態4に係る半導体装置106におけるスイッチオフ時の電流応答特性を示す図である。図15(a)は電流応答特性の全体を示す図であり、図15(b)は図15(a)の拡大図である。図15中、符号aはテール電流を示し、符号bは逆回復時間trrを示し、符号cはスイッチオフ時に発生するノイズを示す。
以下、試験例により本発明をさらに詳細に説明する。
[試験例1]
試験例1は、本発明の半導体装置が、ソフトリカバリー特性に優れた半導体装置であることを示すための試験例である。
基本的には、実施形態4に係る半導体装置と同様の構造を有する半導体装置を試料1~3(実施例)とした。但し、880℃で重金属拡散工程を実施したものを試料1とし、850℃で重金属拡散工程を実施したものを試料2とし、820℃で重金属拡散工程を実施したものを試料3とした。また、ライフタイムキラーとして重金属を拡散する代わりに電子線を照射したものを試料4(比較例)とした。
10Aの順方向電流IFを流した順バイアス状態から500A/μsの割合で順方向電流IFが減少するようにスイッチオフしたときのリカバリ特性(電流応答特性及び電圧応答特性)を逆方向電圧VRが300Vになるまで測定した。測定は、di/dt法逆回復波形試験装置を用いて行った。
図16は、試験例1におけるスイッチオフ時の応答特性を示す図である。図16(a)はスイッチオフ時における電流応答特性を示す図であり、図16(b)はスイッチオフ時における電圧応答特性を示す図である。図中、符号S1は試料1についての電圧応答特性を示し、符号S2は試料2についての電圧応答特性を示し、符号S3は試料3についての電圧応答特性を示し、符号S4は試料4についての電圧応答特性を示す。
試験例2は、本発明の半導体装置が、低い電圧でピンチオフされる半導体装置であることを示すための試験例である。
基本的には、実施形態4に係る半導体装置と同様の構造を有する半導体装置を試料5(実施例)とした。試料5と同様の構造を有し重金属(白金)を導入していないものを試料6(比較例)とした。
カソード電極に対してアノード電極に逆方向電圧VR(0.05V~600V)を印加したときの各試料(試料5及び6)の静電容量を測定した。測定は、CV測定装置を用いて行った。
図17は、試験例2における静電容量を示す図である。図7中、符号S5は試料5についての静電容量を示し、符号S6は試料6についての静電容量を示す。
Claims (9)
- 第1導電型の第1半導体層と、前記第1半導体層よりも低濃度の第1導電型不純物を含有する第1導電型の第2半導体層とを有し、前記第1半導体層及び前記第2半導体層とがこの順序で積層された構造を有する半導体基体と、
前記第2半導体層の表面に選択的に形成され、第1導電型不純物とは反対導電型の第2導電型不純物を前記第2半導体層が含有する第1導電型不純物の濃度よりも高い濃度で含有する第2導電型の高濃度拡散領域と、
前記第2半導体層及び前記高濃度拡散領域の表面上に形成され、前記第2半導体層との間でショットキー接合を形成し、前記高濃度拡散領域との間でオーミック接合を形成するバリアメタル層とを備える半導体装置であって、
前記半導体基体には、前記第2半導体層内においては前記第2半導体層の表面で濃度が最も高くなるように重金属が拡散されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第2半導体層の表面における深さ位置をD1とし、
前記高濃度拡散領域の最深部における深さ位置をD2とし、
前記深さ位置D2よりも深く、かつ、前記第1半導体層と前記第2半導体層との境界面よりも浅い深さ位置をD3とし、
前記第1半導体層と前記第2半導体層との境界面における深さ位置をD4とし、
前記第1半導体層の表面における深さ位置をD5としたとき、
前記深さ位置D4における前記重金属の濃度は、前記深さ位置D3における前記重金属の濃度よりも高いことを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記深さ位置D3は、スイッチオフ時におけるテール電流を制御し得る深さ位置であることを特徴とする半導体装置。 - 請求項3に記載の半導体装置において、
前記深さ位置D2における前記重金属の濃度は、前記深さ位置D3における前記重金属の濃度よりも高いことを特徴とする半導体装置。 - 請求項1~4のいずれかに記載の半導体装置において、
前記深さ位置D1における前記重金属の濃度は、前記深さ位置D5における前記重金属の濃度よりも高いことを特徴とする半導体装置。 - 請求項1~5のいずれかに記載の半導体装置において、
前記重金属は、前記第1半導体層の表面側から拡散されてなることを特徴とする半導体装置。 - 請求項1~6のいずれかに記載の半導体装置において、
前記第2半導体層の表面における前記重金属の濃度は、前記高濃度拡散領域の表面における前記重金属の濃度よりも高いことを特徴とする半導体装置。 - 請求項1~6のいずれかに記載の半導体装置において、
前記高濃度拡散領域の表面における前記重金属の濃度は、前記第2半導体層の表面における前記重金属の濃度よりも高いことを特徴とする半導体装置。 - 請求項1~8のいずれかに記載の半導体装置において、
前記重金属は、白金であることを特徴とする半導体装置。
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EP2871679A1 (en) | 2015-05-13 |
EP2871679B1 (en) | 2019-02-06 |
CN104508823A (zh) | 2015-04-08 |
CN104508823B (zh) | 2017-03-01 |
JPWO2014006695A1 (ja) | 2016-06-02 |
JP5457613B1 (ja) | 2014-04-02 |
US9142624B2 (en) | 2015-09-22 |
EP2871679A4 (en) | 2016-03-09 |
US20150001667A1 (en) | 2015-01-01 |
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