WO2014005502A1 - 发光元件及其制作方法 - Google Patents

发光元件及其制作方法 Download PDF

Info

Publication number
WO2014005502A1
WO2014005502A1 PCT/CN2013/078623 CN2013078623W WO2014005502A1 WO 2014005502 A1 WO2014005502 A1 WO 2014005502A1 CN 2013078623 W CN2013078623 W CN 2013078623W WO 2014005502 A1 WO2014005502 A1 WO 2014005502A1
Authority
WO
WIPO (PCT)
Prior art keywords
light
layer
emitting element
semiconductor layer
emitting
Prior art date
Application number
PCT/CN2013/078623
Other languages
English (en)
French (fr)
Inventor
刘艳
吴裕朝
吴冠辰
王瑞庆
陈浩明
Original Assignee
Liu Yan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Liu Yan filed Critical Liu Yan
Publication of WO2014005502A1 publication Critical patent/WO2014005502A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/385—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate

Definitions

  • the present invention relates to the field of light-emitting elements, and in particular to a light-emitting element and a method of fabricating the same. Background technique
  • FIG. 1 is a schematic structural view of a gallium nitride (GaN) light emitting diode (LED) in the prior art.
  • the light emitting diode includes an n-type gallium nitride layer 20, a light emitting layer 30, a p-type gallium nitride layer 40, and an indium tin oxide (ITO) layer 90, which are sequentially formed on the substrate 10, wherein the n-type nitrogen
  • the gallium layer 20 and the p-type gallium nitride layer 40 are etched away to expose a portion of the n-type gallium nitride layer 20, and a negative electrode 82 is formed on the exposed n-type gallium nitride layer 20, in the p-type nitrogen
  • a positive electrode 81 is formed on the gallium layer 40 and the germanium layer 90, and a protective layer 61 is formed on the positive electrode 81, the germanium layer 90, the n-type gallium nitride layer
  • the electrodes must be disposed on the front side of the light emitting diode, that is, the positive electrode 81 is formed on the front surface of the p-type gallium nitride layer 40, and the negative electrode 82 is formed on the n-type nitride.
  • the surface of the p-type gallium nitride layer 40 must be etched from the surface of the p-type gallium nitride layer 40 to the n-type gallium nitride layer 20, and the etched trench must be sufficiently wide to be n-type by wire bonding.
  • the surface of the gallium nitride layer 20 forms a negative electrode 82.
  • the light-emitting region originally composed of the region in which the light-emitting layer 30 is located is etched away, thereby affecting the light-emitting effect; on the other hand, since the substrate 10 made of sapphire has poor thermal conductivity, the heat generated when the LED emits light It is difficult to disperse in time, which will reduce the performance of the LED. Summary of the invention
  • the technical problem to be solved by the present invention is how to reduce the light-shielding area of the light-emitting element, increase the current spreading efficiency, and increase the light-emitting area of the light-emitting element.
  • a light emitting device includes: a substrate; a first conductive semiconductor layer on the substrate; and a light emitting layer located at the first conductive a front surface of the semiconductor layer; a second conductive semiconductor layer on a front surface of the light emitting layer; a positive electrode on a front surface of the second conductive semiconductor layer; and a negative electrode at least partially located in the first conductive semiconductor The side of the layer.
  • a method of fabricating a light emitting device including: forming a first conductive type semiconductor layer on a substrate; and forming a first conductive type semiconductor layer on the first conductive type semiconductor layer Forming a light emitting layer on a front surface; forming a second conductive type semiconductor layer on a front surface of the light emitting layer; forming a first trench, the first trench extending from the second conductive type semiconductor layer to the first conductive type semiconductor a layer; a reflective layer formed on a front surface of the second conductive type semiconductor layer and a bottom surface and a peripheral surface of the first trench; an electrode layer formed on the reflective layer; and a separating step: removing a portion of the reflection The layer and the electrode layer are separated such that the electrode layer is separated from a positive electrode located on a front surface of the second conductive type semiconductor layer and a negative electrode at least partially located on a side surface of the first conductive type semiconductor layer.
  • the light-emitting element and the manufacturing method thereof provided by the embodiment of the invention effectively reduce the light-shielding area of the conventional light-emitting element and improve the current spreading efficiency by forming the negative electrode on the side surface of the light-emitting element;
  • the negative electrode needs to etch less light-emitting layer, thereby increasing the light-emitting area and improving the light-emitting quality of the light-emitting element;
  • the heat emitted by the light-emitting layer is close to the printed circuit board (PCB), The heat conduction effect can be better; further, since the light-emitting element fabricated by the method provided by the present invention can be bonded or soldered to the PCB by flip chip technology, the wire connection cost is reduced.
  • PCB printed circuit board
  • FIG. 1 is a schematic structural view of a gallium nitride light emitting diode in the prior art
  • FIG. 2 is a flow chart of a method for fabricating a light-emitting element according to an embodiment of the present invention
  • 3(a)-3(d) are cross-sectional views of light emitting elements in respective processes of a method of fabricating a light emitting device according to an embodiment of the present invention
  • Figure 3 (e) is a perspective view corresponding to Figure 3 (d);
  • FIG. 4 is a cross-sectional view of a light emitting device in a method of fabricating a light emitting device according to another embodiment of the present invention.
  • Figure 5 is a schematic view showing the light-emitting element shown in Figure 4 connected to a PCB;
  • 6(a)-6(e) are cross-sectional views showing a light-emitting element in each process of a method for fabricating a light-emitting element according to still another embodiment of the present invention.
  • Figure 7 (a) - Figure 7 (b) is a schematic structural view of a PCB connected to the light-emitting element shown in Figure 6 (e) and a schematic structural view after packaging;
  • FIG. 8 is a cross-sectional view of a light-emitting element having a tilted negative electrode according to an embodiment of the present invention
  • FIG. 9 is a cross-sectional view of a light-emitting element having a tilted negative electrode according to another embodiment of the present invention.
  • 10(a) and 10(b) are respectively a perspective view and a cross-sectional view of a light-emitting element having a three-sided negative electrode according to an embodiment of the present invention
  • FIG. 11 is a perspective view of a light-emitting element having a double-sided negative electrode according to an embodiment of the present invention
  • FIG. 12 is a perspective view of a light-emitting element having a double-sided negative electrode according to another embodiment of the present invention
  • FIG. 13 is a perspective view of a light-emitting element having a single-sided negative electrode according to an embodiment of the present invention
  • FIG. 14 (a) - FIG. 14 (c) are perspective views of a light-emitting element having a plurality of positive electrodes according to an embodiment of the present invention, respectively. , section and top view;
  • Figure 15 is a top plan view of a light-emitting element having a plurality of positive electrodes according to another embodiment of the present invention.
  • 16 is a schematic structural diagram of a light emitting device after packaging according to an embodiment of the present invention.
  • Figure 17 (a) - Figure 17 (b) are a cross-sectional view and a plan view, respectively, of a high voltage LED according to an embodiment of the present invention.
  • FIG. 3(d) is a schematic structural diagram of a light-emitting element according to an embodiment of the present invention, the light-emitting element
  • the device includes: a substrate 10, a first conductive type semiconductor layer 20, a light emitting layer 30, and a second conductive type semiconductor layer 40 sequentially formed on the substrate 10, further comprising a positive electrode 81 and a negative electrode 82, wherein the positive electrode 81 is formed on the first On the front surface of the two-conductivity-type semiconductor layer 40, the negative electrode 82 is formed at least partially on the side surface of the first-conductivity-type semiconductor layer 20.
  • the first conductive type semiconductor layer 20 in the present embodiment is made of n-type gallium nitride
  • the second conductive type semiconductor layer 40 is made of a p-type gallium nitride layer.
  • the side of the p-type gallium nitride layer 40 away from the light-emitting layer 30 is referred to as the front side
  • the side contacting the light-emitting layer 30 is referred to as the back side
  • the remaining four sides are referred to as the side surfaces.
  • One side of the n-type gallium nitride layer 20 contacting the light-emitting layer 30 is referred to as a front surface
  • the side contacting the substrate 10 is referred to as a back surface
  • the remaining four faces are referred to as side faces.
  • One side of the light-emitting layer 30 contacting the p-type gallium nitride layer 40 is referred to as a front surface
  • the side contacting the n-type gallium nitride layer 20 is referred to as a back surface
  • the light-emitting layer 30 is not associated with an n-type gallium nitride layer 20 and a p-type.
  • the four faces in contact with the gallium nitride layer 40 are referred to as sides.
  • the negative electrode 82 is formed only on the side of the n-type gallium nitride layer 20, and the direction is perpendicular to the lateral plane of the n-type gallium nitride layer 20; in other embodiments, negative The electrode 82 may also be formed on the side surface and the front surface of the n-type gallium nitride layer 20 (the structure may be as shown in FIG. 4) according to actual needs; or may be formed on the side of the n-type gallium nitride layer 20 and the side of the light-emitting layer 30.
  • the side surface of the p-type gallium nitride layer 40 and the front surface of the p-type gallium nitride layer 40 may be located on the side surface of the n-type gallium nitride layer 20.
  • the negative electrode 82 may also be obliquely formed on the side surface of the n-type gallium nitride layer 20 (the structure thereof may be as shown in FIG. 8).
  • the side surface of the n-type gallium nitride layer 20 on which the negative electrode 82 is formed is also It is a corresponding inclined surface; it can also be formed obliquely on the side and front side of the n-type gallium nitride layer 20 (the structure can be as shown in FIG. 9). This structure is more advantageous for the subsequent packaging process when the negative electrode 82 is formed obliquely.
  • the negative electrode 82 of the present embodiment may be formed on four sides of the n-type gallium nitride layer 20 (the structure may be as shown in FIG. 3(e)); or may be formed in the n-type according to actual needs.
  • Three sides of the gallium nitride layer 20 (the structure can be as shown in FIG. 10 (a) and FIG. 10 (b)); can also be formed in n-type gallium nitride
  • the opposite two sides the structure may be as shown in FIG. 11
  • the adjacent two sides the structure may be as shown in FIG. 12
  • One side of the gallium nitride layer 20 (the structure of which can be as shown in FIG. 13).
  • the light-emitting element formed of the negative electrode 82 formed on the four side faces of the n-type gallium nitride layer 20 has the best current spreading efficiency.
  • the light emitting element provided in this embodiment may further include a protective layer 61 formed between the positive electrode 81 and the negative electrode 82 and extending from the p-type gallium nitride layer 40 to the n-type gallium nitride.
  • Layer 20 (the structure can be as shown in Figure 6 (e)).
  • the protective layer 61 can be formed in a grid or a plurality of strips to divide the positive electrode 81 into a plurality of squares (the structure can be as shown in FIG. 14(a) - FIG. 14(c)) or a triangle (which is The structure may be as shown in Figure 15 or other shaped electrodes connecting a plurality of positive electrodes 81 and negative electrodes 82 together.
  • the negative electrode 82 may be formed in a spiral shape or other shape such that the other end thereof is closer to the positive electrode 81 located at the intermediate portion of the light-emitting element, so that the current can be evenly distributed.
  • FIG. 2 is a flow chart of a method for fabricating a light-emitting element according to an embodiment of the present invention, and combined with FIG. 3
  • Step S10 the first conductive type semiconductor layer 20, the light emitting layer 30, and the second conductive type semiconductor layer 40 are sequentially formed on the substrate 10.
  • the substrate 10 may be specifically a sapphire substrate.
  • the material of the first conductive semiconductor layer 20 may be n-type gallium nitride or n-type aluminum indium gallium arsenide (AlGalnP); the material of the second conductive semiconductor layer 40 may be p-type gallium nitride or It is p-type aluminum indium gallium phosphide.
  • the first conductive type semiconductor layer 20 and the second conductive type semiconductor layer 40 in the respective embodiments of the present application are made of n-type gallium nitride and p-type gallium nitride, respectively.
  • Step S20 forming at least one first trench 50 on the light-emitting element shown in FIG. 3(a) obtained in step S10, the first trench 50 extending from the p-type gallium nitride layer 40 to the n-type Gallium nitride layer 20.
  • the number, width and shape of the first grooves 50 in this step are not particularly limited.
  • the first trench 50 may be formed on the four sides of the light emitting element in a ring shape; the first trench 50 may also be formed on two sides, three sides or one side of the light emitting element.
  • Step S30 the reflective layer 70 and the electrode layer 80 are sequentially formed on the light-emitting element shown in Fig. 3(b) obtained in the step S20.
  • a reflective layer 70 is formed on the front surface of the p-type gallium nitride 40 and the bottom surface and the peripheral surface of the first trench 50.
  • the material of the reflective layer 70 may be a metal or semiconductor having good electrical conductivity.
  • a prior art Step Coverage process can be employed.
  • the material of the electrode layer 80 may be gold or other conductive metal, and the electrode layer 80 needs to completely cover the reflective layer 70, as shown in Fig. 3(c). In addition, this step can be achieved by a coating process.
  • Step S40 removing the partially reflective layer 70 and the electrode layer 80 such that the electrode layer 80 is separated into a positive electrode 81 on the front side of the p-type gallium nitride layer 40 and a negative electrode 82 on the side of the n-type gallium nitride layer 20. .
  • This step can be achieved by etching or stripping.
  • the size of the positive electrode 81 varies depending on the package method. If the flip chip technology is used for packaging, the larger the area of the positive electrode 81 is, the better (as shown in Fig. 10 (a), Fig. 10 (b)); however, if the conventional wire bonding method is adopted, the area of the positive electrode 81 is required. Keep it as small as possible (as shown in Figure 3 (e)), as long as you can connect the cable to reduce the shading area. Further, the negative electrode 82 may be entirely located on the side of the n-type gallium nitride layer 20 or partially on the side of the n-type gallium nitride layer 20.
  • the negative electrode may be located on the side of the n-type gallium nitride layer 20, the side of the light-emitting layer 30, the side of the p-type gallium nitride layer 40, and the front side of the p-type gallium nitride layer 40.
  • step S20 or after step S40 the following steps may be further included:
  • Step S20' at least one second trench 60 is formed on the light-emitting element obtained in the previous step, and the second trench 60 extends from the p-type gallium nitride layer 40 to the n-type gallium nitride layer 20, A protective layer 61 is formed in the two trenches 60.
  • the material of the protective layer 61 must be insulated and poor in conductivity, stable in structure and difficult to be used with other materials. chemical reaction.
  • the material of the protective layer 61 in this step is silicon dioxide (SiO 2 ).
  • a plurality of light-emitting elements may be packaged onto a PCB board 91 according to actual needs, and the structure thereof may be as shown in FIG. 16, which is simpler than the conventional wire bonding method, and has A light-emitting element having a single-sided negative electrode and a light-emitting element having a double-sided negative electrode can be packaged in this manner.
  • a plurality of light-emitting elements can be connected in series to form a high-voltage LED (HVLED).
  • HVLED high-voltage LED
  • the first trench 50 needs to be etched to the substrate 10, and the respective negative electrodes 82 are separated by the non-conductivity of the substrate 10.
  • the electrode layer 80 still extends to the n-type gallium nitride layer 20, i.e., the negative electrode 82 is still formed on the side of the n-type gallium nitride layer 20.
  • forming a protective layer 61 in a portion of the first trench 50 without the electrode layer 80, and then respectively connecting each of the positive electrode 81 and the negative electrode 82 in series (the structure can be as shown in FIG. 17(a) - FIG. 17(b) Show).
  • Figure 3 (a) - Figure 3 (d) is a cross-sectional view of a light-emitting element in each process of a method of fabricating a light-emitting element according to an embodiment of the present invention.
  • the positive electrode 81 is located on the front surface of the p-type gallium nitride layer 40, and the negative electrode 82 is located on the side of the n-type gallium nitride layer 20.
  • the method includes the following steps:
  • Step S101 an n-type gallium nitride layer 20, a light-emitting layer 30, and a p-type gallium nitride layer 40 are sequentially formed on the substrate 10.
  • the substrate 10 in this step may specifically be a sapphire substrate.
  • the structure of the light-emitting element obtained in this step can be as shown in Fig. 3 (a).
  • Step S102 a first trench 50 is formed along the outer side of the light-emitting element on the light-emitting element obtained in step S101.
  • the first trench 50 also extends downward from the p-type gallium nitride layer 40 to the n-type gallium nitride layer 20.
  • the first trench 50 is located on four sides of the light-emitting element and has a ring shape.
  • Step S103, the reflective layer 70 and the electrode layer 80 are sequentially formed on the light-emitting element obtained in step S102.
  • the reflective layer 70 and the electrode layer 80 in this step are located on the front surface of the p-type gallium nitride layer 40 and the bottom surface and the circumferential surface of the first trench 50, and the electrode layer 80 The reflective layer 70 is completely covered.
  • Step S104 removing the partially reflective layer 70 and the electrode layer 80 to separate the electrode layer 80 into the positive electrode 81 and the negative electrode 82.
  • the reflective layer 70 and the electrode layer 80 in the first trench 50 are etched or peeled off. Further, since the present embodiment adopts a wire bonding process, most of the reflective layer 70 and the electrode layer 80 on the front surface of the p-type gallium nitride layer 40 are removed, leaving only the front center of the p-type gallium nitride layer 40. A part of the electrode layer 80 of a small area may be used as the positive electrode 81.
  • the positive electrode 81 is located on the front surface of the p-type gallium nitride 40, and the negative electrode 82 is located on the side of the n-type gallium nitride layer 20.
  • the method includes the following steps:
  • Steps S201-S203 are the same as steps S101-S103; reference can be made to Figs. 3(a) - 3(c).
  • Step S204 removing the partially reflective layer 70 and the electrode layer 80 to separate the electrode layer 80 into the positive electrode 81 and the negative electrode 82.
  • this step differs from step S104 in that a portion of the electrode layer at the bottom of the first trench 50 is left such that the electrode layer 80 on the front side and the side surface of the n-type gallium nitride layer 20 constitutes the negative electrode 82. . Further, since the light-emitting element of the present embodiment is packaged by a flip chip technique, the area of the positive electrode 81 formed on the front surface of the p-type gallium nitride layer 40 can be made as large as possible.
  • the light-emitting element obtained in step S204 is inverted, and the positive electrode 81 is soldered or bonded or sintered on the printed circuit board in the direction of the arrow shown in FIG.
  • the negative electrode 82 may be soldered or bonded to the upper surface of the PCB 91 in the recess 93 on the (PCB) 91.
  • the PCB 91 in this embodiment is specifically a two-layer metal printed circuit board (MCPCB) with a thermally conductive insulating layer 92 between the two layers of metal. In this case, the two layers of metal of PCB 91 can be used as separate Positive and negative electrodes.
  • FIG. 6 (a) - FIG. 6 (e) are respectively a cross-sectional view of a light-emitting element in each process of a method for fabricating a light-emitting element according to another embodiment of the present invention; a light-emitting element fabricated by the method, a negative electrode 82
  • the front surface and the side surface of the p-type gallium nitride layer 40, the side surface of the light-emitting layer 30, and the side surface of the n-type gallium nitride layer 20 are formed.
  • the method includes:
  • Step S301 is the same as step S101; reference can be made to Fig. 3(a).
  • Step S302 forming a second trench 60 on the light-emitting element obtained in the previous step, and forming a protective layer 61 in the second trench 60.
  • the second trench 60 extends downward from the p-type gallium nitride layer 40 to the n-type gallium nitride layer 20, and the second trench 60 is located in the light-emitting element.
  • the four sides are ring-shaped.
  • the material of the protective layer 61 is preferably SiO 2 for isolating the luminescent layer 30 to prevent the luminescent layer 30 from being contaminated in subsequent fabrication processes.
  • Step S303 forming a first trench 50 on the light-emitting element obtained in step S202.
  • the first trench 50 is located outside the second trench 60, and the first trench 50 may be the same depth as the second trench 60 or may be deeper than the second trench 60 ( 6 (b) shows a case where the first trench 50 is deeper than the second trench 60); the first trench 50 also extends downward from the p-type gallium nitride layer 40 to the n-type gallium nitride layer 20
  • the first trench 50 may be formed adjacent to the second trench 60 or may be formed with the second trench
  • the first trench 50 is also ring-shaped. .
  • Step S304 sequentially forming a reflective layer 70 and an electrode layer on the light-emitting element obtained in the previous step
  • the reflective layer 70 and the electrode layer 80 are formed on the front surface of the p-type gallium nitride layer 40, the front surface of the protective layer 61, and the bottom surface and the periphery of the first trench 50. surface.
  • Step S305 the partially reflective layer 70 and the electrode layer 80 are removed to separate the electrode layer 80 into the positive electrode 81 and the negative electrode 82. Specifically, as shown in FIG. 6(d), the reflective layer 70 and the electrode layer 80 corresponding to the front surface of the protective layer 61 are etched or peeled off.
  • Step S306 cutting the light-emitting element obtained in the previous step along the circle in which the first trench 50 is located to form a positive electrode 81 on the front surface of the p-type gallium nitride layer 40 and a p-type gallium nitride layer.
  • the front side and the side surface of the 40, the side surface of the light emitting layer 30, and the side negative electrode 82 of the n-type gallium nitride layer 20 may have a structure as shown in Fig. 6(e).
  • FIG. 7(a) shows a schematic structural view of another PCB 91
  • FIG. 7(b) shows a schematic structural view of the light-emitting element and the PCB 91 of FIG. 6(e).
  • the light-emitting element and the manufacturing method thereof provided by the embodiment of the invention effectively reduce the light-shielding area of the conventional light-emitting element and improve the current spreading efficiency by forming the negative electrode on the side surface of the light-emitting element;
  • the negative electrode needs to etch less light-emitting layer, thereby increasing the light-emitting area and improving the light-emitting quality of the light-emitting element; on the other hand, since the heat emitted by the light-emitting layer is closer to the PCB, the heat conduction effect can be better; Since the light-emitting element fabricated by the method provided by the present invention can be bonded or soldered to the PCB by flip chip technology, the wire connection cost is reduced.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

一种发光元件及其制作方法，该发光元件包括：基板；第一导电型半导体层，位于所述基板上；发光层，位于所述第一导电型半导体层的正面；第二导电型半导体层，位于所述发光层的正面；正电极，位于所述第二导电型半导体层的正面；以及负电极，至少部分位于所述第一导电型半导体层的侧面。所述发光二极管及其制作方法，通过把负电极形成于发光元件的侧面上，有效减少了传统发光元件的遮光面积，并且提高了电流散布效率；同时由于形成于侧面的负电极所需蚀刻掉的发光层较少，从而增加了发光区域，改善了发光元件的发光品质。

Description

发光元件及其制作方法
技术领域
[01]本发明涉及发光元件技术领域， 具体涉及一种发光元件及其制作方法。 背景技术
[02] 图 1为现有技术中氮化镓（GaN)发光二极管（Light Emitting Diode, LED) 的结构示意图。 如图 1所示， 该发光二极管包括依次形成于基板 10上的 n型氮 化镓层 20、 发光层 30、 p型氮化镓层 40以及氧化铟锡 （ITO) 层 90， 其中 η型 氮化镓层 20和 ρ型氮化镓层 40被蚀刻掉一部分而暴露了部分 η型氮化镓层 20， 在该暴露的 η型氮化镓层 20上形成有负电极 82， 在 ρ型氮化镓层 40以及 ΙΤΟ层 90上形成有正电极 81， 并在正电极 81、 ΙΤΟ层 90、 η型氮化镓层 20以及负电极 82上形成有保护层 61。
[03] 由于蓝宝石 （Sapphire) 制作的基板 10不导电， 故电极必须设置在发光 二极管的正面， 即正电极 81形成于 p型氮化镓层 40的正面， 负电极 82形成于 n 型氮化镓 20的正面。 这种结构中， 无论发光二极管如何放置， 其电流方向都 是垂直的。 但是在制作负电极 82时， 必须将发光二极管由 p型氮化镓层 40的 表面蚀刻至 n型氮化镓层 20， 且蚀刻的沟槽必须足够宽， 才能通过打线的方 式在 n型氮化镓层 20的表面形成负电极 82。 这样， 原本由发光层 30所在的区 域构成的发光区域就被蚀刻掉了一部分， 从而影响了发光效果； 另一方面由 于蓝宝石制作的基板 10的导热性较差， 因此 LED发光时所产生的热量难以及 时散出， 从而会降低 LED的性能。 发明内容
技术问题 [04]本发明要解决的技术问题是如何减少发光元件的遮光面积，并提高电流 散布效率， 增加发光元件的发光区域。
解决方案
[05]为了解决上述技术问题，根据本发明的一实施例，提供了一种发光元件， 包括： 基板； 第一导电型半导体层， 位于所述基板上； 发光层， 位于所述第 一导电型半导体层的正面； 第二导电型半导体层， 位于所述发光层的正面； 正电极， 位于所述第二导电型半导体层的正面； 以及负电极， 至少部分位于 所述第一导电型半导体层的侧面。
[06]为了解决上述技术问题， 根据本发明的另一实施例， 提供了一种发光元 件制作方法， 包括： 在基板上形成第一导电型半导体层； 在所述第一导电型 半导体层的正面形成发光层； 在所述发光层的正面形成第二导电型半导体 层； 形成第一沟槽， 所述第一沟槽从所述第二导电型半导体层延伸至所述第 一导电型半导体层； 在所述第二导电型半导体层的正面以及所述第一沟槽的 底面和周面上形成反射层； 在所述反射层上形成电极层； 以及分离步骤： 去 除掉部分所述反射层和所述电极层， 使得所述电极层分离成位于所述第二导 电型半导体层的正面的正电极和至少部分位于所述第一导电型半导体层的 侧面的负电极。
有益效果
[07]本发明实施例提供的发光元件及其制作方法，通过把负电极形成于发光 元件的侧面上， 有效减少了传统发光元件的遮光面积， 并且提高了电流散布 效率； 同时由于形成于侧面的负电极所需蚀刻掉的发光层较少， 从而增加了 发光区域， 改善了发光元件的发光品质； 另一方面由于发光层散发的热量由 于离印刷电路板（PrintedCircuitBoard, PCB )较近， 因此可以导热效果更好； 进一步地由于采用本发明提供的方法制作的发光元件可以采用覆晶技术通 过粘接或焊接的方式连接到 PCB板上， 因此降低了导线连接成本。 [08]根据下面参考附图对示例性实施例的详细说明，本发明的其它特征及方 面将变得清楚。 附图说明
[09]包含在说明书中并且构成说明书的一部分的附图与说明书一起示出了 本发明的示例性实施例、 特征和方面， 并且用于解释本发明的原理。
图 1是现有技术中氮化镓发光二极管的结构示意图；
图 2是本发明一个实施例提供的发光元件制作方法的流程图；
图 3 (a) -图 3 (d)分别是本发明一个实施例提供的发光元件制作方法的 各工艺过程中发光元件的剖面图；
图 3 (e) 是与图 3 (d) 对应的立体图；
图 4是本发明另一个实施例提供的发光元件制作方法中发光元件的剖面 图；
图 5是图 4所示的发光元件与 PCB板连接的示意图；
图 6 (a) -图 6 (e)分别是本发明又一个实施例提供的发光元件制作方法 的各工艺过程中发光元件的剖面图；
图 7 (a) -图 7 (b)分别是与图 6 (e)所示的发光元件连接的 PCB的结构 示意图以及封装后的结构示意图；
图 8是本发明一个实施例提供的具有倾斜负电极的发光元件的剖面图； 图 9是本发明另一个实施例提供的具有倾斜负电极的发光元件的剖面 图；
图 10 (a) 和图 10 (b) 分别是本发明一个实施例提供的具有三面负电极 的发光元件的立体图和剖面图；
图 11是本发明一个实施例提供的具有双面负电极的发光元件的立体图； 图 12是本发明另一个实施例提供的具有双面负电极的发光元件的立体 图； 图 13是本发明一个实施例提供的具有单面负电极的发光元件的立体图； 图 14 (a) -图 14 (c)分别是本发明一个实施例提供的具有若干正电极的 发光元件的立体图、 剖面图和俯视图；
图 15是本发明另一个实施例提供的具有若干个正电极的发光元件的俯 视图；
图 16是本发明一个实施例提供的封装之后的发光元件的结构示意图； 以 及
图 17 (a) -图 17 (b)分别是本发明一个实施例提供的高压 LED的剖面图 和俯视图。
附图标记列表
10： 基板； 20: n型氮化镓层； 30: 发光层； 40: p型氮化镓层； 50: 第 一沟槽； 60: 第二沟槽； 61 : 保护层； 70: 反射层； 80: 电极层； 81 : 正电 极； 82: 负电极； 90: ITO层； 91 : PCB; 92： 导热绝缘层； 93: 凹槽 100。 具体实施方式
[10] 以下将参考附图详细说明本发明的各种示例性实施例、 特征和方面。 附 图中相同的附图标记表示功能相同或相似的元件。尽管在附图中示出了实施 例的各种方面， 但是除非特别指出， 不必按比例绘制附图。
[11]在这里专用的词"示例性 "意为 "用作例子、 实施例或说明性"。 这里作为
"示例性"所说明的任何实施例不必解释为优于或好于其它实施例。
[12]另外， 为了更好的说明本发明， 在下文的具体实施方式中给出了众多的 具体细节。 本领域技术人员应当理解， 没有这些具体细节， 本发明同样可以 实施。 在另外一些实例中， 对于大家熟知的方法、 手段、 元件和电路未作详 细描述， 以便于凸显本发明的主旨。
[13] 图 3 (d)是本发明一个实施例提供的发光元件的结构示意图， 该发光元 件包括： 基板 10， 依次形成于基板 10上的第一导电型半导体层 20、 发光层 30 以及第二导电型半导体层 40， 还包括正电极 81和负电极 82， 其中正电极 81形 成于第二导电型半导体层 40的正面， 负电极 82至少部分形成于第一导电型半 导体层 20的侧面。
[14]优选地， 本实施例中的第一导电型半导体层 20采用 n型氮化镓制作， 第 二导电型半导体层 40采用 p型氮化镓层制作。
[15]本实施例中， 将 p型氮化镓层 40远离发光层 30的一面称之为正面， 将接 触发光层 30的一面称之为背面， 将剩下的四个面称之为侧面。 将 n型氮化镓 层 20接触发光层 30的一面称之为正面， 将接触基板 10的一面称之为背面， 将 剩下的四个面称之为侧面。 将发光层 30接触 p型氮化镓层 40的一面称之为正 面， 接触 n型氮化镓层 20的一面称之为背面， 将发光层 30不与 n型氮化镓层 20 和 p型氮化镓层 40接触的四个面称之为侧面。
[16]本实施例中， 优选地， 负电极 82仅形成于 n型氮化镓层 20的侧面， 方向 为垂直于 n型氮化镓层 20所在的横向平面； 于其它实施例中， 负电极 82也可 以根据实际需要形成于 n型氮化镓层 20的侧面和正面（其结构可如图 4所示）； 还可以形成于 n型氮化镓层 20的侧面、 发光层 30的侧面、 p型氮化镓层 40的侧 面以及 p型氮化镓层 40的正面 （其结构可如图 6 (e)所示）， 只要有一部分位 于 n型氮化镓层 20的侧面即可。 而且， 负电极 82还可以倾斜形成于 n型氮化镓 层 20的侧面 （其结构可如图 8所示）， 这种情况下， n型氮化镓层 20形成有负 电极 82的侧面也为相应的倾斜面； 还可以倾斜形成于 n型氮化镓层 20的侧面 和正面 （其结构可如图 9所示）。 当负电极 82倾斜形成时， 这种结构更有利于 后续封装工艺的进行。
[17]此外，本实施例的负电极 82可以形成于 n型氮化镓层 20的四个侧面上（其 结构可如图 3 (e)所示）； 也可以根据实际需要形成于 n型氮化镓层 20的三个 侧面上 （其结构可如图 10 (a) 和图 10 (b) 所示）； 还可以形成于 n型氮化镓 层 20的两个侧面上， 相对的两个侧面 （其结构可如图 11所示）或者相邻的两 个侧面 （其结构可如图 12所示） 皆可； 还可以只形成于 n型氮化镓层 20的一 个侧面上（其结构可如图 13所示）。 上述方案中， 形成于 n型氮化镓层 20的四 个侧面上的负电极 82所构成的发光元件的电流散布效率最好。
[18]进一步地， 本实施例提供的发光元件还可以包括保护层 61， 保护层 61形 成于正电极 81和负电极 82之间并从 p型氮化镓层 40延伸至 n型氮化镓层 20 (其 结构可如图 6 (e) 所示）。
[19]此外， 为了提高电流散布效率， 以及对于发光元件太大的情况， 仅靠侧 面的负电极 82导电可能会导致电流不会流到发光元件的中间部分，从而降低 中间部分的发光效率， 因此可以将保护层 61做成田字格状或多个条状， 以将 正电极 81分隔成若干个方形（其结构可如图 14 (a) -图 14 (c)所示）或三角 形（其结构可如图 15所示）或其它形状的电极， 将若干个正电极 81与负电极 82连接在一起。 或者将负电极 82做成螺旋状或其他形状， 使其另一端能够离 位于发光元件中间部分的正电极 81较近， 从而使得电流能够分布均匀。
[20] 图 2是本发明一个实施例提供的发光元件制作方法的流程图，并结合图 3
(a) -图 3 (d) 所示， 该方法包括：
[21]步骤 S10、 在基板 10上依次形成第一导电型半导体层 20、 发光层 30以及 第二导电型半导体层 40。
[22]本实施例中， 基板 10可具体为蓝宝石基板。第一导电型半导体层 20的材 料可以为 n型氮化镓， 也可以为 n型磷化铝铟镓（AlGalnP); 第二导电型半导 体层 40的材料可以为 p型氮化镓， 也可以为 p型磷化铝铟镓。 优选地， 本申请 各实施例中的第一导电型半导体层 20和第二导电型半导体层 40分别采用 n型 氮化镓和 p型氮化镓制作。
[23]步骤 S20、 在步骤 S10得到的如图 3 (a)所示的发光元件上形成至少一个 第一沟槽 50， 该第一沟槽 50从 p型氮化镓层 40延伸至 n型氮化镓层 20。 [24]本步骤中第一沟槽 50的数量、 宽度与形状均无特殊限定。第一沟槽 50可 以形成于发光元件的四个侧面上， 呈圈状； 第一沟槽 50还可以形成于发光元 件的两个侧面、 三个侧面或一个侧面上。
[25]步骤 S30、 在步骤 S20得到的如图 3 (b)所示的发光元件上依次形成反射 层 70和电极层 80。
[26]具体地， 在 p型氮化镓 40的正面以及第一沟槽 50的底面和周面形成反射 层 70。 该反射层 70的材料可以为导电性能较好的金属或半导体。 在形成反射 层 70时， 为了增加表面的接触面积， 可以采用现有技术中的阶梯覆盖 （Step Coverage) 工艺。 电极层 80的材料可为金或其它导电金属， 电极层 80需完全 覆盖反射层 70， 如图 3 (c) 所示。 此外， 本步骤可以采用镀膜工艺来实现。
[27]步骤 S40、 去除掉部分反射层 70和电极层 80， 使得电极层 80分离成位于 p 型氮化镓层 40正面的正电极 81和位于 n型氮化镓层 20侧面的负电极 82。
[28]本步骤可以采用蚀刻或者剥离的工艺来实现。正电极 81的大小根据封装 方式的不同而不同。 若采用覆晶技术封装， 正电极 81的面积越大越好（如图 10 (a)、 图 10 (b) 所示）； 然而， 若采用传统的打线封装方式， 则正电极 81 的面积需要尽量小 （如图 3 (e) 所示）， 只要能够打上连接线即可， 以减少 遮光面积。 此外， 负电极 82可以全部位于 n型氮化镓层 20的侧面， 也可以部 分位于 n型氮化镓层 20的侧面。 例如： 负电极可位于 n型氮化镓层 20的侧面、 发光层 30的侧面、 p型氮化镓层 40的侧面以及 p型氮化镓层 40的正面。
[29]此外， 为了保护因蚀刻沟槽而暴露的发光层， 于步骤 S20之前或步骤 S40 之后， 还可包括以下步骤：
[30]步骤 S20'， 在上一步骤得到的发光元件上形成至少一个第二沟槽 60， 第 二沟槽 60从 p型氮化镓层 40延伸至 n型氮化镓层 20，在第二沟槽 60中形成保护 层 61。
[31]该保护层 61的材料必须绝缘且导电性差，结构稳定且不易与其它材料起 化学反应。 优选地， 本步骤中保护层 61的材料为二氧化硅 （Si02)。
[32]优选地， 为了节省成本， 可以根据实际需要将若干个发光元件封装到一 块 PCB板 91上， 其结构可如图 16所示， 这种封装方式比传统打线方式更为简 单， 具有单面负电极的发光元件、 具有双面负电极的发光元件均可以采用这 种方式来封装。
[33]此外还可以串联几个发光元件制成高压 LED (HVLED)o 这种情况下， 第一沟槽 50需要蚀刻至基板 10， 利用基板 10的不导电性将各个负电极 82隔 开。 但是电极层 80仍延伸至 n型氮化镓层 20， 即负电极 82仍然形成于 n型氮化 镓层 20的侧面。 并在第一沟槽 50中没有电极层 80的部分形成保护层 61， 然后 将各个正电极 81以及负电极 82分别串联即可（其结构可如图 17 (a) -图 17 (b ) 所示）。
[34]此外还可以于本实施例的发光元件上覆盖上荧光粉以制成白光 LED。
[35]下面以具体的实施例来对发光元件制作方法进行说明。
[36] 图 3 (a) -图 3 (d) 为本发明一个实施例提供的发光元件制作方法的各 工艺过程中发光元件的剖面图。 本方法形成的发光元件， 正电极 81位于 p型 氮化镓层 40的正面， 负电极 82位于 n型氮化镓层 20的侧面。 该方法包括以下 步骤：
[37]步骤 S101、在基板 10上依次形成 n型氮化镓层 20、发光层 30和 p型氮化镓 层 40。
[38]本步骤中的基板 10可具体为蓝宝石基板。该步骤得到的发光元件结构可 如图 3 (a) 所示。
[39]步骤 S102、在步骤 S101得到的发光元件上沿着该发光元件的外侧形成第 一沟槽 50。
[40]结合图 3 (b)所示， 第一沟槽 50也从 p型氮化镓层 40向下延伸至 n型氮化 镓层 20。 第一沟槽 50位于发光元件的四个侧面上， 呈圈状。 [41]步骤 S103、 在步骤 S102得到的发光元件上依次形成反射层 70和电极层 80。
[42]结合图 3 (c) 所示， 本步骤中的反射层 70和电极层 80位于 p型氮化镓层 40的正面以及第一沟槽 50的底面和周面上， 且电极层 80完全覆盖反射层 70。
[43]步骤 S104、 去除掉部分反射层 70和电极层 80， 以将电极层 80分离为正电 极 81和负电极 82。
[44]结合图 3 (d) 以及图 3 (e)所示， 具体地， 将第一沟槽 50中的反射层 70 和电极层 80蚀刻或剥离掉。 进一步地， 由于本实施例采用打线封装工艺， 因 此将 p型氮化镓层 40正面的大部分反射层 70和电极层 80都去除掉， 仅留下位 于 p型氮化镓层 40正面中央较小面积的一部分电极层 80作为正电极 81即可。
[45] 图 4为本发明另一个实施例提供的发光元件制作方法中的发光元件的剖 面图。 本方法形成的发光元件， 正电极 81位于 p型氮化镓 40的正面， 负电极 82位于 n型氮化镓层 20的侧面。 该方法包括以下步骤：
[46]步骤 S201-S203、 与步骤 S101-S103相同； 可参考图 3 (a) -图 3 (c)所示。
[47]步骤 S204、去除掉部分反射层 70和电极层 80， 以将电极层 80分离为正电 极 81和负电极 82。
[48]结合图 4所示， 本步骤与步骤 S104的区别在于： 保留第一沟槽 50底部的 部分电极层， 使得位于 n型氮化镓层 20正面和侧面的电极层 80构成负电极 82。 此外， 本实施例的发光元件采用覆晶技术来封装， 因此形成于 p型氮化镓层 40的正面的正电极 81的面积可以尽量大。
[49]在后续采用覆晶技术的封装工艺中， 如图 5所示， 将步骤 S204得到的发 光元件倒置， 按照图 5所示箭头方向将正电极 81焊接或粘接或烧结在印刷电 路板（PCB ) 91上的凹槽 93内， 将负电极 82焊接或粘接在 PCB 91的上表面上 即可。 本实施例中的 PCB 91具体为双层金属印刷电路板（MCPCB ) , 两层金 属之间具有导热绝缘层 92。这种情况下， 可以将 PCB 91的两层金属分别作为 正极和负极。
[50] 图 6 (a) -图 6 (e)分别是本发明又一个实施例提供的发光元件制作方法 的各工艺过程中发光元件的剖面图； 采用该方法制作的发光元件， 负电极 82 形成于 p型氮化镓层 40的正面和侧面、发光层 30的侧面以及 n型氮化镓层 20的 侧面。 该方法包括：
[51]步骤 S301、 与步骤 S101相同； 可参考图 3 (a) 所示。
[52]步骤 S302、在上一步骤得到的发光元件上形成第二沟槽 60， 并在第二沟 槽 60中形成保护层 61。
[53]结合图 6 (a) 所示， 本实施例中， 第二沟槽 60从 p型氮化镓层 40向下延 伸至 n型氮化镓层 20， 第二沟槽 60位于发光元件的四个侧面上并呈圈状。 保 护层 61的材料优选为 Si02， 用于对发光层 30进行隔离， 避免发光层 30在后续 制作工艺中受到污染。
[54]步骤 S303、 在步骤 S202得到的发光元件上形成第一沟槽 50。
[55]结合图 6 (b)所示， 第一沟槽 50位于第二沟槽 60的外侧， 第一沟槽 50可 以与第二沟槽 60深度相同也可以比第二沟槽 60深（图 6 (b) 中示出了第一沟 槽 50比第二沟槽 60深的情况）； 第一沟槽 50也从 p型氮化镓层 40向下延伸至 n 型氮化镓层 20; 第一沟槽 50可以与第二沟槽 60相邻形成， 也可以与第二沟槽
60相隔一定的距离形成， 无论第一沟槽 50与第二沟槽 60是否相邻， 对所形成 的负电极 82的功能都没有影响； 本实施例中， 第一沟槽 50也呈圈状。
[56]步骤 S304、 在上一步骤得到的发光元件上依次形成反射层 70和电极层
80。
[57]具体地， 结合图 6 (c) 所示， 该反射层 70和电极层 80形成于 p型氮化镓 层 40的正面、 保护层 61的正面以及第一沟槽 50的底面和周面。
[58]步骤 S305、 去除部分反射层 70和电极层 80， 以将电极层 80分离成正电极 81和负电极 82。 [59]具体地， 结合图 6 (d)所示， 将保护层 61正面对应的反射层 70和电极层 80蚀刻或剥离掉。
[60]步骤 S306、沿第一沟槽 50所在的圈将上一步骤得到的发光元件切开， 以 形成位于 p型氮化镓层 40的正面的正电极 81和位于 p型氮化镓层 40的正面和 侧面、 发光层 30的侧面和 n型氮化镓层 20的侧面的负电极 82， 其结构可如图 6 (e) 所示。
[61] 图 7 (a) 示出了另一 PCB 91的结构示意图， 图 7 (b) 示出了图 6 (e) 的 发光元件与 PCB 91封装后的结构示意图。
[62]本发明实施例提供的发光元件及其制作方法，通过把负电极形成于发光 元件的侧面上， 有效减少了传统发光元件的遮光面积， 并且提高了电流散布 效率； 同时由于形成于侧面的负电极所需蚀刻掉的发光层较少， 从而增加了 发光区域， 改善了发光元件的发光品质； 另一方面由于发光层散发的热量离 PCB板较近， 因此导热效果可以更好； 进一步地由于采用本发明提供的方法 制作的发光元件可以采用覆晶技术通过粘接或焊接的方式连接到 PCB板上， 因此降低了导线连接成本。
[63] 以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局限 于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易 想到变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保护 范围应所述以权利要求的保护范围为准。

Claims

权 利 要 求 书
1、 一种发光元件， 其特征在于， 包括：
基板；
第一导电型半导体层， 位于所述基板上；
发光层， 位于所述第一导电型半导体层的正面；
第二导电型半导体层， 位于所述发光层的正面；
正电极， 位于所述第二导电型半导体层的正面； 以及
负电极， 至少部分位于所述第一导电型半导体层的侧面。
2、 根据权利要求 1所述的发光元件， 其特征在于， 所述负电极至少还部 分位于所述第一导电型半导体层的正面。
3、 根据权利要求 1所述的发光元件， 其特征在于， 所述负电极至少还部 分位于所述发光层的侧面、所述第二导电型半导体层的侧面以及所述第二导 电型半导体层的正面。
4、 根据权利要求 1或 2所述的发光元件， 其特征在于， 所述第一导电型 半导体层的形成有所述负电极的侧面为倾斜面。
5、 根据权利要求 1-3中任一项所述的发光元件， 其特征在于， 所述负电 极至少部分位于所述第一导电型半导体层的一个侧面、 两个侧面、 三个侧面 或者四个侧面上。
6、 根据权利要求 4所述的发光元件， 其特征在于， 所述负电极至少部分 位于所述第一导电型半导体层的一个侧面、 两个侧面、 三个侧面或者四个侧 面上。
7、 根据权利要求 1所述的发光元件， 其特征在于， 还包括保护层， 所述 保护层位于所述正电极与所述负电极之间， 并从所述第二导电型半导体层延 伸至所述第一导电型半导体层。
8、 一种发光元件制作方法， 其特征在于， 包括：
在基板上形成第一导电型半导体层；
在所述第一导电型半导体层的正面形成发光层；
在所述发光层的正面形成第二导电型半导体层； 形成第一沟槽，所述第一沟槽从所述第二导电型半导体层延伸至所述第 一导电型半导体层；
在所述第二导电型半导体层的正面以及所述第一沟槽的底面和周面上 形成反射层；
在所述反射层上形成电极层； 以及
分离步骤： 去除掉部分所述反射层和所述电极层， 使得所述电极层分离 成位于所述第二导电型半导体层的正面的正电极和至少部分位于所述第一 导电型半导体层的侧面的负电极。
9、 根据权利要求 8所述的发光元件制作方法， 其特征在于， 所述第一沟 槽位于所述发光元件的一个侧面、 两个侧面、 三个侧面或四个侧面上。
10、 根据权利要求 8所述的发光元件制作方法， 其特征在于， 所述分离 步骤包括：
去除掉部分所述反射层和所述电极层， 使得所述电极层分离成位于所述 第二导电型半导体层的正面的正电极和至少部分位于所述第一导电型半导 体层的侧面和正面的负电极。
11、 根据权利要求 8所述的发光元件制作方法， 其特征在于， 所述分离 步骤包括：
去除掉部分所述反射层和所述电极层， 使得所述电极层分离成位于所述 第二导电型半导体层的正面的正电极和至少部分位于所述第一导电型半导 体层的侧面、 所述发光层的侧面、 所述第二导电型半导体层的侧面和正面的 负电极。
12、 根据权利要求 8所述的发光元件制作方法， 其特征在于， 还包括： 形成从所述第二导电型半导体层延伸至所述第一导电型半导体层的第 二沟槽， 并在所述第二沟槽中形成保护层。
PCT/CN2013/078623 2012-07-02 2013-07-02 发光元件及其制作方法 WO2014005502A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201210227813.5 2012-07-02
CN201210227813 2012-07-02

Publications (1)

Publication Number Publication Date
WO2014005502A1 true WO2014005502A1 (zh) 2014-01-09

Family

ID=48691058

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/078623 WO2014005502A1 (zh) 2012-07-02 2013-07-02 发光元件及其制作方法

Country Status (4)

Country Link
US (1) US20140001510A1 (zh)
CN (2) CN103531686A (zh)
TW (1) TWM484188U (zh)
WO (1) WO2014005502A1 (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103531686A (zh) * 2012-07-02 2014-01-22 东莞市正光光电科技有限公司 发光元件及其制作方法
CN103346218B (zh) * 2013-07-09 2016-03-23 佛山市国星半导体技术有限公司 一种led芯片及其制作方法
CN103996773B (zh) * 2014-06-06 2016-09-28 厦门市三安光电科技有限公司 一种倒装发光二极管结构及其制作方法
CN105336827A (zh) * 2015-10-20 2016-02-17 聚灿光电科技股份有限公司 Led芯片及其制备方法
US10899063B2 (en) * 2016-10-24 2021-01-26 Lifetime Products, Inc. Blow molded part including compression molded element
US11205677B2 (en) * 2017-01-24 2021-12-21 Goertek, Inc. Micro-LED device, display apparatus and method for manufacturing a micro-LED device
JP6747353B2 (ja) * 2017-03-29 2020-08-26 豊田合成株式会社 半導体発光素子とその製造方法
US10431465B2 (en) * 2017-09-18 2019-10-01 Vanguard International Semiconductor Corporation Semiconductor structures and methods of forming the same
CN108155273A (zh) * 2018-01-31 2018-06-12 江苏新广联科技股份有限公司 增加led倒装芯片发光面积的结构和制作方法
TWI661584B (zh) * 2018-05-18 2019-06-01 光磊科技股份有限公司 發光晶粒、封裝結構及其相關製造方法
CN110165034B (zh) * 2019-03-11 2024-05-14 佛山市国星半导体技术有限公司 一种高亮度led芯片及其制备方法和封装方法
JPWO2021054081A1 (zh) * 2019-09-18 2021-03-25

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11150300A (ja) * 1997-11-14 1999-06-02 Nichia Chem Ind Ltd 窒化物半導体素子
CN101667713A (zh) * 2009-09-23 2010-03-10 中国电子科技集团公司第十三研究所 半导体激光器用新型氮化铝陶瓷载体倾斜端面制作方法
JP2010258064A (ja) * 2009-04-22 2010-11-11 Nichia Corp 半導体素子及びその製造方法
CN203038965U (zh) * 2012-07-02 2013-07-03 刘艳 发光元件

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102054913B (zh) * 2010-11-09 2013-07-10 映瑞光电科技(上海)有限公司 发光二极管及其制造方法、发光装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11150300A (ja) * 1997-11-14 1999-06-02 Nichia Chem Ind Ltd 窒化物半導体素子
JP2010258064A (ja) * 2009-04-22 2010-11-11 Nichia Corp 半導体素子及びその製造方法
CN101667713A (zh) * 2009-09-23 2010-03-10 中国电子科技集团公司第十三研究所 半导体激光器用新型氮化铝陶瓷载体倾斜端面制作方法
CN203038965U (zh) * 2012-07-02 2013-07-03 刘艳 发光元件

Also Published As

Publication number Publication date
TWM484188U (zh) 2014-08-11
US20140001510A1 (en) 2014-01-02
CN103531686A (zh) 2014-01-22
CN203038965U (zh) 2013-07-03

Similar Documents

Publication Publication Date Title
WO2014005502A1 (zh) 发光元件及其制作方法
US10886438B2 (en) Manufacturing method of light-emitting device
US9425359B2 (en) Light emitting diode
TWI532212B (zh) 半導體發光裝置及其製造方法
WO2013137571A1 (ko) 발광 다이오드 및 그것을 제조하는 방법
US11417802B2 (en) Method of making a light emitting device and light emitting device made thereof
TW201308666A (zh) 發光二極體陣列及其製造方法
WO2017167189A1 (zh) 半导体发光器件及其制造方法
US20100237379A1 (en) Light emitting device
CN102646769A (zh) 发光二极管组件、发光二极管封装结构及其制造方法
JP5632034B2 (ja) 発光ダイオードチップ及びその製造方法
US9698305B2 (en) High voltage LED flip chip
JP5515685B2 (ja) 発光素子及びそれを用いた発光装置の製造方法
KR101910556B1 (ko) 질화갈륨 기판을 갖는 발광 다이오드
JP2010040937A (ja) 半導体発光素子、発光装置、照明装置及び表示装置
CN102956783B (zh) 半导体芯片、半导体发光器件及其制作方法
TWI488337B (zh) 發光元件及其製作方法
TWI470834B (zh) 半導體發光結構及其製造方法
TWI548118B (zh) 發光元件及其製作方法
TWI447942B (zh) 軸對稱發光二極體之製造方法
US11482653B2 (en) Light emitting diode apparatus
CN118099331A (zh) 一种超薄led芯片的制备方法及超薄led芯片
JP2005286134A (ja) フリップチップ型半導体発光素子
TW201434175A (zh) 發光元件及其製作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13812938

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13812938

Country of ref document: EP

Kind code of ref document: A1