WO2013189873A9 - Verfahren zum herstellen von halbleiterdünnschichten auf fremdsubstraten - Google Patents
Verfahren zum herstellen von halbleiterdünnschichten auf fremdsubstraten Download PDFInfo
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- WO2013189873A9 WO2013189873A9 PCT/EP2013/062481 EP2013062481W WO2013189873A9 WO 2013189873 A9 WO2013189873 A9 WO 2013189873A9 EP 2013062481 W EP2013062481 W EP 2013062481W WO 2013189873 A9 WO2013189873 A9 WO 2013189873A9
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- Prior art keywords
- thin film
- foreign substrate
- temperature
- semiconductor
- semiconductor thin
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- 239000010409 thin film Substances 0.000 title claims abstract description 132
- 239000004065 semiconductor Substances 0.000 title claims abstract description 92
- 239000000758 substrate Substances 0.000 title claims abstract description 82
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 claims abstract description 33
- 238000010438 heat treatment Methods 0.000 claims abstract description 31
- 239000000463 material Substances 0.000 claims abstract description 27
- 238000002844 melting Methods 0.000 claims abstract description 24
- 230000008018 melting Effects 0.000 claims abstract description 24
- 239000010408 film Substances 0.000 claims abstract description 21
- 238000001816 cooling Methods 0.000 claims abstract description 13
- 238000000137 annealing Methods 0.000 claims abstract description 10
- 230000007423 decrease Effects 0.000 claims abstract description 8
- 239000000155 melt Substances 0.000 claims abstract description 4
- 239000007789 gas Substances 0.000 claims description 21
- 238000000151 deposition Methods 0.000 claims description 19
- 230000008021 deposition Effects 0.000 claims description 19
- 238000006243 chemical reaction Methods 0.000 claims description 13
- 238000007711 solidification Methods 0.000 claims description 3
- 230000008023 solidification Effects 0.000 claims description 3
- 239000013078 crystal Substances 0.000 abstract description 32
- 238000002425 crystallisation Methods 0.000 abstract description 14
- 230000008025 crystallization Effects 0.000 abstract description 14
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 230000003247 decreasing effect Effects 0.000 abstract 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 25
- 229910010271 silicon carbide Inorganic materials 0.000 description 24
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 17
- 229910002804 graphite Inorganic materials 0.000 description 16
- 239000010439 graphite Substances 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 229910052710 silicon Inorganic materials 0.000 description 15
- 239000010703 silicon Substances 0.000 description 15
- 239000000919 ceramic Substances 0.000 description 13
- 238000005229 chemical vapour deposition Methods 0.000 description 12
- 239000011888 foil Substances 0.000 description 12
- 238000002156 mixing Methods 0.000 description 5
- ATUOYWHBWRKTHZ-UHFFFAOYSA-N Propane Chemical compound CCC ATUOYWHBWRKTHZ-UHFFFAOYSA-N 0.000 description 4
- 125000004429 atom Chemical group 0.000 description 4
- 239000012159 carrier gas Substances 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 238000001953 recrystallisation Methods 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000001534 heteroepitaxy Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000035515 penetration Effects 0.000 description 3
- 238000005204 segregation Methods 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- 238000004857 zone melting Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- LVQULNGDVIKLPK-UHFFFAOYSA-N aluminium antimonide Chemical compound [Sb]#[Al] LVQULNGDVIKLPK-UHFFFAOYSA-N 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000001294 propane Substances 0.000 description 2
- IHGSAQHSAGRWNI-UHFFFAOYSA-N 1-(4-bromophenyl)-2,2,2-trifluoroethanone Chemical compound FC(F)(F)C(=O)C1=CC=C(Br)C=C1 IHGSAQHSAGRWNI-UHFFFAOYSA-N 0.000 description 1
- 229910000851 Alloy steel Inorganic materials 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229920000049 Carbon (fiber) Polymers 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- KTSFMFGEAAANTF-UHFFFAOYSA-N [Cu].[Se].[Se].[In] Chemical compound [Cu].[Se].[Se].[In] KTSFMFGEAAANTF-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 239000004917 carbon fiber Substances 0.000 description 1
- 239000012876 carrier material Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- -1 for example Chemical compound 0.000 description 1
- 238000001657 homoepitaxy Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Classifications
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/36—Carbides
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
- C30B33/02—Heat treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02376—Carbon, e.g. diamond-like carbon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02529—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02598—Microstructure monocrystalline
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Definitions
- the main objective in the production of semiconductor thin films on foreign substrates is to produce a thin film with the largest possible semiconductor single crystals.
- the size, i. the diameter and the thickness of the semiconductor single crystal significantly determines the quality of the thin film, especially in thin-film solar cells, where the single crystal size has a direct influence on the efficiency of the solar cell.
- Previous methods usually consist of applying a PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition) or PECVD (Physically Enhanced CVD) method polycrystalline semiconductor material to the foreign substrate and then by a zone melting process or by annealing (annealing) of the Thin film at elevated temperature, the average single crystal size of the thin film to improve.
- PVD Physical Vapor Deposition
- CVD Chemical Vapor Deposition
- PECVD Physical Enhanced CVD
- the invention proposes a method by which the average single crystal size, in particular the diameter of the single crystals, in the thin film can be increased by an order of magnitude in an economical manner.
- the foreign substrate is heated so strongly that the semiconductor thin film melts at a temperature which is above the melting temperature of the semiconductor thin film, whereupon the Temperature is slowly lowered to below the melting temperature of the semiconductor thin film and until the solidification of the semiconductor thin film, and then further reduced to normal temperature;
- the foreign substrate is heated so that the temperature, starting from the contact surface of the foreign substrate with the thin film in the vertical direction across the semiconductor thin film continuously decreases to the surface of the thin film.
- Measure c is crucial for the formation of the largest possible single crystals.
- the atomic layers directly on the exposed surface of the thin film can orient themselves undisturbed during crystallization, whereby the formation of large-area and some atomic layers of thick single crystals is promoted. These then serve as growth nuclei for the next lower-lying atomic layers such that these large-area single crystals grow in thickness in the direction of the contact surface with the foreign substrate. Only the atomic layers in the immediate vicinity of the contact surface with the foreign substrate are disturbed during crystallization and degenerate to an amorphous or polycrystalline boundary layer. A slow lowering of the temperature to below the melting temperature of the semiconductor material is achieved and ensured by a corresponding reduction of the heating power.
- Fig. 1 shows the temperature profile described in measure c) of the invention over the coordinate x across the semiconductor thin film 20 at a time tl, where the entire semiconductor thin film has melted, and at a later time t2 during the slow lowering of the temperature T to slightly below the melting temperature Tc, where the surface of the thin film begins to solidify. Shown is also the growth direction 12 of the single crystals, from the surface in the direction of the foreign substrate 30.
- the crystallization front 10 divides the semiconductor thin film 20 when lowering the temperature in two areas: in a solidified monocrystalline region 25 and in the remaining still liquid portion of the semiconductor thin film.
- Measure c) of the invention absolutely requires that the temperature of the foreign substrate during cooling is always higher than the temperature of the thin layer. There are basically two ways to achieve this:
- the foreign substrate consists of a thin plate or film and is coated on one side with a thin film, this can only be achieved by a planar heating source mounted directly on the uncoated surface of the foreign substrate, or by the foreign substrate by direct electric current passage is heated.
- the foreign substrate consists of a thin plate or foil and is coated on both sides or the foreign substrate consists of a solid or hollow body with only one outer surface, e.g. a ball, this can be achieved by applying the heat from outside to the foreign substrate and the thin film through a heat source. Once the desired temperature is reached, you can reduce the heating power. Upon cooling, a temperature profile then sets across the thin film, which satisfies measure c) of the invention.
- Measure c) of the invention can not be fulfilled if the heating or heat source imprints or transfers the heat from the outside to the thin film, eg in high-frequency heating, induction heating, resistance heating and zone melting, as well as in cylindrical CVD reactors by heating the reactor wall (Hot Wall reactor). In these types of heating, when heated, the most gaseous environment is at a higher temperature than the semiconductor thin film and the foreign substrate.
- the temperature gradient is reversed, ie the temperature decreases continuously from the interior of the thin layer in the direction of the exposed surface of the thin layer and in the direction of the foreign substrate.
- the result is that when lowering the temperature to below the melting temperature of the semiconductor thin film first the atomic layers on the exposed surface of the thin film and at the same time in proximity to the foreign substrate crystallize or solidify. That is, the growth direction of the crystals simultaneously proceeds from the exposed surface of the thin film and from the contact surface of the foreign substrate with the thin film toward the inside of the thin film.
- two crystallization fronts set up in the direction of the interior of the thin film, which meet on cooling and divide the thin film into two regions of different crystal structure.
- the crystals which first form in the immediate vicinity of the foreign substrate are disturbed in growth by the foreign substrate and form small-sized single crystals which grow in thickness toward the inside of the thin film but not in the surface.
- the result is a polycrystalline crystal structure in this region of the thin film.
- the crystals which first form on the exposed surface of the thin film and grow toward the inside of the thin film form a portion of the thin film where the crystals are free to wash in area and thickness.
- the result is a rather monocrystalline structure of the thin film in this area.
- the polycrystalline crystal structure area of the thin film is much thicker than the monocrystalline structure area.
- the polycrystalline structure region extends throughout the thickness of the thin film since the foreign substrate dissipates the heat much faster than the exposed surface of the thin film and thus accelerates the rate of crystallization from the foreign substrate toward the interior of the thin film.
- FIG. 2 shows the temperature profile over the coordinate x, which is typical for the abovementioned previous methods, across the semiconductor thin layer 20, the two crystallization directions 12 and 13, the two crystallization fronts 10 and 11, and the two regions 25 and 27 with different crystal structure, at one time tl where the entire semiconductor thin film has melted, and at a later time t2 during the slow descent the temperature T to slightly below the melting temperature Tc, where the thin film begins to solidify at the boundary to the foreign substrate and at the same time at the exposed surface of the thin film.
- the graphite block is well electrically and thermally conductive, zone melting locally from one edge to another can not be done by transferring the heat from the graphite block to the thin film, but only when the heat is targeted locally from above the exposed surface of the thin film to the thin film Thin film acts.
- the graphite block serves more as an electrode for the high frequency heating. However, this causes, as explained above, that the surface of the semiconductor thin layer is always at a higher temperature during cooling than the surface of the support material, thus contrary to the measure c) of the invention.
- the German patent DE 41 40 555 A1 includes an arrangement of two heat sources 6 and 7 for heating a semiconductor thin film on a substrate, wherein the heating source 6 below and the heating source 7 above the substrate resp. the semiconductor thin film is attached. It can be clearly deduced from the description of the arrangement in this document that the temperature profile according to step c) of the present invention can not be achieved by the described procedure in this document. For this purpose, the following passage is used in the description of document (1) ⁇ cf. (1) Sp.7 / Z.2 -34 ⁇ :
- the pad 2 is heated to the melting point or above by a first heater 6 ....
- the semiconductor layer 1 is heated by a second heater 7 ... to be melted and recrystallized, and the melted area is moved to successively follow the movement of the second heater to melt and recrystallize the entire semiconductor layer.
- Heating device 6 is not used to melt the semiconductor layer 1 and recrystallize, but only heating device 7 serves this purpose
- Heating device 6 serves only to keep during the melting and recrystallization of the semiconductor layer 1, the pad 2 in the molten state, to a temperature which is below the melting temperature of the semiconductor layer 1, so that no tensions and bumps during recrystallization in the Semiconductor layer 1 arise and the uniformity of the temperature in the semiconductor layer during recrystallization is improved (see. (l) Sp.5 / Z.46-54 ⁇
- the heating device 7 according to FIG. 1 (b) imprints the heat from above onto the semiconductor layer 1, it follows from points 1 and 2 above by means of elementary heat conduction laws that a temperature profile of the plate occurs when the semiconductor layer 1 melts 11 from in the direction of the base 2 qualitatively adjusts, as shown in Fig. 2 of the present invention at time tl. If the heating power of the heating device 7 is reduced in order to allow a recrystallization, then a temperature curve sets in, as shown in FIG. 2 of the present invention at the time t2. A detailed description of this temperature profile can be found in the description of the patent application ⁇ cf. S.3 / Z.24 - S4./Z.20, S.4 / Z.28 - S.5 / Z.3 ⁇ . However, this temperature profile is opposite to the temperature profile of step c) of the present invention.
- German Auslegeschrift 1521465 and Offenlegungsschrift 2536174 describe carrier plates and foreign substrates which are heated by direct current passage or by a mounted on the underside of the carrier plate heat source.
- measure c) of the invention it is not explicitly mentioned in these documents because the positive influence on the crystallization was not known. This also explains the fact that it is expressly mentioned in these documents that either the deposition of the thin layer from the gas phase or the annealing of the thin layer takes place in each case below the melting temperature of the thin layer. It follows that measures b) and c) of the invention can not be fulfilled simultaneously.
- Measure b) is, however, a prerequisite for the fact that the positive influence of measure c) on the crystallization at all comes into play.
- the melting temperature of the foreign substrate should be higher than that of the semiconductor thin film to prevent penetration and mixing of the semiconductor material with the foreign substrate but this does not necessarily have to be necessary. Therefore, iron, titanium, chromium, molybdenum or alloys of these substances are particularly suitable for economic reasons as metal for the foreign substrate.
- the surface of the foreign substrate can be planar or curved.
- the invention is not limited to thin films of a particular semiconductor material.
- ternary semiconductors such as e.g. Copper indium diselenide.
- binary and ternary semiconductor materials may undergo segregation during the fusing process, which may limit the applicability of the process to these semiconductors.
- a further advantageous measure in the context of the invention is the application of a plurality of superimposed semiconductor thin layers, wherein each semiconductor thin layer may consist of different semiconductor material or different doping. This can be advantageous in particular for the production of semiconductor thin films of different doping or for the production of tandem solar cells.
- measures a) to c) of the invention There are basically two ways to apply the measures a) to c) of the invention.
- the first possibility is to apply the measures a) to c) of the invention separately for each semiconductor thin film. That is, one applies a first semiconductor thin film, for example by means of deposition from the gas phase, to the foreign substrate and performs the measures b) and c). Then, a second semiconductor thin film is applied to the first thin film prepared according to the measures a) to c), and the measures b) and c) are repeated for the second thin film. These steps are repeated for each additional applied semiconductor thin film.
- tandem solar cells it is common for the production of tandem solar cells to produce the lowermost thin films of silicon, and to produce higher-lying thin films of a semiconductor material having a higher band gap, for example, aluminum antimonide (melting temperature 1050 ° C., band gap 1.6 eV) or gallium arsenide (Melting temperature 1238 ° C, band gap 1.4 eV).
- the second possibility is to apply the measures a) to c) of the invention for all applied semiconductor thin films together. This means that one after the other several thin layers, for example by means of deposition from the gas phase, on the foreign substrate on. Then, the temperature of the foreign substrate is set so high that all applied thin films are melted together.
- the temperature of the foreign substrate is slowly lowered so that first the uppermost thin film is solidified, then the underlying thin film, then the next lower-lying thin film, etc., to the lowermost thin film.
- This possibility can be particularly favorable if the thin layers consist of the same semiconductor material but are provided with different doping, or if higher layers consist of semiconductor material whose melting temperature Tel is below the melting temperature Tc2 of the semiconductor material of deeper layers, ie if Tel ⁇ Tc2 ,
- the doping of the semiconductor thin films is usually carried out by means of deposition from the gas phase of a reaction gas containing the dopant.
- a reaction gas containing the dopant e.g. Phosphine or ammonia
- p-doping e.g. Diborane.
- gases are mixed in the appropriate concentration of the carrier gases and the reaction gases containing the semiconductor materials.
- graphite foils Prior to coating with semiconductor material, argon gas or hydrogen gas may be heated at elevated temperature, e.g. 900 ° C, to flow over the graphite foil to improve the surface quality of the graphite foil. It may also be advantageous to provide the graphite foil with a highly doped intermediate layer of silicon carbide (SiC). On the one hand, this intermediate layer ensures the electrical contact between silicon thin film and graphite foil, and on the other hand prevents the penetration or diffusion of later-applied semiconductor material into the graphite foil. For producing this Zwichen für of SiC, various methods are known, e.g. the method described in German Offenlegungsschrift 2536174. Analogously, amorphous boundary layers, which form on cooling at the interface with the master substrate or between different thin layers, can be highly doped in order to ensure electrical contact between the layers.
- a high quality SiC thin film may also be formed by a CVD method followed by annealing the deposited layer at high temperature, e.g. above 1350 ° C, produce.
- high temperature e.g. above 1350 ° C
- the homogeneity of the deposited layer must differ as little as possible from the stoichiometric mixing ratio 1: 1 everywhere
- SiC single crystals of a SiC thin film can be formed by post-diffusing Si atoms to the surface through an already formed SiC film.
- the Si atoms can be replaced by a max. Diffuse 10-20 nm thick SiC layer through.
- This property also makes it possible to heal crystal defects by annealing at high temperatures.
- Measure h) is intended to prevent Si atoms from having to travel more than 10-20 nm during diffusion in order to compensate for slight local fluctuations in homogeneity and to heal crystal defects.
- Measure h) can be achieved by suitably adjusting the mixing ratio of the reaction gases used in a CVD method for silicon and carbon, for example, silane and propane.
- a SiC thin film on a Si thin film can be produced tandem solar cells made of silicon and silicon carbide.
- a SiC thin film By the above-described diffusion barrier of silicon through a SiC thin film prevents mixing of silicon thin film and SiC thin film, even above the melting temperature of silicon.
- the forming amorphous intermediate layer at the interface of Si thin film and SiC thin film serves to compensate for the material stresses that arise due to the different thermal expansion coefficients of both layers during cooling.
- This intermediate layer can also be highly doped to ensure electrical contact between the SiC thin film and the Si thin film.
- this amorphous SiC thin film is very well permeable to the longer wavelength light absorbed in the Si thin film.
- the temperature of the semiconductor thin layer it may be necessary, depending on the semiconductor material, for the temperature of the semiconductor thin layer to be lowered as quickly as possible to normal temperature or actively cooled in order to prevent segregation or segregation of certain elements of the semiconductor material.
- FIG. 3 and Fig. 4 show a further advantageous in the context of the invention measure.
- a serving as a foreign substrate and electrically conductive film 14 extends by means of a suitable support structure on several levels parallel to each other.
- Fig. 3 shows the side view of the support frame
- Fig. 4 shows the cross section.
- the support framework should advantageously be as light as possible and dimensionally stable over the entire temperature range, for example between 0 and 2000 ° C, to allow rapid and homogeneous heating and cooling.
- the support frame consists of U-rails 17, which are made of carbon fiber.
- the U-rails 17 are electrically insulated from the next higher and lower U-rails and the conductive foil 14 by means of thin plates 15 made of ceramic and thin slats 16 made of ceramic.
- the strips 15 and U-rails 17 may advantageously also have cross braces in order to additionally support the film 14. It is also possible to subdivide the film 14 into several segments, eg a separate film for each level, and to connect each segment separately to an electrical heating source. Since, when lowering the temperature by measure c) of the invention, the heat always flows from the interior of the support frame to its outer sides, the temperature decreases accordingly from the interior of the support frame to the outside. This has the consequence that when lowering the temperature, the edges of the support frame and thus the graphite foil may have a slightly lower temperature than inside and thus the solidification resp.
- FIGS. 5 and 6 show the side view of the support frame with such reduced to the support points 50 U-rails and ceramic strips.
- the electrically conductive film merely as a heating source, and to take another film as a foreign substrate for the coating. If the serving as a foreign substrate film is also electrically conductive, the films must be electrically isolated from each other by means of another thin ceramic layer. Further measures may be required if penetration of the reaction gases between the films and the insulating layers is to be avoided.
- Fig. 7 shows the cross section of a cylindrical CVD reactor which is designed for high temperatures and for receiving a carrier framework as described above.
- the reactor consists of a cylinder jacket 30 of a steel alloy, a thermally insulating ceramic shell 31, an additionally thermally insulating layer of ceramic fleece 32, and a housing 33 made of thin-walled ceramic plates, which serves for shaping the ceramic fleece 32.
- the cavity 34 with a rectangular cross-section serves to receive a support frame as described above, wherein the cross-sectional area of the cavity 34 and the cross-sectional area of the support frame should advantageously be matched as closely as possible.
- Fig. 8 shows the same cylindrical CVD reactor with the carrier framework shown in Fig. 4, which is inserted into the cavity 34 of the CVD reactor.
- reaction and carrier gases are admitted in a certain amount and until reaching a certain pressure in the reactor;
- the deposition is carried out from the gas phase, wherein during the deposition, the inlets and outlets of the reactor are closed;
- the residual gases are discharged from the reactor or discharged.
- the pressure in the CVD reactor by decomposition of the reaction gases in other gases may continue to increase, for example, silane in hydrogen according to SiH 4 -> Si + 2 H. 2 twice.
- the cylinder jacket 30 of the CVD reactor must be dimensioned accordingly.
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Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
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ES201490138A ES2536929B1 (es) | 2012-06-18 | 2013-06-17 | Procedimiento para la producción de películas delgadas semiconductoras sobre sustratos externos |
CN201380031962.7A CN104412361B (zh) | 2012-06-18 | 2013-06-17 | 用于在异体基质上制造半导体薄层的方法 |
JP2015516645A JP2015522949A (ja) | 2012-06-18 | 2013-06-17 | 異種基板上に半導体薄膜を生成するための方法 |
US14/406,566 US9293327B2 (en) | 2012-06-18 | 2013-06-17 | Method for producing semiconductor thin films on foreign substrates |
DE112013003052.7T DE112013003052A5 (de) | 2012-06-18 | 2013-06-17 | Verfahren zum Herstellen von Halbleiterdünnschichten auf Fremdsubstraten |
Applications Claiming Priority (2)
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DE102012012088A DE102012012088A1 (de) | 2012-06-18 | 2012-06-18 | Verfahren zum Herstellen von Halbleiterdünnschichten auf Fremdsubstraten |
DE102012012088.5 | 2012-06-18 |
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WO2013189873A1 WO2013189873A1 (de) | 2013-12-27 |
WO2013189873A9 true WO2013189873A9 (de) | 2014-02-27 |
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PCT/EP2013/062481 WO2013189873A1 (de) | 2012-06-18 | 2013-06-17 | Verfahren zum herstellen von halbleiterdünnschichten auf fremdsubstraten |
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US (1) | US9293327B2 (de) |
JP (1) | JP2015522949A (de) |
CN (1) | CN104412361B (de) |
DE (2) | DE102012012088A1 (de) |
ES (1) | ES2536929B1 (de) |
WO (1) | WO2013189873A1 (de) |
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CN105609406B (zh) * | 2014-11-19 | 2018-09-28 | 株式会社日立国际电气 | 半导体器件的制造方法、衬底处理装置、气体供给系统 |
JP2020520129A (ja) | 2017-05-10 | 2020-07-02 | マクマホン, シェーン トマスMCMAHON, Shane Thomas | 薄膜結晶化プロセス |
Family Cites Families (15)
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US3335038A (en) | 1964-03-30 | 1967-08-08 | Ibm | Methods of producing single crystals on polycrystalline substrates and devices using same |
BE666629A (de) | 1964-08-04 | |||
DE2536174C3 (de) | 1975-08-13 | 1983-11-03 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum Herstellen von polykristallinen Siliciumschichten für Halbleiterbauelemente |
CN85103942B (zh) * | 1985-05-16 | 1988-03-16 | 中国科学院上海冶金所 | 绝缘层上多晶硅的激光加热再结晶方法 |
JPH04253323A (ja) * | 1991-01-29 | 1992-09-09 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
DE4135076A1 (de) * | 1991-10-24 | 1993-04-29 | Daimler Benz Ag | Mehrschichtige, monokristallines siliziumkarbid enthaltende zusammensetzung |
US5492752A (en) * | 1992-12-07 | 1996-02-20 | Oregon Graduate Institute Of Science And Technology | Substrates for the growth of 3C-silicon carbide |
US5387067A (en) * | 1993-01-14 | 1995-02-07 | Applied Materials, Inc. | Direct load/unload semiconductor wafer cassette apparatus and transfer system |
US5715361A (en) * | 1995-04-13 | 1998-02-03 | Cvc Products, Inc. | Rapid thermal processing high-performance multizone illuminator for wafer backside heating |
JP3657036B2 (ja) * | 1995-08-11 | 2005-06-08 | Hoya株式会社 | 炭化ケイ素薄膜および炭化ケイ素薄膜積層基板の製造方法 |
JPH1126470A (ja) * | 1997-07-08 | 1999-01-29 | Sony Corp | 半導体基板、半導体装置および太陽電池、半導体基板の製造方法および薄膜半導体の製造方法、半導体基板に対する処理装置 |
AU2003258289A1 (en) * | 2002-08-19 | 2004-03-03 | The Trustees Of Columbia University In The City Of New York | A single-shot semiconductor processing system and method having various irradiation patterns |
US20040224469A1 (en) * | 2003-05-08 | 2004-11-11 | The Board Of Trustees Of The University Of Illinois | Method for forming a strained semiconductor substrate |
US7569462B2 (en) * | 2006-12-13 | 2009-08-04 | Applied Materials, Inc. | Directional crystallization of silicon sheets using rapid thermal processing |
EP2190033A1 (de) * | 2008-11-24 | 2010-05-26 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Tandemsolarzelle aus kristallinem Silizium und kristallinem Siliziumcarbid sowie Verfahren zu dessen Herstellung |
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- 2012-06-18 DE DE102012012088A patent/DE102012012088A1/de not_active Withdrawn
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- 2013-06-17 DE DE112013003052.7T patent/DE112013003052A5/de not_active Ceased
- 2013-06-17 ES ES201490138A patent/ES2536929B1/es active Active
- 2013-06-17 US US14/406,566 patent/US9293327B2/en active Active
- 2013-06-17 JP JP2015516645A patent/JP2015522949A/ja active Pending
- 2013-06-17 WO PCT/EP2013/062481 patent/WO2013189873A1/de active Application Filing
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DE112013003052A5 (de) | 2015-03-05 |
WO2013189873A1 (de) | 2013-12-27 |
DE102012012088A1 (de) | 2013-12-19 |
US9293327B2 (en) | 2016-03-22 |
ES2536929B1 (es) | 2016-06-06 |
US20150140795A1 (en) | 2015-05-21 |
CN104412361A (zh) | 2015-03-11 |
ES2536929A2 (es) | 2015-05-29 |
ES2536929R1 (es) | 2015-12-21 |
CN104412361B (zh) | 2017-05-17 |
JP2015522949A (ja) | 2015-08-06 |
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