WO2013163870A1 - 阵列基板、液晶面板和显示装置 - Google Patents

阵列基板、液晶面板和显示装置 Download PDF

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Publication number
WO2013163870A1
WO2013163870A1 PCT/CN2012/084458 CN2012084458W WO2013163870A1 WO 2013163870 A1 WO2013163870 A1 WO 2013163870A1 CN 2012084458 W CN2012084458 W CN 2012084458W WO 2013163870 A1 WO2013163870 A1 WO 2013163870A1
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Prior art keywords
liquid crystal
pixel
array substrate
crystal panel
film transistors
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PCT/CN2012/084458
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English (en)
French (fr)
Inventor
谢畅
柳在健
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/128,035 priority Critical patent/US9733535B2/en
Priority to EP12875825.7A priority patent/EP2846184B1/en
Publication of WO2013163870A1 publication Critical patent/WO2013163870A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]

Definitions

  • Embodiments of the present invention relate to an array substrate, a liquid crystal panel, and a display device. Background technique
  • Liquid crystal displays have the advantages of light weight, low radiation, and portability, and are therefore widely used as displays for terminals such as televisions and computers.
  • the liquid crystal display includes various modes such as an In-Plane Switching (IPS) liquid crystal panel and a Fringe-Field Switching (FFS) liquid crystal panel.
  • the liquid crystal panel includes an array substrate, a color filter substrate, and a liquid crystal layer packaged between the array substrate and the color filter substrate.
  • 1 is a schematic structural view of an array substrate in a prior art IPS liquid crystal panel.
  • the array substrate in the prior art IPS liquid crystal panel includes a substrate (not shown), a gate line 101, a data line 102, a pixel electrode 103, a common electrode 104, a common electrode line 105, and a thin film transistor.
  • TFT TFT
  • the source and the drain of the TFT are connected to the data line 102 and the pixel electrode 103
  • the gate of the TFT is connected to the gate line (or scan line) 101
  • the common electrode 104 is connected to the common electrode line 105.
  • the TFTs are controlled to be turned on (i.e., turned on) or turned off by a gate driver in the liquid crystal panel.
  • a data signal is applied to the pixel electrode 103 through the source driver, the data signal is an alternating voltage, and a constant voltage Vcom is applied to the common electrode 104.
  • the constant voltage Vcom is a value between the high potential of the positive period of the alternating voltage on the pixel electrode 103 and the low potential of the negative period to form an electric field between the pixel electrode 103 and the common electrode 104, which can control the liquid crystal layer In the direction in which the liquid crystal molecules are arranged, the constant voltage is usually an intermediate value between the high potential of the positive period of the alternating voltage and the low potential of the negative period.
  • Vg in the figure indicates a scan signal output from the gate driver
  • Vp in the figure indicates an actual alternating voltage on the pixel electrode 103
  • the source driver in the liquid crystal panel when the gate driver in the liquid crystal panel turns on the TFT connected to the pixel electrode 103, the source driver in the liquid crystal panel applies an alternating voltage to the pixel electrode 103, that is, charges the pixel electrode 103, Since the TFT of the array substrate also includes some parasitic Capacitor, the source driver also charges these parasitic capacitors at the same time. These parasitic capacitors will generate a coupling capacitor.
  • the gate driver in the liquid crystal panel causes the TFT connected to the pixel electrode 103 to be turned off, the source driver stops charging the pixel electrode 103.
  • the voltage drop generated by the gate driver when the TFT is turned off (usually at 30 40V) will be fed back to the pixel electrode 103 through the coupling capacitor, causing a voltage drop of A Vp on the pixel electrode 103. Since the voltage applied to the common electrode 104 is a constant voltage, and the pixel electrode 103 has a voltage drop of A Vp at both the positive cycle and the negative cycle of the alternating voltage, the voltage value on the pixel electrode 103 is relative to the common electrode 104.
  • the constant voltage is asymmetrical, which affects the grayscale value of the displayed image, resulting in the afterimage of the image.
  • An embodiment of the present invention provides an array substrate, including: a substrate; and a plurality of gate lines and a plurality of data lines formed on the substrate, two adjacent gate lines and two adjacent data lines Intersecting each other to form a pixel region, wherein each of the pixel regions includes two pixel electrodes and two thin film transistors (TFTs), and drains of the two thin film transistors are respectively connected to the two pixel electrodes.
  • TFTs thin film transistors
  • the sources of the two thin film transistors are respectively connected to the two data lines, and the gates of the two thin film transistors are connected to one of the two gate lines.
  • a liquid crystal panel including an array substrate, a liquid crystal panel, and a liquid crystal layer encapsulated between the array substrate and the liquid crystal panel, the array substrate comprising: a plurality of gate lines and a plurality of a data line, two adjacent gate lines and two adjacent data lines intersect each other to form a pixel region; a source driver connected to the data line; and a gate driver connected to the gate line
  • Each of the pixel regions includes two pixel electrodes and two thin film transistors (TFTs), and drains of the two thin film transistors are respectively connected to the two pixel electrodes, and sources of the two thin film transistors
  • TFTs thin film transistors
  • the poles are respectively connected to the two data lines, and the gates of the two thin film transistors are connected to one of the two gate lines.
  • Another embodiment of the present invention provides a display device including the above liquid crystal panel.
  • FIG. 1 is a schematic structural view of an array substrate in a prior art IPS liquid crystal panel
  • FIG. 2 is a voltage signal diagram of a pixel electrode and a common electrode of the prior art
  • FIG. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a liquid crystal panel according to an embodiment of the present invention.
  • Figure 5 is a voltage signal diagram of the two pixel electrodes of Figure 4. detailed description
  • Embodiments of the present invention provide an array substrate, a liquid crystal panel, and a display device to solve the problem that a liquid crystal panel of the prior art is prone to occurrence of afterimages when displaying an image.
  • the array substrate, the liquid crystal panel, and the display device provided by the embodiments of the present invention are described in detail below with reference to the accompanying drawings.
  • FIG. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • the array substrate in this embodiment includes a substrate (not shown), a gate driver (not shown) formed on the substrate, and a source driver (not shown). , M gate lines 101, N data lines 102, and TFTs, wherein the gate driver is connected to the gate line 101, the source driver is connected to the data line 102, and the gate driver is used to output a scan signal to the gate line 101, the source The driver is for outputting a data signal to the data line 102.
  • Each pixel region includes two pixel electrodes 103 and two TFTs.
  • the drains of the two TFTs are respectively connected to the two pixel electrodes 103.
  • the sources of the two TFTs are respectively connected to the adjacent two data lines 102, and two The gate of the TFT is connected to one of the adjacent two gate lines 101. That is, it is connected to the same gate line 101.
  • the source driver in one pixel region, when the gate driver outputs a scan signal to the gate line 101 to turn on the two TFTs, the source driver will select two adjacent data lines 102 in the pixel region.
  • the alternating voltages are respectively applied so that the alternating voltages on the adjacent two data lines 102 are in the positive period and the negative period, respectively, so that the alternating voltages on the two pixel electrodes 103 in the pixel region are also in the positive period and the negative period, respectively.
  • the period is such that an electric field is formed between the two pixel electrodes 103.
  • the pixel electrode 103 may be designed in a comb shape, and two comb-shaped pixel electrodes in one pixel region are disposed to enhance the electric field intensity between the pixel electrodes 103, but the present invention The embodiment is not limited to this.
  • the pixel electrode 103 is usually formed of a transparent conductive material such as indium tin oxide or indium oxide.
  • the liquid crystal panel of the present embodiment may include an array substrate 10, a color filter substrate 20, and a liquid crystal layer 30 that is packaged between the array substrate 10 and the color filter substrate 20, and data lines on the array substrate 10 and The source driver is connected to receive the data signal, and the gate line on the array substrate 20 is connected to the gate driver to receive the scan signal.
  • the array substrate 10 in the liquid crystal panel of the present embodiment may employ the structure shown in Fig. 3, but the embodiment of the invention is not limited thereto.
  • the pole driver applies opposite polarity data signals to the two pixel electrodes 103 (ie, the adjacent two pixel electrodes 103) in one pixel region through the adjacent two data lines 102, and the data signals of opposite polarities are respectively located at
  • the alternating voltages of the positive and negative periods are controlled by the timing of the alternating voltages on the adjacent two pixel electrodes 103 such that the alternating voltages on the adjacent two pixel electrodes 103 are in a positive period and a negative period, respectively.
  • the voltage difference between the two pixel electrodes 103 in one pixel region is the difference between the high voltage of the positive period of the alternating voltage and the low voltage of the negative period.
  • the constant voltage applied to the common electrode is usually an alternating voltage applied to the pixel electrode.
  • the intermediate value between the high voltage of the positive period and the low voltage of the negative period, the voltage difference between the pixel electrode and the common electrode is about half of the difference between the high voltage and the low voltage of the alternating voltage. Therefore, in order to obtain the same electric field intensity in the liquid crystal layer, the difference between the high voltage and the low voltage of the alternating voltage applied to the two pixel electrodes 103 in the embodiment of the present invention is applied to the prior art.
  • the half of the difference between the high voltage and the low voltage of the alternating voltage on the pixel electrode reduces the difference between the high voltage and the low voltage of the alternating voltage of the source driver output by half, thereby saving energy consumption. .
  • the source driver stops applying the opposite polarity data signal to the two pixel electrodes 103, and the coupling capacitor generated by the two TFTs is simultaneously fed back to the gate driver when the TFT is turned off.
  • the two pixel electrodes 103 (whose alternating voltages are in a positive cycle and a negative cycle, respectively) generate a voltage drop of A Vp , as shown in FIG. 5 , Vg represents a gate line.
  • the scanning signals, Vpl and Vp2 respectively represent the actual alternating voltages on the two pixel electrodes 103 in one pixel region
  • a horizontal electric field is formed between two pixel electrodes by respectively applying data signals of opposite polarities on two pixel electrodes in one pixel region, when the gate driver turns off the TFT, The coupling capacitance generated by the two TFTs is respectively fed back to the two pixel electrodes, so that the voltage drops of A Vp are generated by the two pixel electrodes to achieve self-compensation, ensuring the balance and stability of the voltage difference between the two pixel electrodes.
  • the afterimage of the display image is effectively improved, and the alternating voltage applied to the pixel electrode can be reduced, thereby saving energy consumption.
  • the embodiment of the present invention further provides a display device including the above-described liquid crystal panel, and the liquid crystal panel in this embodiment can adopt the structure shown in FIG.
  • a horizontal electric field is formed between the two pixel electrodes by alternating voltages of the two pixel electrodes, and two pixels are formed when the gate driver turns off the TFT.
  • the electrodes both generate a voltage drop of A Vp to achieve self-compensation, ensuring a balance and stability of the voltage difference between the two pixel electrodes, thereby effectively improving the afterimage of the displayed image, and at the same time reducing the alternating voltage applied to the pixel electrode, saving Energy consumption.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Liquid Crystal Display Device Control (AREA)

Abstract

一种阵列基板，包括：基板；多条栅线（101）和多条数据线（102），形成在基板上，相邻的两条栅线（101）和相邻的两条数据线（102）彼此相交而构成一个像素区域，每个像素区域包括二个像素电极（103）和二个薄膜晶体管（TFT），二个薄膜晶体管（TFT）的漏极分别与二个像素电极（103）连接，二个薄膜晶体管（TFT）的源极分别与两条数据线连接，二个薄膜晶体管（TFT）的栅极与两条栅线之一连接。

Description

阵列基板、 液晶面板和显示装置 技术领域
本发明的实施例涉及一种阵列基板、 液晶面板和显示装置。 背景技术
液晶显示器具有重量轻、 辐射低和便于携带等优点， 因此广泛用作电视 机和电脑等终端的显示器。
液晶显示器包括水平场开关（ In-Plane Switching, IPS )液晶面板、 边缘 场开关（ Fringe-Field Switching, FFS )液晶面板等多种模式。 液晶面板包括 阵列基板、 彩膜基板和封装在阵列基板和彩膜基板之间的液晶层。 图 1为现 有技术的 IPS液晶面板中的阵列基板的结构示意图。 如图 1所示， 现有技术 的 IPS液晶面板中的阵列基板包括基板（图中未示出 ) 、 栅线 101、 数据线 102、 像素电极 103、 公共电极 104、 公共电极线 105和薄膜晶体管（ TFT ) , 其中， TFT的源极和漏极分别与数据线 102和像素电极 103连接， TFT的栅 极与栅线（或扫描线） 101连接， 公共电极 104与公共电极线 105连接。 通 过液晶面板中的栅极驱动器来控制各 TFT 的开启 （即， 导通）或关闭。 在 TFT开启时， 通过源极驱动器对像素电极 103施加数据信号， 数据信号为交 变电压， 在公共电极 104上施加恒定电压 Vcom。 恒定电压 Vcom为像素电 极 103上的交变电压的正周期的高电位和负周期的低电位之间的一个值， 以 在像素电极 103和公共电极 104之间形成电场， 该电场可以控制液晶层中液 晶分子的排列方向， 恒定电压通常为交变电压的正周期的高电位和负周期的 低电位之间的中间值。
图 2为现有技术的像素电极和公共电极上的电压信号图。 如图 2所示， 图中 Vg表示栅极驱动器输出的扫描信号，图中 Vp表示像素电极 103上的实 际交变电压， 图中 Vp'表示施加在像素电极 103上的目标交变电压， 其中， △ Vp=Vp'-Vp。 在现有技术中， 当液晶面板中的栅极驱动器使得与像素电极 103连接的 TFT导通时， 液晶面板中的源极驱动器对像素电极 103施加交变 电压， 即对像素电极 103进行充电， 由于阵列基板的 TFT中还包括一些寄生 电容， 源极驱动器同时也会对这些寄生电容充电， 这些寄生电容将产生耦合 电容； 当液晶面板中的栅极驱动器使得与像素电极 103连接的 TFT关闭时， 源极驱动器停止对像素电极 103充电，栅极驱动器使 TFT关闭时所产生的电 压降（通常在 30 40V )将通过耦合电容反馈到像素电极 103上， 造成像素 电极 103上产生 A Vp的电压降。由于施加在公共电极 104上的电压为恒定电 压，而像素电极 103在处于交流电压的正周期和负周期时都会有 A Vp的电压 降， 所以像素电极 103上的电压值相对于公共电极 104上的恒定电压是非对 称的， 从而影响所显示图像的灰阶值， 导致出现图像的残像。 同时， 由于在 制备液晶面板的过程中会使液晶层内残留一些带电离子， 这些带电离子在电 场作用下堆积在取向层的附近， 所以当液晶面板显示下一帧图像时， 液晶层 中电场将发生变化， 而液晶层中残留的带电离子产生的电场却无法迅速相应 变化， 残留的带电离子产生的电场使液晶面板仍然显示之前的一帧图像， 导 致图像的残像更为严重。 发明内容
本发明的一个实施例提供一种阵列基板， 其包括： 基板； 以及多条栅线 和多条数据线， 形成在所述基板上， 相邻的两条栅线和相邻的两条数据线彼 此相交而构成一个像素区域， 其中， 每个所述像素区域内包括二个像素电极 和二个薄膜晶体管（TFT ), 所述二个薄膜晶体管的漏极分别与所述二个像素 电极连接， 所述二个薄膜晶体管的源极分别与所述两条数据线连接， 所述二 个薄膜晶体管的栅极与所述两条栅线之一连接。
本发明的另一实施例提供一种液晶面板， 其包括阵列基板、 液晶面板和 封装在所述阵列基板和所述液晶面板之间的液晶层， 所述阵列基板包括： 多 条栅线和多条数据线， 相邻的两条栅线和相邻的两条数据线彼此相交而构成 一个像素区域； 源极驱动器， 与所述数据线连接； 以及栅极驱动器， 与所述 栅线连接， 其中， 每个所述像素区域内包括二个像素电极和二个薄膜晶体管 ( TFT ), 所述二个薄膜晶体管的漏极分别与所述二个像素电极连接， 所述二 个薄膜晶体管的源极分别与所述两条数据线连接， 所述二个薄膜晶体管的栅 极与所述两条栅线之一连接。
本发明的另一实施例提供一种显示装置， 其包括上述液晶面板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术的 IPS液晶面板中的阵列基板的结构示意图；
图 2为现有技术的像素电极和公共电极上的电压信号图；
图 3为本发明的实施例提供的阵列基板的结构示意图；
图 4为本发明的实施例提供的液晶面板的结构示意图；
图 5为图 4中的二个像素电极上的电压信号图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明的实施例提供一种阵列基板、 液晶面板和显示装置， 以解决现有 技术的液晶面板在显示图像时容易出现残像的问题。 为使本领域的技术人员 更好地理解本发明的实施例提供的技术方案， 下面结合附图对本发明的实施 例提供的阵列基板、 液晶面板和显示装置进行详细描述。
图 3为本发明的实施例提供的阵列基板的结构示意图。 如图 3所示， 本 实施例中的阵列基板包括基板（图中未示出 ) 以及在该基板上形成的栅极驱 动器（图中未示出） 、 源极驱动器（图中未示出） 、 M条栅线 101、 N条数 据线 102和 TFT, 其中， 栅极驱动器与栅线 101连接， 源极驱动器与数据线 102连接， 栅极驱动器用于向栅线 101输出扫描信号， 源极驱动器用于向数 据线 102输出数据信号。 相邻的二条栅线和相邻的二条数据线彼此相交而构 成一个像素区域， M条栅线 101和 N条数据线 102彼此相交而构成（ M-1 ) X ( N-1 )个像素区域。 每个像素区域中包括二个像素电极 103和二个 TFT, 二个 TFT的漏极分别与二个像素电极 103连接， 二个 TFT的源极分别与相 邻的二条数据线 102连接，二个 TFT的栅极与相邻的二条栅线 101之一连接， 即与同一条栅线 101连接。
在本实施例中， 在一个像素区域中， 当栅极驱动器向栅线 101输出扫描 信号以使二个 TFT导通时，源极驱动器将对该像素区域中的相邻的两条数据 线 102分别施加交变电压， 使相邻的两条数据线 102上的交变电压分别处于 正周期和负周期， 使像素区域内的二个像素电极 103上的交变电压也分别处 于正周期和负周期， 从而在二个像素电极 103之间形成电场。
在本发明的实施例中， 像素电极 103可以设计成梳齿状， 一个像素区域 内的二个梳齿状的像素电极交 4 殳置，以增强像素电极 103之间的电场强度， 但是本发明的实施例不限于此。
在本发明的实施例中， 像素电极 103通常由透明导电材料形成， 例如氧 化铟锡或氧化铟辞等。
图 4为本发明的实施例提供的液晶面板的结构示意图， 图 5为图 4中的 二个像素电极上的电压信号图。 如图 4所示， 本实施例的液晶面板可以包括 阵列基板 10、 彩膜基板 20以及对盒封装在阵列基板 10和彩膜基板 20之间 的液晶层 30, 阵列基板 10上的数据线与源极驱动器连接以接收数据信号， 阵列基板 20上的栅线与栅极驱动器连接以接收扫描信号。为了便于说明，本 实施例的液晶面板中的阵列基板 10可以釆用图 3所示的结构，但是本发明的 实施例不限于此。 在一个像素区域内的二个像素电极 103上分别施加如图 5 所示的数据信号， 当栅极驱动器向栅线 101输出扫描信号以控制将一个像素 区域内的二个 TFT导通时，源极驱动器通过相邻的二条数据线 102向一个像 素区域内的二个像素电极 103 (即相邻的二个像素电极 103 )分别施加极性相 反的数据信号，极性相反的数据信号为分别处于正周期和负周期的交变电压， 通过控制相邻的二个像素电极 103上的交变电压的时序以使相邻的二个像素 电极 103上的交变电压分别处于正周期和负周期。 因为在一个像素区域内的 二个像素电极 103上的交变电压分别处于正周期和负周期， 所以在二个像素 电极 103 之间由于电压差而形成水平电场， 该水平电场可以控制液晶层 30 中液晶分子的排列方向。
在本发明的实施例中， 在一个像素区域内的二个像素电极 103之间的电 压差为交变电压的正周期的高电压和负周期的低电压之间的差值。 在现有技 术中， 在公共电极上施加的恒定电压通常为施加在像素电极上的交变电压的 正周期的高电压和负周期的低电压之间的中间值， 像素电极与公共电极之间 的电压差约为交变电压的高电压和低电压之间的差值的一半。 因此， 为了在 液晶层中获得相同的电场强度， 本发明的实施例中施加在二个像素电极 103 上的交变电压的高电压和低电压之间的差值约为现有技术中施加在像素电极 上的交变电压的高电压和低电压之间的差值的一半， 使源极驱动器输出的交 变电压的高电压和低电压之间的差值降低了一半， 从而节省了能耗。
当栅驱动电路输出的扫描信号使 TFT关闭时，源极驱动器停止对二个像 素电极 103施加极性相反的数据信号， 栅极驱动器使 TFT关闭时二个 TFT 所产生的耦合电容分别同时反馈到一个像素区域内的二个像素电极 103上， 使二个像素电极 103 (其交变电压分别处于正周期和负周期）都产生 A Vp的 电压降， 如图 5所示， Vg表示栅线上的扫描信号， Vpl和 Vp2分别表示一 个像素区域内的二个像素电极 103上的实际交变电压， Vpl'和 Vp2'分别表示 施加在像素电极 103上的目标交变电压， 其中， △ Vp=Vpl'-Vpl=Vp2'-Vp2。 由于二个像素电极 103同时产生 A Vp的电压降而实现了自补偿，确保两个二 个像素电极 103之间的电压差的平衡和稳定，从而有效改善显示图像的残像。
在本发明的实施例中， 通过在一个像素区域内的二个像素电极上分别施 加极性相反的数据信号， 以在二个像素电极之间形成水平电场， 当栅极驱动 器使 TFT关闭时， 二个 TFT所产生的耦合电容分别反馈到二个像素电极上， 使二个像素电极都产生 A Vp的电压降而实现了自补偿，确保二个像素电极之 间的电压差的平衡和稳定， 从而有效改善显示图像的残像， 同时还能降低施 加在像素电极的交变电压， 节省了能耗。
本发明的实施例还提供一种显示装置， 其包括上述的液晶面板， 本实施 例中的液晶面板可以釆用图 4所示的结构。 在本发明的实施例中， 通过使二 个像素电极的交变电压分别处于正周期和负周期， 以在二个像素电极之间形 成水平电场， 当栅极驱动器使 TFT关闭时， 二个像素电极都产生 A Vp的电 压降而实现自补偿， 确保二个像素电极之间的电压差的平衡和稳定， 从而有 效改善显示图像的残像， 同时还能降低施加在像素电极的交变电压， 节省了 能耗。
以上实施例仅用以说明本发明的技术方案， 而非对其限制； 尽管参照前 述实施例对本发明进行了详细的说明， 本领域的普通技术人员应当理解： 其 依然可以对前述各实施例所记载的技术方案进行修改， 或者对其中部分技术 特征进行等同替换； 而这些修改或者替换， 并不使相应技术方案的本质脱离 本发明各实施例技术方案的精神和范围。

Claims

权利要求书
1. 一种阵列基板， 包括：
基板； 以及
多条栅线和多条数据线， 形成在所述基板上， 相邻的两条栅线和相邻的 两条数据线彼此相交而构成一个像素区域，
其中，每个所述像素区域内包括二个像素电极和二个薄膜晶体管（ TFT ), 所述二个薄膜晶体管的漏极分别与所述二个像素电极连接 , 所述二个薄膜晶 体管的源极分别与所述两条数据线连接， 所述二个薄膜晶体管的栅极与所述 两条栅线之一连接。
2. 根据权利要求 1所述的阵列基板， 其中， 所述像素电极为梳齿状， 每 个所述像素区域内的所述二个像素电极交错设置。
3. 根据权利要求 1或 2所述的阵列基板， 其中， 所述像素电极的材料包 括氧化铟锡或氧化铟辞。
4. 根据权利要求 1至 3中任一项所述的阵列基板， 还包括：
栅极驱动器， 与所述栅线连接， 用于向所述栅线输出扫描信号； 以及 源极驱动器， 与所述数据线连接， 用于向所述数据线输出数据信号。
5. 一种液晶面板， 包括阵列基板、 液晶面板和封装在所述阵列基板和所 述液晶面板之间的液晶层， 所述阵列基板包括：
多条栅线和多条数据线， 相邻的两条栅线和相邻的两条数据线彼此相交 而构成一个像素区域；
源极驱动器， 与所述数据线连接； 以及
栅极驱动器， 与所述栅线连接，
其中，每个所述像素区域内包括二个像素电极和二个薄膜晶体管（ TFT ), 所述二个薄膜晶体管的漏极分别与所述二个像素电极连接， 所述二个薄膜晶 体管的源极分别与所述两条数据线连接， 所述二个薄膜晶体管的栅极与所述 两条栅线之一连接。
6. 根据权利要求 5所述的液晶面板， 其中，每个所述像素区域内的所述 二个像素电极之间形成的电场控制所述液晶层中液晶分子的排列方向。
7. 根据权利要求 4至 6中任一项所述的液晶面板， 其中， 所述源极驱动 器施加在所述相邻的二条数据线上的数据信号极性相反。
8. 根据权利要求 4至 7中任一项所述的液晶面板， 其中， 所述像素电极 为梳齿状， 每个所述像素区域内的所述二个像素电极交错设置。
9. 根据权利要求 4至 8中任一项所述的液晶面板， 其中， 所述像素电极 的材料包括氧化铟锡或氧化铟辞。
10. 一种显示装置， 包括权利要求 4至 9中任一项所述的液晶面板。
PCT/CN2012/084458 2012-05-04 2012-11-12 阵列基板、液晶面板和显示装置 WO2013163870A1 (zh)

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