WO2013157047A1 - Transistor utilisant un semi-conducteur au nitrure et son procédé de fabrication - Google Patents

Transistor utilisant un semi-conducteur au nitrure et son procédé de fabrication Download PDF

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WO2013157047A1
WO2013157047A1 PCT/JP2012/002749 JP2012002749W WO2013157047A1 WO 2013157047 A1 WO2013157047 A1 WO 2013157047A1 JP 2012002749 W JP2012002749 W JP 2012002749W WO 2013157047 A1 WO2013157047 A1 WO 2013157047A1
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layer
barrier layer
transistor
nitride semiconductor
algan
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PCT/JP2012/002749
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Japanese (ja)
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大石　敏之
裕太郎 山口
大塚　浩志
山中　宏治
正敏 中山
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三菱電機株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the present invention relates to a high electron mobility transistor (HEMT) using a nitride semiconductor typified by GaN and a method for manufacturing the same.
  • HEMT high electron mobility transistor
  • the channel layer is crystal-grown on the buffer layer, and electrodes (source electrode S, gate electrode G, drain electrode D) are formed on the barrier layer (
  • source electrode S, gate electrode G, drain electrode D) are formed on the barrier layer (
  • the barrier layer thickness is constant (that is, the barrier layer thickness under the gate electrode is equal to the barrier layer thickness between the source-gate and between the gate-drain).
  • GaN HEMTs are used for high-power high-frequency amplifiers or power switch circuits. To increase the frequency of the amplifier or to make the power switch circuit normally off, it is effective to reduce the barrier layer thickness under the gate electrode. However, if the barrier layer thickness under the gate electrode is reduced in the conventional structure, the source The thickness of each barrier layer between the gate and between the gate and the drain is also reduced.
  • the concentration of a two-dimensional electron gas (hereinafter referred to as 2DEG) formed in the channel decreases.
  • 2DEG concentration under the gate electrode is controlled by the gate voltage. Since the resistance is inversely proportional to the product of the electron concentration and the electron velocity, when the barrier layer is thinned, the parasitic resistance between the source and the gate and between the gate and the drain increases. This increase in parasitic resistance is a factor that decreases the amplification efficiency of the amplifier and increases the loss of the power switch circuit.
  • an X-band amplifier has a barrier layer thickness of 20 nm or less under the gate electrode, and a normally-off power switch circuit has a barrier layer thickness of 5 nm or less under the gate electrode.
  • Non-Patent Document 1 also describes other HEMT structures in FIGS. 10 and 12.
  • This structure is a recessed gate structure, and a part of the barrier layer under the gate electrode is etched to fill the space between the source and the gate and between the gate and the drain with the nitride semiconductor.
  • the electric field concentrates at the gate electrode end, and a gate leakage current flows through GaN or AlGaN located on the side of the gate electrode.
  • the Al composition of AlGaN above the barrier layer is smaller than the Al composition of the barrier layer, and it is difficult to increase 2DEG.
  • the barrier layer when the barrier layer is made thin in order to cope with the higher frequency or normally-off, the parasitic resistance between the source and the gate and between the gate and the drain is increased, and the amplification efficiency is lowered. Or there existed a subject that switching loss increased. Further, when the barrier layer thickness is reduced, there is a problem that gate leakage current easily flows from the gate electrode and reliability is lowered.
  • the present invention has been made to solve the above problems, and a transistor using a nitride semiconductor capable of reducing the generation of parasitic resistance and gate leakage current due to the thinning of the barrier layer, and its It aims at obtaining a manufacturing method.
  • a transistor using a nitride semiconductor according to the present invention is provided with a channel layer in which electrons travel and at least one of In, Al, and Ga, which is provided on the channel layer and forms a two-dimensional electron gas in the channel layer.
  • the insulating film layer including Si and N formed on the barrier layer and the Al composition is greater than 0 and less than or equal to 1
  • a cap layer composed of a nitride semiconductor layer is provided on at least a side surface of the gate electrode on the drain electrode side.
  • FIG. 1 is a view showing a structure of a transistor using a nitride semiconductor according to Embodiment 1 of the present invention, and shows a cutaway side view of the main part of the transistor.
  • the transistor shown in FIG. 1 includes a substrate 1, a buffer device 2, a channel layer 3, a barrier layer 4, a SiN cap layer 5, an AlGaN cap layer 6, a source electrode 7, a drain electrode 8, a gate electrode 9, and a protective film 10. Composed.
  • the GaN HEMT according to the present invention is used as a single amplifier, but can also be applied to a transistor constituting a monolithic microwave integrated circuit (MMIC).
  • MMIC monolithic microwave integrated circuit
  • the substrate 1 As the substrate 1, a sapphire, SiC, Si, GaN substrate or the like is used. In particular, a semi-insulating SiC substrate having a good thermal conductivity is generally used, but a very general Si substrate as a semiconductor substrate is often used because of its low price.
  • the buffer layer 2 is a layer inserted between the substrate 1 and the channel layer 3, and for the purpose of improving the crystallinity of the channel layer 3 and confining electrons in the channel, AlN, AlGaN, GaN / InGaN. Various structures such as AlN / AlGaN and their superlattices are used.
  • the channel layer 3 is a layer through which electrons (current) necessary for transistor operation flow.
  • a typical channel layer is a GaN layer, but InGaN, AlGaN, and multilayer structures thereof can also be used.
  • the In composition is made larger than 0 and smaller than 1.
  • the barrier layer 4 an AlGaN single layer is often used.
  • the interface where the channel layer 3 and the barrier layer 4 are in contact is formed by a heterojunction having a wider band gap than the channel layer 3. Any structure from the substrate 1 to the barrier layer 4 can be applied to the present invention.
  • the SiN cap layer 5 is an insulating film layer containing Si and N formed on the barrier layer 4.
  • the AlGaN cap layer 6 is a nitride semiconductor layer made of AlGaN having an Al composition greater than 0 and 1 or less.
  • the SiN cap layer 5 and the AlGaN cap layer 6 are provided on at least the side surface of the gate electrode 9 on the drain electrode 8 side.
  • the source electrode 7 and the drain electrode 8 are electrodes that extract current (electrons) in the channel layer 3 out of the HEMT. For this reason, it forms so that resistance between an electrode and 2DEG13 may be reduced as much as possible.
  • FIG. 1 shows the case where it is formed so as to be in contact with the barrier layer 4, it may be formed so as to be in direct contact with the 2DEG 13. Further, an n + region may be formed below the source electrode 7 and the drain electrode 8.
  • the gate electrode 9 is formed to include a metal that is in Schottky contact with the barrier layer 4, and the transistor operation is realized by controlling the 2DEG concentration below the gate electrode 9.
  • the protective film 10 is formed on a part of the lower side of the gate electrode 9 (left and right lateral parts). However, even if the protective film 10 is omitted, the effect of the present invention can be obtained. . Further, a structure in which the lower surface of the gate electrode 9 is formed in the barrier layer 4 (gate recess structure) may be used. Furthermore, since it is essential that the AlGaN cap layer 6 has polarization, even if it is not AlGaN, the effect of the present invention can be obtained as long as the material has polarization.
  • the Al composition of the AlGaN cap layer 6 is not less than the Al composition of the barrier layer 4 in order to reduce the parasitic resistance 14 shown in FIG.
  • the nitride semiconductor has polarization (spontaneous polarization, piezo polarization) that is not found in other semiconductors such as Si, GaAs, and SiC.
  • the parasitic resistance 14 is reduced by using a characteristic characteristic of a nitride semiconductor and based on a principle that cannot be considered in other semiconductors.
  • FIG. 2 is a diagram showing the relationship between Al composition and polarization.
  • the magnitude of polarization spontaneous polarization, piezoelectric polarization
  • resistance is inversely proportional to the product of electron concentration and electron velocity
  • parasitic resistance 14 decreases as 2DEG concentration increases. Therefore, by making the Al composition of the AlGaN cap layer 6 higher than the Al composition of the barrier layer 4, the polarization increases, the 2DEG concentration increases, and the parasitic resistance 14 can be reduced.
  • 2DEG 13 increases as the AlGaN film thickness on the channel layer 3 increases.
  • the thickness of the AlGaN film on the channel layer 3 is thicker than that of the barrier layer 4 alone. The resistance 14 can be reduced.
  • the barrier layer 4 and the AlGaN cap layer 6 are not a single layer but are composed of a plurality of AlGaN layers, the same effect can be obtained by considering the average Al composition. Further, if the structure up to the AlGaN cap layer 6 is formed on the substrate 1 in the same process, the adverse effect due to the trap 12 can be reduced, and the parasitic resistance 14 during operation (RF operation or switching operation for a large amplitude input) can be reduced. Reduction can also be expected.
  • the transistor according to the present invention is formed up to the barrier layer in the same process as in the prior art.
  • the trap 12 is formed on the barrier layer 4, and the charge state (positive, neutral, negative) of the trap 12 changes according to the gate voltage or the drain voltage.
  • the potential of the channel layer 3 changes according to the charge state of the trap 12
  • the 2DEG concentration increases or decreases. Since the change in the charge state of the trap 12 cannot follow the change in the voltage, the output cannot follow the change in the input signal, and the parasitic resistance 14 during operation increases and normal transistor operation is prevented. This is noticeably observed during high-frequency operation where the voltage changes rapidly or during switching operation where the voltage changes stepwise.
  • traps reduce 2DEG, which increases parasitic resistance.
  • the distance to 2DEG is close and strongly affected.
  • the trap 12 is formed above the SiN cap layer 5 and the AlGaN cap layer 6, and the distance from the 2DEG 13 is long. That is, the distance between the trap 12 and the 2DEG 13 is greater than that of the conventional structure. By separating the distance in this manner, the influence of the trap 12 can be reduced, so that the parasitic resistance during operation can also be reduced.
  • the SiN cap layer 5 which is an insulating film is arrange
  • the drain current was calculated by increasing the drain voltage from 0 V while keeping the source voltage and the gate voltage at 0 V in the transistor structure shown in FIG.
  • the layer thickness of the SiN cap layer 5 was 20 nm
  • the layer thickness of the AlGaN cap layer 6 was 40 nm
  • the Al composition of the barrier layer 4 was 0.2 (polarization was 8E + 12 cm ⁇ 2 ).
  • Polarization was set at the interface between the channel layer 3 and the barrier layer 4.
  • the polarization value was increased.
  • the Al composition was 0.5 and the polarization was 2E + 13 cm ⁇ 2
  • the Al composition was 0.9 and the polarization was 4E + 13 cm ⁇ 2 .
  • FIG. 3 is a diagram showing the relationship between the barrier layer thickness and the parasitic resistance.
  • the conventional structure increases the parasitic resistance when the thickness of the barrier layer is thinner than 20 nm, and the parasitic resistance is 73. Increase to 0 ⁇ mm.
  • the present invention when the Al composition of the AlGaN cap layer 6 is 0.2 and the layer thickness is 40 nm, as shown by a black circle plot in FIG. It can be seen that is suppressed to almost the same value. Further, when the Al composition of the AlGaN cap layer 6 is set to 0.5, as shown by the black square plot in FIG.
  • the polarization increases, so that the parasitic resistance 14 is further reduced and the thickness of the barrier layer 4 is increased. Even when the thickness is as thin as 4 nm, the parasitic resistance 14 can be reduced to 1.2 ⁇ mm. Furthermore, when the thickness of the barrier layer 4 is 10 nm and the Al composition of the AlGaN cap layer 6 is 0.9, the parasitic resistance 14 is 0.6 ⁇ mm, which is more effective (not shown in FIG. 3). Thus, it can be seen that the present invention is effective even with the barrier layer 4 having a thickness less than 20 nm.
  • FIG. 4 is a diagram showing the relationship between the Al composition of the cap layer and the parasitic resistance.
  • the Al composition of the barrier layer 4 is 0.2
  • the thickness of the SiN cap layer 5 is 20 nm
  • the thickness of the AlGaN cap layer 6 is 40 nm.
  • the thickness of the barrier layer 4 is 10 nm
  • the effect of the present invention can be obtained and the parasitic resistance can be obtained. 14 is decreasing.
  • the thickness of the barrier layer 4 is 4 nm
  • the parasitic resistance 14 increases when the Al composition of the AlGaN cap layer 6 is 0.3, as shown by a black square plot in FIG.
  • the barrier layer 4 has a thickness of 10 nm or less and the AlGaN cap layer 6 has an Al composition of 0.2 or more, or the barrier layer 4 has a thickness of 4 nm or less and the AlGaN cap layer. If the Al composition of 6 is higher than 0.3, the above effect can be obtained.
  • FIG. 5 is a diagram showing a profile of the two-dimensional electron gas concentration between the gate and the drain, and shows an electron concentration profile calculated from the barrier layer 4 toward the channel direction (that is, the depth direction).
  • the profile of the structure of the present invention is a1
  • the profile of the conventional structure is b1.
  • the Al composition of the barrier layer 4 is 0.2 and the layer thickness is 4 nm.
  • the AlGaN cap layer 6 has an Al composition of 0.5, a layer thickness of 40 nm, and the SiN cap layer 5 has a layer thickness of 20 nm.
  • the source voltage, the gate voltage, and the drain voltage are all 0V.
  • both the structure of the present invention and the conventional structure have an electron peak at the interface between the barrier layer 4 and the channel layer 3 to form 2DEG 13.
  • the electron concentration is 2.9E + 20 cm ⁇ 3 . That is, the electron concentration in the structure of the present invention is 2.6 times higher than the electron concentration 1.1E + 20 cm ⁇ 3 of the conventional structure shown by the profile b1, which is considered to be a factor for reducing the parasitic resistance. It is done.
  • the source electrode is open, and the current-voltage characteristics between the gate and the drain are calculated.
  • the Schottky characteristics of the reverse voltage a model is adopted in which electrons tunnel through the interface between the gate electrode 9 and the semiconductor and current flows.
  • the layer structure was such that the Al composition of the barrier layer 4 was 0.2, the layer thickness of the SiN cap layer 5 was 20 nm, the Al composition of the AlGaN cap layer 6 was 0.2, and the layer thickness was 40 nm.
  • FIG. 6 is a diagram showing the relationship between the barrier layer thickness and the gate leakage current.
  • the gate leakage current tends to increase when the barrier layer is thinned.
  • the gate leakage current is suppressed by one digit or more than the conventional structure.
  • FIG. 7 is a diagram showing the relationship between the gate leakage current and the reverse gate voltage, and shows the current-voltage characteristics when the thickness of the barrier layer 4 is 4 nm.
  • the characteristic curve in the structure of the present invention is a2, and the characteristic curve in the conventional structure is b2.
  • the gate leakage current increases as the gate voltage increases, that is, the electric field at the gate electrode end increases.
  • the reverse gate voltage is almost constant at 5 V or more, and the gate leakage current is remarkably suppressed.
  • FIG. 8 is a diagram showing a current density profile at the heterointerface between the barrier layer and the channel layer.
  • the current density profile (the channel at the heterointerface between the channel layer 3 and the barrier layer 4) is shown.
  • the profile along the heterointerface from the lower side of the gate electrode 9 toward the drain side) is shown.
  • the profile in the structure of the present invention is a3, and the profile in the conventional structure is b3.
  • the gate leakage current is reduced by providing the SiN cap layer 5 which is an insulating film on the side of the gate electrode end.
  • the SiN layer is placed in the cap layer.
  • it is provided so as to be sandwiched between AlGaN / SiN / AlGaN cap layers.
  • the SiN layer is preferably disposed at the lowermost part of the cap layer.
  • the SiN layer may have a thickness that can maintain insulation, and may be 2 to 10 nm. Furthermore, since it is sufficient if the insulating property is better than that of AlGaN, a small amount of AlGaN may be contained in the SiN layer.
  • a cap composed of the SiN cap layer 5 containing Si and N formed on the barrier layer 4 and the AlGaN layer 6 having an Al composition greater than 0 and 1 or less. Since the layer is provided on at least the side surface of the gate electrode 9 on the drain electrode 8 side, generation of parasitic resistance 14 and gate leakage current due to the thinning of the barrier layer 4 can be reduced.
  • the thickness of the barrier layer 4 is 20 nm or less, and the Al composition of the AlGaN cap layer 6 that is the cap layer is 0.2 or more, so that it is compared with the conventional structure. Gate leakage current can be significantly suppressed.
  • the channel layer 3 is made of InGaN
  • the barrier layer 4 is made of AlGaN
  • the cap layer is an SiN cap layer containing Si and N formed on the barrier layer 4. 5 and the AlGaN layer 6 having an Al composition greater than 0 and less than or equal to 1, the generation of parasitic resistance 14 and gate leakage current due to the thinning of the barrier layer 4 can be reduced.
  • FIG. 9 is a diagram showing a structure of a transistor using a nitride semiconductor according to Embodiment 2 of the present invention, and shows a cutaway side view of the main part of the transistor.
  • insulating films 15 and 16 and an n + region 17 are added to the structure of FIG.
  • the insulating film 15 is an insulating film provided on the drain side
  • the insulating film 16 is an insulating film provided on the source side.
  • the n + region 17 is formed in the barrier layer 4.
  • a voltage of several tens of volts (for example, 30 V or 50 V) is applied as a drain voltage, and a high voltage is applied between the gate and the drain. For this reason, as shown in FIG. 1, when the SiN cap layer 5 is in direct contact with the gate electrode 9 and the drain electrode 8, an excess current may flow from the drain electrode 8 to the gate electrode 9 through the AlGaN cap layer 6. Therefore, in the transistor according to the second embodiment, excess current can be suppressed by removing the AlGaN cap layer 6.
  • the 2DEG concentration decreases. For this reason, the n + region 17 is provided to reduce the parasitic resistance generated in this portion.
  • the insulating film 15 On the drain side.
  • a high reverse voltage of about ⁇ 40 V is applied to the gate electrode 9, it is necessary to remove not only the drain side but also the source side AlGaN cap layer 6. Insulating films 15 and 16 may be formed in the region where the AlGaN cap layer 6 is removed.
  • the drain electrode 8 since the drain electrode 8 is configured not to contact the AlGaN layer 6, current flowing from the drain electrode 8 to the gate electrode 9 through the AlGaN cap layer 6 can be suppressed. it can.
  • FIG. 10 is a view showing a structure of a transistor using a nitride semiconductor according to Embodiment 3 of the present invention, and shows a cutaway side view of the main part of the transistor.
  • the gate electrode 9 is not in contact with the barrier layer 4 and the SiN cap layer 5 is interposed with respect to the structure of FIG.
  • the gate electrode 9 since the gate electrode 9 is in direct contact with the barrier layer 4, a gate leakage current inevitably flows. For example, as shown in FIG. 8, the gate leakage current is reduced, but a current of about 4E + 3 A / cm 3 is still flowing. Thus, the gate leakage current can be further suppressed by interposing the SiN cap layer 5 below the gate electrode 9 as in the third embodiment.
  • the SiN cap layer 5 is interposed between the gate electrode 9 and the barrier layer 4, the gate leakage current can be further suppressed.
  • Embodiment 4 a method for manufacturing a transistor using a nitride semiconductor according to the present invention will be described with reference to FIG. In FIG. 11, the process proceeds from FIG. 11A to FIG. 11F.
  • the buffer layer 2, the channel layer 3, the barrier layer 4, the SiN cap layer 5 and the AlGaN cap layer 6 are formed on the substrate 1 in the step shown in FIG.
  • MOCVD or MBE can be used.
  • the SiN cap layer 5 is not present in the conventional structure.
  • a dopant for GaN As a dopant for GaN, a commonly used atom is silicon Si, and nitrogen is originally contained in GaN. Therefore, a conventional manufacturing apparatus using Si as a dopant gas and a gas used for N of GaN can be used as it is for forming the SiN layer. That is, layer formation from the buffer layer 2 to the AlGaN cap layer 6 can be simultaneously created by a process using a dopant gas by the same manufacturing apparatus.
  • the AlGaN cap layer 6 can be formed simultaneously from the buffer layer 2, traps (not shown in FIG. 11A) are formed on the surface of the AlGaN cap layer 6. For this reason, since the distance between the trap and 2DEG is larger than that of the conventional structure, the parasitic resistance during operation can be reduced.
  • Silane can be used as the gas for supplying Si, and nitrogen or ammonia can be used for N. Further, when the MOCVD method is used, the growth temperature is about 700 ° C. to 1200 ° C. Even if the SiN cap layer 5 is not a crystal but a polycrystal or an amorphous material, insulation can be secured. Since the AlGaN cap layer 6 may be a structure exhibiting polarization, it may be polycrystalline as long as orientation can be ensured, even if it is not a single crystal. In this case, since the magnitude of polarization is the strongest in a crystal in which the arrangement of atoms is aligned, a layer with good crystallinity or a layer with high orientation is desirable.
  • the protective film 10 protects the surface during or after the wafer process.
  • Typical materials are SiN and SiO, but other materials may be used. Further, it can be formed by various methods such as a plasma CVD method and a sputtering method, and the protective film 10 may be formed as part of the crystal growth in FIG. Even if the process is performed without forming the protective film 10, the effect of the present invention can be obtained.
  • the protective film formed with the conventional structure can be used as it is. If the protective film 10 is SiN, the protective film 10 can be simultaneously formed in the process shown in FIG.
  • the source electrode 7 and the drain electrode 8 are formed.
  • a portion corresponding to the source electrode 7 and the drain electrode 8 is opened in a mask such as a resist or SiO, and etching is performed using a mask such as a resist or SiO, so that an AlGaN cap corresponding to the source electrode 7 and the drain electrode 8 is etched.
  • Layer 6 and SiN cap layer 5 are removed.
  • a metal layer such as Ti / Al / Ni / Au, Ti / Al or the like is formed on the removed portion, and heat treatment is performed, whereby the source electrode 7 and the drain electrode 8 are completed.
  • a heat treatment in which a dopant such as Si ions is implanted and electrically activated.
  • the AlGaN cap layer 6 on the side of the source electrode 7 and the drain electrode 8 is removed, the structure described in the second embodiment is obtained.
  • the SiN cap layer 5 may or may not be on the side of the source electrode 7 and the drain electrode 8.
  • the AlGaN cap layer 6 and the SiN cap layer 5 in the region where the gate electrode 9 is formed are removed by photolithography and etching.
  • the structure shown in the third embodiment can be formed by removing only the AlGaN cap layer 6.
  • a recessed gate structure can be formed.
  • a pattern in which the gate electrode portion is opened is formed on the resist 18 by photolithography. Thereafter, a metal having Schottky characteristics is deposited by EB (electron beam) deposition or sputtering, and the resist 18 is removed (lifted off).
  • EB electron beam
  • the transistor structure (same structure as in Embodiment 1) shown in FIG. 11F can be formed.
  • a protective film, a wiring, a via hole wiring, a capacitor, and a resistor are created as necessary, but the description is omitted here.
  • the buffer layer 2, the channel layer 3, the barrier layer 4, the SiN cap layer 5 and the AlGaN cap layer 6 are simultaneously formed on the substrate 1 by one manufacturing apparatus. Since the process is included, it is possible to provide a transistor that can reduce generation of parasitic resistance and gate leakage current due to thinning of the barrier layer with a simple procedure.
  • any combination of each embodiment, any component of each embodiment can be modified, or any component can be omitted in each embodiment. .
  • the transistor using the nitride semiconductor according to the present invention can reduce the generation of parasitic resistance and gate leakage current due to the thinning of the barrier layer, and thus is suitable for a transistor of a high frequency amplifier or a power switch circuit.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

La présente invention concerne un transistor comportant une couche de coiffe, ladite couche de coiffe étant configurée à partir d'une couche de coiffe SiN (5) contenant Si et N qui est formée sur une couche barrière (4) et une couche AlGan (6) qui comprend un rapport de composition de Al compris entre 0 et 1, est prévue au moins sur la surface latérale d'une électrode de grille (9) sur le côté d'une électrode de drain (8).
PCT/JP2012/002749 2012-04-20 2012-04-20 Transistor utilisant un semi-conducteur au nitrure et son procédé de fabrication WO2013157047A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007073656A (ja) * 2005-09-06 2007-03-22 Nippon Telegr & Teleph Corp <Ntt> 窒化物半導体を用いたヘテロ構造電界効果トランジスタ
JP2007150106A (ja) * 2005-11-29 2007-06-14 Nec Corp Ｉｉｉ族窒化物半導体基板
JP2007250950A (ja) * 2006-03-17 2007-09-27 Nippon Telegr & Teleph Corp <Ntt> 窒化物半導体を用いたヘテロ構造電界効果トランジスタ
JP2009010107A (ja) * 2007-06-27 2009-01-15 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
JP2010147347A (ja) * 2008-12-19 2010-07-01 Fujitsu Ltd 化合物半導体装置及びその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007073656A (ja) * 2005-09-06 2007-03-22 Nippon Telegr & Teleph Corp <Ntt> 窒化物半導体を用いたヘテロ構造電界効果トランジスタ
JP2007150106A (ja) * 2005-11-29 2007-06-14 Nec Corp Ｉｉｉ族窒化物半導体基板
JP2007250950A (ja) * 2006-03-17 2007-09-27 Nippon Telegr & Teleph Corp <Ntt> 窒化物半導体を用いたヘテロ構造電界効果トランジスタ
JP2009010107A (ja) * 2007-06-27 2009-01-15 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
JP2010147347A (ja) * 2008-12-19 2010-07-01 Fujitsu Ltd 化合物半導体装置及びその製造方法

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